WO2025106020A1

WO2025106020A1 - Wox-based hole-selective contact layer, photovoltaic devices incorporating the layer, and manufacturing methods therefor

Info

Publication number: WO2025106020A1
Application number: PCT/SG2024/050738
Authority: WO
Inventors: Nitin NAMPALLI; Krishna Singh
Original assignee: National University of Singapore
Current assignee: National University of Singapore
Priority date: 2023-11-17
Filing date: 2024-11-15
Publication date: 2025-05-22
Anticipated expiration: 2026-05-17

Abstract

The present invention relates to a WOx-based hole-selective contact layer designed for use in photovoltaic cells. This WOx-based hole-selective contact layer comprises at least one WOx layer with a thickness ranging from 1 to 200 nm, and may be configured as multiple layers, featuring an inner layer in direct contact with a silicon wafer substrate and an outer layer in contact with an electrode. The present invention is designed to minimize interface resistance between the layers and their respective contacts, thereby enhancing the efficiency of photovoltaic cells. Furthermore, the present invention provides a method for manufacturing the WOx-based contact layer using a plasma- enhanced chemical vapor deposition (PECVD) process with optimized gas ratios, and the method can be applied to various types of silicon wafer substrates in solar cells, including tandem solar cells.

Description

DESCRIPTION

TITLE OF INVENTION: [WOX-BASED HOLE-SELECTIVE CONTACT LAYER, PHOTOVOLTAIC DEVICES INCORPORATING THE LAYER, AND MANUFACTURING METHODS THEREFOR]

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority to Singapore patent application No. 10202303252S, title “Hole Selective Contacts, Photovoltaic Devices Made Thereof and Methods of Formation”, filed on 17 November 2023, the contents of which are incorporated herein by reference.

TECHNICAL FIELD

[0002] The present disclosure relates generally to photovoltaic cell technology, specifically to structures of hole-selective contact layers, photovoltaic cells incorporating these layers, and their manufacturing methods.

BACKGROUND

[0003] The following discussion of the background to the invention is intended to facilitate an understanding of the present invention only. It should be appreciated that the discussion is not an acknowledgement or admission that any of the material referred to was published, known or part of the common general knowledge of the person skilled in the art in any jurisdiction as at the priority date of the invention.

[0004] Photovoltaic (PV) cells (also known as “solar cells”) are devices that effectively absorb solar radiation energy and converts it into electrical energy using the photovoltaic effect. When sunlight illuminates a semiconductor P-N junction, it generates new hole-electron pairs (V-E pairs). Under the influence of the electric field at the P-N junction, holes flow from the N region to the P region, and electrons flow from the P region to the N region, creating a current once the circuit is connected. These photovoltaic cells form critical components of solar power generation systems. Notably, crystalline silicon heterojunction (SHJ) photovoltaic cells stand out as a promising nextgeneration photovoltaic technology, offering high energy conversion efficiency, a simple low-temperature manufacturing process, a low temperature coefficient, and dual-sided power generation capability. These advantages make them potential candidates for future advancements in solar energy technology.

[0005] Given that transition metal oxides (TMOs) can induce efficient carrier selectivity and reduce parasitic absorption losses, thereby producing a significant current gain, TMOs can be considered for use in crystalline silicon heterojunction (SHJ) solar cells. For instance, current silicon heterojunction (SHJ) solar cells employ hole- selective contacts (HSC) based on transition metal oxides (TMOs).

[0006] For example, European Patent Application Publication No. EP4162534A1 , titled “Methodology for efficient hole transport layer using transition metal oxides”, discloses single or hetero junction Si-based solar cell comprising a hole transport layer, characterized in that the hole transport layer comprises at least one transition metal oxide, wherein the hole transport layer has a thickness of 1.5-9 nm, wherein the hole transport layer is provided on a plasma pre-treated surface layer, wherein the plasma pre-treated surface is a surface passivation layer, such as wherein the surface passivation layer is an a-Si:H pre-treated layer. Also, Chinese Patent Publication No. CN 1049930064, titled “A kind of silicon heterogenous solar cell of transition metal oxide and preparation method thereof, provides a silicon heterojunction solar cell incorporating a transition metal oxide as a hole transport layer. This cell includes a metal back electrode as the positive terminal, an inverted silicon pyramid array, an N- type silicon substrate, a silicon pyramid array, and the transition metal oxide film as the hole transport layer. However, despite these advancements, these solar cells still face several technical challenges in industrial applications, including complex and potentially hazardous fabrication processes.

[0007] Thus, there exists a need to improved photovoltaic cells and alleviate at least one of the aforementioned problems in the conventional arts.

SUMMARY

[0008] Specifically, to address the above-mentioned technical problems, the present invention specifically uses the following technical solutions:

[0009] Accordingly, an aspect of the invention refers to a WOx-based hole-selective contact layer, wherein comprising: at least one WOx layer with a thickness of 1-200 nm.

[0010] In some embodiments, the at least one WOx layer comprises at least two WOx layers; wherein the at least two WOx layers comprise an inner layer arranged to be in direct contact with a silicon wafer substrate, and an outer layer arranged to be in direct contact with an electrode; and, wherein the at least two WOx layers are configured to have a total thickness of 60-200 nm.

[0011] In some embodiments, the at least one WOx layer comprises three WOx layers.

[0012] In some embodiments, the inner layer is treated to reduce a first interface resistance between the inner layer and the silicon wafer substrate to less than 1 Q-cm².

[0013] In some embodiments, the first interface resistance between the inner layer and the silicon wafer substrate is arranged to be less than 0.1 Q-cm².

[0014] In some embodiments, a local area of the outer layer that contacts the electrode is treated to reduce a second interface resistance between the local area and the electrode to less than 1 Q-cm².

[0015] In some embodiments, the second interface resistance between the local area and the electrode is less than 0.1 £2-cm².

[0016] In some embodiments, the inner layer is configured to have a thickness of 1- 10 nm; and/or, the outer layer is configured to have a thickness of 20-600 nm.

[0017] In some embodiments, the WOx-based hole-selective contact layer further comprises at least one i-aSi layer configured to be placed between an inner layer of the at least one WOx layer and a silicon wafer substrate; and the inner layer is configured to have a thickness of 1-10 nm.

[0018] In some embodiments, the at least one WOx layer is configured to have a total thickness of 40-200 nm.

[0019] In some embodiments, the at least one i-aSi layer, the inner layer of the at least one WOx layer, or both, are treated to achieve a third interface resistance between

the at least one i-aSi layer and the inner layer of less than 1 Q-cm², or less than 0.1 Q- cm².

[0020] In some embodiments, the at least one i-aSi layer is configured to have a total thickness less than or equal to 15 nm.

[0021] In some embodiments, the WOx-based hole-selective contact layer further comprises at least one LT layer configured to be placed on an outer layer of the at least one WOx layer; wherein the outer layer is farthest from a silicon wafer substrate.

[0022] In some embodiments, the outer layer is configured to have a thickness of 1- 15 nm.

[0023] In some embodiments, the outer layer is treated to achieve a fourth interface resistance between the outer layer and the at least one LT layer of less than 1 Q-cm², or less than 0.1 Q-cm².

[0024] In some embodiments, the inner layer of the at least one WOx layer arranged to be in contact with the silicon wafer substrate is configured to have a thickness of 1 -10 nm; and the inner layer is treated to achieve a first interface resistance between the inner layer and the silicon wafer substrate of less than 1 Q-cm², or less than 0.1 Q-cm².

[0025] In some embodiments, the inner layer of the at least one WOx layer and the outer layer of the at least one WOx layer are the same layer as a single layer of WOx layer.

[0026] In some embodiments, the LT layer is a TOO layer.

[0027] In some embodiments, the TOO layer is configured as a double layer.

[0028] In some embodiments, the method for manufacturing WOx-based hole- selective contact layer comprises a step of: S201 depositing at least one WOx layer on a silicon wafer substrate using a PECVD method based on a first set of deposition parameters, with the at least one WOx layer is configured to have a thickness of 1 -200 nm; wherein the first set of deposition parameters comprises: a gas ratio of O₂ to WF₆ of 0-20; and, a gas ratio of H₂ to WF₆ of 0-50.

[0029] In some embodiments, the first set of deposition parameters further comprises: a gas ratio of PH₃ to WF₆ of 0-10; a gas ratio of B₂H₆ to WF₆ of 0-10; and/or, a gas ratio of N₂ to WF₆ of 0-10.

[0030] In some embodiments, the first set of deposition parameters further comprises: the gas ratio of O₂ to WF₆ is 1 -5; and, the gas ratio of H₂ to WF₆ is 0-5.

[0031] In some embodiments, the first set of deposition parameters comprises: the gas ratio of PH₃ to WF₆ is 0-5; the gas ratio of B₂H₆ to WF₆ is 0-5; and/or, the gas ratio of N₂ to WF₆ is 0-3.

[0032] In some embodiments, the at least one WOx layer comprises an inner layer arranged to be in direct contact with a silicon wafer substrate; and, wherein the inner layer is configured to have a thickness of 1 -10 nm.

[0033] In some embodiments, prior to the step of S201 , the method further comprises a step of: S101 , depositing at least one i-aSi layer on the silicon wafer substrate using the PECVD method so that in the step of S201 , the at least one WOx layer is placed on the at least i-aSi layer.

[0034] In some embodiments, prior to the step of S201 , the method further comprises a step of: S1012, depositing at least one modified i-aSi layer on the substrate using the PECVD method based on a second set of deposition parameters; wherein the second set of deposition parameters comprises: a gas ratio of H2 to SiH4 is 0-50; or 20-35.

[0035] In some embodiments, the at least one modified i-aSi layer is configured to have a thickness of 4-50nm or 5-20 nm.

[0036] In some embodiments, the at least one WOx layer is configured to have a thickness of 4-100 nm.

[0037] In some embodiments, the at least one WOx layer is configured to have a thickness of 5-40 nm.

[0038] In some embodiments, after the step of S201 , the method further comprises a step of: S301 , depositing at least one LT layer on the at least one WOx layer.

[0039] Another aspect of the invention refers to a solar cell, comprising: a silicon wafer substrate that comprises a top side and a rear side; and, a hole-selective contact layer placed on either the top side or the rear side; wherein the hole-selective contact layer is a WOx-based hole-selective contact layer according to the various embodiments of the present invention.

[0040] In some embodiments, the silicon wafer substrate is a monocrystalline silicon wafer substrate, multi-crystalline silicon wafer substrate, an N-type silicon wafer substrate, or a P-type silicon wafer substrate.

[0041] In some embodiments, the solar cell is a tandem solar cell, comprising a first solar cell unit located below and a second solar cell unit located above, wherein the WOx-based hole-selective contact layer and the second solar cell unit are configured to be on the same side of the first solar cell unit; or, the WOx-based hole-selective contact layer and the second solar cell are arranged to be located on opposite sides of the first solar cell unit.

[0042] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

[0043] BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the figures, which illustrate, by way of non-limiting examples only, embodiments of the present invention,

[0045] [Fig. 1]: schematic structural diagram of a WOx-based hole-selective contact (HSC) according to a first embodiment of the present invention (i.e., WOx only (no i-aSi or TOO) 13d);

[0046] [Fig. 2]: schematic structural diagram of a WOx-based HSC according to a second embodiment of the present invention (i.e., WOx/TCO (no i-aSi) 13c);

[0047] [Fig. 3]: schematic structural diagram of a WOx-based HSC according to a third embodiment of the present invention (i.e., i-aSi/WOx (no TCO) 13b);

[0048] [Fig. 4]: schematic structural diagram of a WOx-based HSC according to a fourth embodiment of the present invention (i.e. , i-aSi/WOx/TCO);

[0049] [Fig. 5]: schematic structural diagram of a WOx-based HSC (with modified I- aSi (131 a)) according to a fifth embodiment of the present invention ;

[0050] [Fig. 6]: schematic structural diagram of a WOx-based HSC (with a two-layer WOx) according to a sixth embodiment of the present invention;

[0051] [Fig. 7]: schematic structural diagram of a WOx-based HSC (with a three-layer WOx) according to a seventh embodiment of the present invention;

[0052] [Fig. 8]: schematic structural diagram of a WOx-based HSC (with a modified WOx layer in contact with the i-aSi layer) according to an eighth embodiment of the present invention;

[0053] [Fig. 9]: schematic structural diagram of a WOx-based HSC (with a modified WOx layer in contact with the LT layer) according to a ninth embodiment of the present invention;

[0054] [Fig. 10]: schematic structural diagram of a WOx-based HSC (including a TCO layer) according to a tenth embodiment of the present invention;

[0055] [Fig. 11]: schematic structural diagram of a solar cell with a WOx-based HSC according to a first solar cell embodiment of the present invention (with the WOx-based HSC located on the rear side of the n-type substrate);

[0056] [Fig. 12]: schematic structural diagram of a solar cell with a WOx-based HSC according to a second solar cell embodiment of the present invention (with the WOx- based HSC located on the front side of the n-type substrate);

[0057] [Fig. 13]: schematic structural diagram of a solar cell with a WOx-based HSC according to a third solar cell embodiment of the present invention (with the WOx-based HSC located on the rear side of the p-type substrate);

[0058] [Fig. 14]: schematic structural diagram of a solar cell with a WOx-based HSC according to a fourth solar cell embodiment of the present invention (with the WOx- based HSC located on the rear side of a monocrystalline silicon wafer substrate);

[0059] [Fig. 15]: schematic structural diagram of a solar cell with a WOx-based HSC according to a fifth solar cell embodiment of the present invention (with the WOx-based HSC located on the rear side of a polycrystalline silicon wafer substrate);

[0060] [Fig. 16]: schematic structural diagram of a tandem solar cell with a WOx- based HSC according to an embodiment of the present invention;

[0061] [Fig. 17A]: flowchart of a method for preparing an i-aSi/WOx/TCO HSC according to a first method embodiment of the present invention;

[0062] [Fig. 17B]: flowchart of a method for preparing an i-aSi/WOx/TCO HSC according to a second method embodiment of the present invention;

[0063] [Fig. 17C]: flowchart of a method for preparing an i-aSi/WOx/TCO HSC according to a third method embodiment of the present invention;

[0064] [Fig. 17D]: flowchart of a method for preparing an i-aSi/WOx/TCO HSC according to a fourth method embodiment of the present invention;

[0065] [Fig. 17E]: flowchart of a method for preparing a WOx-based HSC according to an embodiment of the present invention;

[0066] [Fig. 17F]: flowchart showing the deposition of at least one i-aSi layer in the WOx-based HSC preparation method according to an embodiment of the present invention;

[0067] [Fig. 17G]: flowchart showing the deposition of at least one WOx layer in the WOx-based HSC preparation method according to an embodiment of the present invention;

[0068] [Fig. 17H]: flowchart showing the deposition of at least one TCO layer in the WOx-based HSC preparation method according to an embodiment of the present invention.

[0069] [Fig. 171]: a schematic illustration of a photovoltaic cell prepared with a WOx- based HSC according to one embodiment of the present invention.

[0070] [Fig. 18]: comparison of the extinction coefficient of p-aSi and WOx as a function of wavelength;

[0071] [Fig. 19]: comparison of short-circuit current Jsc between HJ solar cells based on p-aSi HSC and those based on WOx HSC;

[0072] [Fig. 20]: comparison of pseudo fill factor between HJ solar cells based on p- aSi HSC and those based on WOx HSC;

[0073] [Fig. 21]: comparison of series resistance and the impact of series resistance on fill factor (FF) loss in solar cells based on WOx, MoOx, and VOx, respectively;

[0074] [Fig. 22]: comparison of heat resistance and its impact on solar cell efficiency in cells based on WOx, MoOx, and VOx, respectively;

[0075] [Fig. 23]: comparison of the effects of WOx HSCs prepared by sputtering, evaporation, and PECVD methods on solar cell efficiency; and,

[0076] [Fig. 24]: schematic structural diagram of the conventional p-aSi HSCs used in the conventional solar cells.

DETAILED DESCRIPTION

[0077] Throughout this document, unless otherwise indicated to the contrary, the terms “comprising”, “consisting of’, “having” and the like, are to be construed as non- exhaustive, or in other words, as meaning “including, but not limited to".

[0078] Furthermore, throughout the document, unless the context requires otherwise, the word “include” or variations such as “includes” or “including” will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers.

[0079] Throughout the description, it is to be appreciated that the term “tungstenoxide” (WOx) refers to is a compound of tungsten and oxygen commonly used as a thin- film material in electronics and energy applications, including solar cells.

[0080] Throughout the description, it is to be appreciated that the term “interface resistance” refers to the resistance encountered at the junction between two adjacent materials or layers within the cell, which affects charge carrier transfer across the interface and impacts the cell’s electrical performance. In general, lower interface resistance is desirable to minimize energy losses, improve charge extraction, and enhance the cell’s power conversion efficiency. In the context of the present invention, Interface resistance is measured using the metric of specific contact resistivity (a measure of the electrical resistance at the interface between two materials, typically expressed in units of ohm-square centimeters (Q-cm²)), assessed under illumination conditions that are representative of the actual operating environment of a solar cell.

[0081] Unless defined otherwise, all other technical and scientific terms used herein have the same meaning as is commonly understood by a skilled person to which the subject matter herein belongs.

[0082] This present invention discloses: (1) a novel hole-selective contact (HSC) designs for solar photovoltaic cells, comprising a stack of thin films, at least one of which is a tungsten-oxide (WOx) layer (i.e., WOx-containing HSC); (2) methods for manufacturing/fabricating the WOx-containing HSC; (3) photovoltaic cell devices utilizing the WOx-containing HSC of the present invention; and (4) methods for forming the photovoltaic cells comprising the WOx-containing HSC of the present invention.

[0083] According to a first aspect, the present invention discloses a HSC comprising of a stack of thin film layers deposited on a silicon wafer substrate 11 with up to three main components: (1.1 ) zero, one, or a plurality of thin film layers of intrinsic amorphous silicon (i-aSi), in direct contact with the silicon wafer substrate 11 ; (1.2) one, two, or three thin film layers of WOx, positioned above any underlying i-aSi (if present) and in contact with subsequent layers; and (1.3) zero, one, or a plurality of thin film layers of a lateral transport material, such as transparent conductive oxide (TCO), positioned above the WOx layer(s). This WOx-containing HSC of the present invention has demonstrated better performance compared to conventional HSCs that utilize p-type amorphous silicon (p-aSi). Consequently, this WOx-based HSC offers the potential for lower cost per watt ($/W) in photovoltaic cell devices and may improve safety by eliminating the need for pyrophoric gases, such as SiH4, required in traditional p-aSi HSCs.

[0084] In other words, there are four types of WOx-based hole-selective contact (HSC) structures according to the first aspect of the present invention:

[0085] WOx only HSC 13d: a configuration with at least one WOx layer 132 arranged on the rear side of the silicon wafer substrate 11 , where the WOx layer 132 directly functions as the hole-selective contact layer, making direct contact with both the silicon wafer substrate 11 and the electrode 600, as shown in WOx-only HSC 13d in Fig. 1. In this configuration, there are neither i-aSi nor TOO layers.

[0086] WOx/TCO HSC 13c: a configuration with at least one WOx layer 132 on the rear side of the silicon wafer substrate 11 , and other layers 700, such as an LT layer 200 or a TCO layer 700a, stacked on the outer layer of the WOx layer 132, which is positioned farthest from the silicon wafer substrate 11. In this configuration, the innermost WOx layer is in direct contact with the silicon wafer substrate 11 , as shown in WOx/TCO HSC 13c in Fig. 2. In this configuration, there is no i-aSi layer.

[0087] i-aSi/WOx HSC 13b: a configuration with at least one WOx layer 132 on the rear side of the silicon wafer substrate 11 , with at least one i-aSi layer 131 positioned between the WOx layer 132 and the silicon wafer substrate 11 , as illustrated in I- aSi/WOx HSC 13b in Fig. 3. In this configuration, there is no TCO layer.

[0088] i-aSi/WOx/TCO HSC 13a: a configuration with at least one i-aSi layer 131 on the rear side of the silicon wafer substrate 11 , followed by at least one WOx layer 132 stacked on top of the i-aSi layer 131 , and at least one other layer 700, such as an LT layer 200 or a TCO layer 700a, stacked on top of the WOx layer 132, as shown in I- aSi/WOx/TCO HSC 13a in Fig. 4.

[0089] In addition, the present invention specifies the thickness, number of layers, and purpose of each component layer. Incorporating multiple layers of i-aSi, WOx, and TCO materials allows for enhanced device performance by optimizing: (a) the interface between i-aSi (or silicon wafer substrate 11) and WOx, (b) the bulk properties of the WOx layer, and (c) the interface between WOx and the lateral transport material, such as a TCO layer.

[0090] In some embodiments, regarding the i-aSi layer(s), if included, the total thickness of the i-aSi should not exceed 15 nm. This total thickness of the i-aSi layer(s) may comprise one, two, or more consecutively deposited i-aSi layers, each with an individual thickness of 1-10 nm. The i-aSi layer in direct contact with the WOx layer can be specially modified to achieve a low interface resistance between it and the overlying

WOx layer. In such cases, the interface resistance should be below 1 Q-cm², and preferably below 0.1 Q-cm^z.

[0091] In some embodiments, regarding the WOx layer(s), the total thickness of the WOx should be between 1 and 200 nm. Within this range, the WOx layers can comprise one, two or three consecutively deposited WOx layers, each with a unique composition and a thickness that can vary from 1 to 200 nm.

[0092] In some embodiments, if i-aSi layer is present in the HSC stack, the WOx layer in contact with the i-aSi layer may have a thickness of 1 -10 nm and may be specially modified to achieve a low interface resistance with the underlying i-aSi layer. In such cases, the interface resistance should be less than 1 Q-cm², and preferably less than 0.1 Q-cm². Subsequent WOx layers deposited afterward may have different compositional properties compared to this modified WOx layer.

[0093] In some embodiments, if no i-aSi is present in the HSC stack, the WOx layer in contact with the silicon substrate may have a thickness of 1-10 nm and can be specially modified to achieve a low interface resistance with the underlying silicon substrate. In such cases, the interface resistance should be less than 1 D-cm², and preferably less than 0.1 £l-cm². Subsequent WOx layers deposited afterward may have different compositional properties compared to this modified WOx layer.

[0094] In some embodiments, if a lateral transport (LT) layer is present in the HSC stack, the WOx layer in contact with the LT layer(s) may have a thickness of 1 -15 nm and can be specially modified to ensure a low interface resistance with the overlying LT layer. In such cases, the interface resistance should be less than 1 D-cm², and preferably less than 0.1 Q-cm².

[0095] In some embodiments, if a lateral transport (LT) layer is not present in the HSC stack, the total thickness of the WOx layer may range from 40 to 200 nm. This total WOx thickness should comprise two or more layers: inner layers (closer to the silicon substrate) and outer layers (further from the silicon substrate). The outer layer should have a thickness between 20 and 200 nm and exhibit a sheet resistance of less than 1000 Q/sq, preferably below 400 Q/sq. If specific regions of the outermost WOx layer make direct contact with a metal electrode, the contact resistivity at these interface regions should be less than 1 Q-cm², and more preferably below 0.1 Q-cm², as

measured by specific contact resistivity under illumination conditions representative of the solar cell’s operating point

[0096] In some embodiments, if both LT layers and i-aSi layers are absent in the HSC, and the HSC comprises entirely of WOx, the total thickness of the WOx must be between 60 and 200 nm, with an average sheet resistance of no more than 400 Q/sq, more preferably below 300 Q/sq, even more preferably below 200 Q/sq, and most preferably below 100 Q/sq. The total WOx thickness must comprise at least two layers, and preferably three or more layers. In this configuration, the innermost WOx layer should have a contact resistivity with the silicon substrate of less than 1 Q-cm², and more preferably below 0.1 Q-cm². If specific regions of the outermost WOx layer make direct contact with a metal electrode, the contact resistivity at these interface regions should be less than 1 Q-cm², and more preferably below 0.1 Q-cm², as quantified by specific contact resistivity under illumination conditions representative of the solar cell’s operating point.

[0097] According to a second aspect, the invention discloses a method for manufacturing WOx-containing HSC stacks as described in the first aspect. This method comprises a series of vacuum-based thin-film deposition steps applied to one side of a silicon wafer substrate 11 . Initially, the i-aSi layer(s) (if present) are deposited, followed by WOx layer(s) and finally the lateral transport materials. The i-aSi layer(s) are deposited using plasma-enhanced chemical vapor deposition (PECVD) process. Specific PECVD parameters are provided for the i-aSi layer that interfaces with the overlying WOx layer, although these parameters are optional.

[0098] For other i-aSi layer(s) that do not contact the WOx layer, deposition parameters are not restricted. WOx layer deposition may be performed by PECVD, sputtering, or evaporation. For PECVD-deposited WOx, all WOx layers are deposited sequentially in the same process chamber to maintain a continuous vacuum environment. Detailed process parameters for PECVD, sputtering, and evaporation are provided to achieve optimal WOx layer properties. The lateral transport layer (e.g., TCO thin films) is preferably deposited via sputtering, though other methods may also be suitable. When TCO sputtering is used, preferred sputter parameters to achieve high- performance TCO are described. All deposition techniques used are compatible with commercial mass production, offering significant cost advantages. Additionally, specific

deposition conditions are developed to ensure (1) high performance of the WOx-based HSC and (2) compatibility with existing silicon heterojunction solar cell manufacturing processes. It has been shown that comparable performance can be achieved using PECVD, sputtering, or evaporation for WOx layers; however, PECVD provides more precise control over material properties due to the number of adjustable process parameters, making it the preferred method.

[0099] According to a third aspect, the present invention discloses photovoltaic solar cell devices incorporating the WOx-containing HSC described in the first aspect of the present invention on at least one side of the solar cell. As shown in Fig. 17, these solar cells are manufactured using the process flow defined in the second aspect of the present invention. The solar cell may be a single-junction silicon cell or a multi-junction cell, with the silicon wafer substrate properties specified (monocrystalline vs. multicrystalline silicon; n-type or p-type doped silicon). The side of the silicon wafer substrate on which the WOx-containing HSC is applied can be either the front (illuminated side of the silicon wafer substrate) or rear side (non-illuminated side of the silicon wafer substrate). The configuration of layers on the opposite side of the substrate is unrestricted.

[0100] Specific embodiments of a single-junction silicon solar cell, as described in the third aspect of the present invention, comprise: (a) an n-type monocrystalline silicon substrate, (b) the WOx-containing HSC applied to the rear side, (c) the WOx-containing HSC composed of two i-aSi layers, one WOx layer, and two TCO layers, and (d) an electron-selective contact (ESC) comprising a stack of i-aSi, n-type amorphous silicon (n-aSi), and TCO. This configuration has demonstrated improved performance over incumbent heterojunction solar cells that utilize an HSC containing only p-aSi (see Fig. 24).

[0101] According to a fourth aspect, the present invention discloses methods for forming the solar cells described in the third aspect of the present invention. These methods comprise (a) utilizing a subset of the processes defined for forming the WOx- based HSC in the second aspect, and (b) applying the WOx-based HSC to one side of the wafer (referred to as the "HSC side") only after passivating the opposite side of the wafer ("opposite side"). A specific embodiment corresponding to this method is

provided, aligning with the embodiment described in the third aspect of the present invention.

[0102] The methods in this fourth aspect of the present invention are shown to be cost-effective, as they reduce the total number of process steps and minimize contamination risk. Additionally, WOx-based HSCs demonstrate excellent thermal stability, tolerating temperatures up to at least 200 °C, which is superior to HSCs that use alternative metal oxides, such as MoOx and VOx. This thermal stability is crucial because subsequent processing steps required to complete the device may involve temperatures of 200 °C or higher. Thus, the enhanced thermal stability of WOx-based HSCs contributes to improved performance in the final solar cell devices.

[0103] Referring to Fig. 1 , the present invention provides a WOx-only HSC 13d, comprising at least two WOx layers 132 with a total thickness of 60-200 nm. In some embodiments, the WOx layers 132 comprises three layers. In this configuration, there is neither i-aSi nor TCO layers.

[0104] In some embodiments, the thickness of each WOx layer 132 may be the same or different.

[0105] In some embodiments, the inner layer among at least two WOx layers 132, closest to the silicon wafer substrate 11 , is configured to have a thickness of 1-10 nm.

[0106] In some embodiments, the inner layer is treated to reduce the interface resistance between the inner layer and the silicon wafer substrate 11 to less than 1 Q- cm². In some embodiments, the interface resistance between the inner layer and the silicon wafer substrate 11 is less than 0.1 Q-cm².

[0107] In some embodiments, the outer layer among at least two WOx layers 132, farthest from the silicon wafer substrate 11 , has a thickness of 1-15 nm.

[0108] In some embodiments, a local area on the outer layer that contacts the electrode has an interface resistance with the electrode of less than 1 Q-cm². In some embodiments, the interface resistance between the outer layer and the electrode 600 is less than 0.1 Q-cm².

[0109] Referring to Fig. 2, the present invention also provides a WOx/TCO HSC 13c, comprising at least one WOx layer stacked on the rear side of the silicon wafer substrate 11 and at least one LT layer 200 stacked on the outer layer of the WOx layer, which is farthest from the silicon wafer substrate 11 . In this configuration, there is no i- aSi layer.

[0110] In some embodiments, the outer layer contacts the at least one LT layer with a thickness of 1-15 nm.

[0111] In some embodiments, the outer layer in contact with at least one LT layer is treated so that the interface resistance between the outer layer and the LT layer 200 is less than 1 Q-cm². In some embodiments, this interface resistance is less than 0.1 Q- cm².

[0112] In some embodiments, the inner layer of at least one WOx layer 132, which contacts the silicon wafer substrate 11 , is configured to have a thickness of 1-10 nm.

[0113] In some embodiments, the inner layer is treated to achieve an interface resistance with the silicon wafer substrate 11 of less than 1 £l-cm². In some embodiments, this interface resistance is less than 0.1 £l-cm².

[0114] In some embodiments, the inner layer and the outer layer are the same layer, meaning only a single WOx layer is provided.

[0115] In some embodiments, the LT layer 200 is a TOO layer 700a. In some embodiments, this TOO layer 700a is considered as a double layer.

[0116] Referring to Fig. 3, the present invention further provides an i-aSi/WOx HSC 13b, comprising at least one i-aSi layer 131 stacked on the rear side of the silicon wafer substrate 11 , and at least one WOx layer 132 stacked on the i-aSi layer 131. In this configuration, there is no TCO layer.

[0117] In some embodiments, the total thickness of the i-aSi layer is less than 15 nm.

[0118] In some embodiments, the total thickness of at least one WOx layer 132 is 40-

200 nm.

[0119] In some embodiments, the layer of at least one WOx layer 132 that contacts at least one i-aSi layer 131 (i.e., the layer closest to the silicon wafer substrate 11) serves as the inner layer, with a thickness of 1-10 nm.

[0120] In some embodiments, the inner layer in contact with at least one i-aSi layer 131 is pre-treated to reduce the interface resistance between the i-aSi layer 131 and the inner layer to less than 1 Q-cm². Preferably, the contact resistivity is less than 0.1 Q- cm².

[0121] In some embodiments, the inner layer of at least one WOx layer 132 may not be pre-treated, while the i-aSi layer 131 that contacts this inner layer is pre-treated to reduce the interface resistance between the i-aSi layer 131 and the inner layer to less than 1 Q-cm². In some embodiments, this interface resistance is less than 0.1 D-cm². In some embodiments, both the inner layer of at least one WOx layer 132 and the i-aSi layer 131 in contact with this inner layer can be pre-treated to achieve the reduced interface resistance.

[0122] Referring to Fig. 4, the present invention also provides an i-aSi/WOx/TCO HSC 13a, which comprises: at least one i-aSi layer 131 stacked on the rear side of the silicon wafer substrate 11 ; at least one WOx layer 132 stacked on the i-aSi layer 131 ; and at least one LT layer 200 stacked on the outer layer of the WOx layer 132, farthest from the silicon wafer substrate 11. In this embodiment, the layer of at least one WOx layer 132 closest to the silicon wafer substrate 11 is the inner layer, which contacts at least one i-aSi layer 131 , while the layer of at least one WOx layer 132 farthest from the silicon wafer substrate 11 is the outer layer, which contacts at least one LT layer 200.

[0123] In some embodiments, the total thickness of at least one i-aSi layer should not exceed 15 nm, with each layer having a thickness of 1 -10 nm.

[0124] Referring to Fig. 5, at least one i-aSi layer 131 comprises a modified i-aSi layer 131a that is in contact with the WOx layer 132, wherein the modified i-aSi layer 131a has been pre-treated/modified to reduce the interface resistance between the modified i-aSi layer 131 a and the WOx layer 132 to less than 1 £l-cm². In some embodiments, the interface resistance is less than 0.1 Q-cm².

[0125] Referring to Fig. 8, the inner WOx layer may also be pre-treated to reduce the interface resistance between the i-aSi layer 131 and the modified inner WOx layer 132a to less than 1 Q-cm². In some embodiments, the interface resistance is less than 0.1 Clem².

[0126] Referring to Fig. 9, the outer WOx layer in contact with at least one LT layer 200 in at least one WOx layer 132 is pre-treated to reduce the interface resistance between the modified WOx layer 132a (i.e., the outer layer) and the LT layer 200 to less than 1 Q-cm². In some embodiments, the interface resistance is less than 0.1 Q-cm².

[0127] In some embodiments, the outer layer in contact with at least one LT layer 200 (i.e., either an unmodified WOx layer 132 or a modified WOx layer 132a) is configured to have a thickness of 1-15 nm.

[0128] Referring to Fig. 6 and Fig. 7, preferably, the WOx layer is configured as duallayer or triple-layer structure.

[0129] According to various embodiment, the present invention discloses photovoltaic cell, comprising the WOx-based HSC from the various embodiments of the present invention.

[0130] In some embodiments, the WOx-based HSC 13 may be placed on either side of the silicon wafer substrate in the photovoltaic cell.

[0131] Referring to Fig. 10, Fig. 11 and Fig. 16, a photovoltaic cell with a photovoltaic absorber layer comprises an N-type substrate 110, wherein the WOx-based HSC 13 is positioned on the rear side of the N-type substrate 110, with a contact terminal 400 (e.g., electrode 600) placed on the WOx-based HSC 13; other layers 700 (e.g., ESC stack or ETL stack 100) are arranged on the front side of the N-type substrate 110, with corresponding contact terminals 400 on those layers.

[0132] Referring to Fig. 16, a photovoltaic cell comprises an N-type substrate 110, wherein the WOx-based HSC 13 is positioned on the front side of the N-type substrate 110, with a contact terminal 400 (e.g., electrode 600) on the WOx-based HSC 13; other layers 700 are arranged on the rear side of the N-type substrate 110, with corresponding contact terminals 400 on those layers.

[0133] Referring to Fig. 13, the photovoltaic cell comprises a P-type substrate 111 , with the WOx-based HSC 13 positioned or placed on the rear side of the P-type substrate 111 and a contact terminal 400 (e.g., electrode 600) positioned or placed on the WOx-based HSC 13. Other layers 700 are arranged on the front side of the P-type substrate 111 , with corresponding contact terminals 400.

[0134] Referring to Fig. 14 and Fig. 15, the silicon wafer substrate 11 of the solar cell may be either a monocrystalline silicon substrate 11 a or a polycrystalline silicon substrate 11 b.

[0135] In some embodiments, the WOx-based HSC 13 of the present invention can also be used in tandem solar cells, comprising a plurality of solar cell units.

[0136] Referring to Fig. 16, a tandem solar cell with two photovoltaic absorber layers is illustrated. The bottom solar cell unit includes an N-type silicon substrate 110. The front side of the N-type silicon substrate 110 has other layers 700, over which additional layers 134 from the top solar cell unit are stacked. The rear side of the N-type silicon substrate 110 is configured with the WOx-based HSC 13, along with corresponding contact terminals 400. In other words, in this rear-side positioning configuration, the WOx-based HSC 13 is placed on the rear side of the N-type silicon substrate, helping to facilitate charge transport and collection at the back of the bottom solar cell unit.

[0137] Alternatively, the WOx-based HSC 13 may be positioned on the front side of the N-type silicon substrate 110, between the bottom solar cell unit and the additional layers 134 of the top solar cell unit, with other layers 700 arranged on the rear side of the N-type silicon substrate 110. In other words, in this front-side positioning, the WOx- based HSC 13 can be placed on the front side of the N-type silicon substrate, between the N-type silicon substrate and the additional layers 134 from the top solar cell unit. This configuration can be beneficial if the design or fabrication of the tandem solar cell requires front-side contact for improved efficiency or simplified layering.

[0138] In some embodiments, a perovskite or chalcogenide layer can be used in the top solar cell unit, with the WOx-based HSC 13 positioned either on the opposite side of the top solar cell unit (preferred in some specific embodiments) or on the same side.

[0139] In some embodiments, a method is provided for forming the WOx-based HSC 13 (see Fig. 17E). Referring to Fig. 17A and Fig. 17G, the preparation method for a WOx-based HSC 13 (e.g., i-aSi/WOx/TCO HSC 13a) in the present invention comprises the following steps of:

[0140] S101 : Depositing at least one i-aSi layer on one side of the substrate (e.g, the rear side) using the PECVD method (e.g, a standard PECVD process routinely applied in the conventional arts).

[0141] S201 : Depositing at least one WOx layer on the i-aSi layer.

[0142] The WOx layers may be deposited via PECVD, sputtering, or evaporation. For PECVD-deposited WOx, all WOx layers are deposited in the same process chamber, ensuring that the silicon wafer substrate 11 remains in a continuous vacuum environment between the deposition of each successive WOx layer 132. Table 1 below summarizes a possible set of process parameters for forming WOx layers with desired properties using PECVD, sputtering, and evaporation, according to some embodiments of the present invention. In some embodiments, the thickness of the WOx layer 132 preferably ranges from 4 to 100 nm, and even more preferably from 5 to 40 nm. In other embodiments, the thickness may more broadly range from 1 to 200 nm, which are also suitable for achieving the technical advantages of the present invention.

[0143] Table 1 :

[0144] In conventional methods, the deposition of p-type amorphous silicon (p-aSi) by PECVD requires silane (SiH₄) and hydrogen (H_z) gases. Silane is a pyrophoric and flammable gas, demanding strict safety protocols and specialized handling to mitigate fire hazards. Consequently, the current PECVD process for p-aSi deposition is both costly and high-risk, with the safe handling of silane adding complexity and expense to production.

[0145] In contrast, the PECVD process in the present invention for depositing WOx- based HSC layers utilizes tungsten hexafluoride (WF₆) and oxygen (O₂), both of which are non-flammable and present a significantly lower safety risk than SiH₄. As a result, they do not require the same stringent safety measures, reducing the overall safety risk in mass production and lowering handling costs. This shift to non-flammable gases in the WOx-based process makes it a safer and more cost-effective choice for large-scale manufacturing.

[0146] S301 : Deposit at least one LT layer using the sputtering method (e.g., a conventional sputtering process).

[0147] In other embodiments, to achieve an interface resistance of less than 1 Q-cm² between the LT layer in contact with the WOx layer, the sputtering parameters are adjusted to produce an improved LT layer with refined properties (see Fig. 17H).

[0148] While sputtering is the preferred method for depositing subsequent lateral transport layers (e.g, TCO thin films), other deposition methods may also be used. Where TCO sputtering is applied, the preferred sputter parameters for obtaining a high- performance TCO are specified. A possible set of sputtering parameters is summarized in Table. 2 below.

[0149] Table 2:

[0150] Similarly, only the process parameters for the TL layer in contact with the WOx layer are required to be restricted, as specified in the table above, to obtain an improved LT layer. For other TL layers, there are no such restrictions, and conventional process parameters may be used.

[0151] The thin-film deposition methods used above to produce WOx-based hole- selective contacts (HSCs) for silicon heterojunction solar cells (e g., PECVD (Plasma- Enhanced Chemical Vapor Deposition), sputtering, and evaporation) are commonly used in large-scale commercial production and are therefore cost-effective. Additionally, specific deposition conditions have been optimized to ensure (1) high performance of the WOx-based HSC and (2) full compatibility with existing silicon heterojunction solar cell manufacturing processes. Studies show that comparable device performance can be achieved using PECVD, sputtering, or evaporation processes for WOx; however, in some embodiments, PECVD might be preferred due to its ability to provide enhanced control over material properties through a greater number of adjustable process parameters.

[0152] Referring to Fig. 17B, the present invention provides an alternative method for preparing a WOx-based HSC (e.g., i-aSi/WOx/TCO HSC 13a). This method comprises the same steps as the previous preparation method, but with a modification: in this embodiment, at least one i-aSi layer is deposited using an modified PECVD method, alongside other i-aSi layers deposited with a conventional PECVD process. For instance, when depositing multiple i-aSi layers, the modified PECVD method is

specifically applied to deposit the i-aSi layer in contact with the WOx layer, while the remaining layers are not restricted to specific deposition methods. The Step S101 thus comprises:

[0153] S1011 : Depositing at least one i-aSi layer using a conventional PECVD method.

[0154] S1012: Depositing at least one modified i-aSi layer using the modified PECVD method.

[0155] The thin-film deposition process starts with the i-aSi layer(s), followed by the deposition of WOx layer(s) and then the lateral transport layers. The i-aSi layer(s) are deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0156] Referring to Fig. 17F, specific PECVD parameters are provided for the deposition of the i-aSi layer that is in direct contact with the WOx layer, although their use is optional. A set of parameters for the PECVD method is summarized in Table 3.

[0157] Table 3:

[0158] For all other i-aSi layers not in contact with the overlying WOx, the deposition parameters are not required to be restricted in the present invention.

[0159] The present invention provides an alternative method for preparing a WOx- based HSC (e g., i-aSi/WOx/TCO HSC 13a). This method comprises the same steps as any of the previously described preparation methods, with one difference: in this

embodiment, at least one WOx layer is deposited using an modified PECVD method, in addition to other WOx layers deposited with a conventional PECVD process. For instance, when depositing multiple WOx layers, the modified PECVD method is used specifically for the WOx layer that contacts the i-aSi layer (and/or the LT layer), whether it is the inner or outer layer, while other layers might not be restricted in deposition method.

[0160] Referring to Fig. 17C, when the modified PECVD method is used to deposit the WOx layer in contact with the LT layer, step S201 specifically comprises:

[0161] S2011 : Depositing at least one WOx layer using a conventional PECVD method.

[0162] S2012: Depositing at least one modified WOx layer using the modified PECVD method.

[0163] Referring to [Fig. 17D], when the modified PECVD method is used to separately deposit the inner layer in contact with the i-aSi layer and the outer layer in contact with the LT layer, step S201 specifically comprises:

[0164] S2010: Depositing at least one modified WOx layer using the modified PECVD method.

[0165] S2011 : Depositing at least one WOx layer using a conventional PECVD method.

[0166] S2012: Depositing at least one improved WOx layer using the modified PECVD method.

[0167] Additionally, when the modified PECVD method is used specifically to deposit only the inner layer in contact with the i-aSi layer, step S201 comprises:

[0168] S2010: Depositing at least one improved WOx layer using the modified PECVD method.

[0169] S2011 : Depositing at least one WOx layer using a conventional PECVD method.

[0170] In other embodiments, when preparing an HSC without an LT layer, such as i- aSi/WOx HSC 13b, the method comprises steps S101 and S201. Here, the difference is that, without the LT layer, the WOx layer will be in direct contact with the electrode 600. Therefore, during the deposition of at least one WOx layer, the modified PECVD method can be used to deposit the outer layer specifically in the area where it contacts the electrode.

[0171] Similarly, in other embodiments, when preparing an HSC without an i-aSi layer, such as a WOx/TCO HSC 13c, the method comprises steps S201 and S301. The difference here is that, without the i-aSi layer, the WOx layer will be in direct contact with the silicon wafer substrate 11 (e.g., monocrystalline silicon substrate 11a or polycrystalline silicon substrate 11 b). Therefore, during the deposition of at least one WOx layer, the modified PECVD method is first used to deposit at least one WOx layer on the silicon wafer substrate 11 , followed by other PECVD methods to deposit the remaining WOx layers. If only a single WOx layer is needed, this layer is deposited directly using the modified PECVD method. Alternatively, the remaining WOx layers may also be deposited directly using the modified PECVD method.

[0172] Similarly, in other embodiments, when preparing an HSC comprising solely of WOx layers (i.e., a WOx-only HSC 13d), at least one WOx layer is directly deposited using step S201 . Furthermore, since there is no i-aSi layer or LT layer, at least two WOx layers are deposited, with the inner layer in contact with the silicon wafer substrate 11 and the outer layer in contact with the electrode, both deposited using the modified PECVD method.

[0173] In the conventional arts, the throughput of the HSC formation sequence for a solar cell in general may depend on (1 ) the number of layers to be deposited and (2) the deposition rate of each layer. Conventional HSCs in solar cells typically comprise a 2-10 nm thick i-aSi layer deposited by PECVD (0.1 -1 nm/s deposition rate), followed by a 2- 10 nm thick p-aSi layer also deposited by PECVD (0.5 nm/s deposition rate), and then a 60-100 nm thick TCO layer deposited by sputtering. In other words, the performance and production costs of solar cell hole-selective contacts (HSCs) are influenced by the number of layers and the deposition rate of each layer. Conventional HSCs in silicon heterojunction (SHJ) solar cells typically comprise a multi-layer stack comprising a PECVD-deposited intrinsic amorphous silicon (i-aSi) layer, a p-type doped amorphous

silicon (p-aSi) layer, and a sputtered transparent conductive oxide (TCO) layer. This layered approach requires both PECVD and sputtering processes, resulting in lengthy processing times, high operational expenses (opex), and significant capital expenses (capex) due to the need for multiple deposition methods and layers.

[0174] In contrast, the present invention demonstrates various WOx-based HSC configurations with significantly reduced processing time. In one approach, the HSC comprises solely of WOx layers with a total thickness of 60-100 nm, all deposited in a single machine using PECVD (0.1 -0.5 nm/s deposition rate). This method allows for substantial reductions in both capex and opex. In other configurations, WOx replaces one or two layers in the HSC stack, resulting in further cost savings.

[0175] Furthermore, existing SHJ solar cells use an HSC structure that comprises an intrinsic amorphous silicon (i-aSi) layer and a p-type, boron-doped amorphous silicon (p-aSi) layer. p-aSi, with its optical bandgap of less than 2 eV, exhibits high parasitic absorption in the 250-400 nm range of the solar spectrum. Moreover, as a lower-density amorphous material, p-aSi is more vulnerable to ion bombardment damage from the sputtering processes commonly used to deposit transparent conductive oxides (TCOs) in later stages of solar cell fabrication. This ion bombardment can reduce the pseudo-fill factor (pFF) and fill factor (FF) of the solar cell. Combined, these effects, lower Jsc and pFF, lead to decreased solar cell efficiency.

[0176] In contrast, the present invention replaces the p-aSi-based HSC with a tungsten oxide (WOx)-based HSC. As a transition metal oxide (TMO) with an optical bandgap greater than 2 eV and a higher density than a-Si, WOx has a lower extinction coefficient (k) in the 300-600 nm wavelength range and is less susceptible to ion bombardment damage than p-aSi. Consequently, WOx-based HSCs achieve higher Jsc and pFF, leading to improved solar cell efficiency.

[0177] To demonstrate the technical effects and advantages of replacing the p-aSi layer with a WOx layer, the experiments were conducted comparing i-aSi/WOx/TCO HSC 13a with i-aSi/p-aSi/TCO HSC, the results of which are summarized in Fig. 18 - Fig. 20. Specifically:

[0178] Referring to Fig. 18, in the wavelength range of 300-600 nm, WOx in the present invention helps achieve a lower extinction coefficient (k) compared to p-aSi.

[0179] Referring to Fig. 19, compared to HJ solar cells with p-aSi-based HSCs, the HJ solar cells with WOx-based HSCs in this invention show a 5% increase in short- circuit current (Jsc).

[0180] Referring to Fig. 20, compared to HJ solar cells with p-aSi-based HSCs, the HJ solar cells with WOx-based HSCs in this invention show a 4.8% increase in pseudo fill factor (pFF).

[0181] Other transition metal oxides (TMOs), such as molybdenum oxide (MoOx) and nickel oxide (NiOx), are also known to form functional HSCs. The suitability of TMOs for use as an HSC in solar cells depends on factors such as: (1) whether the material can withstand the additional thermal load from subsequent fabrication steps, such as paste curing (typically over 200 °C), soldering (typically over 200 °C), and encapsulation (typically 150 °C), without degradation; and (2) whether the HSC achieves performance comparable to or better than traditional p-aSi-based HSCs.

[0182] MoOx-based HSCs are known to degrade at temperatures above 150 °C, making them unsuitable for commercial solar cells. NiOx-based HSCs are thermally stable but perform poorly compared to p-aSi-based HSCs. The present invention utilizes a WOx-based HSC, which is both thermally stable and performs comparably to p-aSi- based HSCs. As a result, WOx-based HSCs appear to be a suitable option for commercial solar cell production among various TMOs.

[0183] Referring to Fig. 21 , the experimental results show that WOx-based HSCs help achieve low series resistance (i.e., Rs) and accordingly FF loss due to Rs, when comparing with VOx and MoOx.

[0184] Referring to Fig. 22, compared to other transition metal oxides (TMOs), solar cells with WOx-based HSCs exhibit higher thermal stability, with no drop in efficiency even at 200°C.

[0185] As to the aspect of manufacturing and fabrication process, in the conventional arts, chemical vapor deposition (CVD) involves gaseous precursors that react in a vacuum chamber to form a film directly on the substrate. The deposition rate can be enhanced by igniting a plasma (PECVD). The PECVD process has a high utilization rate of gas precursors, which helps to lower the operational costs (opex) of CVD

processes. In contrast, Physical Vapor Deposition (PVD) methods involve transferring material from a solid source to the substrate via vapor. However, the area ratio of the substrate to the total deposition area is lower in PVD than in CVD, resulting in lower source utilization (i.e., the amount of material deposited on the substrate compared to the amount consumed from the source), which increases the opex of PVD processes. High-performance transition metal oxides (TMOs), such as WOx, are typically deposited using PVD techniques, including thermal evaporation, electron-beam evaporation, or magnetron sputtering. However, PVD-based processes for high-performance TMOs like WOx have higher operational costs and require the purchase of dedicated PVD equipment for mass production.

[0186] In contrast, the present invention utilizes a WOx-based HSC in which the WOx layer(s) are deposited using PECVD, achieving comparable or even superior performance to WOx deposited via PVD. This approach enables a higher deposition rate and greater source utilization without sacrificing performance. As a result, PECVD- deposited WOx-based HSCs are more compatible and cost-effective for commercial solar cell production than other deposition methods.

[0187] Referring to [Fig. 23], the efficiency of solar cells with WOx-based HSCs deposited by the PECVD method in this invention is higher than that of solar cells with WOx-based HSCs prepared by sputtering and evaporation methods.

[0188] Summary of the Technical Advantages

[0189] In current silicon heterojunction (SHJ) solar cells, one type of hole-selective contact (HSC) uses intrinsic amorphous silicon (i-aSi) combined with p-type doped amorphous silicon (p-aSi), while another type is based on transition metal oxides (TMOs). Since p-aSi has an optical bandgap of less than 2 eV, solar cells with HSCs based on p-aSi exhibit relatively lower short-circuit current density (Jsc) and pseudo fill factor (pFF), leading to reduced solar cell efficiency.

[0190] However, the use of TMOs in solar cells also requires careful consideration of several factors. Specifically, two aspects need to be evaluated: (1 ) whether the material can withstand the additional thermal load from subsequent fabrication steps, such as

paste curing (typically over 200 °C), soldering (typically over 200 °C), and encapsulation (typically 150 °C); and (2) whether the HSC offers performance comparable to or better than that of traditional p-aSi-based HSCs. In other words, the thermal stability of the HSC needs to be considered, as further processing steps that reach or exceed 200 °C may be required to complete the device after the HSC is formed.

[0191] Among various TMOs, MoOx and NiOx are the most commonly used as hole transport layers in the conventional arts. However, in comparison with TMOs such as MoOx and VOx, the WOx-based HSC proposed in the present invention, either as a standalone hole-selective contact layer with specific thickness and layer count or in combination with an i-aSi layer and/or LT layer, each with defined thickness and layer configuration, demonstrates enhanced thermal stability (withstanding at least 200 °C, as shown in Figure 22), which in turn ensures higher performance in the final solar cell manufactured. Furthermore, the present invention suggests modifications to the WOx layer in contact with the substrate, i-aSi, or TL layer to reduce interface resistance between the contact layers, thereby further improving solar cell efficiency.

[0192] In summary, the present invention enhances solar cell performance compared to existing p-aSi HSC-based heterojunction solar cells by leveraging the improved transparency of WOx over p-aSi, resulting in higher short-circuit current density (Jsc), and better screening of sputtering damage, which improves open-circuit voltage (Voc) and pseudo fill factor (pFF). As a result, this technology enables solar cells and modules with comparable or even superior efficiency, producing high-performance solar panel products.

[0193] The WOx-based HSC developed in the present invention is thermally stable at temperatures exceeding 200 °C, allowing it to undergo screen-printing and curing at temperatures comparable to those used in current silicon heterojunction solar cells. Additionally, no modifications are necessary for other fabrication steps, such as screen printing, curing, soldering, or encapsulation, when producing solar panels with this technology.

[0194] By replacing the incumbent p-aSi, which is deposited via PECVD, with WOx also deposited via PECVD, the present invention allows existing PECVD equipment to be adapted for WOx deposition, eliminating the need for new machinery and lowering capital expenditure (capex) required for upgrades. Furthermore, the PECVD deposition time for WOx-based HSCs is shorter than for traditional p-aSi-based HSCs, which enhances process throughput and reduces operational costs (opex).

[0195] According to various embodiments, the present invention introduces additional concepts: (1) eliminating the need for intrinsic amorphous silicon (i-aSi) layers, and/or (2) removing the requirement for transparent conductive oxide (TCO) in the HSC of a heterojunction solar cell. By potentially removing up to two fabrication steps, PECVD for i-aSi and sputtering for TCO, this method of the present invention might help achieve reductions in production costs and complexity, especially in industrial-scale applications.

[0196] Also, the WOx layer in the present invention can be deposited using alternative low-cost methods such as thermal evaporation or sputtering, further decreasing capex and opex by substituting PECVD with more economical deposition techniques.

[0197] Furthermore, unlike PECVD p-aSi, which requires pyrophoric, flammable silane gas (SiH₄), WOx deposition uses tungsten hexafluoride (WF₆), a non-pyrophoric, non-flammable, and liquifiable gas. This change contributes to a safer manufacturing process by reducing the risks associated with gas handling.

[0198] It should be further appreciated by the person skilled in the art that variations and combinations of features described above, not being alternatives or substitutes, may be combined to form yet further embodiments falling within the intended scope of the invention.

[0199] As would be understood by a person skilled in the art, each embodiment, may be used in combination with other embodiment or several embodiments.

[0200] Abbreviation

[0201] Reference Numbers:

11 : silicon wafer substrate

11 a: Mono-crystalline Si-wafer

11 b: Multi-crystalline Si-wafer

110: n-type substrate

111 : p-type substrate

13: WOx-based HSC (WOx HSC)

13a: i-aSi/WOx/TCO HSC

13b: i-aSi/WOx HSC

13c: WOx/TCO HSC

13d: WOx only HSC

131 : i-aSi layer(s)

131a: Modified i-aSi layer

132: WOx layer(s)

132a: Modified WOx layer(s)

134: Top cell layers (i.e., additional layers from the top solar cell unit)

600: Electrode

100: ETL stack

: LT layer(s) : Contact terminals : electrode : other layer(s) a: TCO layer(s)

Claims

1. A WOx-based hole-selective contact layer, wherein ccomprising: at least one WOx layer with a thickness of 1-200 nm.

2. The WOx-based hole-selective contact layer according to claim 1 , wherein comprising at least two WOx layers; wherein the at least two WOx layers comprise an inner layer arranged to be in direct contact with a silicon wafer substrate, and an outer layer arranged to be in direct contact with an electrode; and, wherein the at least two WOx layers are configured to have a total thickness of 60-200 nm.

3. The WOx-based hole-selective contact layer according to claim 2, wherein comprising three WOx layers.

4. The WOx-based hole-selective contact layer according to claim 2 or 3, wherein the inner layer is treated to reduce a first interface resistance between the inner layer and the silicon wafer substrate to less than 1 Q-cm².

5. The WOx-based hole-selective contact layer according to claim 4, wherein the first interface resistance between the inner layer and the silicon wafer substrate is arranged to be less than 0.1 Q-cm².

6. The WOx-based hole-selective contact layer according to claim 2 or 3, wherein a local area of the outer layer that contacts the electrode is treated to reduce a second interface resistance between the local area and the electrode to less than 1 Q-cm².

7. The WOx-based hole-selective contact layer according to claim 6, wherein the second interface resistance between the local area and the electrode is less than 0.1 Clem².

8. The WOx-based hole-selective contact layer according to claim 2, wherein the inner layer is configured to have a thickness of 1-10 nm; and/or, the outer layer is configured to have a thickness of 20-600 nm.

9. The WOx-based hole-selective contact layer according to claim 1 , wherein, further comprising at least one i-aSi layer configured to be placed between an inner layer of the at least one WOx layer and a silicon wafer substrate; and the inner layer is configured to have a thickness of 1-10 nm.

10. The WOx-based hole-selective contact layer according to claim 9, wherein the at least one WOx layer is configured to have a total thickness of 40-200 nm.

11 . The WOx-based hole-selective contact layer according to claim 9, wherein, the at least one i-aSi layer, the inner layer of the at least one WOx layer, or both, are treated to achieve a third interface resistance between the at least one i-aSi layer and the inner layer of less than 1 Q-cm², or less than 0.1 Q-cm².

12. The WOx-based hole-selective contact layer according to claim 9, wherein, the at least one i-aSi layer is configured to have a total thickness less than or equal to 15 nm.

13. The WOx-based hole-selective contact layer according to claim 1 or 9, further comprising at least one LT layer configured to be placed on an outer layer of the at least one WOx layer; wherein the outer layer is farthest from a silicon wafer substrate.

14. The WOx-based hole-selective contact layer according to claim 13, wherein the outer layer is configured to have a thickness of 1-15 nm.

15. The WOx-based hole-selective contact layer according to claim 14, wherein, the outer layer is treated to achieve a fourth interface resistance between the outer layer and the at least one LT layer of less than 1 Q-cm², or less than 0.1 Q-cm².

16. The WOx-based hole-selective contact layer according to claim 13, wherein,

the inner layer of the at least one WOx layer arranged to be in contact with the silicon wafer substrate is configured to have a thickness of 1 -10 nm; and the inner layer is treated to achieve a first interface resistance between the inner layer and the silicon wafer substrate of less than 1 Q-cm², or less than 0.1 £l-cm².

17. The WOx-based hole-selective contact layer according to claim 14, wherein the inner layer of the at least one WOx layer and the outer layer of the at least one WOx layer are the same layer as a single layer of WOx layer.

18. The WOx-based hole-selective contact layer according to claim 13, wherein the LT layer is a TOO layer.

19. The WOx-based hole-selective contact layer according to claim 18, wherein the TOO layer is configured as a double layer.

20. A method for manufacturing WOx-based hole-selective contact layer, wherein the method comprises a step of:

S201 depositing at least one WOx layer on a silicon wafer substrate using a PECVD method based on a first set of deposition parameters, with the at least one WOx layer is configured to have a thickness of 1-200 nm; wherein the first set of deposition parameters comprises: a gas ratio of O₂ to WF₆ of 0-20; and, a gas ratio of H₂ to WF₆ of 0-50.

21 . The method for manufacturing WOx-based hole-selective contact layer according to claim 20, wherein, the first set of deposition parameters further comprises: a gas ratio of PH₃ to WF₆ of 0-10; a gas ratio of B₂H₆ to WF₆ of 0-10; and/or, a gas ratio of N₂ to WF₆ of 0-10.

22. The method for manufacturing WOx-based hole-selective contact layer according to claim 20, wherein, the first set of deposition parameters further comprises:

the gas ratio of O₂ to WF₆ is 1-5; and, the gas ratio of H₂ to WF₆ is 0-5.

23. The method for manufacturing WOx-based hole-selective contact layer according to claim 21 , wherein, the first set of deposition parameters comprises: the gas ratio of PH₃ to WF₆ is 0-5; the gas ratio of B₂H₆ to WF₆ is 0-5; and/or, the gas ratio of N₂ to WF₆ is 0-3.

24. The method for manufacturing WOx-based hole-selective contact layer according to claim 22, wherein, the at least one WOx layer comprises an inner layer arranged to be in direct contact with a silicon wafer substrate; and, wherein the inner layer is configured to have a thickness of 1 -10 nm.

25. The method for manufacturing WOx-based hole-selective contact layer according to claim 22, prior to the step of S201 , further comprising a step of:

S101 , depositing at least one i-aSi layer on the silicon wafer substrate using the PECVD method so that in the step of S201 , the at least one WOx layer is placed on the at least i-aSi layer.

26. The method for manufacturing WOx-based hole-selective contact layer according to any one of claims 20 to 25, prior to the step of S201 , further comprising a step of:

S1012, depositing at least one modified i-aSi layer on the substrate using the PECVD method based on a second set of deposition parameters; wherein the second set of deposition parameters comprises: a gas ratio of H2 to SiFU is 0-50; or 20-35.

27. The method for manufacturing WOx-based hole-selective contact layer according to claim 26, wherein the at least one modified i-aSi layer is configured to have a thickness of 4-50nm or 5-20 nm.

28. The method for manufacturing WOx-based hole-selective contact layer according to claim 25, wherein the at least one WOx layer is configured to have a thickness of 4-100 nm.

29. The method for manufacturing WOx-based hole-selective contact layer according to claim 28, wherein the at least one WOx layer is configured to have a thickness of 5-40 nm.

30. The method for manufacturing WOx-based hole-selective contact layer according to claim 20, 25, or 26, after the step of S201 , further comprising a step of:

S301 , depositing at least one LT layer on the at least one WOx layer.

31 . A solar cell, comprising: a silicon wafer substrate that comprises a top side and a rear side; and, a hole-selective contact layer placed on either the top side or the rear side; wherein the hole-selective contact layer is a WOx-based hole-selective contact layer according to any one of claims 1 to 19.

32. The solar cell according to claim 31 , wherein, the silicon wafer substrate is a monocrystalline silicon wafer substrate, multicrystalline silicon wafer substrate, an N-type silicon wafer substrate, or a P-type silicon wafer substrate.

33. The solar cell according to claim 31 , wherein, the solar cell is a tandem solar cell, comprising a first solar cell unit located below and a second solar cell unit located above, wherein the WOx-based hole-selective contact layer and the second solar cell unit are configured to be on the same side of the first solar cell unit; or, the WOx-based hole-selective contact layer and the second solar cell are arranged to be located on opposite sides of the first solar cell unit.