[go: up one dir, main page]

WO2025104772A1 - Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar - Google Patents

Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar Download PDF

Info

Publication number
WO2025104772A1
WO2025104772A1 PCT/JP2023/040703 JP2023040703W WO2025104772A1 WO 2025104772 A1 WO2025104772 A1 WO 2025104772A1 JP 2023040703 W JP2023040703 W JP 2023040703W WO 2025104772 A1 WO2025104772 A1 WO 2025104772A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
type
receiving element
semiconductor light
inalas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2023/040703
Other languages
English (en)
Japanese (ja)
Inventor
栄太郎 石村
晴央 山口
亮太 竹村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2023/040703 priority Critical patent/WO2025104772A1/fr
Priority to JP2024514404A priority patent/JP7511793B1/ja
Publication of WO2025104772A1 publication Critical patent/WO2025104772A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Definitions

  • This disclosure relates to semiconductor photodetectors, optical line termination devices, multilevel intensity modulation transceivers, digital coherent receivers, radio-over-fiber systems, SPAD sensor systems, and lidar devices.
  • PD photodiodes
  • APD avalanche photodiodes
  • the Passive Optical Network In the access network that connects optical communication subscribers, the Passive Optical Network (PON) is the main system used. PON systems started with the G(E)-PON system that transmits signals of 1 to 2 Gbps, and in the future, 10G-EPON systems and XG-PON systems that transmit signals of 10 Gbps are expected to increase. Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is considering the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50 Gbps-class transmission will also be put into practical use in access networks in the future.
  • ITU-T International Telecommunication Union Telecommunication Standardization Sector
  • APDs which are semiconductor light receiving elements used in PON systems, have an element structure consisting of a light absorption layer (InGaAs), an electric field relaxation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs).
  • a high electric field of about 800 kV/cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer.
  • the electric field relaxation layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer.
  • the ionization rate of electrons is expressed as ⁇
  • the ionization rate of holes as ⁇ .
  • the greater the ratio of the ionization rates of electrons and holes the smaller the excess noise generated during multiplication and the higher the receiving sensitivity. Furthermore, the greater the ratio of the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider bandwidth.
  • k ⁇ / ⁇ .
  • Compound semiconductor materials such as InAlAs or InP are used for the multiplication layer of APDs for optical communications.
  • InAlAs is selected as the material for the multiplication layer, the difference in the ionization rates of electrons and holes will be greater than in InP. Note that in InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is approximately twice that of electrons. On the other hand, if InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is approximately five times that of holes. Therefore, since the reception sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.
  • APDs which are semiconductor light receiving elements, are required to have a wide response bandwidth and high receiving sensitivity.
  • APDs have a problem in that the time required for multiplication, that is, the multiplication time, becomes longer as the multiplication factor increases, resulting in a decrease in bandwidth at high multiplication factors.
  • APDs with a multiplication layer made of InAlAs, which is used in optical communications have a wider bandwidth than APDs made of other semiconductor materials, but when the multiplication factor is 6 or more, the bandwidth remains at about 20 GHz. In other words, there is a problem in that the bandwidth of 37.5 GHz or more required for 50G-PON systems is difficult to achieve when conventional APDs are used.
  • Patent Document 1 describes an APD that uses a superlattice, but the superlattice is applied to the multiplication layer and electric field relaxation layer, not the electron transport layer, and furthermore, the thickness of each layer is 5 nm to 10 nm, so it acts as a quantum well that reflects the band gap of each layer. If the thickness of each layer in the stack exceeds a few nm, energy unevenness that reflects the band gap of each layer is created, which impedes the transport of carriers and reduces the transport speed.
  • the response bands of the semiconductor light-emitting elements and semiconductor light-receiving elements, the optical output of the semiconductor light-emitting elements, and the receiving sensitivity of the semiconductor light-receiving elements are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the subscriber's side.
  • DSP digital signal processor
  • the Optical Line Terminal i.e. the receiving device on the central office side
  • SOA Semiconductor Optical Amplifier
  • EML electro-absorption modulated laser diode
  • DSPs and SOAs consume very large amounts of power, which is a factor in increasing costs, and it is feared that the replacement of existing PON systems with 50G-PON systems will not progress.
  • transceivers are designed that incorporate expensive and power-hungry DSPs and SOAs into the ONU and OLT, but this creates problems such as increased power consumption and costs.
  • This disclosure has been made to solve the problems described above, and aims to provide a semiconductor light-receiving element that operates over a wide bandwidth.
  • the semiconductor light receiving element comprises: An InP substrate; an n-type semiconductor layer formed on the InP substrate; an electron transit layer formed on the n-type semiconductor layer and having a digital alloy structure; an n-type electric field relaxation layer formed on the electron transit layer; a multiplication layer formed on the n-type electric field buffer layer; a p-type electric field buffer layer formed on the multiplication layer; a light absorbing layer formed on the p-type electric field buffer layer.
  • the optical line terminal comprises: The semiconductor light receiving element described above, an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal; A forward error correction circuit is connected to the clock data recovery circuit and corrects an error in the clock data.
  • a multi-level intensity modulation transmitting/receiving device includes: The semiconductor light receiving element described above for receiving an optical signal intensity-modulated into multiple values; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal; A digital signal processing circuit is connected to the analog/digital conversion circuit and processes the digital signal.
  • the radio-over-fiber system comprises: a light source that emits an analog modulated optical signal; The semiconductor light receiving element described above for receiving the analog-modulated optical signal; a transmission path for transmitting an analog electrical signal output from the semiconductor light receiving element to an antenna; and an antenna connected to the transmission line for emitting the analog electrical signal as a radio wave signal.
  • a digital coherent receiving device includes: The semiconductor light receiving element described above, a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal; a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter; and a digital signal processing circuit connected to the 90-degree hybrid device for processing a digital signal.
  • the SPAD (Single Photon Avalanche Diode) sensor system comprises: A SPAD sensor constituted by the semiconductor light receiving element described above; a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor; and an optoelectronic measurement circuit that measures the electrical signal output from the SPAD sensor.
  • the LIDAR device comprises: A light source that emits light in a pulsed manner; the semiconductor light receiving element described above for receiving light emitted from the light source and reflected by an object; an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element; and a distance measuring circuit that calculates a distance based on the electrical signal amplified by the amplifier circuit.
  • At least the electron transport layer is configured with a digital alloy structure, which has the effect of providing a semiconductor light receiving element that operates over a wide bandwidth.
  • optical line termination device multilevel intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device disclosed herein use the semiconductor light receiving element disclosed herein as the semiconductor light receiving element, and therefore have the effect of providing devices and systems with excellent performance.
  • FIG. 1 is a cross-sectional view showing an element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a first embodiment.
  • 1 is a cross-sectional view showing an element structure of an edge-illuminated PD, which is an example of a semiconductor light-receiving element according to a first embodiment.
  • FIG. 2 is a diagram showing the relationship between the lattice constant of each constituent material and the amount of strain based on InP.
  • 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment.
  • FIG. 11 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment.
  • FIG. FIG. 13 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer.
  • 7A to 7C are diagrams showing the ionization rates of electrons and holes.
  • FIG. 13 is a graph showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer.
  • 9A to 9D are diagrams showing the ionization rates in the multiplication layer and the electric field relaxation layer, with FIG. 9A showing the ionization rate in the case of a random alloy structure multiplication layer, FIG.
  • FIG. 9B showing the ionization rate in the case of a digital alloy structure multiplication layer
  • FIG. 9C showing the ionization rate in the case of a partially disordered digital alloy structure multiplication layer
  • FIG. 9D showing the ionization rate in the case of a combination of a thick electric field relaxation layer and a digital alloy structure multiplication layer.
  • 11 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a third embodiment.
  • 11 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a third embodiment.
  • 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth embodiment.
  • 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth embodiment.
  • 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fifth embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a sixth embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a seventh embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a seventh embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment.
  • FIG. 13 is a cross
  • FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a ninth embodiment.
  • FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a tenth embodiment.
  • FIG. 12 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to an eleventh embodiment.
  • FIG. 23 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a twelfth embodiment.
  • FIG. 23 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a thirteenth embodiment.
  • FIG. A configuration diagram showing an optical line terminal (OLT) of a 50G-PON system relating to embodiment 14.
  • FIG. 1 is a configuration diagram showing an optical line terminal (OLT) of a 50G-PON system as a comparative example.
  • FIG. 23 is a diagram illustrating the configuration of a multilevel intensity modulation transmitting/receiving device according to a fifteenth embodiment.
  • 31A and 31B are diagrams showing received waveforms of a multi-level intensity modulation transmitting/receiving device according to embodiment 15.
  • 32A and 32B are diagrams for explaining the operation of a PD when a high optical input is applied.
  • FIG. 1 is a diagram illustrating the operation of an APD when a high optical input is applied.
  • FIG. 23 is a diagram illustrating a configuration of a radio-on-fiber system according to a sixteenth embodiment of the present invention.
  • FIG. 1 illustrates a configuration of a radio-on-fiber system as a comparative example.
  • FIG. 38A is a diagram showing waveforms of a digital coherent receiving device which is a comparative example
  • FIG. 38B is a diagram showing waveforms of a digital coherent receiving device according to embodiment 17.
  • FIG. 23 is a diagram showing the configuration of a SAPD sensor system according to an eighteenth embodiment.
  • FIG. 40A is a diagram showing the multiplication characteristics of a SAPD sensor system which is a comparative example
  • FIG. 40B is a diagram showing the multiplication characteristics of a SAPD sensor system according to embodiment 18.
  • FIG. 13 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each multiplication layer configuration.
  • FIG. 43A is a diagram showing a received waveform of an APD of a LIDAR device which is a comparative example
  • FIG. 43B is a diagram showing a received waveform of an APD of a LIDAR device according to embodiment 19.
  • Embodiment 1 ⁇ Features of the semiconductor photodetector (PD) according to the first embodiment>
  • a digital alloy structure electron transit layer which is a structural feature of the semiconductor light receiving element according to the first embodiment, will be described below.
  • the semiconductor light receiving element according to the first embodiment is a PD, but both will be described together, including an APD, which is a semiconductor light receiving element described in the second embodiment and thereafter.
  • fc_PD The 3 dB bandwidth fc_PD of a PD is given by the following equation (1), where frc is the bandwidth limitation due to the RC time constant, and ftr is the bandwidth limited by the time it takes for carriers to travel through the depletion layer.
  • fc_PD 1/((1/frc) 2 +(1/ftr) 2 ) 0.5 (1)
  • Vav is the average saturated transit velocity of electrons and holes
  • Wt is the total thickness of the depletion layer.
  • the traveling speed of electrons and holes is proportional to the electric field, but when an electric field of several tens of kV/cm or more is applied to the electrons and holes, they reach a saturation speed and become constant.
  • the time it takes for the electrons and holes to pass through the depletion layer can be shortened by increasing the travel speed of the electrons and holes.
  • the electron speed Ve is greater than the hole speed Vh.
  • the electrons can travel 1350 nm in the time it takes the holes to travel 1000 nm, even if a 350 nm electron travel layer (only electrons travel because it is on the n side) is provided on the n side of the light absorption layer of the PD, the time it takes for the electrons and holes to travel through the depletion layer does not increase.
  • the thickness W of the depletion layer is increased by the thickness of the electron transport layer, i.e., 350 nm, so the RC time constant decreases, and as a result, a wider bandwidth of the PD can be achieved.
  • This is the role of the electron transport layer.
  • an electron transport layer referred to as a carrier collection layer in Non-Patent Document 1
  • it is possible to increase the speed as well as to pass a large photocurrent.
  • the electron transit layer is effective in broadening the bandwidth of semiconductor light receiving elements, and if the transit speed of electrons and holes in the electron transit layer can be further increased, it will be possible to achieve even wider bandwidths for PDs and APDs.
  • FIG. 6 shows the dead space of an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer. Figure 6 will be described in detail later.
  • De the electron dead space length in the case of an InAlAs random alloy structure.
  • De is approximately 40 nm, as shown in Figure 6. It was found that in the case of an InAlAs digital alloy structure, De is approximately 80 nm, compared to the InAlAs random alloy structure.
  • the ionization rate ratio k of electrons and holes drops sharply due to the dead space effect when the multiplication layer is made thinner.
  • the reason for the drop in the ionization rate ratio k is thought to be that, if the dead space length for holes is Dh, then the multiplication layer thickness becomes thinner than Dh, and holes cannot be multiplied.
  • Dh is about 80 nm
  • Dh is about 170 nm.
  • Non-Patent Document 3 reports that the effective carrier speed in a multiplication layer with a layer thickness of 200 nm increases by 169%. This is because the effect of the dead space in the 200 nm layer thickness becomes large when the layer thickness is about 200 nm. In other words, the traveling speed increases as the dead space increases. Therefore, by using an InAlAs digital alloy structure with a longer dead space for the electron travel layer instead of the conventional InAlAs random alloy structure, the traveling speed in the electron travel layer increases, and the time it takes to travel in the depletion layer can be shortened.
  • the travel speed of holes can be increased, it is possible to introduce a hole travel layer.
  • the travel speed in the hole travel layer can be increased, and the time it takes to travel in the depletion layer can be shortened.
  • Fig. 1 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of a semiconductor light-receiving element 100 according to the first embodiment.
  • Fig. 2 is a cross-sectional view showing the element structure of an edge-illuminated PD which is an example of a semiconductor light-receiving element 100a according to the first embodiment.
  • the front-illuminated PD which is an example of the semiconductor light-receiving element 100 according to the first embodiment, includes an n-type InP substrate 1, an n-type InP buffer layer 2 having a carrier concentration of 1 to 5 ⁇ 10 18 cm -3 and a layer thickness of 0.1 to 1.0 ⁇ m, which are successively formed on the n-type InP substrate 1, an InAlAs electron transit layer 3 having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) having a carrier concentration of 1 ⁇ 10 17 cm -3 or less and a layer thickness of 50 nm to 1000 nm are alternately laminated a plurality of times (hereinafter referred to as an i-type InAlAs digital alloy structure electron transit layer 3), an i-type InAlGa
  • i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5 ⁇ 10 17 cm -3 or less and a layer thickness of 5 to 50 nm
  • p-type InP window layer 7 having a carrier concentration of 5 ⁇ 10 17 cm -3 or more and a layer thickness of 0.1 to 3.0 ⁇ m
  • p-type InGaAs contact layer 8 an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1; and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.
  • a p-type InP window layer may be used instead of the p-type InP window layer 7.
  • the n-type InP buffer layer 2 is also called an n-type semiconductor layer.
  • the semiconductor light receiving element 110 has a layer structure similar to that of the semiconductor light receiving element 100, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface on which the incident light 90 is incident.
  • Silicon (Si) is optimal as the n-type dopant for the n-type InP buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InP buffer layer 2 into the i-type InAlAs digital alloy structure electron transit layer 3, causing the digital alloy structure to become disordered.
  • disordering refers to the phenomenon in which the compositions of the layers in the digital alloy structure mix together, resulting in a random alloy structure with an average composition.
  • the i-type InAlAs digital alloy structure electron transit layer 3 is composed of semiconductor layers in which AlAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order.
  • the layer thicknesses of the AlAs layers and InAs layers are each in the range of 2 atomic layers to 6 atomic layers.
  • the reason for 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layers and InAs layers not to function as a quantum well structure.
  • the digital alloy structure has two types of semiconductor layers, each made of a different semiconductor material, alternately stacked in a period of 2 atomic layers to 6 atomic layers.
  • the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal.
  • the reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.
  • a layer thickness of 4 to 6 atomic layers is also preferable, which reduces the number of shutter switching times during crystal growth by molecular beam epitaxy (MBE).
  • the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably in the range of 2 to 6 atomic layer periods.
  • the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is within the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is 500 nm, the AlAs layer (2 atomic layers)/InAs layer (2 atomic layers) repetition is 417 times. As shown in FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is most preferably in the range of 50 nm to 200 nm.
  • the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even in the layer thickness range of 50 nm to 400 nm.
  • the i-type InAlAs digital alloy structure electron transit layer 3 may be laminated by alternately forming InAs layers and AlAs layers in that order.
  • the conductivity type of the InAlAs digital alloy electron transport layer is, for example, i-type, and the carrier concentration is, for example, 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the conductivity type of the InAlAs digital alloy electron transport layer may be p-type or n-type, and the carrier concentration is, for example, 5 ⁇ 10 17 cm ⁇ 3 or less.
  • an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness 2-6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness 2-6 atomic layers, Al composition ratio Z) are alternately laminated, as shown in Figure 3, which shows the relationship between the lattice constant of each constituent material and the amount of strain based on InP, can also be used as the electron transit layer of the present disclosure.
  • a digital alloy structure made of InAlAsSb, a material system to which antimony (Sb) has been added can also be used as the electron transit layer of the present disclosure.
  • the i-type InAlGaAs graded layer 4 and the i-type InAlGaAs/InAlAs graded layer 6 are layers in which the band gap is gradually changed by changing the composition of InAlGaAs, and each layer thickness is within the range of 5 to 50 nm.
  • the composition of InAlGaAs may be changed stepwise, and the band gap is intermediate between that of an InP layer and an InGaAs layer.
  • the carrier concentration is 5 ⁇ 10 17 cm -3 or less, and if the carrier concentration is low, it may be p-type or n-type.
  • the i-type InAlGaAs graded layer 4 and the i-type InAlGaAs/InAlAs graded layer 6 are not necessarily required and may be omitted.
  • two types of i-type InAlGaAs layers with different compositions are alternately stacked multiple times on an i-type InGaAs light absorption layer 5 to form an i-type InAlGaAs/InAlAs graded layer 6.
  • a front-illuminated PD which is an example of the semiconductor light-receiving element 100 according to the first embodiment, can be realized by using metal organic vapor phase epitaxy (MOVPE) or MBE on an n-type InP substrate 1.
  • MOVPE metal organic vapor phase epitaxy
  • a method for manufacturing the semiconductor light-receiving element 100 according to the first embodiment will be described below.
  • An n-type InP buffer layer 2 having a thickness of 0.1 to 1 ⁇ m and a carrier concentration of 1 to 5 ⁇ 10 18 cm ⁇ 3 is crystal-grown on an n-type InP substrate 1 by MOVPE or MBE.
  • An i-type InAlAs digital alloy structure electron transit layer 3 having a carrier concentration of 1 ⁇ 10 17 cm -3 or less and a layer thickness of 50 nm to 1000 nm is crystal-grown on the n-type InP buffer layer 2. That is, an AlAs layer (having a layer thickness of two atomic layers, approximately 0.6 nm) and an InAs layer (having a layer thickness of two atomic layers, approximately 0.6 nm) are crystal-grown alternately in this order from above the n-type InP buffer layer 2, thereby forming the i-type InAlAs digital alloy structure electron transit layer 3.
  • the i-type InAlGaAs graded layer 4 having a thickness of 5 nm to 50 nm and a carrier concentration of 5 ⁇ 10 17 cm ⁇ 3 or less is crystal-grown.
  • an i-type InGaAs light absorption layer 5 having a thickness of 50 nm to 3 ⁇ m, an i-type InAlGaAs/InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 ⁇ m to 3 ⁇ m, and a p-type InGaAs contact layer 8 are successively grown by crystal growth.
  • a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back surface of the n-type InP substrate 1.
  • the p-type electrode 32 of the PD is made of metal materials such as Ti and Au. Note that a voltage is applied to the PD in the reverse direction, and the operating voltage is 0V to 10V.
  • incident light 90 is incident perpendicularly to the i-type InGaAs light absorption layer 5.
  • the diameter of the PD's light receiving part when it is circular, or the size of the long side when it is rectangular, is within the range of 5 ⁇ m to 1 mm.
  • the incident surface of the PD is coated with an anti-reflective coating (not shown).
  • incident light 90 is incident from a direction parallel to the i-type InGaAs light absorption layer 5.
  • the end face is covered with an insulating film, an organic film, or a semiconductor layer.
  • an Fe-doped semi-insulating InP buried layer 20 is formed on the end face.
  • the layer thickness of the Fe-doped semi-insulating InP buried layer 20 is in the range of 100 nm to 5 ⁇ m in the incident direction.
  • the bandwidth of the PD is affected by both the bandwidth frc due to the capacitance and the bandwidth ftr due to the carrier transit time, so part of the bandwidth improvement effect due to the reduction in the pn junction capacitance is offset.
  • a PD having an InAlAs digital alloy structure electron transit layer according to the present disclosure will be referred to as the DA-PD of the present disclosure.
  • the semiconductor light receiving element according to the first embodiment has an i-type InAlAs digital alloy structure electron transit layer, which provides an effect of providing a semiconductor light receiving element that operates over a wide band.
  • Embodiment 2 ⁇ Features of the semiconductor photodetector (APD) according to the second embodiment>
  • APD semiconductor photodetector
  • a next-generation high-speed PON system can be realized without using a DSP or an SOA.
  • the response bandwidth is as follows: (1) RC time constant (R is the element resistance, C is the element capacitance) (2) Carrier transit time (the time it takes for an electron or hole to travel through the depletion layer)
  • Multiplication time TM Multiplication rate M/GB product (6)
  • GB product 1/(2 ⁇ Nk ⁇ av) (7)
  • Multiplication time TM 2 ⁇ NkM ⁇ av (8) It becomes.
  • GB product is the product of the multiplication factor and the bandwidth
  • k is the ionization rate ratio
  • N is a coefficient that is loosely dependent on the ionization rate ratio k
  • ⁇ av is the average time it takes for electrons and holes to travel through the multiplication layer. Therefore, by reducing the ionization rate ratio k, it is possible to shorten the multiplication time TM. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, in other words, to make the ionization rate ratio k approach zero.
  • Non-Patent Document 2 In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. In addition, in order to reduce the ionization rate ratio k, a digital alloy structure has been proposed in which semiconductor layers of different compositions are alternately stacked in a cycle of 1 to 6 atomic layers. However, even with the digital alloy structure, it is difficult to make the ionization rate ratio k zero unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 2.
  • the inventors therefore fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer in which two-atom InAs layers and two-atom AlAs layers are alternately stacked in order to reduce the ionization rate ratio k of the digital alloy structure.
  • a multiplication layer made of normal InAlAs made of bulk crystal, that is, an InAlAs random alloy structure multiplication layer.
  • the distance that carriers travel in the multiplication layer until they are ionized is called the dead space.
  • the length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, so in the case of an InAlAs random alloy structure made of a normal bulk crystal, if the thickness of the multiplication layer is thinned to a level of several tens of nm, the ionization rate ratio k decreases because the holes cannot be ionized.
  • the thickness of the multiplication layer is thinned to a level of several tens of nm, a new problem occurs in that leakage currents such as tunnel currents increase because a higher electric field must be applied to the multiplication layer to obtain the desired multiplication rate. In other words, an increase in the tunnel current increases the noise generated by the APD.
  • the thinning of the multiplication layer of an APD having a digital alloy structure has a greater effect of reducing the ionization rate ratio k than the thinning of the multiplication layer of an APD made of conventional materials.
  • Fig. 4 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 110 according to the second embodiment.
  • Fig. 5 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of the semiconductor light receiving element 110a according to the second embodiment.
  • the semiconductor light receiving element 110 includes an n-type InP substrate 1, an n-type InAlAs buffer layer 2a having a carrier concentration of 1 to 5 ⁇ 10 cm ⁇ 3 and a thickness of 0.1 to 1.0 ⁇ m, which are successively formed on the n-type InP substrate 1, an InAlAs electron transit layer 3 having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, approximately 0.6 nm ) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, approximately 0.6 nm) having a carrier concentration of 1 ⁇ 10 cm ⁇ 3 or less and a layer thickness of 50 to 1000 nm are alternately laminated a plurality of times, an n-type InAlAs electric field relaxation layer 12 having a carrier concentration of 1 ⁇ 10 to 5 ⁇ 10 cm ⁇ 3 and a layer thickness of 10 to 70 nm, and an n-type InA
  • a p-type InP electric field relaxation layer 14 having a carrier concentration of 1 ⁇ 10 16 to 5 ⁇ 10 18 cm -3 and a thickness of 10 to 70 nm ; an i-type InGaAs light absorption layer 5 having a carrier concentration of 1 ⁇ 10 17 cm -3 or less and a thickness of 50 nm to 3.0 ⁇ m; an i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5 ⁇ 10 17 cm -3 or less and a thickness of 5 to 50 nm;
  • the p-type InP window layer 7 has a thickness of 0.1 to 3.0 ⁇ m and a conductivity type of ⁇ 3 or more, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.
  • a p-type InAlAs window layer may be used instead of the p-type InP window layer 7, a p-type InAlAs window layer may be used.
  • the n-type InAlAs buffer layer 2a is also called an n-type semiconductor layer.
  • the semiconductor light receiving element 110a according to the second embodiment shown in FIG. 5 has a layer structure similar to that of the semiconductor light receiving element 110, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface on which the incident light 90 is incident.
  • Silicon (Si) is optimal as the n-type dopant for the n-type InAlAs buffer layer 2a.
  • the n-type InAlAs buffer layer 2a may have either a random alloy structure or a digital alloy structure.
  • the i-type InAlAs digital alloy structure electron transit layer 3 is composed of semiconductor layers in which AlAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order.
  • the layer thicknesses of the AlAs layers and InAs layers are each in the range of 2 atomic layers to 6 atomic layers.
  • the reason for using 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layers and InAs layers not to function as a quantum well structure.
  • the number of atomic layers in each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal.
  • the reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.
  • a layer thickness of 4 to 6 atomic layers which reduces the number of shutter switching times during crystal growth by MBE, is also optimal.
  • the number of atomic layers in each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably in the range of 2 to 6 atomic layer periods.
  • the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is within the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is 500 nm, the AlAs layer (2 atomic layers)/InAs layer (2 atomic layers) repetition is 417 times. As shown in FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is most preferably within the range of 50 nm to 200 nm.
  • the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even within the range of 50 nm to 400 nm.
  • the thickness of only the first AlAs layer of the i-type InAlAs digital alloy structure electron transit layer 3 may be formed by alternating layers of InAs and AlAs layers.
  • the conductivity type of the i-type InAlAs digital alloy structure electron transit layer 3 is i-type, and the carrier concentration is, for example, 1 ⁇ 10 17 cm -3 or less.
  • the conductivity type of the i-type InAlAs digital alloy structure electron transit layer 3 may be p-type or n-type, in which the carrier concentration is 5 ⁇ 10 17 cm -3 or less.
  • an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Z) are alternately stacked can also be applied as the electron transit layer of the present disclosure.
  • a digital alloy structure made of InAlAsSb, a material system containing antimony (Sb) can also be applied as the electron transit layer of the present disclosure.
  • the n-type electric field buffer layer does not necessarily have to be InAlAs, and may be an n-type InP or n-type InAlAs digital alloy structure.
  • the n-type InAlAs electric field buffer layer 12 is provided to prevent an excessive electric field from being applied to the i-type InAlAs multiplication layer 13, causing multiplication.
  • the electron speed begins to decrease, that is, an overshoot phenomenon of the traveling speed occurs, so the n-type InAlAs electric field buffer layer 12 has the function of adjusting the electric field so that the traveling speed is maximized.
  • the i-type InAlGaAs/InAlAs graded layer 6 is a layer in which the band gap is gradually changed by changing the composition of InAlGaAs, and each layer thickness is within the range of 5 to 50 nm.
  • the composition of InAlGaAs may be changed stepwise, and the band gap is intermediate between that of an InP layer and an InGaAs layer.
  • the carrier concentration is 5 ⁇ 10 17 cm -3 or less, and if the carrier concentration is low, it may be p-type or n-type.
  • the i-type InAlGaAs/InAlAs graded layer 6 is not necessarily required and may be omitted.
  • a layer having an intermediate band gap such as InAlGaAs or InGaAsP and a thickness of 0.1 ⁇ m or less may be provided between the p-type InP electric field relaxation layer 14 and the i-type InGaAs light absorption layer 5. This is because it is possible to prevent the accumulation of electrons and holes at the heterojunction interface.
  • two types of i-type InAlGaAs layers with different compositions are alternately stacked multiple times on the i-type InGaAs light absorbing layer 5 to form an i-type InAlGaAs/InAlAs graded layer 6.
  • Ti and Au are used for the p-type electrode 32 of the APD, which is an example of a semiconductor light receiving element according to the second embodiment.
  • a voltage is applied in the reverse direction to the APD, and the operating voltage is 10V to 100V.
  • the electric field of the i-type InAlAs multiplication layer 13 when the APD is operating is 500kV/cm to 900kV/cm.
  • the electric field of the i-type InGaAs light absorption layer 5 is set to 300kV/cm or less.
  • the multiplication factor is used at 3 to 30, but is 100 or more when operating in Geiger mode.
  • the APD according to the second embodiment like the PD according to the first embodiment, employs an i-type InAlAs digital alloy structure electron transit layer 3 with a long dead space length, thereby increasing the speed of electrons in the electron transit layer, shortening the transit time, and improving the bandwidth limit ftr. As a result, an effect is achieved in which the bandwidth of the APD is further improved.
  • the semiconductor light receiving element according to the second embodiment has an i-type InAlAs digital alloy structure electron transit layer, which provides an effect of providing a semiconductor light receiving element having high reception sensitivity and operating over a wide band.
  • a modified example of embodiment 2 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the second embodiment, and an edge-illuminated APD, which is another example, will be described below.
  • the semiconductor light receiving element according to the modified example of the second embodiment is structurally different in that the i-type InAlAs multiplication layer 13 of the semiconductor light receiving element according to the second embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • an i-type InAlAs digital alloy multiplication layer is a digital alloy structure in which i-type AlAs layers (for example, two atomic layers, approximately 0.6 nm thick) and i-type InAs layers (for example, two atomic layers, approximately 0.6 nm thick) are alternately stacked multiple times.
  • i-type AlAs layers for example, two atomic layers, approximately 0.6 nm thick
  • i-type InAs layers for example, two atomic layers, approximately 0.6 nm thick
  • the thickness of the i-type InAlAs digital alloy structure multiplication layer is in the range of 40 nm to 1000 nm. However, in order to increase the dead space effect in the i-type InAlAs digital alloy structure multiplication layer, the thickness of the i-type InAlAs digital alloy structure multiplication layer may be in the range of 40 nm to 170 nm. Furthermore, considering the typical degree of variation in layer thickness during the manufacture of the semiconductor light receiving element 100 of 20%, it is more preferable that the thickness of the i-type InAlAs digital alloy structure multiplication layer is in the range of 50 nm to 140 nm.
  • Fig. 6 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer.
  • the inventors have clarified that, as shown in the graph of Fig. 6, the InAlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer.
  • FIGS. 7A to 7C show the ionization rates of electrons and holes, respectively, with FIG. 7A showing the case of electron ionization, FIG. 7B showing the case of hole ionization, and FIG. 7C showing the ionization rate when the multiplication layer is thinned.
  • the dead space length is about 45 nm, so the thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm).
  • thinning the multiplication layer to 70 nm increases the electric field in the multiplication layer, and a sudden increase in the tunnel current increases noise, making it difficult to obtain an APD with good reception sensitivity.
  • the dead space length is approximately 85 nm, so even if the thickness of the multiplication layer is approximately 1.5 times that of the dead space (approximately 130 nm), it is possible to make the ionization rate ratio k approach zero. Therefore, the effect of the tunnel current is small in the APD according to the modified example of embodiment 2.
  • the dead space is highly dependent on the applied electric field, and when the reciprocal of the applied electric field is 1.27 ⁇ 10 ⁇ 6 cm/V, the dead space length is approximately 50 nm, as shown in the graph of Fig. 6, so the multiplication layer needs to be thinned to 75 nm.
  • the thickness of the InAlAs digital alloy structure multiplication layer can be made thicker than the thickness of the InAlAs random alloy structure multiplication layer.
  • Fig. 8 is a diagram showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer.
  • the inventors fabricated APDs having an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, respectively, measured the ionization rate ratio k, and further plotted the results in Fig. 8 together with the measurement results of References 1 and 2 described in Fig. 8.
  • References 1 and 2 in Fig. 8 are as follows: (1) Literature 1 Yuan Yuan, et al “Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys”pp. 794, Vol. 6, No.
  • the effect of reducing the ionization rate ratio k due to the dead space does not appear unless the thickness of the multiplication layer is 80 nm or less.
  • the thickness of the multiplication layer is made thinner than 80 nm, the tunnel current increases rapidly and tunnel breakdown occurs.
  • the multiplication layer is about 60 nm thick, it is barely possible to reduce the ionization rate ratio k and limit the tunnel current, but the margin for the layer thickness is only a few nm, making it extremely difficult to stably manufacture APDs.
  • the ionization rate ratio k is also large at 0.12. In other words, with the conventional InAlAs random alloy structure multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by making the layer thinner to APDs.
  • the dead space is large, and as shown in FIG. 8, as the multiplication layer is made thinner, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm.
  • the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the range of multiplication factors 1 to 10.
  • the layer thickness of the InAlAs digital alloy structure multiplication layer is more than twice as thick as that of the InAlAs random alloy structure multiplication layer.
  • the optimal thickness range for an InAlAs digital alloy structure multiplication layer is 40 nm to 170 nm, and layer thicknesses within this range can be fabricated with sufficient reproducibility.
  • the thickness of the InAlAs digital alloy structure multiplication layer at which the dead space effect is sufficient to reduce the ionization rate ratio k is considered to be approximately twice the dead space length when the reciprocal of the applied electric field is 1.47 x 10 -6 cm/V. Considering that the dead space length is 85 nm as shown in Figure 8, therefore, 170 nm, which is twice the dead space length, is a suitable upper limit for the thickness of the InAlAs digital alloy structure multiplication layer.
  • the graph in Figure 6 shows that the thickness of the multiplication layer is preferably 150 nm or less. Furthermore, in order to achieve a tunnel current of 1 ⁇ A or less and an ionization rate ratio k of approximately zero, the optimal thickness of the multiplication layer is in the range of 60 nm to 130 nm. If a margin of 10 nm is allowed when fabricating an APD, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.
  • the length of the dead space is preferably 50 nm to 90 nm.
  • Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough that it does not affect noise, and the thicker the multiplication layer, the more the tunnel current decreases.
  • the ionization rate ratio k starts to decrease as the multiplication layer is made thinner at values De of approximately 80 nm and Dh of approximately 170 nm.
  • De is about 40 nm and Dh is about 80 nm.
  • Dh is about 170 nm.
  • dopants in the electric field relaxation layer that is, impurities, may diffuse into the InAlAs digital alloy structure multiplication layer during the manufacturing process, causing disorder within the multiplication layer.
  • FIGS. 9A to 9D show the ionization rates in the multiplication layer and the electric field relaxation layer.
  • FIG. 9A shows the ionization rate in the case of an InAlAs random alloy structure multiplication layer
  • FIG. 9B shows the ionization rate in the case of an InAlAs digital alloy structure multiplication layer
  • FIG. 9C shows the ionization rate in the case of a partially disordered InAlAs digital alloy structure multiplication layer
  • FIG. 9D shows the ionization rate in the case of a combination of a thick electric field relaxation layer and an InAlAs digital alloy structure multiplication layer.
  • the dead space length of the InAlAs digital alloy structure multiplication layer shown in FIG. 9B is longer, but due to dopant diffusion from the electric field relaxation layer, the dead space length of the partially disordered InAlAs digital alloy structure multiplication layer is shorter as shown in FIG. 9C.
  • N is the impurity concentration
  • t is time
  • D is the diffusion constant
  • x is position
  • F is the external force acting on the diffusion.
  • materials for the electric field buffer layer include InP, InAlAs random alloy structure, and InAlAs digital alloy structure.
  • p-type dopants for the electric field buffer layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP electric field buffer layer and an InAlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier with the InAlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in formula (11).
  • the carrier concentration of the electric field relaxation layer is preferably 2 ⁇ 10 18 cm -3 or less .
  • Zn doping is optimal, and the carrier concentration is optimally 2 ⁇ 10 18 cm -3 or less. Note that if the impurity concentration is higher than 2 ⁇ 10 18 cm -3 , the amount of inactive impurities increases and diffusion is likely to occur, so the carrier concentration must be 5 ⁇ 10 18 cm -3 or less.
  • ⁇ E W ⁇ q ⁇ N/ ⁇ (12)
  • the thickness of the electric field relaxation layer is about 10 nm.
  • the carrier concentration of the electric field relaxation layer is controlled to be 5 ⁇ 10 18 cm -3 or less.
  • the electric field relaxation layer needs to have a thickness of 10 nm or more.
  • the dead space length is 45 nm or less, so the layer thickness of the random alloy structure electric field buffer layer needs to be 70 nm or less.
  • the dead space length is 85 nm or less, so the layer thickness of the digital alloy electric field buffer layer needs to be 130 nm or less.
  • dead space lengths shown in Figures 9A to 9D have the following relationship: dead space ( Figure 9A) ⁇ dead space ( Figure 9D) ⁇ dead space ( Figure 9C) ⁇ dead space ( Figure 9B).
  • the 3 dB bandwidth f c of the APD having the InAlAs digital alloy structure multiplication layer according to the first embodiment is limited only by the RC time constant and the carrier transit time according to equations (6), (7), and (8) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (13).
  • fc_APD 1/((1/frc) 2 +(1/ftr) 2 ) 0.5 (13)
  • the transit time ftr of a carrier includes the transit time through the light absorption layer plus the transit time through the multiplication layer.
  • Vav is the average saturation transit velocity of electrons and holes
  • Wt is the total thickness of the light absorption layer and the multiplication layer.
  • the semiconductor photodetector according to the modified example of the second embodiment further includes a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that operates over a wide bandwidth and has excellent low noise characteristics.
  • Fig. 10 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 120 according to the embodiment 3.
  • Fig. 11 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 120a according to the embodiment 3.
  • the semiconductor light receiving element 120 according to the third embodiment shown in FIG. 10 includes an n-type InP substrate 1, an n-type InP buffer layer 2 having a carrier concentration of 1 to 5 ⁇ 10 18 cm -3 and a layer thickness of 0.1 to 1.0 ⁇ m, which are successively formed on the n-type InP substrate 1, an i-type InAlAs digital alloy structure electron transit layer 3 having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) having a carrier concentration of 1 ⁇ 10 17 cm -3 or less and a layer thickness of 50 to 1000 nm are alternately laminated a plurality of times, an i-type InAlGaAs graded layer 4 having a carrier concentration of 5 ⁇
  • n-type InP buffer layer 2 is also called an n-type semiconductor layer.
  • the semiconductor light receiving element 120a according to the third embodiment shown in FIG. 11 has the same configuration as the semiconductor light receiving element 120 according to the third embodiment, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate, and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.
  • the semiconductor photodetectors 120 and 120a according to the third embodiment differ from the semiconductor photodetectors 100 and 100a according to the first embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and in that a p-type diffusion region 15 is provided in the n-type InP window layer 11.
  • the n-type InP window layer 11 of the semiconductor photodetectors 120 and 120a has a thickness of 0.1 ⁇ m or more and 3 ⁇ m or less, and a carrier concentration of 5 ⁇ 10 17 cm -3 or less.
  • the n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.
  • the p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or gas phase.
  • the carrier concentration of the p-type diffusion region 15 is 5 ⁇ 10 17 cm ⁇ 3 or more.
  • the tip of the p-type diffusion region 15 may be located at a depth up to the middle of the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs/InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light absorption layer 5.
  • the p-type diffusion region 15 has a depth reaching the i-type InGaAs light absorption layer 5.
  • a p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.
  • the p-type layered part has a uni-traveling carrier (UTC) structure.
  • UTC uni-traveling carrier
  • the p-type InGaAs part of the i-type InGaAs light absorption layer 5 may be formed during epitaxial crystal growth instead of being made into a p-type layer as described above.
  • an n-type electrode 31 is provided on the back side.
  • an n-type electrode 31a is provided on the front side.
  • an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the semiconductor layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b.
  • the semiconductor light-receiving element 120a may use a p-type InP substrate or an n-type InP substrate instead of the Fe-doped semi-insulating InP substrate 1a.
  • a mesa structure such as a front-illuminated PD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment shown in Fig. 1
  • the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration.
  • an InAlAs digital alloy structure is used as the electron transit layer
  • high strain is applied to each layer constituting the i-type InAlAs digital alloy structure electron transit layer 3, so that dislocation defects and disorder are likely to occur from the exposed portion toward the inside, which may result in a problem of deterioration of the semiconductor light-receiving element.
  • the dark current generated in the side portion may shorten the life of the semiconductor light receiving element compared to the conventional InAlAs random alloy structure.
  • the portion of the i-type InAlAs digital alloy structure electron transit layer 3 to which an electric field is applied that is, the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, so that the effect of preventing the occurrence of deterioration and disorder in the i-type InAlAs digital alloy structure electron transit layer 3 in which each layer is highly distorted is achieved.
  • Fig. 12 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 130 according to the fourth embodiment.
  • Fig. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 130a according to the fourth embodiment.
  • the semiconductor light receiving element 130 includes an n-type InP substrate 1, an n-type InAlAs buffer layer 2a having a carrier concentration of 1 to 5 ⁇ 10 cm ⁇ 3 and a thickness of 0.1 to 1.0 ⁇ m, which are successively formed on the n-type InP substrate 1, an i-type InAlAs digital alloy structure electron transit layer 3 having a digital alloy structure in which an i-type AlAs layer (e.g., two atomic layers, about 0.6 nm thick) and an i-type InAs layer (e.g., two atomic layers, about 0.6 nm thick) having a carrier concentration of 1 ⁇ 10 cm ⁇ 3 or less and a thickness of 50 to 1000 nm are alternately laminated a plurality of times, an n-type InAlAs electric field relaxation layer 12 having a carrier concentration of 1 ⁇ 10 to 5 ⁇ 10 cm ⁇ 3 and a
  • a p-type InP electric field relaxation layer 14 having a carrier concentration of 1 ⁇ 10 16 to 5 ⁇ 10 18 cm -3 and a thickness of 10 to 70 nm ; an i-type InGaAs light absorption layer 5 having a carrier concentration of 1 ⁇ 10 17 cm -3 or less and a thickness of 50 nm to 3.0 ⁇ m; an i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5 ⁇ 10 17 cm -3 or less and a thickness of 5 to 50 nm;
  • the InAlAs buffer layer 2a is composed of an n-type InP window layer 11 having a thickness of 0.1 to 3.0 ⁇ m and a refractive index of ⁇ 3 or less, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31 formed on the back surface side of the n-
  • the semiconductor light receiving element 130a according to the fourth embodiment shown in FIG. 13 has the same configuration as the semiconductor light receiving element 130 according to the fourth embodiment, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate, and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.
  • the semiconductor photodetectors 130 and 130a according to the fourth embodiment differ from the semiconductor photodetectors 110 and 110a according to the second embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and in that a p-type diffusion region 15 is provided in the n-type InP window layer 11.
  • the n-type InP window layer 11 of the semiconductor photodetectors 120 and 130 has a thickness of 0.1 ⁇ m or more and 3 ⁇ m or less, and a carrier concentration of 5 ⁇ 10 17 cm -3 or less.
  • the n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.
  • the p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or gas phase.
  • the carrier concentration of the p-type diffusion region 15 is 5 ⁇ 10 17 cm ⁇ 3 or more.
  • the tip of the p-type diffusion region 15 may be located at a depth up to the middle of the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs/InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light absorption layer 5.
  • the p-type diffusion region 15 has a depth reaching the i-type InAlGaAs/InAlAs graded layer 6.
  • a p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.
  • an n-type electrode 31 is provided on the back side.
  • an n-type electrode 31a is provided on the front side. That is, in the semiconductor light receiving element 130a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the semiconductor layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b.
  • a p-type InP substrate or an n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.
  • a mesa structure such as a front-illuminated APD, which is an example of the semiconductor light-receiving element 110 according to the second embodiment shown in Fig. 3, the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration.
  • an InAlAs digital alloy structure is used as the electron transit layer, high strain is applied to each layer of the i-type InAlAs digital alloy structure electron transit layer 3, so that dislocation defects and disorder are likely to occur from the exposed portion toward the inside, which may result in the semiconductor light-receiving element being deteriorated.
  • the dark current generated in the side portion may shorten the life of the semiconductor light receiving element compared to the conventional InAlAs random alloy structure.
  • a front-illuminated APD which is an example of a semiconductor light-receiving element according to a modification of the fourth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the fourth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving elements 130 and 130a according to the fourth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the semiconductor photodetector according to the modified example of the fourth embodiment further includes a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • FIG. 14 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 140 according to the fifth embodiment.
  • the front-illuminated APD which is an example of the semiconductor photodetector 140 according to the fifth embodiment, is characterized in that, in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor photodetector 130 according to the fourth embodiment, a separation groove 17 is provided along the outer periphery of the p-type diffusion region 15 formed in the n-type InP window layer 11.
  • the depth of the separation groove 17 is preferably in the range of 2 ⁇ m to 5 ⁇ m.
  • the opening width of the separation groove 17 is preferably in the range of 0.5 ⁇ m to 100 ⁇ m.
  • the bottom of the separation groove 17 reaches at least the i-type InAlAs digital alloy structure electron transit layer 3. Note that FIG. 14 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2a.
  • Either dry etching or wet etching may be used to form the separation groove 17. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.
  • the inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO2 .
  • the surface protective film 18 also serves as an anti-reflective coating for the light receiving section.
  • the thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm.
  • the surface protective film 18 may also be an organic film such as benzocyclobutene (BCB).
  • each layer of the InAlAs digital alloy structure is highly strained, so that the InAlAs digital alloy structure is easily disordered when stress is applied from the outside. Therefore, as in the semiconductor light receiving element 140 according to the fifth embodiment, by providing the separation groove 17 along the outer periphery of the p-type diffusion region 15, the stress that affects the entire wafer during the manufacturing process can be alleviated.
  • the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 140 can be alleviated. Furthermore, since the i-type InAlAs digital alloy structure electron transit layer 3 is exposed in the separation groove 17, it is desirable that the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so that it does not become a starting point of deterioration.
  • the portion of the i-type InAlAs digital alloy structure electron transit layer 3 to which an electric field is applied that is, the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, which has the effect of preventing deterioration in the i-type InAlAs digital alloy structure electron transit layer 3, in which each layer is highly distorted.
  • the separation groove 17 relieves stress even when the semiconductor light receiving element 140 is in operation, no disorder occurs even if the semiconductor light receiving element 140 is used for a long period of time.
  • the semiconductor light receiving element 140 of embodiment 5 can achieve high reliability by operating in a wide band for a long period of time and maintaining low noise.
  • a modified example of embodiment 5 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the fifth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the fifth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 140 according to the fifth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the semiconductor photodetector according to the modified example of the fifth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and can prevent disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer despite the Zn diffusion for forming a p-type diffusion region being performed during the formation of the device structure. Furthermore, the presence of the separation groove can relieve stress, so that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • FIG. 15 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 140a according to the sixth embodiment.
  • the front-illuminated APD which is an example of the semiconductor light-receiving element 140 according to the fifth embodiment, receives light from the front side
  • the back-illuminated APD which is an example of the semiconductor light-receiving element 140a according to the sixth embodiment, is characterized in that it has an element structure in which a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is incident on the n-type InP substrate 1 through an anti-reflective coating film 35 formed so as to cover the opening 33.
  • the opening 33 which is an incident region of the incident light 90 and is covered with the anti-reflective coating film 35, is provided on the back side of the n-type InP substrate 1 facing the p-type electrode 32.
  • the center part of the p-type InGaAs contact layer 8 is partially removed, and a surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO 2 is formed on the exposed p-type diffusion region 15, and the surface protective film 18 is further covered with the p-type electrode 32, thereby increasing the reflectance of light from the p-type electrode 32.
  • the area of the p-type diffusion region 15 can be made smaller in a back-illuminated APD such as the semiconductor light receiving element 140a than in a front-illuminated APD such as the semiconductor light receiving element 140, it is possible to further reduce the stress generated during p-type diffusion, thereby further preventing disordering of the i-type InAlAs digital alloy structure electron transit layer 3.
  • disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented, and the stress can be further reduced by the separation groove 17, resulting in the effect of obtaining a semiconductor light receiving element that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • the semiconductor light receiving element of the sixth embodiment since the element structure is a back-illuminated APD, the area of the p-type diffusion region can be made smaller than that of a front-illuminated APD, and the stress can be further alleviated by the separation groove, so that a semiconductor light receiving element having high reliability, wideband operation, and excellent low noise characteristics can be obtained.
  • the i-type InGaAs light absorbing layer 5 can be made thinner, so that the transit time of electrons and holes can be shortened, and by combining with the i-type InAlAs digital alloy structure electron transit layer 3, a semiconductor light receiving element capable of further widening the bandwidth can be obtained.
  • a back-illuminated APD which is an example of a semiconductor light-receiving element according to a modification of the sixth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the sixth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the back-illuminated APD, which is an example of the semiconductor light receiving element 140 according to the sixth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the back-illuminated APD which is an example of a semiconductor photodetector according to a modification of the sixth embodiment, like the semiconductor photodetector according to the fifth embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step for forming the p-type diffusion region 15, disordering of the InAlAs digital alloy structure multiplication layer can be prevented. Therefore, for example, the dead space length does not become shorter as shown in FIG. 9C, but a long state of the dead space length as shown in FIG. 9B can be maintained.
  • the semiconductor photodetector of the modification of the sixth embodiment since the device structure is a back-illuminated APD, the area of the p-type diffusion region can be made smaller than that of a front-illuminated APD, and the device has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range. Even though Zn diffusion is performed to form the p-type diffusion region when the device structure is formed, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented, and further, stress can be alleviated by the presence of the separation groove. Therefore, a semiconductor photodetector having higher reliability, wider bandwidth operation, and excellent low noise characteristics can be obtained.
  • Fig. 16 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 150 according to the seventh embodiment.
  • Fig. 17 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 150a according to the seventh embodiment.
  • the semiconductor light receiving element 150 according to the seventh embodiment has the same configuration as the semiconductor light receiving element 100 according to the first embodiment from the n-type InP substrate 1 to the i-type InAlGaAs/InAlAs graded layer 6, and therefore the description thereof will be omitted.
  • the semiconductor light receiving element 150 is composed of a structure from an n-type InP substrate 1 to an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a thickness of 0.1 to 3.0 ⁇ m, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.
  • the semiconductor light receiving element 150a according to the seventh embodiment shown in FIG. 17 has the same configuration as the semiconductor light receiving element 150 according to the seventh embodiment, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate, and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.
  • the semiconductor light receiving element 150, 150a according to the seventh embodiment differs from the semiconductor light receiving element 100 according to the first embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25.
  • the n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order not to lengthen the carrier travel time.
  • the conductivity type of the n-type InP window layer 11 may be undoped instead of n-type.
  • the carrier concentration is preferably 5.0 ⁇ 10 17 cm -3 or less.
  • the manufacturing method of the semiconductor light receiving element 150, 150a according to the seventh embodiment is characterized in that the p-type InAlAs conductive layer 25 is crystal-grown on the n-type InP window layer 11 by MOVPE or MBE, and then the p-type InGaAs contact layer 8 is crystal-grown, after which the p-type InAlAs conductive layer 25 is removed, leaving the light receiving portion.
  • the thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less.
  • the carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0 ⁇ 10 17 cm -3 or more, in order to reduce the element resistance.
  • the p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.
  • the semiconductor light receiving element 150 shown in FIG. 16 has an n-type electrode 31 on the back side
  • the semiconductor light receiving element 150a shown in FIG. 17 has an n-type electrode 31a on the front side. That is, in the semiconductor light receiving element 150a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2b are partially removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2b.
  • a p-type InP substrate or an n-type InP substrate may be used.
  • the light absorption layer region directly below the light receiving part to which a high electric field is applied is separated from the side part of the element, so that the semiconductor light receiving element can be highly reliable. Therefore, it is possible to achieve both high sensitivity and high reliability of the semiconductor light receiving element. In other words, a semiconductor light receiving element, that is, a PD, with excellent reliability can be obtained.
  • the semiconductor photodetector of the seventh embodiment similarly to the semiconductor photodetector of the third embodiment, the electron transit layer is separated from the side portion of the element, and therefore high reliability can be obtained, and therefore a semiconductor photodetector that is highly reliable and operates over a wide bandwidth can be obtained.
  • Fig. 18 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 160 according to the eighth embodiment.
  • Fig. 19 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 160a according to the eighth embodiment.
  • the semiconductor light receiving element 160 according to the eighth embodiment has the same configuration as the semiconductor light receiving element 110 according to the second embodiment from the n-type InP substrate 1 to the i-type InAlGaAs/InAlAs graded layer 6, and therefore the description thereof will be omitted.
  • the semiconductor light receiving element 160 according to the eighth embodiment shown in FIG. 18 is composed of a structure from an n-type InP substrate 1 to an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a layer thickness of 0.1 to 3.0 ⁇ m, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.
  • the semiconductor light receiving element 160a according to the eighth embodiment shown in FIG. 19 has the same configuration as the semiconductor light receiving element 160 according to the eighth embodiment, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate, and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.
  • the semiconductor light receiving element 160, 160a according to the eighth embodiment differs from the semiconductor light receiving element 110 according to the second embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25.
  • the n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order not to lengthen the carrier travel time.
  • the conductivity type of the n-type InP window layer 11 may be undoped instead of n-type.
  • the carrier concentration is preferably 5.0 ⁇ 10 17 cm -3 or less.
  • the manufacturing method of the semiconductor light receiving element 160, 160a according to the eighth embodiment is characterized in that the p-type InAlAs conductive layer 25 is crystal-grown on the n-type InP window layer 11 by MOVPE or MBE, and then the p-type InGaAs contact layer 8 is crystal-grown, after which the p-type InAlAs conductive layer 25 is removed, leaving the light receiving portion.
  • the thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less.
  • the carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0 ⁇ 10 17 cm -3 or more, in order to reduce the element resistance.
  • the p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.
  • the semiconductor light receiving element 160 shown in FIG. 18 has an n-type electrode 31 on the back side
  • the semiconductor light receiving element 160a shown in FIG. 19 has an n-type electrode 31a on the front side. That is, in the semiconductor light receiving element 160a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2b are partially removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2b.
  • a p-type InP substrate or an n-type InP substrate may be used.
  • the light absorption layer region directly below the light receiving part to which a high electric field is applied is separated from the side part of the element, so that the semiconductor light receiving element can be highly reliable. Therefore, it is possible to achieve both high sensitivity and high reliability of the semiconductor light receiving element. In other words, a semiconductor light receiving element with excellent reliability, that is, an APD, can be obtained.
  • the semiconductor photodetector of the eighth embodiment like the semiconductor photodetector of the fourth embodiment, the electron transit layer is separated from the side portion of the element, and therefore, an effect is achieved in that a semiconductor photodetector having high reliability, wideband operation, and excellent low noise characteristics is obtained.
  • a modified example of embodiment 8 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the eighth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the eighth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 160, 160a according to the eighth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • a front-illuminated APD which is an example of a semiconductor photodetector according to a modified example of embodiment 8, can maintain a long dead space length as shown in FIG. 9B, for example, without shortening the dead space length as shown in FIG. 9C, similarly to the semiconductor photodetector according to the modified example of embodiment 2.
  • the semiconductor photodetector according to the modified example of the eighth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and therefore has the effect of providing a semiconductor photodetector which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • Embodiment 9. 20 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 170 according to the ninth embodiment.
  • the front-illuminated APD which is an example of the semiconductor light-receiving element 170 according to the ninth embodiment, is characterized in that a separation groove 17 is further provided along the outer periphery of the p-type InAlAs conductive layer 25 in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor light-receiving element 160 according to the eighth embodiment.
  • the depth of the separation groove 17 is preferably in the range of 2 ⁇ m to 5 ⁇ m.
  • the opening width of the separation groove 17 is preferably in the range of 0.5 ⁇ m to 100 ⁇ m.
  • the bottom of the separation groove 17 reaches at least the i-type InAlAs digital alloy structure electron transit layer 3. Note that FIG. 20 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2a.
  • Either dry etching or wet etching may be used to form the separation groove 17. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.
  • the inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO2 .
  • the surface protective film 18 also serves as an anti-reflective coating for the light receiving section.
  • the thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm.
  • the surface protective film 18 may also be an organic film such as BCB.
  • each layer of the InAlAs digital alloy structure is highly strained, so that when stress is applied from the outside, disordering is likely to occur. Therefore, as in the semiconductor light receiving element 170 according to the ninth embodiment, by providing the separation groove 17 along the outer periphery of the p-type InAlAs conductive layer 25, the stress that affects the entire wafer during the manufacturing process can be alleviated.
  • the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 170 can be alleviated.
  • the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so that it does not become a starting point of deterioration.
  • the separation groove can relieve stress due to heat treatment and the like in the manufacturing process, and therefore disordering of the digital alloy structure electron transit layer can be prevented. This makes it possible to maintain the ionization rate ratio k at approximately zero, and provides the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • a modified example of embodiment 9 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the ninth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the ninth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 170 according to the ninth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the semiconductor photodetector according to the modified example of the ninth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and since high-temperature heat treatment is not required, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented. Furthermore, the presence of the separation groove can relieve stress, so that an advantageous effect is achieved in that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.
  • FIG. 21 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 170a according to the tenth embodiment.
  • the front-illuminated APD which is an example of the semiconductor light-receiving element 170 according to the ninth embodiment, receives light from the front side as shown in Fig. 20
  • the back-illuminated APD which is an example of the semiconductor light-receiving element 170a according to the tenth embodiment, is characterized in that it has an element structure in which a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is made incident on the n-type InP substrate 1 through an anti-reflective coating film 35 formed so as to cover the opening 33, as shown in Fig. 21.
  • the opening 33 which is an incident region of the incident light 90 and is covered with the anti-reflective coating film 35, is provided on the back side of the n-type InP substrate 1 facing the p-type electrode 32.
  • the center part of the p-type InGaAs contact layer 8 is partially removed, and the surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO 2 is formed on the exposed p-type InAlAs conductive layer 25, and the surface protective film 18 is further covered with the p-type electrode 32, thereby increasing the reflectance of light from the p-type electrode 32.
  • the back-illuminated APD which is an example of the semiconductor light receiving element 170a according to the tenth embodiment, can reduce stress caused by heat treatment during the manufacturing process by using a separation groove, similar to the semiconductor light receiving element 170 according to the ninth embodiment, thereby preventing disordering of the InAlAs digital alloy structure multiplication layer.
  • the area of the p-type InAlAs conductive layer 25 can be made smaller in a back-illuminated APD such as the semiconductor light receiving element 170a than in a front-illuminated APD, it is possible to further reduce stress due to heat treatment in the manufacturing process, and therefore the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be further prevented.
  • the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented, so that a semiconductor light receiving element that is highly reliable, operates in a wide band, and has excellent low noise characteristics can be obtained.
  • the i-type InGaAs light absorption layer 5 can be made thinner, shortening the transit time of electrons and holes, and by combining it with the i-type InAlAs digital alloy structure electron transit layer 3, a semiconductor light receiving element with an even wider bandwidth can be obtained.
  • the area of the mesa-shaped p-type InAlAs conductive layer 25 can be reduced compared to that of a front-illuminated APD, so the effect of stress from the mesa portion of the p-type InAlAs conductive layer 25 is reduced, and the i-type InAlAs digital alloy structure electron transit layer 3 does not become disordered.
  • the semiconductor photodetector 170a according to the tenth embodiment can operate in a wide band for a long period of time and maintain low noise.
  • the area of the p-type conductive layer can be made small, and therefore the stress generated in the heat treatment process can be further reduced, thereby further preventing disordering of the i-type InAlAs digital alloy structure electron transit layer.
  • the separation groove can further reduce the stress, resulting in an advantageous effect of providing a semiconductor light-receiving element that is highly reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.
  • a modified example of embodiment 10 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the tenth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the tenth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 170a according to the tenth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the semiconductor photodetector according to the modified example of the tenth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and since high-temperature heat treatment is not required, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented. Furthermore, the presence of the separation groove can relieve stress, so that an advantageous effect is achieved in that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.
  • Embodiment 11. 22 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 180 according to the eleventh embodiment.
  • the semiconductor light receiving element 180 comprises an Fe-doped semi-insulating InP substrate 1a, and, successively formed on the Fe-doped semi-insulating InP substrate 1a, a p-type InAlGaAs contact layer 40 having a carrier concentration of 1 to 5 ⁇ 10 cm ⁇ 3 and a layer thickness of 0.1 to 1 ⁇ m, a p-type InP conductive layer 41 having a carrier concentration of 1 to 5 ⁇ 10 cm ⁇ 3 and a layer thickness of 0.1 to 1 ⁇ m, a p-type or low carrier concentration (5 ⁇ 10 17 cm ⁇ 3 or less) n-type or i-type InAlGaAs/InAlAs graded layer 42, an i-type InGaAs light absorbing layer 43 having a carrier concentration of 5 ⁇ 10 17 cm ⁇ 3 or less and a layer thickness of 0.1 to 2.0 ⁇ m, and an n
  • the p-type InAlGaAs contact layer 40 and the p-type InP conductive layer 41 are also called p-type semiconductor layers.
  • the central portion of the n-type InGaAs contact layer 50 is partially removed, and a surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO2 is formed on the exposed n-type InAlAs conductive layer 49, and this is further covered with an n-type electrode 51, thereby increasing the reflectance of light from the n-type electrode 51.
  • a method for manufacturing the semiconductor light receiving element 180 according to the eleventh embodiment will be described below.
  • MOVPE or MBE a p-type InAlGaAs contact layer 40 having a carrier concentration of 1 to 5 ⁇ 10 18 cm -3 is crystal-grown to a thickness of 0.1 to 1 ⁇ m on an Fe-doped semi-insulating InP substrate 1a.
  • An n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.
  • the p-type InAlGaAs contact layer 40 may be made of p-type InP, p-type InGaAsP, or p-type InGaAs instead of p-type InAlGaAs.
  • a p-type InP conductive layer 41 having a carrier concentration of 1 to 5 ⁇ 10 18 cm ⁇ 3 and a thickness of 0.1 to 1 ⁇ m is grown by crystal growth on the p-type InAlGaAs contact layer 40.
  • the p-type InP conductive layer 41 may be p-type InGaAsP or p-type InAlGaAs instead of p-type InP.
  • an i-type, n-type or p-type InAlAs layer with a small barrier against holes may be provided on the p-type InP conductive layer 41. Furthermore, after the p-type or low carrier concentration (5 ⁇ 10 17 cm -3 or less) n-type or i-type InAlGaAs/InAlAs graded layer 42 is crystal-grown, the i-type InGaAs light absorbing layer 43 is crystal-grown to a thickness of 0.1 to 2 ⁇ m.
  • the i-type InGaAs light absorbing layer 43 may be an n-type or p-type with a low carrier concentration (5 ⁇ 10 17 cm -3 or less) instead of an i-type.
  • either or both of the p-type InP conductive layer 41 and the n-type InAlGaAs/InAlAs graded layer 42 are not necessarily required.
  • the p-type InP electric field buffer layer 44 having a carrier concentration of 1 ⁇ 10 17 to 5 ⁇ 10 18 cm -3 is crystal-grown to a thickness of 10 to 100 nm.
  • Examples of p-type dopants for the p-type InP electric field buffer layer 44 include Be, Zn, and C.
  • the p-type InP electric field buffer layer 44 does not necessarily have to be p-type InP, and may be p-type InAlAs or a p-type InAlAs digital alloy structure.
  • an InAlGaAs/InAlAs graded layer with a thickness of 10 to 100 nm, which has an intermediate band gap value, such as InAlGaAs or InGaAsP, may be provided.
  • An i-type InAlAs multiplication layer 45 and an n-type InAlAs field adjustment layer 46 are crystal-grown as multiplication layers on the p-type InP field relaxation layer 44.
  • the n-type InAlAs field adjustment layer 46 is provided to prevent the electron travel speed from being saturated or the electrons from being multiplied due to an excessive electric field being applied to the i-type InAlAs digital alloy structure electron travel layer 47.
  • the i-type InAlAs digital alloy structure electron transit layer 47 is crystal-grown as an electron transit layer on the n-type InAlAs field adjustment layer 46.
  • the i-type InAlAs digital alloy structure electron transit layer 47 is composed of semiconductor layers in which an AlAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) and an InAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order from the Fe-doped semi-insulating InP substrate 1a side.
  • the i-type InAlAs digital alloy structure electron transit layer 47 may also be formed in the order of an InAs layer and an AlAs layer.
  • the number of atomic layers in each layer of the i-type InAlAs digital alloy structure electron transit layer 47 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer is, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.
  • the thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is in the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is 500 nm, the AlAs layer (2 atomic layers)/InAs layer (2 atomic layers) repetition is 417 times. As shown in FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is most preferably in the range of 50 nm to 200 nm.
  • the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even in the layer thickness range of 50 nm to 400 nm.
  • the InAlAs digital alloy structure electron transit layer 47 may be of an i-type conductivity with a carrier concentration of 1 ⁇ 10 17 cm ⁇ 3 or less, but may also be of a p-type or n-type conductivity with a carrier concentration of 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the n-type InAlAs field adjustment layer 48 is crystal-grown to a thickness of 0.1 to 2 ⁇ m.
  • the n-type InAlAs field adjustment layer 48 also functions as a window layer, but this is not essential.
  • the n-type InAlAs field adjustment layer 48 is a layer that adjusts the electric field at the outermost surface, and the carrier concentration is preferably in the range of 1 ⁇ 10 16 to 5 ⁇ 10 18 cm -3 . Weakening the electric field at the outermost surface has the effect of suppressing local breakdown and improving reliability.
  • n-type InAlAs conductive layer 49 is grown as an n-type conductive layer, and an n-type InGaAs contact layer 50 is grown as an n-type contact layer, on the n-type InAlAs field adjustment layer 48.
  • the n-type InAlAs conductive layer 49 and the n-type InGaAs contact layer 50 each have a thickness of 0.1 to 2 ⁇ m and a carrier concentration of 5 ⁇ 10 cm to 8 ⁇ 10 cm.
  • the n-type InAlAs conductive layer 49 and the n-type InGaAs contact layer 50 are etched into a mesa shape to form a first mesa.
  • the second mesa is formed by etching the p-type InAlGaAs contact layer 40 so as to include the first mesa outside the first mesa.
  • the second mesa does not need to reach the p-type InAlGaAs contact layer 40 as long as the i-type InGaAs light absorption layer 43 can be electrically isolated. It is preferable that the distance between the first mesa and the second mesa is 1 ⁇ m or more.
  • the first mesa may be formed after the second mesa is formed.
  • the p-type electrode 52 is formed on the p-type InAlGaAs contact layer 40, and the n-type electrode 51 is formed on the n-type InGaAs contact layer 50. Since the ohmic resistance of an n-type semiconductor is one order of magnitude smaller than that of a p-type semiconductor, it is not necessarily necessary to use the n-type InGaAs contact layer 50 having a small band gap, and n-type InP, n-type InGaAlAs, or n-type InGaAsP may also be used. Alternatively, a direct contact may be made with the n-type InAlAs conductive layer 49.
  • the semiconductor light receiving element 180 of the eleventh embodiment is characterized in that the conductivity type of the semiconductor light receiving element 170a of the tenth embodiment is inverted from n type to p type and from p type to n type, and the conductivity type of the upper surface side is made n type.
  • a first function and effect of the semiconductor light receiving element 180 according to the eleventh embodiment will be described below. If the i-type InAlAs digital alloy structure electron transit layer 47 is held at high temperature for a long time during epitaxial crystal growth, it may become disordered and become an InAlAs random alloy structure. In the semiconductor light receiving element 180 according to the eleventh embodiment, the total layer thickness of each semiconductor layer above the i-type InAlAs digital alloy structure electron transit layer 47 is about one-third thinner than that of the semiconductor light receiving element 170a according to the tenth embodiment.
  • the crystal growth time required for epitaxially growing each remaining semiconductor layer after the i-type InAlAs digital alloy structure electron transit layer 47 is crystal grown is about one-third shorter than that of the semiconductor light receiving element 190 according to the seventh embodiment, so that the i-type InAlAs digital alloy structure electron transit layer 47 is less likely to become disordered.
  • the upper electrode of the semiconductor light receiving element is a p-type electrode 32 in the back-illuminated APD shown in Fig. 21, and an n-type electrode 51 in the back-illuminated APD shown in Fig. 22.
  • To increase the speed it is necessary to reduce the electrode area of the front side electrode and reduce the electric capacitance.
  • the electrode area of the upper electrode is reduced, the contact resistance between the electrode and the semiconductor layer increases, which causes a problem that the RC time constant increases and the response band becomes narrower.
  • the upper electrode i.e., the n-type electrode 51
  • the n-type electrode 51 is in contact with the n-type semiconductor, so the ohmic resistance is reduced to one tenth of that of the contact between the p-type electrode and the p-type semiconductor.
  • an APD was used as an example of the semiconductor light receiving element 180 according to the eleventh embodiment, but the PD may also have an element structure in which the conductivity types are inverted, for example, from n-type to p-type and p-type to n-type in the semiconductor light receiving element 150 according to the seventh embodiment.
  • the crystal growth time required for epitaxially growing the remaining semiconductor layers after the InAlAs digital alloy structure electron transit layer is crystal grown is about one third shorter than that of the semiconductor light receiving element of the tenth embodiment, and therefore the InAlAs digital alloy structure electron transit layer is less likely to become disordered, and therefore a semiconductor light receiving element having high reliability, wideband operation, and excellent low noise characteristics can be obtained.
  • the i-type InGaAs light absorbing layer 43 can be made thinner, and the transit time of electrons and holes can be shortened, and by combining the i-type InAlAs digital alloy structure electron transit layer 47, a semiconductor light receiving element capable of further widening the bandwidth can be obtained.
  • a modified example of embodiment 11 A front-illuminated APD and a back-illuminated APD, which are examples of semiconductor light-receiving elements according to a modification of the eleventh embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the eleventh embodiment is structurally different in that the i-type InAlAs multiplication layer 45 in the front-illuminated APD and back-illuminated APD, which are examples of the semiconductor light receiving element 180 according to the eleventh embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the crystal growth time required for epitaxially growing the remaining semiconductor layers after the i-type InAlAs digital alloy structure multiplication layer is grown is approximately one-third shorter than that of the semiconductor photodetector 190 according to the seventh embodiment, and therefore disordering of the i-type InAlAs digital alloy structure multiplication layer is less likely to occur.
  • the semiconductor photodetector according to the modification of the eleventh embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and the crystal growth time required for epitaxially growing the remaining semiconductor layers after the i-type InAlAs digital alloy structure multiplication layer is grown is shorter than that of an element structure having an opposite conductivity type. This prevents the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer from becoming disordered, thereby providing an effect of providing a semiconductor photodetector which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • Embodiment 12. 23 is a cross-sectional view showing the element structure of a front-illuminated type PD, which is an example of a semiconductor light-receiving element 190 according to the twelfth embodiment.
  • the semiconductor light receiving element 190 according to the twelfth embodiment is structurally different from the semiconductor light receiving element 100 according to the first embodiment in that an electron transit layer is provided on the p-type electrode 32 side, i.e., on the light receiving portion side, of the i-type InGaAs light absorbing layer 5. That is, from the n-type InP substrate 1 side, the i-type InGaAs light absorbing layer 5, the i-type InAlGaAs/InAlAs graded layer 6, and the i-type InAlAs digital alloy structure electron transit layer 3a are formed in this order.
  • each layer of the semiconductor light receiving element 190 in embodiment 12 are the same as those in embodiment 1, so the description is omitted.
  • the hole dead space length Dh is approximately 80 nm, whereas in the case of an InAlAs digital alloy structure, the hole dead space length Dh is approximately 170 nm.
  • the hole dead space length is about twice as long as the electron dead space length, holes can travel quickly with a layer thickness of 200 nm or less. Therefore, by providing an i-type InAlAs digital alloy structure hole travel layer, a broadband PD can be achieved.
  • the semiconductor light receiving element according to the twelfth embodiment has an InAlAs digital alloy electron transit layer, which provides an effect of providing a semiconductor light receiving element that operates over a wide band.
  • Embodiment 13 24 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 200 according to the thirteenth embodiment.
  • the semiconductor light receiving element 200 according to the thirteenth embodiment is structurally different from the semiconductor light receiving element 110 according to the second embodiment in that an electron transit layer is provided on the p-type electrode 32 side, i.e., on the light receiving portion side, of the i-type InGaAs light absorbing layer 5. That is, from the n-type InP substrate 1 side, the i-type InGaAs light absorbing layer 5, the i-type InAlGaAs/InAlAs graded layer 6, and the i-type InAlAs digital alloy structure electron transit layer 3a are formed in this order.
  • each layer of the semiconductor light receiving element 200 in embodiment 13 are the same as those in embodiment 2, so the description is omitted.
  • the hole dead space length Dh is approximately 80 nm, whereas in the case of an InAlAs digital alloy structure, the hole dead space length Dh is approximately 170 nm.
  • the hole dead space length is about twice as long as the electron dead space length, holes can travel quickly with a layer thickness of 200 nm or less. Therefore, by inserting an i-type InAlAs digital alloy structure hole travel layer, it is possible to achieve a broadband APD.
  • the semiconductor light receiving element according to the thirteenth embodiment has an InAlAs digital alloy electron transit layer, which makes it possible to obtain a semiconductor light receiving element that operates over a wide band and has excellent low noise characteristics.
  • a modified example of embodiment 13 A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the thirteenth embodiment, will be described below.
  • the semiconductor light receiving element according to the modified example of the thirteenth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 200 according to the thirteenth embodiment, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.
  • the layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of the second embodiment, and therefore a description thereof will be omitted.
  • the semiconductor photodetector according to the modified example of embodiment 13 has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.
  • Embodiment 14 25 is a configuration diagram showing an optical line terminal (OLT) 260 of a 50G-PON system according to embodiment 14.
  • the optical line terminal 260 includes a forward error correction (FEC) 261, a driver amplifier 262, a light source 263, a wavelength division multiplexing (WDM) 264, a clock data recovery (CDR) 265 which is a clock data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 of the present disclosure.
  • FEC forward error correction
  • WDM wavelength division multiplexing
  • CDR clock data recovery
  • the DA-PD of the present disclosure may be applied instead of the DA-APD 268 of the present disclosure.
  • the APD of this disclosure refers to an APD described in each of the above embodiments in which the electron transit layer has an InAlAs digital alloy structure, or an APD in which both the electron transit layer and the multiplication layer have an InAlAs digital alloy structure. Furthermore, the PD of this disclosure refers to a PD described in each of the above embodiments in which the electron transit layer has an InAlAs digital alloy structure.
  • FIG. 26 is a configuration diagram showing an optical line terminal (ONU) 270 of a 50G-PON system according to embodiment 14.
  • the optical line terminal 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.
  • FIG. 27 is a configuration diagram showing an optical line terminal (OLT) 250a of a 50G-PON system as a comparative example.
  • the optical line terminal 250a as a comparative example includes a forward error correction circuit FEC251 (Forward Error Correction: FEC), a driver amplifier 252, a light source 253, an optical multiplexer/demultiplexer WDM254 (Wavelength Division Multiplexing: WDM), a digital signal processing circuit DSP255, an analog-to-digital converter ADC256 (Analog-to-digital converter: ADC), an analog-to-digital conversion circuit A burst TIA257 (Trans Impedance Amplifier), and a conventional APD258.
  • FEC251 Forward Error Correction: FEC
  • FEC Forward Error Correction
  • WDM254 Widelength Division Multiplexing: WDM
  • DSP255 digital signal processing circuit
  • ADC256 Analog-to-digital converter
  • ADC Analog-to-digital
  • the optical line terminal 250a of the 50G-PON system which is a comparative example, requires digital bandwidth compensation, i.e., a DSP 255.
  • digital bandwidth compensation is not required.
  • the DA-APD of the present disclosure i.e., an APD having at least an InAlAs digital alloy structure electron transport layer, it is possible to reduce the electrical capacitance without degrading the bandwidth.
  • Iph is the photocurrent of the APD
  • M is the multiplication factor
  • q is the unit charge
  • Id is the dark current to be multiplied
  • F is the excess noise factor of the APD
  • B is the bandwidth
  • Kb is the Boltzmann constant
  • T is the absolute temperature
  • Ft is the noise figure of the amplifier
  • Rt is the input resistance.
  • the term on the left of the denominator represents the shot noise of the APD, and the term on the right of the denominator represents the thermal noise of the amplifier.
  • the system is designed with the ionization rate ratio k for an unthinned InAlAs multiplication layer set to 0.2.
  • an APD with an InAlAs digital alloy structure as a multiplication layer that is, the DA-APD of the present disclosure
  • the dead space effect works even with a layer thickness of 100 nm or more, so it can be applied to APDs.
  • the SN ratio is improved by 3 dB when the DA-APD of the present disclosure is applied.
  • FIG. 28 is a diagram showing the configuration of an optical line terminal (OLT) of a 50G-PON system according to embodiment 14.
  • the optical line terminal 260a of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure.
  • the DA-PD of the present disclosure may be applied instead of the DA-APD 268 of the present disclosure.
  • FIG. 29 is a diagram showing the configuration of an optical line terminal (ONU) of a 50G-PON system according to embodiment 14.
  • the optical line terminal 260b of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.
  • the APD having an InAlAs digital alloy structure multiplication layer controls the thickness of the multiplication layer within a predetermined range to set the ionization rate ratio k to zero, thereby making the multiplication time in formula (6) almost zero.
  • the response band of the APD does not deteriorate even if the multiplication factor is increased.
  • the band is limited only by the RC time constant and the carrier travel time, as in the case of conventional PDs. Therefore, the wide band required for the 50G-PON system is possible, and reception is possible without digital band compensation by a DSP.
  • the DA-APD or DA-PD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining an optical line terminal that can increase the transmission distance of an optical signal and reduce power consumption.
  • FIG. 30 is a diagram showing a configuration of a multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 15.
  • Fig. 31A and Fig. 31B are diagrams showing received waveforms of the multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 15.
  • the multilevel intensity modulation transmitter/receiver 300 is a multilevel intensity modulation transmitter/receiver using the PAM (Pulse Amplitude Modulation) method, which is a multilevel intensity modulation method.
  • PAM Pulse Amplitude Modulation
  • the digital signal generated in the DSP 301 is converted to analog in the DAC 302a, amplified in the driver amplifier 303, and drives the light source 304 consisting of a DFB laser or EML to emit an optical signal to the optical fiber cable 310.
  • the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element of the present disclosure, where the optical signal is converted to a current and multiplied, and is then amplified in the Linear-TIA 306, converted to a digital signal in the ADC 302b, and signal processing is performed by the DSP 301.
  • the DA-PD of the present disclosure may be used instead of the DA-APD 305 of the present disclosure.
  • TDECQ Transmitter Dispersion and Eye Closure Quaternary
  • the optical modulation amplitude is the total amplitude from level 0 to level 3
  • Qt is a value dependent on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers)
  • R is the additional noise value required to achieve the SER value.
  • TDECQ (dB) is defined as, for example, 3 dB or less. In order to reduce TDECQ (dB), (1) The eye opening at each level must be uniform. (2) The noise at each level must be low.
  • the semiconductor light receiving element In order for the eye opening at each of the four levels, which have different optical signal strengths, to be uniform, the semiconductor light receiving element must have excellent linearity.
  • a semiconductor light receiving element has good linearity when the photocurrent Iph increases in proportion to the optical input power Pin. In other words, even if the optical input power Pin changes, if Iph/Pin is constant, it can be said to have good linearity.
  • PAM needs to receive signals with a wide range of strengths, from low to high, it needs to have an excellent dynamic range.
  • the dynamic range can be said to be good.
  • the received waveform in Figure 31B if the linearity and dynamic range deteriorate, the eye opening formed between levels 2 and 3 deteriorates.
  • Figures 32A and 32B are diagrams for explaining the operation of a PD when a high optical input is applied.
  • a space charge effect acts as if a voltage drop occurs due to the series resistance and no voltage is applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution as shown in Figure 32B.
  • Rsc is the resistance due to the space charge effect
  • Rd is the element resistance
  • Rlo is the load resistance.
  • Rd and the load resistance are usually several tens of ohms, but Rsc can be several hundreds of ohms or more.
  • Rsc when the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, Rsc can be expressed by the following formula (19).
  • Rsc W ⁇ Td/(2 ⁇ S) (19)
  • W is the thickness of the depletion layer
  • ⁇ is the dielectric constant
  • S is the pn junction area.
  • the resistance Rsc due to the space charge effect is proportional to the time it takes for electrons and holes to pass through the depletion layer, Td, so that Rsc can be reduced by increasing the speed of electrons and holes passing through to reduce Td.
  • the transit time of electrons in the electron transport layer is short, so Rsc is reduced, and as a result, the eye opening becomes uniform, so that TDECQ satisfies the specified value. Furthermore, it is possible to increase the transmission distance and reduce the driving current of the transmitting laser.
  • FIG. 33 is a diagram for explaining the operation of the APD at high light input.
  • N is the Emmons coefficient (which depends gently on the ionization rate ratio k)
  • M is the multiplication factor
  • ⁇ av is the average time it takes for electrons and holes to travel through the multiplication layer.
  • the residence time Tdm excludes the one-way transit time that carriers take to traverse the multiplication layer.
  • Figure 34 shows the residence time Tdm of electrons and holes for each material that makes up the multiplication layer.
  • the residence time Tdm within the multiplication layer is dramatically reduced. In other words, electrons and holes are quickly discharged from the multiplication layer, suppressing the space charge effect in the multiplication layer, resulting in improved linearity and dynamic range in the InAlAs digital alloy structure multiplication layer.
  • the eye opening of PAM4 was non-uniform as shown in FIG. 31B, but with the DA-APD disclosed herein, the eye opening is uniform as shown in FIG. 31A, making it possible for TDECQ to satisfy the specified value. Therefore, when the DA-APD disclosed herein is used, an APD can be used in a PAM transceiver, which makes it possible to increase the transmission distance of optical signals and reduce the drive current of the transmitting laser.
  • the DA-APD or DA-PD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining a multi-level intensity modulation transmitting/receiving device that can increase the transmission distance of an optical signal and reduce power consumption.
  • Fig. 35 is a schematic diagram showing the configuration of a radio on fiber system 400 (Radio on fiber: RoF) according to a sixteenth embodiment.
  • Fig. 36 is a schematic diagram showing the configuration of a radio on fiber system 450, which is a comparative example.
  • the radio on fiber system 400 includes a light source 401, a transmission line 402 such as an optical fiber cable, a DA-APD 403 of the present disclosure, and an antenna 404. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 403 of the present disclosure.
  • an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal.
  • the converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission path 402.
  • the transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 according to the present disclosure.
  • the converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.
  • the radio-on-fiber system 400 is capable of efficiently supplying signals to an antenna 404 that is located at a distance from an electrical signal source.
  • the system since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has the advantage of being simple in configuration and consuming little power.
  • the time Td for electrons and holes to pass through the depletion layer is short, so Rsc is small.
  • a response with good linearity can be obtained over a wide dynamic range, and a large current amplitude can be obtained.
  • the residence time Tdm of electrons and holes in the multiplication layer is short, so changes in the electric field distribution in the multiplication layer are suppressed.
  • a response with excellent linearity can be obtained over a wide dynamic range.
  • the DA-APD 403 of the present disclosure multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.
  • the multiplication factor of the DA-APD403 disclosed herein can be in the range of 1.2 to 10 times. However, as the multiplication factor increases, the signal becomes distorted, so it is desirable to use a multiplication factor in the range of 1.2 to 5 times. Also, considering the loss of the optical fiber and the fact that the quantum efficiency of the APD is about 80% and not 100%, it is optimal to use a multiplication factor of 2 to 3 times to compensate for such losses.
  • the radio-on-fiber system of the sixteenth embodiment is configured using the DA-APD or DA-PD of the present disclosure, which has the effect of making it possible to output a strong radio signal even if the optical transmission distance is long.
  • Embodiment 17. 37 is a schematic diagram showing a configuration of a digital coherent receiving apparatus 500 according to embodiment 17.
  • the digital coherent receiving apparatus 500 according to embodiment 17 is characterized in that it uses the DA-APD 505a of the present disclosure. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 505a of the present disclosure.
  • optical signals with both phase and intensity modulated are polarization multiplexed and transmitted through optical fiber.
  • digital coherent receiving device 500 the optical signal input from optical fiber cable 501 is first polarized and separated by polarization separator 502. After polarization separation, each polarized signal light is input to 90-degree hybrid device 503a and 90-degree hybrid device 503b, respectively. Meanwhile, the laser light locally emitted from semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.
  • the signal light and the laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output.
  • the four optical signals i.e., the orthogonal I and Q components for each polarization, totaling four optical signals, are each incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, each of which is made up of two DA-APDs 505a of the present disclosure connected in series as a pair.
  • the electrical signal output from the balanced detector 505 is input to the DSP 506.
  • the digital coherent receiving device 500 according to the seventeenth embodiment has the above configuration.
  • FIG. 38A is a diagram showing waveforms of a digital coherent receiving device which is a comparative example
  • FIG. 38B is a diagram showing waveforms of a digital coherent receiving device according to embodiment 17.
  • a PD was used as a semiconductor light receiving element that receives signal light.
  • the DA-APD 505a disclosed herein can multiply the signal, making it possible to suppress the local light.
  • FIG. 33 an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, resulting in saturation of the multiplication factor and making it impossible to ensure a dynamic range. This causes problems not only in that a sufficient amplitude of the electrical signal cannot be obtained, but also in that the analog signal is distorted.
  • FIG. 38A in the comparative example, the interval between waveforms A1 and B1 becomes narrow, and the intensity signal of the constellation waveform is distorted, making it difficult to apply an APD.
  • the time Td for electrons and holes to pass through the depletion layer is short, so Rsc is small. Since the effect of the resistance Rsc due to the space charge effect is small, a constellation waveform with excellent linearity can be obtained over a wide dynamic range.
  • the residence time Tdm of electrons and holes in the multiplication layer is short, so that changes in the electric field distribution in the multiplication layer are suppressed.
  • FIG. 38B when the DA-APD 505a as disclosed herein is used, the interval between waveform A and waveform B becomes wider, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if the signal is multiplied by the APD, the original signal can be reproduced, and a large current amplitude can be obtained.
  • the multiplication factor of the DA-APD505a disclosed herein can be within the range of 1.2 to 10 times. However, as the signal becomes distorted as the multiplication factor increases, it is preferable to use a multiplication factor within the range of 1.2 to 5 times.
  • the DA-APD or DA-PD disclosed herein is applied as a semiconductor photodetector for receiving an optical signal, and thus it is possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.
  • Embodiment 18. 39 is a schematic diagram showing the configuration of a SPAD sensor (Single Photon Avalanche Diode) system according to embodiment 18.
  • the SPAD sensor system 600 includes a photoelectron measurement circuit 601, a SPAD sensor 602 including the DA-APD of the present disclosure, and a quenching circuit 603.
  • the SPAD can be used not only to count the number of photons but also as a light receiving element with good sensitivity. However, it is necessary to constantly repeat the A: Quenching voltage, which will be described later, and the B: Geiger mode voltage, which will be described later. The repetition period is on the order of nanoseconds to microseconds. If the repetition period of the A: Quenching voltage and B: Geiger mode voltage can be shortened, it is possible to increase the response speed of the SPAD. In order to increase the response speed of the SPAD, it is necessary to reduce the pn junction capacitance, and it is effective to increase the thickness of the depletion layer by thickening the transport layer.
  • a DA-APD having at least the InAlAs digital alloy structure electron transport layer of the present disclosure even if the transport layer is made thick, the transport time is short, so there is little degradation in response speed.
  • the DA-APD of the present disclosure when used in a SPAD, it becomes possible to switch between A: Quenching voltage and B: Geiger mode voltage, which have a fast response speed, and it is possible to improve the response band of the SPAD sensor 602.
  • the SPAD sensor system 600 uses a DA-APD5 having an electron transport layer and a multiplication layer made of the InAlAs digital alloy structure of the present disclosure
  • photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602 made of the DA-APD of the present disclosure, generating pairs of electrons and holes, and the electrons flow into the multiplication layer.
  • An electric field approximately 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.
  • This state is called the Geiger mode.
  • the electrons are multiplied to a level of 106.
  • the generated electrons flow as a current and flow into the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.
  • FIG. 40A is a diagram showing the multiplication characteristics of a SAPD sensor system as a comparative example
  • FIG. 40B is a diagram showing the multiplication characteristics of a SAPD sensor system according to embodiment 18. If an electric field equal to or greater than the avalanche breakdown electric field is continuously applied to the multiplication layer, an excess current will flow, so after detecting a photon, the voltage applied to the SPAD sensor 602 is quickly reduced to weaken the electric field in the multiplication layer. This is called quenching. In other words, as shown in the comparison of the multiplication characteristics of the SPAD sensor in FIG. 40A and FIG.
  • the voltage is reduced from B: Geiger mode voltage to A: quenching voltage to stop the chain multiplication, and then the voltage is increased again from A: quenching voltage to B: Geiger mode voltage to make it possible to receive incident photons with high sensitivity.
  • the quenching circuit 603 that controls the voltage is classified into a passive circuit and an active circuit.
  • a passive circuit when a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in the resistor connected in series to the SPAD sensor 602, and the voltage applied to the SPAD sensor 602 decreases.
  • the quenching circuit 603 operates to repeatedly apply a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor 602.
  • the SPAD sensor system 600 according to the eighteenth embodiment can be used not only for counting the number of photons but also as a highly sensitive semiconductor light receiving element. However, it is necessary to constantly repeat the voltage from B: Geiger mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger mode voltage can be reduced, the repetition period can be shortened and the response speed of the SPAD sensor system 600 can be increased.
  • the passive quenching circuit 603 it is possible to reduce the resistance value connected in series to the SPAD sensor 602, which increases the response speed of the SPAD sensor 602.
  • the voltage amplitude is reduced, which allows for simplification of the drive circuit and power saving, and also makes it possible to widen the response band.
  • the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field is increased, the dead space length becomes shorter, so the multiplication factor increases rapidly and leads to breakdown.
  • the APD of the InAlAs random alloy multiplication layer and the APD having the digital alloy InAlAs multiplication layer with a thick multiplication layer if the voltage at which the dark current exceeds 10 ⁇ A is set as the breakdown voltage, the multiplication factor at 90% of the breakdown voltage exceeds 10 times.
  • the multiplication factor at a voltage of 90% of the breakdown voltage is 10 times or less.
  • the voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field buffer layer, so here we verify the effect using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (approximately 12 V), the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.
  • Figure 41 shows the calculated difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAlAs digital alloy structure multiplication layer of the present disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is 170 kV/cm, which is exceptionally low. The electric field is 120 kV/cm lower than that of an InAlAs digital alloy structure multiplication layer having a layer thickness of 200 nm or more that has a similar superlattice structure to the InAlAs digital alloy structure multiplication layer of the present disclosure but is not thinned.
  • the DA-APD of the present disclosure is used in the SPAD sensor, and therefore the difference between the quenching electric field and the Geiger mode electric field, that is, the applied voltage difference, can be reduced, thereby achieving the effect of obtaining a SPAD sensor system that enables an improved response band, a simplified quenching circuit, and reduced power consumption.
  • Fig. 42 is a diagram showing the configuration of a LIDAR (Light Detection and Ranging: LiDAR) device according to embodiment 19.
  • Fig. 43A is a diagram showing a received waveform of an APD 700 of a LIDAR device that is a comparative example
  • Fig. 43B is a diagram showing a received waveform of the APD of the LIDAR device 700 according to embodiment 19.
  • the LIDAR device 700 includes a light source 701, a DA-APD 702 of the present disclosure, a TIA 703, and a distance measurement circuit 704. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 702 of the present disclosure.
  • the light source 701 emits pulsed light (hereinafter referred to as pulsed light) or frequency-modulated light.
  • the distance to the object 705 is calculated by measuring the time it takes for the pulsed light emitted from the light source to hit the object 705 and return to the semiconductor light receiving element.
  • An LD or the like is used as the light source 701.
  • the amount of light from the LD needs to be increased, but for eye safety reasons, there is an upper limit to the amount of light emitted from the LD. For this reason, it is necessary to increase the sensitivity of the semiconductor light receiving element. Therefore, in the LIDAR device 700 according to the 19th embodiment, the DA-APD 702 disclosed herein is used with high amplification as the semiconductor light receiving element.
  • the detected light pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and the time when the intensity of the pulse signal exceeds a preset discrimination line is determined to be the arrival time, as shown in Figures 43A and 43B.
  • the timing of the emission of the light pulse from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between the two by the speed of light and dividing by 2.
  • a method is also used in which frequency-modulated light is emitted and the distance is calculated from the frequency difference between the emitted wave and the returning reflected wave.
  • the time Td for electrons and holes to pass through the depletion layer is short, and thus the deterioration of response speed is small. Therefore, a highly sensitive receiver can be realized by reducing the pn junction capacitance of the APD and increasing the feedback resistance of the TIA 703. As a result, not only can it be possible to measure the distance to a distant object 705, but the light output of the light source 701 can be reduced, thereby saving power and improving safety for the eyes.
  • the tunnel current does not increase, so it is easy to identify weak light.
  • the residence time in the multiplication layer is short, so as shown in FIG. 43B, a current pulse with a large peak intensity is obtained, and the identification sensitivity is high.
  • ⁇ Effects of the nineteenth embodiment> As described above, according to the LIDAR device of embodiment 19, reflected light from an object is received by the DA-APD or DA-PD of the present disclosure, which makes it possible to measure the distance to a distant object, reduces the power consumption of the light source, and provides a LIDAR device that is also safer for the eyes.
  • this includes modifying, adding, or omitting at least one component, and even extracting at least one component and combining it with a component of another embodiment.

Landscapes

  • Light Receiving Elements (AREA)

Abstract

Un élément de réception de lumière à semi-conducteur (110) de la présente divulgation comprend : un substrat InP (1) ; une couche semi-conductrice de type n (2a) formée sur le substrat InP (1) ; une couche de circulation d'électrons (3) formée sur la couche semi-conductrice de type n (2a) et comprenant une structure d'alliage numérique ; une couche de relaxation de champ électrique de type n (12) formée sur la couche de circulation d'électrons (3) ; une couche de multiplication (13) formée sur la couche de relaxation de champ électrique de type n (12) ; une couche de relaxation de champ électrique de type p (14) formée sur la couche de multiplication (13) ; et une couche d'absorption de lumière (5) formée sur la couche de relaxation de champ électrique de type p (14).
PCT/JP2023/040703 2023-11-13 2023-11-13 Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar Pending WO2025104772A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2023/040703 WO2025104772A1 (fr) 2023-11-13 2023-11-13 Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar
JP2024514404A JP7511793B1 (ja) 2023-11-13 2023-11-13 半導体受光素子、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/040703 WO2025104772A1 (fr) 2023-11-13 2023-11-13 Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar

Publications (1)

Publication Number Publication Date
WO2025104772A1 true WO2025104772A1 (fr) 2025-05-22

Family

ID=91714580

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/040703 Pending WO2025104772A1 (fr) 2023-11-13 2023-11-13 Élément de réception de lumière à semi-conducteur, dispositif de terminaison de ligne optique, dispositif d'émission/réception à modulation d'intensité multiniveau, dispositif de réception cohérente numérique, système radio sur fibre, système de capteur spad et dispositif lidar

Country Status (2)

Country Link
JP (1) JP7511793B1 (fr)
WO (1) WO2025104772A1 (fr)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004543A (ja) * 2011-06-10 2013-01-07 Fujitsu Ltd 受光デバイス、これを用いた光受信機、及び受光デバイスの製造方法
JP2013165104A (ja) * 2012-02-09 2013-08-22 Mitsubishi Electric Corp 半導体受光素子
JP2014096637A (ja) * 2012-11-07 2014-05-22 Kddi Corp Ｒｆ信号光伝送システム
JP2014176072A (ja) * 2013-03-13 2014-09-22 Nippon Telegr & Teleph Corp <Ntt> 通信ネットワーク評価システムおよび方法
JP2016025513A (ja) * 2014-07-22 2016-02-08 日本電信電話株式会社 コヒーレント光受信機
JP2017157974A (ja) * 2016-02-29 2017-09-07 日本オクラロ株式会社 光情報伝送システム、及び光送信器
WO2019087783A1 (fr) * 2017-10-31 2019-05-09 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et système d'imagerie
JP7224560B1 (ja) * 2022-06-22 2023-02-17 三菱電機株式会社 半導体受光素子及び半導体受光素子の製造方法
JP7307287B1 (ja) * 2022-07-19 2023-07-11 三菱電機株式会社 半導体受光素子

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116917825A (zh) * 2020-09-28 2023-10-20 卢米诺有限责任公司 具有低噪声雪崩光电二极管的激光雷达系统
CN114122185B (zh) * 2021-11-23 2023-02-17 中国科学院半导体研究所 一种短波双色红外探测器及其制备方法
CN114361285A (zh) * 2021-12-31 2022-04-15 上海科技大学 1.55微米波段雪崩光电探测器及其制备方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013004543A (ja) * 2011-06-10 2013-01-07 Fujitsu Ltd 受光デバイス、これを用いた光受信機、及び受光デバイスの製造方法
JP2013165104A (ja) * 2012-02-09 2013-08-22 Mitsubishi Electric Corp 半導体受光素子
JP2014096637A (ja) * 2012-11-07 2014-05-22 Kddi Corp Ｒｆ信号光伝送システム
JP2014176072A (ja) * 2013-03-13 2014-09-22 Nippon Telegr & Teleph Corp <Ntt> 通信ネットワーク評価システムおよび方法
JP2016025513A (ja) * 2014-07-22 2016-02-08 日本電信電話株式会社 コヒーレント光受信機
JP2017157974A (ja) * 2016-02-29 2017-09-07 日本オクラロ株式会社 光情報伝送システム、及び光送信器
WO2019087783A1 (fr) * 2017-10-31 2019-05-09 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et système d'imagerie
JP7224560B1 (ja) * 2022-06-22 2023-02-17 三菱電機株式会社 半導体受光素子及び半導体受光素子の製造方法
JP7307287B1 (ja) * 2022-07-19 2023-07-11 三菱電機株式会社 半導体受光素子

Also Published As

Publication number Publication date
JPWO2025104772A1 (fr) 2025-05-22
JP7511793B1 (ja) 2024-07-05

Similar Documents

Publication Publication Date Title
Li et al. High-saturation-current charge-compensated InGaAs-InP uni-traveling-carrier photodiode
Nada et al. A 42-GHz bandwidth avalanche photodiodes based on III-V compounds for 106-Gbit/s PAM4 applications
Ferraro et al. Position sensing and high bandwidth data communication using impact ionization engineered APD arrays
TW201731120A (zh) 光偵測元件
US5308995A (en) Semiconductor strained SL APD apparatus
US20190371956A1 (en) Avalanche Photodetector with Single Mesa Shape
Watanabe et al. Reliability of mesa-structure InAlGaAs-InAlAs superlattice avalanche photodiodes
US5594237A (en) PIN detector having improved linear response
Nada et al. Inverted p-down pin photodiode exceeding 70-GHz bandwidth featuring low operating bias voltage of 2 V
TWI664718B (zh) 凸台狀累增光偵測器元件
JPS5984589A (ja) アバランシフオトダイオード
JP7511793B1 (ja) 半導体受光素子、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置
JP7654146B1 (ja) 半導体受光素子、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置
JP7471550B1 (ja) 半導体受光素子、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置
Okimoto et al. High responsivity and reliability of InP-based waveguide avalanche photodiodes with butt-joint coupled structure
JP7615412B1 (ja) 半導体受光素子、半導体受光素子の製造方法、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置
Huang et al. Highly Reliable, Cost-effective and Temperature-stable Top-illuminated Avalanche Photodiode (APD) for 100G Inter-Datacenter ER4-Lite Applications.
JP7661633B1 (ja) 半導体受光素子、光回線終端装置、多値強度変調送受信装置、デジタルコヒーレント受信装置、光ファイバ無線システム、ｓｐａｄセンサーシステム、及びライダー装置
Yagyu et al. Recent advances in AlInsAs avalanche photodiodes
Nada et al. Practically implementable high-sensitivity 10-Gbit/s avalanche photodiode using inverted p-down design
Takahashi et al. Over 25-dB dynamic range 10-/1-Gbps optical burst-mode receiver using high-power-tolerant APD
TWI724886B (zh) 具複數累增層的單光子偵測器
Beling et al. Advances in photodetectors and optical receivers
Tanaka et al. Highly sensitive and highly reliable APD for 10 Gbit/s optical communication systems
Dries et al. In0. 53Ga0. 47As/In0. 52Al0. 48As separate absorption, charge, and multiplication layer long wavelength avalanche photodiode

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2024514404

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2024514404

Country of ref document: JP