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WO2025199680A1 - Procédés de conception de bloc de synchronisation - Google Patents

Procédés de conception de bloc de synchronisation

Info

Publication number
WO2025199680A1
WO2025199680A1 PCT/CN2024/083571 CN2024083571W WO2025199680A1 WO 2025199680 A1 WO2025199680 A1 WO 2025199680A1 CN 2024083571 W CN2024083571 W CN 2024083571W WO 2025199680 A1 WO2025199680 A1 WO 2025199680A1
Authority
WO
WIPO (PCT)
Prior art keywords
syncblock
shot
pss
pbch
sss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/083571
Other languages
English (en)
Inventor
Chenmeng LI
Wen Tang
Tao Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Singapore Pte Ltd
Original Assignee
MediaTek Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Singapore Pte Ltd filed Critical MediaTek Singapore Pte Ltd
Priority to PCT/CN2024/083571 priority Critical patent/WO2025199680A1/fr
Priority to PCT/CN2025/081533 priority patent/WO2025201010A1/fr
Publication of WO2025199680A1 publication Critical patent/WO2025199680A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H04W56/0015—Synchronization between nodes one node acting as a reference for the others

Definitions

  • the invention discussed below relates generally to wireless communication, and more particularly, to methods for synchronization block pattern design.
  • the signal-to-noise ratio received by the receiver from the transmitter is often low due to poor background environment or long communication distances.
  • time or frequency domain signal accumulation techniques are employed.
  • the transmitter repeats the transmission of a segment of the same signal, while the receiver accumulates all the repeated signals for detection, demodulation, or decoding, or accumulates the detection or demodulation results of each repeated signal segment as the final result.
  • this patent proposes a method for synchronization signal and information pattern design sent by the transmitter to enhance the success rate of detection or decoding at the receiver.
  • the method of synchronization block (SyncBlock) design including the SyncBlock content, periodicity, location in time domain, size in time domain and resource.
  • PSS/SSS/PBCH shot pattern design within a SyncBlock including the shot definition, shot size, shot location in time domain and shot content.
  • FIG. 3 illustrates another exemplary diagram of PSS, SSS and PBCH shot pattern design.
  • the SyncBlock periodicity start symbol is the SyncBlock location reference point in time domain
  • SyncBlock One or multiple SyncBlock (s) is within a SyncBlock periodicity, and each SyncBlock can be described using the method of alternative#1.
  • the one or multiple SyncBlock (s) within the same SyncBlock periodicity is transmitted by the transmitter via the same beam or different beam.
  • the one or multiple SyncBlock (s) within the same SyncBlock periodicity have the same structure and/or pattern, and have different time domain locations.
  • FIG. 1 an exemplary diagram of SyncBlock design is descripted.
  • Both SyncBlock 1 and SyncBlock 2 occurs periodically according to the SyncBlock periodicity.
  • PSS PSS, SSS or PBCH shot pattern
  • the shot content of each PSS, SSS or PBCH shot within the same SyncBlock can be the same or different.
  • the payload of the 1 st PBCH shot and 2 nd PBCH shot can be the same or different.
  • the shot pattern design in the alternative#2 can be applied for all of PSS, SSS and PBCH.
  • FIG. 2 For example, as is shown is Figure 2, an exemplary diagram of shot pattern design within a SyncBlock is descripted. There are 3 PSS shots, 4 PBCH shots and 3 SSS shots within the SyncBlock.
  • an exemplary diagram of shot pattern design within a SyncBlock is descripted.
  • PSS shots and PBCH shots occur within the same SyncBlock.
  • Combinations such as “at least one of A, B, or C, ” “one or more of A, B, or C, ” “at least one of A, B, and C, ” “one or more of A, B, and C, ” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

En raison de différents environnements d'arrière-plan, des distances de communication et des réglementations nationales/régionales, différents modèles de signal de synchronisation et d'informations doivent être proposés. Selon un aspect, la divulgation concerne un procédé de conception de bloc de synchronisation (SyncBlock), comprenant le contenu SyncBlock, la périodicité, l'emplacement dans le domaine temporel, la taille dans le domaine temporel et la ressource. Selon un autre aspect, la divulgation concerne une conception de modèle de plan PSS/SSS/PBCH dans un SyncBlock, y compris la définition du plan, la taille du plan, l'emplacement du plan dans le domaine temporel et le contenu du plan. Selon un autre aspect, la divulgation concerne un procédé de conception de modèle de plan PSS destiné à l'amélioration des performances de détection. L'objectif de la conception de modèle de plan PSS est de permettre que l'écart entre le ou les plans PSS à l'intérieur du ou des SyncBlock (s) soit différent les uns des autres. Plusieurs exemples typiques sont présentés dans la divulgation.
PCT/CN2024/083571 2024-03-25 2024-03-25 Procédés de conception de bloc de synchronisation Pending WO2025199680A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2024/083571 WO2025199680A1 (fr) 2024-03-25 2024-03-25 Procédés de conception de bloc de synchronisation
PCT/CN2025/081533 WO2025201010A1 (fr) 2024-03-25 2025-03-10 Procédés de conception de bloc de synchronisation améliorée dans des communications sans fil

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2024/083571 WO2025199680A1 (fr) 2024-03-25 2024-03-25 Procédés de conception de bloc de synchronisation

Publications (1)

Publication Number Publication Date
WO2025199680A1 true WO2025199680A1 (fr) 2025-10-02

Family

ID=97218210

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2024/083571 Pending WO2025199680A1 (fr) 2024-03-25 2024-03-25 Procédés de conception de bloc de synchronisation
PCT/CN2025/081533 Pending WO2025201010A1 (fr) 2024-03-25 2025-03-10 Procédés de conception de bloc de synchronisation améliorée dans des communications sans fil

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/CN2025/081533 Pending WO2025201010A1 (fr) 2024-03-25 2025-03-10 Procédés de conception de bloc de synchronisation améliorée dans des communications sans fil

Country Status (1)

Country Link
WO (2) WO2025199680A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180302182A1 (en) * 2017-04-14 2018-10-18 Qualcomm Incorporated Synchronization signal block designs for wireless communication
CN111194570A (zh) * 2017-10-06 2020-05-22 高通股份有限公司 用于同步设计的技术和装置
WO2020142999A1 (fr) * 2019-01-10 2020-07-16 Mediatek Singapore Pte. Ltd. Bloc de signal de synchronisation de liaison latérale nr v2x
CN111885696A (zh) * 2020-07-07 2020-11-03 武汉虹信通信技术有限责任公司 5g nr时钟频率同步方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180302182A1 (en) * 2017-04-14 2018-10-18 Qualcomm Incorporated Synchronization signal block designs for wireless communication
CN111194570A (zh) * 2017-10-06 2020-05-22 高通股份有限公司 用于同步设计的技术和装置
WO2020142999A1 (fr) * 2019-01-10 2020-07-16 Mediatek Singapore Pte. Ltd. Bloc de signal de synchronisation de liaison latérale nr v2x
CN111885696A (zh) * 2020-07-07 2020-11-03 武汉虹信通信技术有限责任公司 5g nr时钟频率同步方法及装置

Also Published As

Publication number Publication date
WO2025201010A1 (fr) 2025-10-02

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