WO2025197635A1 - Imaging device - Google Patents

Abstract

An imaging device according to the present invention comprises: a first substrate; a second substrate that is located closer to a second surface than a first surface of the first substrate; a first bonding surface that is located between the first substrate and the second substrate; a photoelectric conversion unit that is located closer to the first surface than the second surface of the first substrate and converts incident light into an electric charge; a first wire that is located between the photoelectric conversion unit and the first substrate; a second wire that is located between the second surface of the first substrate and the first bonding surface; a third wire that is located between a third surface of the second substrate and the first bonding surface; and a first via of which at least a portion is located in the first substrate. The first substrate and the second substrate are laminated with the first bonding surface therebetween. The first wire and the second wire are electrically connected via the first via.

Description

Imaging device

This disclosure relates to an imaging device.

CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras and other devices. One imaging device that uses such image sensors is a stacked imaging device with a structure in which the photoelectric conversion unit is located on the light-incident side of the semiconductor substrate.

For example, Patent Document 1 discloses an imaging device in which the circuitry of an imaging cell including a photoelectric conversion unit and peripheral circuits are formed on the same semiconductor substrate.

JP 2018-50035 A

There is a demand for miniaturization in imaging devices.

This disclosure therefore provides an imaging device that can be miniaturized.

An imaging device according to one aspect of the present disclosure comprises: a first substrate including a first surface and a second surface opposite the first surface, the first surface being closer to a position where incident light enters the imaging device than the second surface; a second substrate located closer to the second surface of the first substrate than the first surface of the first substrate, the second substrate including a third surface and a fourth surface opposite the third surface, the third surface being closer to the first substrate than the fourth surface; a first bonding surface located between the first substrate and the second substrate; a photoelectric conversion unit located closer to the first surface of the first substrate than the second surface of the first substrate and converting the incident light into electric charges; a first wiring located between the photoelectric conversion unit and the first substrate; a second wiring located between the second surface of the first substrate and the first bonding surface; a third wiring located between the third surface of the second substrate and the first bonding surface; and a first via, at least a portion of which is located within the first substrate. The first substrate and the second substrate are stacked via the first bonding surface, and the first wiring and the second wiring are electrically connected via the first via.

This disclosure makes it possible to miniaturize imaging devices.

FIG. 1 is a block diagram showing an example of a schematic configuration of an imaging device according to the first embodiment. FIG. 2 is a diagram showing a circuit configuration of the imaging device according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing an example of a device structure of the imaging device according to the first embodiment. FIG. 4 is a plan view schematically illustrating an example of a planar layout of the imaging device according to the first embodiment. FIG. 5A is a cross-sectional view illustrating a process for forming a wafer including a pixel substrate. FIG. 5B is a cross-sectional view illustrating a process for forming a wafer including a pixel substrate. FIG. 5C is a cross-sectional view for explaining a process of forming a wafer including a pixel substrate. FIG. 5D is a cross-sectional view illustrating a process for forming a wafer including a pixel substrate. FIG. 6A is a cross-sectional view illustrating a process for forming a wafer including a circuit board. FIG. 6B is a cross-sectional view illustrating a process for forming a wafer including a circuit board. FIG. 7A is a cross-sectional view for explaining a process subsequent to bonding of a wafer including a pixel substrate and a wafer including a circuit substrate. FIG. 7B is a cross-sectional view for explaining a process subsequent to bonding of the wafer including the pixel substrate and the wafer including the circuit substrate. FIG. 8 is a schematic cross-sectional view showing an example of a device structure of an imaging device according to Modification 1 of Embodiment 1. In FIG. FIG. 9 is a schematic cross-sectional view showing an example of a device structure of another imaging device according to the first modification of the first embodiment. FIG. 10 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to the second modification of the first embodiment. FIG. 11 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to the third modification of the first embodiment. FIG. 12 is a schematic cross-sectional view showing an example of a device structure of another imaging device according to the third modification of the first embodiment. FIG. 13 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to the fourth modification of the first embodiment. FIG. 14 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to Modification 5 of Embodiment 1. In FIG. FIG. 15 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to the sixth modification of the first embodiment. FIG. 16 is a schematic cross-sectional view showing an example of a device structure of an imaging device according to the seventh modification of the first embodiment. FIG. 17 is a schematic cross-sectional view illustrating an example of a device structure of an imaging device according to the second embodiment. FIG. 18 is a plan view for explaining the size of the first via. FIG. 19 is a plan view schematically illustrating an example of a planar layout of the imaging device according to the second embodiment. FIG. 20 is a plan view schematically showing an example of a planar layout in the case where a pixel isolation region is not formed in the imaging device according to the second embodiment. FIG. 21 is a plan view schematically showing a first example of a planar layout of the imaging device according to the second embodiment. FIG. 22 is a plan view schematically showing a second example of the planar layout of the imaging device according to the second embodiment. FIG. 23 is a plan view schematically showing a third example of the planar layout of the imaging device according to the second embodiment. FIG. 24 is a block diagram illustrating an example of the configuration of a camera system according to the third embodiment.

(Summary of the Disclosure)
As an overview of one aspect of the present disclosure, an example of an imaging device according to the present disclosure is shown below.

(First Aspect)
For example, an imaging device according to a first aspect of the present disclosure includes a first surface and a second surface opposite to the first surface, the first surface being closer to a position where incident light enters the imaging device than the second surface; a second substrate located closer to the second surface of the first substrate than the first surface of the first substrate, the second substrate including a third surface and a fourth surface opposite to the third surface, the third surface being closer to the first substrate than the fourth surface; a first bonding surface located between the first substrate and the second substrate; a photoelectric conversion unit located closer to the first surface than the second surface of the first substrate and converting the incident light into electric charges; a first wiring located between the photoelectric conversion unit and the first substrate; a second wiring located between the second surface of the first substrate and the first bonding surface; a third wiring located between the third surface of the second substrate and the first bonding surface; The first substrate and the second substrate are stacked with the first bonding surface interposed therebetween, and the first wiring and the second wiring are electrically connected to each other through the first via.

This allows the imaging device's circuits to be formed separately on the first and second substrates, thereby enabling the imaging device to be miniaturized. Furthermore, in the imaging device of this embodiment, the first wiring located closer to the first surface than the second surface of the first substrate is electrically connected to the second wiring located between the second surface of the first substrate and the first bonding surface via the first via. This also allows the imaging device to be miniaturized. Specifically, if the first via is used for metal bonding between the first and second substrates, a deep trench must be formed that penetrates the first substrate and extends to the second substrate, and the diameter of the first via must be increased according to the trench depth. Furthermore, in this case, a region must be provided in the first substrate to avoid the effects of stress caused by the formation of the via metal bonding. For example, the distance between the first via and the device element formed on the first substrate, and the distance between multiple first vias must be increased. As a result, the substrate becomes larger. In the imaging device according to this aspect, the first via is electrically connected to the second wiring located between the first bonding surface and the second surface of the first substrate, and the first via is not used for bonding the first substrate and the second substrate together, allowing for a more compact imaging device. Furthermore, in the imaging device according to this aspect, the first via electrically connects the first wiring to the second wiring located between the first bonding surface and the second surface of the first substrate, allowing for a shorter length of the first via than the distance from the first wiring to the first bonding surface. Generally, the longer a via that penetrates a substrate, the larger its diameter. Therefore, by shortening the length of the first via, the diameter of the first via can be reduced, thereby narrowing the area required to form the first via. This allows for a more compact imaging device.

In this specification, being able to miniaturize an imaging device means being able to reduce the area of the board in a plan view.

(Second Aspect)
Furthermore, for example, in the imaging device according to the first aspect of the present disclosure, the first via may be a through silicon via (TSV).

This allows the diameter of the first via, which is a TSV, to be reduced.

(Third Aspect)
Also, for example, the imaging device according to the first or second aspect of the present disclosure may further include a second via located within the first substrate, and the first wiring and the first via may be electrically connected via the second via.

This allows the length of the first via to be further shortened, further reducing the diameter of the first via, thereby further reducing the size of the imaging device.

(Fourth aspect)
Also, for example, the imaging device according to the third aspect of the present disclosure may further include a third via, and the first wiring and the second via may be electrically connected via the third via, the first via and the second via may be directly connected within the first substrate, and the third via and the second via may be directly connected within the first substrate.

This allows the length of the first via to be further shortened, further reducing the diameter of the first via, thereby further reducing the size of the imaging device.

(Fifth aspect)
Also, for example, the imaging device according to the first or second aspect of the present disclosure may further include a third via, and the first wiring and the first via may be electrically connected via the third via, or the first via and the third via may be directly connected within the first substrate.

This allows the length of the first via to be further shortened, further reducing the diameter of the first via, thereby further reducing the size of the imaging device.

(Sixth aspect)
Furthermore, for example, in the imaging device according to any one of the first to fifth aspects of the present disclosure, the first via may have a diameter of 10 nm or less.

This allows the imaging device to be made even smaller.

(Seventh aspect)
Furthermore, for example, in the imaging device according to any one of the first to sixth aspects of the present disclosure, the first bonding surface may include an insulating film bonding and a metal bonding.

This allows for a strong bond even when the metal bond is small on the first bonding surface, making it possible to further miniaturize the image pickup device. Furthermore, by reducing the metal pitch of the hybrid bond made up of insulating film bonding and metal bonding, it is possible to achieve higher density wiring than with a via structure in which thick vias such as TSVs are placed on the periphery of the image pickup device. It also makes it possible to connect the wiring nearly perpendicular to the thickness direction without extending it to the thick vias on the periphery of the image pickup device, thereby shortening the wiring distance.

(Eighth aspect)
Also, for example, the imaging device according to any one of the first to seventh aspects of the present disclosure may further include a first transistor arranged on the first surface of the first substrate and a second transistor arranged on the third surface of the second substrate.

This allows the first and second substrates to be stacked face-to-back.

(Ninth aspect)
Furthermore, for example, an imaging device according to any one of the first to eighth aspects of the present disclosure may further include a pixel array including a plurality of pixels arranged in a matrix, and the first via may be located within an area in which the pixel array is arranged in a planar view.

This reduces the area outside the pixel array, making it possible to miniaturize the imaging device.

(Tenth aspect)
Furthermore, for example, an imaging device according to any one of the first to eighth aspects of the present disclosure may further include a pixel array including a plurality of pixels arranged in a matrix, and the first via may be located outside the area in which the pixel array is arranged in a planar view.

This reduces the area of the pixel array, making it possible to miniaturize the imaging device.

(Eleventh aspect)
Furthermore, for example, an imaging device according to any one of the first to tenth aspects of the present disclosure may further include a third substrate located closer to the fourth surface than the third surface of the second substrate, the third substrate including a fifth surface and a sixth surface opposite the fifth surface, the fifth surface being closer to the second substrate than the sixth surface; a second bonding surface located between the second substrate and the third substrate; a fourth wiring located between the fourth surface of the second substrate and the second bonding surface; a fifth wiring located between the fifth surface of the third substrate and the second bonding surface; and a fourth via, at least a portion of which is located within the second substrate; the second substrate and the third substrate may be stacked via the second bonding surface; the third wiring and the fourth wiring may be electrically connected via the fourth via; and the first via may overlap with the fourth via in a planar view.

As a result, even when three substrates, the first substrate, the second substrate, and the third substrate, are stacked, the first via and the fourth via overlap in a planar view, allowing the imaging device to be made smaller.

(Twelfth Aspect)
Furthermore, for example, an imaging device according to any one of the first to eleventh aspects of the present disclosure may further include a pixel including an intra-pixel element, a charge accumulation section that accumulates the charge, and a plug that electrically connects the photoelectric conversion section and the charge accumulation section, and the intra-pixel element may be located between the first via and the plug in a planar view.

This allows the distance between the first via and the plug to be increased, suppressing noise generated in the plug connected to the charge storage section due to interference from the first via.

(Thirteenth aspect)
Furthermore, for example, an imaging device according to any one of the first to twelfth aspects of the present disclosure may further include a pixel including a charge accumulation section that accumulates the electric charge and a plug that electrically connects the photoelectric conversion section and the charge accumulation section, and the first junction surface may include a metal junction that is located within a region in which the pixel is arranged in a planar view, and the metal junction may be located between the first via and the plug in the planar view.

This allows the distance between the first via and the plug to be increased, suppressing noise generated in the plug connected to the charge storage section due to interference from the first via.

(14th aspect)
Also, for example, an imaging device according to any one of the first to thirteenth aspects of the present disclosure may further include an isolation region located within the first substrate, and the isolation region may overlap with the first via in a planar view.

This allows the first via to be placed in an area where no transistors are placed.

(15th aspect)
Also, for example, an imaging device according to any one of the first to ninth aspects of the present disclosure may further include a plurality of pixels including a first pixel and a second pixel adjacent to the first pixel, each of the plurality of pixels may include a charge accumulation section that accumulates the charge and a plug that electrically connects the photoelectric conversion section and the charge accumulation section, the first via may be located, in a planar view, within a region in which the first pixel is arranged or at a boundary between the first pixel and the second pixel, and the distance between the plug of the first pixel and the plug of the second pixel may be smaller than the distance between the plug of the first pixel and the first via, in the planar view.

This allows the distance between the first via and the plug to be increased, suppressing noise generated in the plug connected to the charge storage section due to interference from the first via.

(16th aspect)
Furthermore, for example, an imaging device according to any one of the first to ninth and fifteenth aspects of the present disclosure may further include a first pixel, a second pixel adjacent to the first pixel, and a pixel isolation region located within the first substrate at the boundary between a region in which the first pixel is arranged in a planar view and a region in which the second pixel is arranged in the planar view, and the first via may overlap the pixel isolation region in the planar view.

This allows the first via to be placed in an area where no transistors are placed. Furthermore, when the first and second substrates are joined by hybrid bonding, reducing the pitch of the metal in the hybrid bond enables higher density wiring than a via structure in which thick vias such as TSVs are placed on the periphery of the image pickup device. Furthermore, it also makes it possible to connect the wiring nearly perpendicular to the thickness direction without extending it to the thick vias on the periphery of the image pickup device, thereby shortening the wiring distance.

(17th aspect)
Furthermore, for example, in the imaging device according to any one of the first to sixteenth aspects of the present disclosure, the first substrate may include pixel elements, and the second substrate may include logic transistors.

(18th aspect)
Also, for example, in an imaging device according to any one of the first to seventeenth aspects of the present disclosure, the photoelectric conversion unit may include an upper electrode, a lower electrode, and a photoelectric conversion layer located between the upper electrode and the lower electrode.

(19th aspect)
Furthermore, for example, in the imaging device according to an eighteenth aspect of the present disclosure, the photoelectric conversion layer may include an organic material.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are examples only and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradictions arise. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components. In each figure, components having substantially the same function are indicated by the same reference numerals, and duplicate descriptions may be omitted or simplified.

Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of this disclosure, and the dimensional ratios and appearance may differ from the actual products. In other words, each drawing is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales and other details do not necessarily match between the drawings.

Furthermore, in this specification, terms indicating the relationship between elements, such as orthogonal and parallel, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that express only the strict meaning, but also expressions that include a substantially equivalent range, for example, a difference of about a few percent.

Furthermore, in this specification, the terms "above" and "below" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light incident side of the imaging device is referred to as "above," and the side opposite the light incident side is referred to as "below." Similarly, the "upper surface" and "lower surface" of each component refer to the surface of the imaging device on the light incident side as the "upper surface" and the surface opposite the light incident side as the "lower surface." Note that terms such as "above," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Furthermore, the terms "above" and "below" apply not only to cases where two components are arranged with a gap between them and another component is present between them, but also to cases where two components are arranged closely together and are in contact with each other. Additionally, in this specification, "planar view" refers to a view from the normal direction of the main surfaces (e.g., the top and bottom surfaces) of the semiconductor substrate (in other words, the thickness direction of the semiconductor substrate).

Furthermore, in this specification and drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction is the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. Furthermore, the negative side of the Z-axis is defined as "downward," and the positive side of the Z-axis is defined as "upward."

Furthermore, in this specification, when a transistor is arranged on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are arranged on either side of the certain surface.

Also, in this specification, "connection" means electrical connection unless otherwise specified.

Furthermore, in this specification, for convenience, the term "light" refers not only to visible light but also to invisible light such as ultraviolet light and near-infrared light.

In addition, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components, etc., unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

(Embodiment 1)
The imaging device according to the first embodiment will be described below.

[composition]
First, a schematic configuration of an image pickup apparatus according to the present embodiment will be described. Fig. 1 is a block diagram showing an example of a schematic configuration of an image pickup apparatus 100 according to the present embodiment.

As shown in FIG. 1, the imaging device 100 includes a pixel substrate 31, which is a semiconductor substrate; a pixel array 14A formed on the pixel substrate 31; a circuit substrate 41, which is also a semiconductor substrate; a peripheral circuit 4 formed on the circuit substrate 41; and a first via 71 for connecting the pixel array 14A and the peripheral circuit 4. The peripheral circuit 4 includes a circuit for driving the pixel array 14A and a circuit for processing signals output by the pixel array 14A. In the example shown in FIG. 1, the peripheral circuit 4 includes a vertical scanning circuit 15, a column signal processing circuit 19, a horizontal signal readout circuit 20, and a voltage control circuit 30. As described below, the column signal processing circuit 19 is provided with multiple pixel arrays 14A corresponding to each column, but in FIG. 1, the pixel array 14A is illustrated as a single block. The peripheral circuit 4 may further include other circuits such as memory, analog circuits, and logic circuits. Furthermore, a portion of the peripheral circuit 4 may be disposed on the pixel substrate 31. Furthermore, at least one of a portion of the in-pixel elements such as transistors of the pixel array 14A and a portion of the peripheral circuit 4 may be formed on one or more separate semiconductor substrates stacked on the pixel substrate 31 and the circuit substrate 41.

In the example shown in FIG. 1, the voltage control circuit 30 and pixel array 14A are electrically connected via the first via 71 and the counter electrode signal line 16. The vertical scanning circuit 15 and pixel array 14A are electrically connected via the first via 71 and the address signal line 26, and the first via 71 and the reset signal line 27. The column signal processing circuit 19 and pixel array 14A are electrically connected via the first via 71 and the vertical signal line 17. Depending on the arrangement of the intra-pixel elements of the pixel array 14A and the circuits of the peripheral circuit 4, some of the electrical connections via the first via 71 may be made without going through the first via 71.

Next, the circuit configuration of the imaging device 100 according to this embodiment will be described. Figure 2 is a diagram showing the circuit configuration of the imaging device 100 according to this embodiment.

As shown in FIG. 2, the pixel array 14A is made up of a plurality of pixels 14. In plan view, the plurality of pixels 14 are arranged in a matrix, i.e., arranged in row and column directions, to form a pixel array region. In this specification, the row direction and column direction refer to the directions in which the rows and columns extend, respectively. In other words, the vertical direction is the column direction, and the horizontal direction is the row direction. In FIG. 2, four pixels 14, arranged in two rows and two columns, are shown as representative examples. Note that there is no particular limit to the number of the plurality of pixels 14. Furthermore, the plurality of pixels 14 may be arranged one-dimensionally, i.e., along one direction. In other words, the imaging device 100 may be a line sensor.

Each pixel 14 includes a photoelectric conversion unit 10 and a charge detection circuit 25. The charge detection circuit 25 includes an amplification transistor 11, a reset transistor 12, and an address transistor 13. The photoelectric conversion unit 10 includes a pixel electrode 50, a photoelectric conversion layer 51, and an upper electrode 52. The specific configuration of the photoelectric conversion unit 10 will be described later.

The imaging device 100 includes a voltage control element for applying a predetermined voltage to the upper electrode 52. The voltage control element includes, for example, a voltage control circuit, a voltage generation circuit such as a constant voltage source, and a voltage reference line such as a ground line. The voltage applied by the voltage control element is called a control voltage. In this embodiment, the imaging device 100 includes a voltage control circuit 30 as the voltage control element.

The voltage control circuit 30 may generate a constant control voltage, or may generate multiple control voltages of different values. Furthermore, for example, the voltage control circuit 30 may generate a control voltage that changes continuously within a predetermined range. The voltage control circuit 30 determines the value of the control voltage to be generated based on instructions from the operator operating the imaging device 100 or instructions from another control unit provided in the imaging device 100, and generates a control voltage of the determined value.

For example, the voltage control circuit 30 generates two or more different control voltages and applies the control voltages to the upper electrode 52, thereby changing the spectral sensitivity characteristics of the photoelectric conversion layer 51. This change in spectral sensitivity characteristics also includes a spectral sensitivity characteristic in which the sensitivity of the photoelectric conversion layer 51 becomes zero to the light to be detected. As a result, for example, in the imaging device 100, while the pixels 14 are reading out detection signals row by row, the voltage control circuit 30 can apply to the upper electrode 52 a control voltage that makes the sensitivity of the photoelectric conversion layer 51 zero, thereby virtually eliminating the influence of incident light when reading out the detection signals. Therefore, even when reading out detection signals row by row, a global shutter operation can be achieved.

In this embodiment, as shown in FIG. 2, the voltage control circuit 30 applies a control voltage to the upper electrodes 52 of the pixels 14 arranged in the row direction via the counter electrode signal line 16, thereby changing the voltage between the pixel electrodes 50 and the upper electrodes 52 and switching the spectral sensitivity characteristics of the photoelectric conversion unit 10. Alternatively, the voltage control circuit 30 realizes electronic shutter operation by applying a control voltage so as to obtain spectral sensitivity characteristics in which sensitivity to light becomes zero at a predetermined timing during imaging. The voltage control circuit 30 may also apply a control voltage to the pixel electrodes 50.

The photoelectric conversion unit 10 converts incident light into electric charges. When light enters the photoelectric conversion unit 10, the photoelectric conversion unit 10 generates, for example, electrons and holes as electric charges. When light enters the photoelectric conversion unit 10, in order for the pixel electrode 50 to collect electrons as signal charges, the pixel electrode 50 is set to a relatively high potential with respect to the upper electrode 52. This causes the electrons to move toward the pixel electrode 50. At this time, a current flows from the pixel electrode 50 to the upper electrode 52. When light enters the photoelectric conversion unit 10, in order for the pixel electrode 50 to collect holes as signal charges, the pixel electrode 50 is set to a relatively low potential with respect to the upper electrode 52. This causes the holes to move toward the pixel electrode 50. At this time, a current flows from the upper electrode 52 to the pixel electrode 50.

The pixel electrode 50 is connected to the gate electrode of the amplification transistor 11, and the signal charge collected by the pixel electrode 50 is stored in a charge storage node 24 located between the pixel electrode 50 and the gate electrode of the amplification transistor 11. In the following, the signal charge will mainly be described as holes, but the signal charge may also be electrons.

The signal charge accumulated in the charge accumulation node 24 is applied to the gate electrode of the amplification transistor 11 as a voltage corresponding to the amount of signal charge. The amplification transistor 11 outputs a voltage corresponding to the voltage applied to its gate electrode. The address transistor 13 selectively reads out the voltage output from the amplification transistor 11 as the signal voltage. The address transistor 13 is also called a row selection transistor. The reset transistor 12 has one of its source and drain connected to the pixel electrode 50, and resets the signal charge accumulated in the charge accumulation node 24. In other words, the reset transistor 12 resets the potential of the gate electrode of the amplification transistor 11 and the pixel electrode 50.

In order to selectively perform the above-mentioned operations in multiple pixels 14, the imaging device 100 is equipped with a power supply line 21, a vertical signal line 17, an address signal line 26, and a reset signal line 27. The power supply line 21, vertical signal line 17, address signal line 26, and reset signal line 27 are each connected to the pixels 14. Specifically, the power supply line 21 is connected to one of the source and drain of the amplification transistor 11. The vertical signal line 17 is connected to one of the source and drain of the address transistor 13. The address signal line 26 is connected to the gate electrode of the address transistor 13. Furthermore, the reset signal line 27 is connected to the gate electrode of the reset transistor 12.

Each of the amplification transistor 11, reset transistor 12, and address transistor 13 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Each of the amplification transistor 11, reset transistor 12, and address transistor 13 is an n-channel MOSFET, but may also be a p-channel MOSFET. Each of the amplification transistor 11, reset transistor 12, and address transistor 13 is an in-pixel element of the pixel 14. The pixel 14 may have other elements, such as transistors and capacitive elements, other than the amplification transistor 11, reset transistor 12, and address transistor 13 as in-pixel elements.

In the example shown in FIG. 2, the peripheral circuit 4 includes the vertical scanning circuit 15, horizontal signal readout circuit 20, multiple column signal processing circuits 19, and voltage control circuit 30 described above, as well as multiple load circuits 18 and multiple differential amplifiers 22. The vertical scanning circuit 15 is also referred to as a row scanning circuit. The horizontal signal readout circuit 20 is also referred to as a column scanning circuit. The column signal processing circuit 19 is also referred to as a row signal storage circuit. The differential amplifier 22 is also referred to as a feedback amplifier.

The vertical scanning circuit 15 is connected to the address signal lines 26 and the reset signal lines 27. The vertical scanning circuit 15 can also be connected to each of the address signal lines 26 and the reset signal lines 27 via first vias 71 (not shown in FIG. 2). The vertical scanning circuit 15 selects the multiple pixels 14 arranged in each row of the pixel array 14A on a row-by-row basis, reads out the signal voltage, and resets the potential of the pixel electrodes 50. The power supply lines 21 function as source follower power supplies and supply a predetermined power supply voltage to each pixel 14. The predetermined power supply voltage can be supplied to the power supply lines 21 via first vias 71 (not shown in FIG. 2).

The horizontal signal readout circuit 20 is electrically connected to a plurality of column signal processing circuits 19. The column signal processing circuits 19 are electrically connected to the pixels 14 arranged in each column of the pixel array 14A via vertical signal lines 17 corresponding to each column of the pixel array 14A. The load circuits 18 are electrically connected to each vertical signal line 17. The load circuits 18 and the amplification transistors 11 form a source follower circuit. In addition, at least one of each column signal processing circuit 19 and each load circuit 18 can be connected to the vertical signal line 17 via a first via 71 not shown in FIG. 2.

Multiple differential amplifiers 22 are provided corresponding to each column of the pixel array 14A. The negative input terminals of the differential amplifiers 22 are connected to the corresponding vertical signal lines 17. The output terminals of the differential amplifiers 22 are connected to the pixels 14 via feedback lines 23 corresponding to each column of the pixel array 14A. The output terminals of the differential amplifiers 22 can also be connected to the feedback lines 23 via first vias 71 (not shown in FIG. 2).

The vertical scanning circuit 15 applies a row selection signal, which controls the on and off of the address transistor 13, to the gate electrode of the address transistor 13 via the address signal line 26. This scans and selects the row to be read out. A signal voltage is read out from the pixels 14 in the selected row to the vertical signal line 17. The vertical scanning circuit 15 also applies a reset signal, which controls the on and off of the reset transistor 12, to the gate electrode of the reset transistor 12 via the reset signal line 27. This selects the row of pixels 14 to be reset. The vertical signal line 17 transmits the signal voltage read out from the pixels 14 selected by the vertical scanning circuit 15 to the column signal processing circuit 19.

The column signal processing circuit 19 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

The horizontal signal readout circuit 20 sequentially reads out signals from multiple column signal processing circuits 19 to the horizontal common signal line 28.

The differential amplifier 22 is connected via a feedback line 23 to the other of the source and drain of the reset transistor 12, which is not connected to the pixel electrode 50. Therefore, when the address transistor 13 and reset transistor 12 are conductive, the differential amplifier 22 receives the output value of the address transistor 13 at its negative input terminal. The differential amplifier 22 performs a feedback operation so that the gate potential of the amplifying transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is, for example, 0V or a positive voltage close to 0V. The feedback voltage refers to the output voltage of the differential amplifier 22. Note that the imaging device 100 does not necessarily have to include the differential amplifier 22. For example, a predetermined reset voltage may be supplied to the other of the drain and source of the reset transistor 12. The reset voltage is, for example, 0V or a voltage close to 0V.

Next, the device structure of the imaging device 100 according to this embodiment will be described. Figure 3 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100 according to this embodiment. Note that, for ease of viewing, the shading indicating the cross section of insulating layers such as interlayer insulating layers within wiring layers such as wiring layers 61, 62, and 63, and insulating layer 55, has been omitted in Figure 3. Also, for ease of viewing, the dimensions of each component, such as thickness, length, and width, have been adjusted appropriately from their actual sizes. This also applies to the subsequent cross-sectional views.

As shown in FIG. 3, the imaging device 100 includes a photoelectric conversion unit 10, a pixel substrate 31, a circuit board 41, wiring layers 61, 62, and 63, an insulating layer 55, a first via 71, a second via 72, a third via 73, and a first bonding surface 81. The imaging device 100 has a structure in which the circuit board 41, wiring layer 63, wiring layer 62, pixel substrate 31, wiring layer 61, insulating layer 55, and photoelectric conversion unit 10 are stacked in this order along the Z axis.

As shown in FIG. 3, the pixel substrate 31 and the circuit substrate 41 are stacked via a first bonding surface 81 located between the pixel substrate 31 and the circuit substrate 41. The pixel substrate 31 and the circuit substrate 41 are each, for example, a p-type or n-type semiconductor substrate in which various impurity regions are formed. The pixel substrate 31 and the circuit substrate 41 may each be a silicon substrate. In this embodiment, the pixel substrate 31 is an example of a first substrate, and the circuit substrate 41 is an example of a second substrate. A well may be formed in each of the pixel substrate 31 and the circuit substrate 41.

The pixel substrate 31 includes an upper surface 31a, which is the light incident side surface onto which incident light is incident, and a lower surface 31b, which is the surface opposite to the upper surface 31a and faces the upper surface 31a. In this embodiment, the upper surface 31a is an example of a first surface, and the lower surface 31b is an example of a second surface. A transistor Tr11, which is an example of a first transistor, is arranged on the upper surface 31a of the pixel substrate 31. The transistor Tr11 is a transistor included in a pixel 14, and is, for example, any of the above-mentioned amplification transistor 11, reset transistor 12, and address transistor 13. Note that, for ease of viewing, Figure 3 shows only one transistor Tr11 arranged on the upper surface 31a. For example, the amplification transistors 11, reset transistors 12, and address transistors 13 of each of the multiple pixels 14 are arranged on the upper surface 31a.

Furthermore, a charge accumulation region 91 that accumulates charges generated in the photoelectric conversion unit 10 is formed in the pixel substrate 31. The charge accumulation region 91 is part of the charge accumulation node 24 described above and is electrically connected to the pixel electrode 50 of the photoelectric conversion unit 10 via a plug 92. The charge accumulation region 91 is an example of a charge accumulation unit. The charge accumulation region 91 is, for example, an impurity region formed by injecting n-type or p-type impurities from the upper surface 31a side of the pixel substrate 31. In one example, the charge accumulation region 91 is an n-type impurity region formed in a p-type semiconductor substrate or a p-type well. The charge accumulation region 91 may function as either the source or drain of the reset transistor 12 connected to the pixel electrode 50. The plug 92 is a contact plug located in the wiring layer 61 and in contact with the charge accumulation region 91. The plug 92 is, for example, formed of polysilicon doped with impurities. The diameter of the plug 92 is, for example, 10 nm or more and 100 nm or less. The charge storage region 91 and the plug 92 are included in each of the multiple pixels 14. In the example shown in FIG. 3, the plug 92 is connected to the pixel electrode 50 through a via, but the plug 92 may also be connected directly to the pixel electrode 50.

The circuit board 41 is located on the lower surface 31b side, which is closer to the lower surface 31b than the upper surface 31a of the pixel substrate 31. The circuit board 41 includes an upper surface 41a and a lower surface, and the upper surface 41a is closer to the position where incident light enters the imaging device 100 than the lower surface. In this embodiment, the upper surface 41a is an example of a third surface. A transistor Tr21, which is an example of a second transistor, is arranged on the upper surface 41a of the circuit board 41. The transistor Tr21 is a transistor included in the peripheral circuit 4. Note that for ease of viewing, Figure 3 shows only one transistor Tr21 arranged on the upper surface 41a. A plurality of transistors, which are at least a portion of the transistors included in each circuit of the peripheral circuit 4, can be arranged on the upper surface 41a.

On pixel substrate 31, transistors are arranged on top surface 31a, and on circuit substrate 41, transistors are arranged on top surface 41a. Pixel substrate 31 and circuit substrate 41 are stacked face-to-back.

The photoelectric conversion unit 10 is located closer to the upper surface 31a of the pixel substrate 31 than to the lower surface 31b. The photoelectric conversion unit 10 is stacked on the upper surface 31a of the pixel substrate 31 via the wiring layer 61 and the insulating layer 55 located above the wiring layer 61.

As described above, the photoelectric conversion unit 10 includes the pixel electrode 50, the photoelectric conversion layer 51, and the upper electrode 52. The photoelectric conversion unit 10 may further include other layers, such as a charge blocking layer, a buffer layer, or a charge transport layer, between the pixel electrode 50 and the photoelectric conversion layer 51 and/or between the photoelectric conversion layer 51 and the upper electrode 52. Furthermore, although not shown in FIG. 3, an insulating protection layer, a color filter, a macrolens, etc. may also be provided above the photoelectric conversion unit 10.

The pixel electrode 50 is located on the upper surface of the insulating layer 55 in the pixel array region R1, which is the region where the pixel array 14A is arranged in a planar view. The pixel electrode 50 is a film-like electrode. The pixel electrode 50 can contain at least one selected from a metal, a metal compound, and polysilicon doped with impurities to provide conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 50 may contain metal nitride as a primary component. The pixel electrode 50 collects one of the positive and negative charges generated in the photoelectric conversion layer 51. The pixel electrode 50 is spatially separated from the pixel electrodes 50 of other adjacent pixels 14, and is thereby electrically isolated from the pixel electrodes 50 of other pixels 14.

The photoelectric conversion layer 51 is located above the pixel electrode 50 and covers it. The photoelectric conversion layer 51 contains an organic semiconductor material or an inorganic semiconductor material such as amorphous silicon or quantum dots. It receives light incident through the upper electrode 52 and generates positive and negative charges through photoelectric conversion. In other words, the photoelectric conversion layer 51 converts light into charges. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 51 is formed, for example, continuously across multiple pixels 14. The photoelectric conversion layer 51 is shared by multiple pixels 14. In other words, the photoelectric conversion layer 51 is monolithically formed at a position closer to the upper surface 31a of the pixel substrate 31 than the lower surface 31b. The photoelectric conversion layer 51 may be provided separately for each pixel 14 or for each block of two or more pixels 14.

The upper electrode 52 is located above the photoelectric conversion layer 51 and covers it. The upper electrode 52 is a film-like electrode. In the example shown in FIG. 3, the side surfaces of the upper electrode 52 and the photoelectric conversion layer 51 are aligned in a planar view. The upper electrode 52 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed above the light-receiving surface of the photoelectric conversion layer 51. The upper electrode 52, like the photoelectric conversion layer 51, is formed continuously across multiple pixels 14. In other words, the upper electrodes 52 of multiple pixels 14 are electrically connected to each other. In other words, the upper electrode 52 is monolithically formed at a position closer to the upper surface 31a of the pixel substrate 31 than the lower surface 31b. The upper electrode 52 may be provided separately for each pixel 14 or for each block of two or more pixels 14.

The potential of the upper electrode 52 is controlled by the voltage control circuit 30 described above. When the imaging device 100 is in operation, the potential of the upper electrode 52 is controlled to make the potential of the upper electrode 52 different from the potential of the pixel electrode 50, allowing the pixel electrode 50 to collect the signal charge generated by photoelectric conversion. For example, the voltage control circuit 30 controls the potential of the upper electrode 52 so that the potential of the upper electrode 52 is higher than the potential of the pixel electrode 50. Specifically, when the imaging device 100 is in operation, a predetermined voltage is applied to the upper electrode 52 by the voltage control circuit 30. A specific example of the predetermined voltage is a positive voltage of approximately 10 V. This allows the pixel electrode 50 to collect the holes, of the hole-electron pairs generated in the photoelectric conversion layer 51, as signal charge. The signal charge collected by the pixel electrode 50 is stored in the charge accumulation region 91 connected to the pixel electrode 50 and detected by the charge detection circuit 25. When electrons are used as signal charges, a predetermined voltage is applied to the upper electrode 52 so that the potential of the upper electrode 52 is lower than the potential of the pixel electrode 50.

In the example shown in FIG. 3, the imaging device 100 further includes a shield electrode 53. The shield electrode 53 is located on the upper surface of the insulating layer 55. The shield electrode 53 is a film-like electrode. The shield electrode 53 faces the upper electrode 52 via the photoelectric conversion layer 51. The shield electrode 53 and the pixel electrode 50 are located on the same plane and are adjacent to each other with a predetermined gap between them. The shield electrode 53 is, for example, arranged to surround the pixel electrode 50 in a planar view. The shield electrode 53 can include at least one selected from a metal, a metal compound, and polysilicon doped with impurities to provide conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides.

The shield electrode 53 is located between two adjacent pixels 14 in a plan view, and suppresses color mixing between the two adjacent pixels 14. The shield electrode 53 is maintained at a predetermined potential, for example, when the imaging device 100 is in operation. There are no particular restrictions on the predetermined potential, as long as it is possible to suppress color mixing between the adjacent pixels 14. Note that the imaging device 100 does not necessarily have to include a shield electrode 53.

The insulating layer 55 is located between the wiring layer 61 and the photoelectric conversion unit 10. The photoelectric conversion unit 10 is laminated on the upper surface of the insulating layer 55. The insulating layer 55 is a layer that is bonded to the support substrate during manufacturing of the imaging device 100. Note that the imaging device 100 does not necessarily have to include the insulating layer 55. In this case, for example, the photoelectric conversion unit 10 covers the upper surface of the wiring layer 61.

The wiring layer 61 is located between the pixel substrate 31 and the photoelectric conversion unit 10. The wiring layer 61 is located closer to the upper surface 31a of the pixel substrate 31 than the lower surface 31b, and covers the upper surface 31a of the pixel substrate 31. The wiring layer 61 includes multiple wirings, including wiring 61a, an interlayer insulating layer between the wirings, and multiple vias that provide electrical connections across the interlayer insulating layer. Furthermore, MIM (Metal-Insulator-Metal) capacitors may be formed within the wiring layer 61. In this specification, a wiring is a flat conductor that extends perpendicular to the thickness direction of a semiconductor substrate such as the pixel substrate 31, and a via is a columnar conductor that extends parallel to the thickness direction of a semiconductor substrate such as the pixel substrate 31. Note that in Figure 3, the structure within the wiring layer 61 is simplified for clarity, and the layer structure of the interlayer insulating layer is not shown. This also applies to other cross-sectional views and other wiring layers.

The wiring 61a is an example of a first wiring, and is located closer to the upper surface 31a of the pixel substrate 31 than to the lower surface 31b, and closer to the pixel substrate 31 than to the photoelectric conversion unit 10. The wiring 61a electrically connects the first via 71 and the pixel 14. The wiring 61a electrically connects, for example, the first via 71 and the transistor Tr11.

The wiring layer 62 is located between the pixel substrate 31 and the wiring layer 63. The wiring layer 62 is bonded to the wiring layer 63 by a first bonding surface 81. The wiring layer 62 is located closer to the lower surface 31b of the pixel substrate 31 than to the upper surface 31a, and covers the lower surface 31b of the pixel substrate 31. The wiring layer 62 includes multiple wirings including wirings 62a and pad wirings 62p, an interlayer insulating layer between the wirings, and multiple vias that provide electrical connection across the interlayer insulating layer.

The wiring 62a is an example of a second wiring and is located between the lower surface 31b of the pixel substrate 31 and the first bonding surface 81. The wiring 62a electrically connects the first via 71 and the pad wiring 62p.

The pad wiring 62p is formed in the lowest part of the wiring layer 62, i.e., in the insulating layer closest to the wiring layer 63. The pad wiring 62p forms a metal junction 81a on the first bonding surface 81.

The wiring layer 63 is located between the wiring layer 62 and the circuit board 41. The wiring layer 63 is located closer to the upper surface 41a of the circuit board 41 than to the lower surface thereof, and covers the upper surface 41a of the circuit board 41. The wiring layer 63 includes a plurality of wirings including wirings 63a and pad wirings 63p, an interlayer insulating layer between the wirings, and a plurality of vias that provide electrical connections across the interlayer insulating layer. Furthermore, an MIM capacitor may be formed within the wiring layer 63.

Wiring 63a is an example of a third wiring, and is located between the upper surface 41a of the circuit board 41 and the first bonding surface 81. Wiring 63a electrically connects pad wiring 63p to the peripheral circuit 4. Wiring 63a electrically connects, for example, pad wiring 63p to transistor Tr21. Furthermore, wiring 63a and wiring 62a are electrically connected via the first bonding surface 81.

The pad wiring 63p is formed in the uppermost insulating layer of the wiring layer 63, i.e., the insulating layer closest to the wiring layer 62. The pad wiring 63p forms a metal junction 81a on the first bonding surface 81.

The wiring and vias in wiring layers 61, 62, and 63 each contain, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. Furthermore, the insulating layers, such as the interlayer insulating layers, in wiring layers 61, 62, and 63 contain, for example, silicon oxide or silicon carbonitride.

The first via 71 penetrates at least a portion of the pixel substrate 31, and at least a portion of it is located within the pixel substrate 31. The first via 71 is, for example, a TSV (Through Silicon Via). The wiring 61a and wiring 62a are electrically connected via the first via 71. The first via 71 is in contact with the wiring 62a.

The first via 71 is, for example, an nTSV (nanoTSV) having a diameter on the nanometer order. The diameter of the first via 71 is, for example, less than 1000 nm. The diameter of the first via 71 may be 100 nm or less, or 10 nm or less. The diameter of the first via 71 is, for example, 1 nm or more. The diameter of the first via 71 may be 5 nm or more. The first via 71 may also be a μTSV (microTSV) having a diameter on the μm order.

The first via 71 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The first via 71 may contain copper as its main component. Here, the main component refers to the component that is contained in the largest amount by mass. In one example, the main component is a component that accounts for more than 50% by mass. The main component may also account for more than 80% by mass.

The first via 71 is formed, for example, by drilling a hole in the thickness direction of the pixel substrate 31 and depositing a metal such as copper in the hole. Furthermore, when a hole is formed, the tip of the hole becomes thinner. In the example shown in FIG. 3, the upper side of the first via 71 is thinner than the lower side, so the first via 71 is formed from the lower surface 31b of the pixel substrate 31. The diameter of the first via 71 exemplified above is the maximum diameter of the first via 71, and in the example shown in FIG. 3, it is the diameter of the lowest part of the first via 71.

The second via 72 is located within the pixel substrate 31. In the example shown in FIG. 3, the second via 72 is formed within an isolation region 95 formed in the pixel substrate 31. The isolation region 95 is an isolation region that separates the pixel array 14A from the peripheral portion of the pixel array 14A. The isolation region 95 is located within the pixel substrate 31. The isolation region 95 is, for example, an STI (Shallow Trench Isolation) structure. The STI structure is formed in the pixel substrate 31 by an STI process. The second via 72 is, for example, a buried via formed by burying a metal within a trench used to form the STI structure. The second via 72 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium.

As shown in FIG. 3, a liner film 71a is formed on the radially outer surface of the first via 71. The first via 71 and the pixel substrate 31 are separated by the liner film 71a. Furthermore, a liner film 72a is formed on the radially outer surface of the second via 72. The second via 72 and the pixel substrate 31 are separated by the liner film 72a. The liner films 71a and 72a include at least an insulating film made of an insulating material such as silicon oxide. The liner films 71a and 72a may have a layered structure of an insulating film and a film of a metal nitride such as titanium nitride or a metal such as titanium.

A portion of the third via 73 is located within the pixel substrate 31. In the example shown in FIG. 3, a portion of the third via 73 is formed within an isolation region 95 formed in the pixel substrate 31. The third via 73 electrically connects the wiring 61a and the first via 71. The third via 73 is in contact with the wiring 61a. The third via 73 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The third via 73 is formed, for example, by forming a hole by etching or the like in the isolation region 95 in the pixel substrate 31 and in the insulating layer above the isolation region 95, and then depositing a metal such as copper in the hole.

The wiring 61a and the first via 71 are electrically connected via the second via 72. The wiring 61a and the second via 72 are also electrically connected via the third via 73. Therefore, the wiring 61a and the first via 71 are electrically connected via the second via 72 and the third via 73. The first via 71 and the second via 72 are directly connected within the pixel substrate 31, and the second via 72 and the third via 73 are directly connected within the pixel substrate 31. The length of the first via 71 may be longer than the lengths of the second via 72 and the third via 73. The first via 71, the second via 72, and the third via 73 overlap each other in a planar view. The first via 71, the second via 72, and the third via 73 also overlap with an isolation region 95 formed on the pixel substrate 31 in a planar view.

The first bonding surface 81 is located between the pixel substrate 31 and the circuit substrate 41. In the example shown in FIG. 3, the lower surface of the wiring layer 62 and the upper surface of the wiring layer 63 are bonded at the first bonding surface 81. In other words, the first bonding surface 81 is located at the interface between the wiring layer 62 and the wiring layer 63. The first bonding surface 81 is also the surface where the wafer including the pixel substrate 31 and the wafer including the circuit substrate 41 are bonded by hybrid bonding, and includes metal bonds 81a and insulating film bonds 81b. For ease of viewing, FIG. 3 shows some of the metal bonds 81a and insulating film bonds 81b with reference numerals, but metal bonds 81a and insulating film bonds 81b are formed throughout the first bonding surface 81.

Metal bond 81a is formed by bonding pad wiring 62p and pad wiring 63p. For example, if pad wiring 62p and 63p contain copper as a main component, metal bond 81a is a Cu-Cu bond. Insulating film bond 81b is formed by bonding an insulating layer in the same layer as pad wiring 62p included in wiring layer 62 to an insulating layer in the same layer as pad wiring 63p included in wiring layer 63.

As described above, in the imaging device 100 according to this embodiment, the pixel substrate 31 on which the pixel array 14A is formed and the circuit substrate 41 on which the peripheral circuit 4 is formed are stacked, which allows the substrate area of the imaging device 100 to be reduced, enabling miniaturization.

Furthermore, in the imaging device 100, the wiring 61a located above the upper surface 31a of the pixel substrate 31 and the wiring 62a located between the lower surface 31b of the pixel substrate 31 and the first bonding surface 81 are electrically connected via the first via 71. This allows the imaging device 100 to be miniaturized. More specifically, if wafers are bonded using TSVs, the TSVs are formed so that they penetrate the pixel substrate 31 and reach the circuit substrate 41. This increases the depth of the trench used to form the TSVs, and therefore requires a larger diameter for the first via 71. In this case, the distance between the transistor Tr11 and the first via 71 also needs to be increased to reduce the effect on the transistor Tr11 formed on the pixel substrate 31 of stress caused by forming a bond with a thick TSV. As a result, the pixel substrate 31 becomes larger. In the imaging device 100, the first via 71 is not used for bonding the pixel substrate 31 and the circuit substrate 41, allowing the imaging device 100 to be miniaturized. Furthermore, in the imaging device 100, the length of the first via 71 can be made shorter than the distance from the wiring 61a to the first bonding surface 81. Generally, the longer a via that penetrates a semiconductor substrate, the larger its diameter. Therefore, by making the length of the first via 71 shorter, the diameter of the first via 71 can be made smaller, and the area for forming the first via 71 can be made narrower. This allows the imaging device 100 to be made smaller.

Furthermore, in the imaging device 100, the wiring 61a and the first via 71 are electrically connected via the second via 72 and the third via 73. This allows the length of the first via 71 to be further shortened, further reducing the diameter of the first via 71, and further reducing the size of the imaging device 100.

Furthermore, in the imaging device 100, the photoelectric conversion unit 10 including the pixel electrode 50, photoelectric conversion layer 51, and upper electrode 52 is disposed above the upper surface 31a of the pixel substrate 31. With this type of photoelectric conversion unit 10, compared to when a photodiode formed on a semiconductor substrate is used as the photoelectric conversion unit, no photoelectric conversion unit is formed within the pixel substrate 31 where the transistors of the pixels 14 are formed, allowing the imaging device 100 to be made more compact. Furthermore, photodiodes are not formed on the pixel substrate 31, and the number of semiconductor substrates stacked in the imaging device 100 can be reduced compared to when a semiconductor substrate with a photodiode formed thereon is stacked on the pixel substrate 31. As a result, the number of junctions between wafers including semiconductor substrates and the number of vias penetrating the semiconductor substrates can also be reduced.

[Flat Layout]
Next, the planar layout of the imaging device 100 according to the present embodiment will be described. FIG. 4 is a plan view schematically illustrating an example of the planar layout of the imaging device 100 according to the present embodiment. FIG. 4 schematically illustrates the arrangement of the amplification transistor 11, the pad wiring 62p for metal bonding, the charge accumulation region 91, the plug 92, and the first via 71 in a planar view. Also, in FIG. 4, pixel regions R2, which are regions in which pixels 14 are arranged in a planar view, are indicated by dashed-dotted rectangles. FIG. 4 illustrates 16 pixel regions R2 corresponding to four rows and four columns of pixels 14. Also, FIG. 4 illustrates the arrangement of the amplification transistor 11, the pad wiring 62p, the charge accumulation region 91, and the plug 92 in the two upper left pixel regions R2 as a representative example, and does not illustrate the arrangement of these elements in the other pixel regions R2.

As shown in FIG. 4, the first via 71 is located outside the pixel array region R1. By making the first via 71 located outside the pixel array region R1 smaller than a conventional TSV, the chip area can be reduced. Furthermore, by locating the first via 71 outside the pixel array region R1, it is positioned offset from the amplifier transistor 11, which makes it possible to prevent the threshold voltage Vth of the amplifier transistor 11 from fluctuating due to the first via 71.

In the example shown in FIG. 4, a plurality of first vias 71 are arranged along the outer periphery of the pixel array region R1, constituting a first via group 71G. In the example shown in FIG. 4, the plurality of first vias 71 are arranged in a single row, but they may also be arranged in two or more rows.

In the example shown in FIG. 4, the amplifier transistor 11 is located, in a plan view, between the plug 92 in the same pixel region R2 as the amplifier transistor 11 and the first via group 71G. This makes the distance between the plug 92 in the same pixel region R2 as the amplifier transistor 11 and the first via 71 longer than the distance between the first via 71 and the amplifier transistor 11, thereby suppressing noise generated in the plug 92 connected to the charge storage region 91 due to interference from the first via 71. Note that a pixel element other than the amplifier transistor 11 may be located in the position of the amplifier transistor 11.

Furthermore, in the example shown in FIG. 4, the plug 92 is positioned closer to the side opposite the side closest to the first via 71, which is closest to the pixel region R2, than to the side closest to the first via 71. This also makes it possible to suppress noise generated in the plug 92 due to interference from the first via 71.

Furthermore, in the example shown in FIG. 4, in a plan view, the pad wiring 62p does not overlap the first via 71 and is located within the pixel region R2. The position of the pad wiring 62p is the same as the position of the above-mentioned metal junction 81a formed by the pad wiring 62p. In a plan view, the pad wiring 62p is located between the plug 92 and the first via group 71G in the same pixel region R2 as the pad wiring 62p. This makes it possible to make the distance between the plug 92 and the first via 71 in the same pixel region R2 as the pad wiring 62p longer than the distance between the first via 71 and the pad wiring 62p, thereby suppressing noise generated in the plug 92 due to interference from the first via 71.

Note that the pad wiring 62p may be located outside the pixel region R2 in plan view. Furthermore, the pad wiring 62p may overlap the first via 71, the amplification transistor 11, or the plug 92 in plan view.

[Manufacturing method]
Next, a method for manufacturing the imaging device 100 according to this embodiment will be described.

In the manufacturing method of the imaging device 100, a wafer including the pixel substrate 31 is formed, a wafer including the circuit substrate 41 is formed, and the wafer including the pixel substrate 31 and the wafer including the circuit substrate 41 are bonded together. Then, the photoelectric conversion unit 10 is further formed, thereby obtaining the imaging device 100.

The manufacturing method of the image pickup device 100 will now be described in detail with reference to the drawings. Figures 5A to 5D are cross-sectional views illustrating the process of forming a wafer including the pixel substrate 31. Figures 6A and 6B are cross-sectional views illustrating the process of forming a wafer including the circuit substrate 41. Figures 7A and 7B are cross-sectional views illustrating the process after bonding the wafer including the pixel substrate 31 and the wafer including the circuit substrate 41. In manufacturing the image pickup device 100, methods for forming impurity regions and isolation regions in semiconductor substrates such as the pixel substrate 31, as well as methods for forming interlayer insulating layers, wiring, vias, electrodes, etc. can use conventionally known methods such as semiconductor integrated circuit manufacturing processes.

First, as shown in Figure 5A, the pixel substrate 31 is prepared. Figure 5A shows the state in which the wiring layer 61, transistor Tr11, charge storage region 91, plug 92, isolation region 95, second via 72, liner film 72a, and third via 73 have been formed on the upper surface 31a of the pixel substrate 31.

Next, as shown in FIG. 5B, an insulating layer 55 is formed on the wiring layer 61, and a support substrate 56 is bonded to the insulating layer 55. Then, the substrate is turned upside down, and with the pixel substrate 31 supported by the support substrate 56, the pixel substrate 31 is thinned, for example, to approximately 3 μm or more and 5 μm or less. This allows the first via 71, which will be formed in a later process, to be shorter. The support substrate 56 is, for example, a silicon substrate or a glass substrate, but is not particularly limited as long as it can support the pixel substrate 31.

Next, as shown in FIG. 5C , a wiring layer 62M, which is the wiring layer 62 before the pad wiring 62p is formed, is formed on the lower surface 31b of the pixel substrate 31. During the formation of the wiring layer 62M, a hole is drilled from the lower surface 31b of the pixel substrate 31 to the pixel substrate 31, and a metal is deposited in the hole to form a first via 71.

5D, pad wiring 62p is formed on the wiring layer 62M to form the wiring layer 62. For example, grooves for forming the pad wiring 62p are formed in an insulating layer 62I formed on the wiring layer 62M, and the grooves are filled with a metal such as Cu to form the pad wiring 62p. Examples of the insulating layer 62I include an insulating film made of an oxide such as _SiO2 , and an insulating film made of SiCN or AlN. In this way, a wafer 31W including the pixel substrate 31, the wiring layer 61, and the wiring layer 62 is formed.

Furthermore, in parallel with the process of forming wafer 31W, or before or after the process of forming wafer 31W, circuit board 41 is prepared as shown in FIG. 6A. FIG. 6A shows the state in which wiring layer 63M and transistor Tr21 have been formed before pad wiring 63p is formed in wiring layer 63 on the upper surface 41a of circuit board 41.

Next, as shown in FIG. 6B , pad wiring 63p is formed on wiring layer 63M to form wiring layer 63. For example, grooves for forming pad wiring 63p are formed in insulating layer 63I formed on wiring layer 63M, and metal such as Cu is filled into the grooves to form pad wiring 63p. The wafer 31W and wafer 41W are hybrid-bonded using the pad wiring 62p and insulating layer 62I, and the pad wiring 63p and insulating layer 63I. Examples of insulating layer 63I include an insulating film made of oxide such as _SiO2 , and an insulating film made of SiCN or AlN. This forms wafer 41W including circuit board 41 and wiring layer 63.

Next, as shown in FIG. 7A, wafer 31W and wafer 41W are bonded together to form a first bonding surface 81. In this embodiment, wafer 31W and wafer 41W are bonded together using hybrid bonding, forming a metal bond 81a between pad wiring 62p and pad wiring 63p, and an insulating film bond 81b between insulating layer 62I around pad wiring 62p and insulating layer 63I around pad wiring 63p. As described above, the pixel substrate 31 is thinned before bonding, so the thickness t1 of the pixel substrate 31 is smaller than, for example, the thickness t2 of the circuit board 41.

Specifically, to form the first bonding surface 81, wafer 31W and wafer 41W are pressed together so that wiring layer 62 and wiring layer 63 face each other, and then heated at a temperature of 350°C or lower (e.g., 300°C to 350°C). This causes the metal (e.g., copper) of pad wiring 62p and pad wiring 63p to thermally expand, forming metal bond 81a. Furthermore, covalent bonds are formed between insulating layers 62I and 63I as water molecules are released, forming insulating film bond 81b. Furthermore, support substrate 56 is peeled off from wafer 31W before or after forming first bonding surface 81.

Next, as shown in FIG. 7B, pixel electrodes 50 and shield electrodes 53 are formed on the insulating layer 55, and a photoelectric conversion layer 51 is formed above the pixel electrodes 50 and shield electrodes 53. The photoelectric conversion layer 51 is formed continuously and monolithically across multiple pixels 14, for example, as described above. The photoelectric conversion layer 51 is formed using, for example, spin coating or vapor deposition. Then, an upper electrode 52 is formed above the photoelectric conversion layer 51, thereby obtaining the imaging device 100 shown in FIG. 3.

In the above manufacturing method, the photoelectric conversion layer 51 is formed after the first bonding surface 81 is formed, so the imaging device 100 can be manufactured without subjecting the photoelectric conversion layer 51 to high-temperature heat treatment. For example, the processes following the formation of the photoelectric conversion layer 51 are performed at temperatures below 250°C.

[Modification 1]
Next, a first modification of the first embodiment will be described. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

Figure 8 is a schematic cross-sectional view showing an example of the device structure of an imaging device 101 according to this modified example. As shown in Figure 8, the imaging device 101 according to this modified example differs from the imaging device 100 according to embodiment 1 mainly in that it does not include a second via 72 and a liner film 72a.

In the imaging device 101, the first via 71 and the third via 73 are directly connected within the pixel substrate 31. As a result, the first via 71 is connected to the wiring 61a via the third via 73, which allows the length of the first via 71 to be shortened, thereby enabling the imaging device 100 to be made more compact.

In the example shown in FIG. 8, the first via 71 is formed from the lower surface 31b side of the pixel substrate 31, but as shown in FIG. 9, it may be formed from the upper surface 31a side of the pixel substrate 31. FIG. 9 is a schematic cross-sectional view showing an example of the device structure of another image capture device 101A according to this modified example. In the image capture device 101A shown in FIG. 9, the lower side of the first via 71 is narrower than the upper side.

[Modification 2]
Next, a description will be given of Modification 2 of Embodiment 1. The following description will focus on the differences between Embodiment 1 and Modification 1 of Embodiment 1, and description of commonalities will be omitted or simplified.

FIG. 10 is a schematic cross-sectional view showing an example of the device structure of an imaging device 102 according to this modification. As shown in FIG. 10, the imaging device 102 according to this modification differs from another imaging device 101A according to Modification 1 of Embodiment 1 mainly in that it does not include a separation region 95.

In the imaging device 102, the first via 71 penetrates the entire pixel substrate 31. In the example shown in FIG. 10, the first via 71 is electrically connected to the wiring 61a via the third via 73, but the third via 73 may not be provided and the first via 71 may be directly connected to the wiring 61a. Also, in the example shown in FIG. 10, the first via 71 is formed from the upper surface 31a side, but it may also be formed from the lower surface 31b side.

[Modification 3]
Next, a description will be given of Modification 3 of Embodiment 1. The following description will focus on the differences from Embodiment 1 and Modifications 1 and 2 of Embodiment 1, and description of commonalities will be omitted or simplified.

FIG. 11 is a schematic cross-sectional view showing an example of the device structure of an imaging device 103 according to this modification. As shown in FIG. 11, the imaging device 103 according to this modification differs from the imaging device 101 according to Modification 1 of Embodiment 1 mainly in that it includes a wiring layer 132 instead of wiring layer 62.

The wiring layer 132 has a configuration in which the wiring such as wiring 62a and the interlayer insulating layer between the pad wiring 62p and the lower surface 31b of the pixel substrate 31 are removed from the wiring layer 62. The wiring layer 132 is composed of the pad wiring 62p and the insulating layer in the same layer as the pad wiring 62p.

In the imaging device 103, the first via 71 is connected to the pad wiring 62p without going through the wiring 62a. The first via 71 is in contact with the pad wiring 62p. This makes it possible to further shorten the first via 71. In this modified example, the pad wiring 62p is an example of the second wiring.

In the example shown in FIG. 11, the first via 71 is formed from the lower surface 31b side of the pixel substrate 31, but as shown in FIG. 12, it may be formed from the upper surface 31a side of the pixel substrate 31. FIG. 12 is a schematic cross-sectional view showing an example of the device structure of another image capture device 103A according to this modified example. In the image capture device 103A shown in FIG. 12, the lower side of the first via 71 is narrower than the upper side.

[Modification 4]
Next, a fourth modification of the first embodiment will be described. The following description will focus on the differences between the first embodiment and modifications 1 to 3 of the first embodiment, and description of commonalities will be omitted or simplified.

FIG. 13 is a schematic cross-sectional view showing an example of the device structure of an imaging device 104 according to this modified example. As shown in FIG. 13, the imaging device 104 according to this modified example differs from the imaging device 100 according to embodiment 1 mainly in that it further includes a pixel substrate 32, a wiring layer 64, a wiring layer 65, a fourth via 74, a fifth via 75, a sixth via 76, and a second bonding surface 82, and in that it includes a wiring layer 143 instead of the wiring layer 63.

The imaging device 104 has a structure in which a circuit board 41, a wiring layer 65, a wiring layer 64, a pixel substrate 32, a wiring layer 143, a wiring layer 62, a pixel substrate 31, a wiring layer 61, an insulating layer 55, and a photoelectric conversion unit 10 are stacked in this order along the Z-axis direction.

As shown in FIG. 13, pixel substrate 31 and pixel substrate 32 are stacked via a first bonding surface 81 located between pixel substrate 31 and pixel substrate 32. Furthermore, pixel substrate 32 and circuit substrate 41 are stacked via a second bonding surface 82 located between pixel substrate 32 and circuit substrate 41. Pixel substrate 32 is, for example, a p-type or n-type semiconductor substrate in which various impurity regions are formed. Pixel substrate 32 may also be a silicon substrate. In this modified example, pixel substrate 31 is an example of a first substrate, pixel substrate 32 is an example of a second substrate, and circuit substrate 41 is an example of a third substrate. A well may be formed in pixel substrate 32.

The pixel substrate 32 is located closer to the bottom surface 31b of the pixel substrate 31 than to the top surface 31a. The pixel substrate 32 includes a top surface 32a and a bottom surface 32b opposite the top surface 32a. The top surface 32a of the pixel substrate 32 is closer to the position where incident light enters the imaging device 104 than the bottom surface 32b. In this modified example, the top surface 32a is an example of the third surface, and the bottom surface 32b is an example of the fourth surface. A transistor Tr12, which is an example of a second transistor, is arranged on the top surface 32a of the pixel substrate 32. The transistor Tr12 is a transistor different from the transistor Tr11 included in the pixel 14, and is, for example, any of the above-mentioned amplification transistor 11, reset transistor 12, and address transistor 13. Note that for ease of viewing, Figure 13 shows only one transistor Tr12 arranged on the top surface 32a. For example, one or two of the amplification transistors 11, reset transistors 12, and address transistors 13 of the multiple pixels 14 are arranged on the upper surface 32a of the pixel substrate 32. In the imaging device 104, for example, the remaining one or two of the amplification transistors 11, reset transistors 12, and address transistors 13 of the multiple pixels 14 are arranged on the upper surface 31a of the pixel substrate 31.

On pixel substrate 31, transistors are arranged on top surface 31a, and on pixel substrate 32, transistors are arranged on top surface 32a, with pixel substrate 31 and pixel substrate 32 stacked face-to-back.

In the imaging device 104, the circuit board 41 is located closer to the bottom surface 32b of the pixel substrate 32 than to the top surface 32a. The transistors on the pixel substrate 32 are arranged on the top surface 32a, and the transistors on the circuit board 41 are arranged on the top surface 41a, with the pixel substrate 32 and the circuit board 41 stacked face-to-back.

The wiring layer 143 is located between the wiring layer 62 and the pixel substrate 32. The wiring layer 143 is located closer to the upper surface 32a of the pixel substrate 32 than the lower surface 32b, and covers the upper surface 32a of the pixel substrate 32. The wiring layer 143 has a configuration in which wiring 63b is added to the wiring layer 63. In this modified example, the wiring 63b is an example of a third wiring, and is located between the upper surface 32a of the pixel substrate 32 and the first bonding surface 81. The wiring 63b electrically connects, for example, at least one of the transistor Tr12 and the wiring 63a to the fourth via 74.

The wiring layer 64 is located between the pixel substrate 32 and the wiring layer 65. The wiring layer 64 is bonded to the wiring layer 65 by the second bonding surface 82. The wiring layer 64 is located closer to the lower surface 32b of the pixel substrate 32 than to the upper surface 32a, and covers the lower surface 32b of the pixel substrate 32. The wiring layer 64 includes multiple wirings including wirings 64a and pad wirings 64p, an interlayer insulating layer between the wirings, and multiple vias that provide electrical connection across the interlayer insulating layer.

The wiring 64a is an example of the fourth wiring and is located between the lower surface 32b of the pixel substrate 32 and the second bonding surface 82. The wiring 64a electrically connects the fourth via 74 and the pad wiring 64p.

The pad wiring 64p is formed in the lowest part of the wiring layer 64, i.e., in the insulating layer closest to the wiring layer 65. The pad wiring 64p forms a metal junction 82a on the second bonding surface 82.

The wiring layer 65 is located between the wiring layer 64 and the circuit board 41. The wiring layer 65 is located closer to the upper surface 41a of the circuit board 41 than to the lower surface thereof, and covers the upper surface 41a of the circuit board 41. In this modification, the upper surface 41a is an example of the fifth surface. The wiring layer 65 includes a plurality of wirings including wirings 65a and pad wirings 65p, an interlayer insulating layer between the wirings, and a plurality of vias that provide electrical connection across the interlayer insulating layer. Furthermore, an MIM capacitor may be formed within the wiring layer 65.

Wiring 65a is an example of a fifth wiring, and is located between the upper surface 41a of the circuit board 41 and the second bonding surface 82. Wiring 65a electrically connects pad wiring 65p to the peripheral circuit 4. Wiring 65a electrically connects, for example, pad wiring 65p to transistor Tr21. Wiring 65a and wiring 64a are also electrically connected via the second bonding surface 82.

The pad wiring 65p is formed in the uppermost insulating layer of the wiring layer 65, i.e., the insulating layer closest to the wiring layer 62. The pad wiring 65p forms a metal junction 82a on the second bonding surface 82.

The wiring and vias in the wiring layers 143, 64, and 65 each contain, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. Furthermore, the insulating layers, such as the interlayer insulating layers, in the wiring layers 143, 64, and 65 contain, for example, silicon oxide or silicon carbonitride.

The fourth via 74, fifth via 75, and sixth via 76 have the same structure as the first via 71, second via 72, and third via 73, respectively, except that they are arranged to penetrate pixel substrate 32 rather than pixel substrate 31. The fourth via 74, fifth via 75, and sixth via 76 may be formed from the same material as the first via 71, second via 72, and third via 73, respectively.

Specifically, the fourth via 74 penetrates at least a portion of the pixel substrate 32, and at least a portion of it is located within the pixel substrate 32. The fourth via 74 is, for example, a TSV. The wiring 63b and wiring 64a are electrically connected via the fourth via 74. The fourth via 74 is in contact with the wiring 64a.

The fourth via 74 is, for example, a nanoTSV. The diameter of the fourth via 74 is, for example, less than 1000 nm. The diameter of the fourth via 74 may be 100 nm or less, or 10 nm or less. The diameter of the fourth via 74 is, for example, 1 nm or more. The diameter of the fourth via 74 may be 5 nm or more.

The fourth via 74 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The fourth via 74 may contain copper as its main component.

In the example shown in FIG. 13, the upper side of the fourth via 74 is narrower than the lower side, so the fourth via 74 is formed from the lower surface 32b side of the pixel substrate 32. The diameter of the fourth via 74 exemplified above is the maximum diameter of the fourth via 74, and in the example shown in FIG. 13, it is the diameter of the lowest part of the fourth via 74.

The fifth via 75 is located within the pixel substrate 32. In the example shown in FIG. 13, the fifth via 75 is formed within an isolation region 95 formed in the pixel substrate 32. The fifth via 75 is, for example, a buried via formed by burying a metal within a trench for forming an STI structure. The fifth via 75 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium.

As shown in FIG. 13, a liner film 74a is formed on the radially outer surface of the fourth via 74. The fourth via 74 and the pixel substrate 32 are separated by the liner film 74a. Furthermore, a liner film 75a is formed on the radially outer surface of the fifth via 75. The fifth via 75 and the pixel substrate 32 are separated by the liner film 75a. The liner films 74a and 75a include at least an insulating film made of an insulating material such as silicon oxide. The liner films 74a and 75a may have a layered structure of an insulating film and a film of a metal nitride such as titanium nitride or a metal such as titanium.

The sixth via 76 is partially located within the pixel substrate 32. In the example shown in FIG. 13, the sixth via 76 is partially formed within an isolation region 95 formed in the pixel substrate 32. The sixth via 76 electrically connects the wiring 63b and the fourth via 74. The sixth via 76 is in contact with the wiring 63b. The sixth via 76 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The sixth via 76 is formed, for example, by forming a hole by etching or the like in the isolation region 95 in the pixel substrate 32 and in the insulating layer above the isolation region 95, and then depositing a metal such as copper in the hole.

Wiring 63b and fourth via 74 are electrically connected via fifth via 75. Wiring 63b and fifth via 75 are also electrically connected via sixth via 76. Therefore, wiring 63b and fourth via 74 are electrically connected via fifth via 75 and sixth via 76. Fourth via 74 and fifth via 75 are directly connected within pixel substrate 32, and fifth via 75 and sixth via 76 are directly connected within pixel substrate 32. The length of fourth via 74 may be longer than the lengths of fifth via 75 and sixth via 76. Fourth via 74, fifth via 75, and sixth via 76 overlap each other in a planar view. Furthermore, fourth via 74, fifth via 75, and sixth via 76 overlap with first via 71, second via 72, and third via 73 in a planar view. Additionally, the fourth via 74, the fifth via 75, and the sixth via 76 overlap with the isolation region 95 formed on the pixel substrate 32 in a plan view.

The second bonding surface 82 is located between the pixel substrate 32 and the circuit substrate 41. In the example shown in FIG. 13, the lower surface of the wiring layer 64 and the upper surface of the wiring layer 65 are bonded at the second bonding surface 82. In other words, the second bonding surface 82 is located at the interface between the wiring layer 64 and the wiring layer 65. The second bonding surface 82 is also the surface where the wafer including the pixel substrate 32 and the wafer including the circuit substrate 41 are bonded by hybrid bonding, and includes metal bonds 82a and insulating film bonds 82b. For ease of viewing, FIG. 13 shows some of the metal bonds 82a and insulating film bonds 82b with reference numerals, but metal bonds 82a and insulating film bonds 82b are formed throughout the second bonding surface 82.

Metal bond 82a is formed by bonding pad wiring 64p and pad wiring 65p. For example, if pad wiring 64p and 65p contain copper as a main component, metal bond 82a is a Cu-Cu bond. Insulating film bond 82b is formed by bonding an insulating layer in the same layer as pad wiring 64p included in wiring layer 64 to an insulating layer in the same layer as pad wiring 65p included in wiring layer 65.

In the imaging device 104, the transistors of the pixel 14 are arranged separately on the pixel substrate 31 and the pixel substrate 32. This allows elements such as pixel transistors to be arranged separately on the upper and lower substrates, further miniaturizing the imaging device 104. By arranging the pixel transistors on separate substrates, the number of elements per area in the pixel 14 is reduced, allowing the area of the amplifier transistor 11 to be increased, for example. Increasing the gate length and/or gate width of the amplifier transistor 11 can achieve noise reduction. Furthermore, the wiring 61a located above the upper surface 31a of the pixel substrate 31 is electrically connected to the wiring 62a located between the lower surface 31b of the pixel substrate 31 and the first bonding surface 81 via the first via 71. Furthermore, the wiring 63b located between the first bonding surface 81 and the upper surface 32a of the pixel substrate 32 is electrically connected to the wiring 64a located between the lower surface 32b of the pixel substrate 32 and the second bonding surface 82 via the fourth via 74. As a result, the fourth via 74 also provides the same effect as the first via 71, allowing the imaging device 104 to be made smaller. Furthermore, in the imaging device 104, the first via 71 overlaps with the fourth via 74 in a plan view, allowing the imaging device 104 to be made more compact effectively.

Note that the electrical connection structure from the wiring 61a including the first via 71 to the pad wiring 62p in the imaging device 104, and the electrical connection structure from the wiring 63b including the fourth via 74 to the pad wiring 64p are not limited to the example shown in FIG. 13, and structures such as those shown in any of FIGS. 8 to 12 may also be applied.

[Modification 5]
Next, a description will be given of Modification 5 of Embodiment 1. The following description will focus on the differences between this embodiment and Embodiment 1 and Modifications 1 to 4 of Embodiment 1, and description of commonalities will be omitted or simplified.

Figure 14 is a schematic cross-sectional view showing an example of the device structure of an imaging device 105 according to this modified example. As shown in Figure 14, the imaging device 105 according to this modified example differs from the imaging device 100 according to embodiment 1 mainly in that it further includes a circuit board 42, wiring layers 64 and 65, a fourth via 74, a fifth via 75, a sixth via 76, and a second bonding surface 82, and in that it includes a wiring layer 143 instead of wiring layer 63.

The imaging device 105 has a structure in which a circuit board 42, a wiring layer 65, a wiring layer 64, a circuit board 41, a wiring layer 143, a wiring layer 62, a pixel substrate 31, a wiring layer 61, an insulating layer 55, and a photoelectric conversion unit 10 are stacked in this order along the Z axis. It can also be said that the imaging device 105 has a structure in which the pixel substrate 32 and the circuit board 41 in the imaging device 104 according to Variation 4 of Embodiment 1 are replaced with the circuit board 41 and the circuit board 42, respectively.

As shown in FIG. 14, circuit board 41 and circuit board 42 are stacked via a second bonding surface 82 located between circuit board 41 and circuit board 42. Circuit board 42 is, for example, a p-type or n-type semiconductor substrate in which various impurity regions are formed. Circuit board 42 may also be a silicon substrate. In this modified example, pixel substrate 31 is an example of a first substrate, circuit board 41 is an example of a second substrate, and circuit board 42 is an example of a third substrate. A well may be formed in circuit board 42.

The circuit board 41 includes an upper surface 41a and a lower surface 41b opposite the upper surface 41a. The upper surface 41a of the circuit board 41 is closer to the position where incident light enters the imaging device 105 than the lower surface 41b. In this modified example, the upper surface 41a is an example of the third surface, and the lower surface 41b is an example of the fourth surface. The circuit board 42 is located closer to the lower surface 41b of the circuit board 41 than the upper surface 41a. The circuit board 42 includes an upper surface 42a which is closer to the position where incident light enters the imaging device 105 than the lower surface. In this modified example, the upper surface 42a is an example of the fifth surface. A transistor Tr22 is arranged on the upper surface 42a of the circuit board 42. The transistor Tr22 is a different transistor from the transistor Tr21 included in the peripheral circuit 4. Note that, for ease of viewing, Figure 14 shows only one transistor Tr22 arranged on the upper surface 42a. Multiple transistors that are part of the transistors included in each circuit of the peripheral circuit 4 can be arranged on the upper surface 42a.

In circuit board 41, the transistors are arranged on the upper surface 41a, and in circuit board 42, the transistors are arranged on the upper surface 42a, with circuit boards 41 and 42 stacked face-to-back.

The elements of each circuit in peripheral circuit 4 are formed separately on circuit board 41 and circuit board 42. There are no particular restrictions on how the elements of each circuit in peripheral circuit 4 are allocated to circuit board 41 and circuit board 42.

For example, one of circuit boards 41 and 42 may have an analog circuit arranged thereon and be supplied with an analog circuit voltage of about 3.3V, while the other may have a digital circuit arranged thereon and be supplied with a digital circuit voltage of about 1.2V. In this case, the gate length of the transistors in the analog circuit may be shorter than the gate length of the transistors in pixels 14, and the gate length of the transistors in the digital circuit may be shorter than the gate length of the transistors in the analog circuit. Also, for example, one of circuit boards 41 and 42 may have N-channel MOSFETs formed as transistors, while the other may have P-channel MOSFETs formed as transistors. Also, for example, one of circuit boards 41 and 42 may have memory such as SRAM (Static Random Access Memory) arranged thereon, while the other may have circuits other than memory arranged thereon.

Peripheral circuit 4 may be located on one of circuit boards 41 and 42, and an image signal processor (ISP) and/or a processor for a neural network may be located on the other.

In the imaging device 105, the wiring layer 143 is located between the wiring layer 62 and the circuit board 41. The wiring layer 143 is located closer to the upper surface 41a of the circuit board 41 than to the lower surface 41b, and covers the upper surface 41a of the circuit board 41. In this modified example, the wiring 63b is an example of a third wiring, and is located between the upper surface 41a of the circuit board 41 and the first bonding surface 81. In the imaging device 105, the wiring 63b electrically connects, for example, at least one of the transistor Tr21 and the wiring 63a to the fourth via 74.

The structure from circuit board 41 to circuit board 42 in imaging device 105 is the same as imaging device 104 according to Variant 4 of Embodiment 1, except that pixel board 32 and circuit board 41 are replaced with circuit board 41 and circuit board 42, respectively. In other words, the structure from circuit board 41 to circuit board 42 in imaging device 105 can be explained by replacing pixel board 32 and circuit board 41 with circuit board 41 and circuit board 42, respectively, in the corresponding parts of the explanation of the structure in Variant 4 of Embodiment 1.

In the imaging device 105, the elements of each circuit in the peripheral circuit 4 are arranged separately on the circuit board 41 and the circuit board 42, which allows the imaging device 105 to be further miniaturized. The imaging device 105 can also be miniaturized by providing the fourth via 74. Furthermore, in the imaging device 105, the first via 71 overlaps with the fourth via 74 in a plan view, which allows the imaging device 105 to be effectively miniaturized.

Note that the electrical connection structure from the wiring 61a including the first via 71 to the pad wiring 62p in the imaging device 105, and the electrical connection structure from the wiring 63b including the fourth via 74 to the pad wiring 64p are not limited to the example shown in FIG. 14, and structures such as those shown in any of FIGS. 8 to 12 may also be applied. Furthermore, the imaging device 105 may further include the pixel substrate 32 described above between the pixel substrate 31 and the circuit board 41.

[Modification 6]
Next, a sixth modification of the first embodiment will be described. The following description will focus on the differences between the sixth modification and the first embodiment and the first to fifth modifications of the first embodiment, and description of commonalities will be omitted or simplified.

FIG. 15 is a schematic cross-sectional view showing an example of the device structure of an imaging device 106 according to this modification. As shown in FIG. 15, the imaging device 106 according to this modification differs from the imaging device 100 according to embodiment 1 mainly in that it further includes a pixel substrate 32, a wiring layer 66, and a third bonding surface 83, and in that it includes a wiring layer 161 instead of wiring layer 61. The imaging device 106 according to this modification also differs from the imaging device 100 according to embodiment 1 in that the electrical connection structure from the wiring 61a, including the first via 71, to the pad wiring 62p is formed on the pixel substrate 32, not the pixel substrate 31, and that the transistor Tr11, charge accumulation region 91, and plug 92 are disposed on the lower surface 31b of the pixel substrate 31.

The imaging device 106 has a structure in which a circuit board 41, a wiring layer 63, a wiring layer 62, a pixel substrate 32, a wiring layer 161, a wiring layer 66, a pixel substrate 31, an insulating layer 55, and a photoelectric conversion unit 10 are stacked in this order along the Z axis.

As shown in FIG. 15, in the imaging device 106, the pixel substrate 31 and the pixel substrate 32 are stacked together with a third bonding surface 83 located between the pixel substrates 31 and 32. The pixel substrate 32 and the circuit substrate 41 are stacked together with a first bonding surface 81 located between the pixel substrate 32 and the circuit substrate 41. In this modified example, the pixel substrate 32 is an example of a first substrate, and the circuit substrate 41 is an example of a second substrate.

In the imaging device 106, the transistors on the pixel substrate 31 are arranged on the lower surface 31b, and the transistors on the pixel substrate 32 are arranged on the upper surface 32a, with the pixel substrates 31 and 32 stacked face-to-face.

The wiring layer 66 is located between the pixel substrate 31 and the wiring layer 161. The wiring layer 66 is located closer to the lower surface 31b of the pixel substrate 31 than to the upper surface 31a, and covers the lower surface 31b of the pixel substrate 31. The wiring layer 66 includes multiple wirings including wirings 66a and pad wirings 66p, an interlayer insulating layer between the wirings, and multiple vias that provide electrical connection across the interlayer insulating layer. MIM capacitance may also be formed within the wiring layer 66.

The wiring 66a is located between the lower surface 31b of the pixel substrate 31 and the third bonding surface 83. The wiring 66a electrically connects the pad wiring 66p to the pixel 14. The wiring 66a electrically connects, for example, the pad wiring 66p to the transistor Tr11.

The pad wiring 66p is formed in the lowest part of the wiring layer 66, i.e., in the insulating layer closest to the wiring layer 161. The pad wiring 66p forms a metal junction 83a on the third bonding surface 83.

The wiring layer 161 is located between the wiring layer 66 and the pixel substrate 32. The wiring layer 161 is located closer to the upper surface 32a of the pixel substrate 32 than the lower surface 32b, and covers the upper surface 32a of the pixel substrate 32. In this modified example, the upper surface 32a is an example of the first surface. The wiring layer 161 has a configuration in which a pad wiring 61p is added to the wiring layer 61. The pad wiring 61p is formed at the uppermost part of the wiring layer 161, that is, in the insulating layer closest to the wiring layer 66. The pad wiring 61p forms a metal junction 83a at the third bonding surface 83. The pad wiring 61p is electrically connected to, for example, at least one of the transistor Tr12 and the wiring 61a.

The wiring and vias in the wiring layers 66 and 161 each contain, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. Furthermore, the insulating layers, such as the interlayer insulating layers, in the wiring layers 66 and 161 contain, for example, silicon oxide or silicon carbonitride.

The third bonding surface 83 is located between the pixel substrate 31 and the pixel substrate 32. In the example shown in FIG. 15, the lower surface of the wiring layer 66 and the upper surface of the wiring layer 161 are bonded at the third bonding surface 83. In other words, the third bonding surface 83 is located at the interface between the wiring layer 66 and the wiring layer 161. The third bonding surface 83 is also the surface where the wafer including the pixel substrate 31 and the wafer including the pixel substrate 32 are bonded by hybrid bonding, and includes metal bonds 83a and insulating film bonds 83b. For ease of viewing, FIG. 15 shows some of the metal bonds 83a and insulating film bonds 83b with reference numerals, but metal bonds 83a and insulating film bonds 83b are formed throughout the third bonding surface 83.

Metal bond 83a is formed by bonding pad wiring 66p and pad wiring 61p. For example, if pad wirings 66p and 61p contain copper as a main component, metal bond 83a is a Cu-Cu bond. Insulating film bond 83b is formed by bonding an insulating layer in the same layer as pad wiring 66p included in wiring layer 66 to an insulating layer in the same layer as pad wiring 61p included in wiring layer 161.

In the imaging device 106, the circuit board 41 is located closer to the bottom surface 32b of the pixel substrate 32 than to the top surface 32a. In this modified example, the bottom surface 32b is an example of the second surface. In the pixel substrate 32, transistors are arranged on the top surface 32a, and in the circuit board 41, transistors are arranged on the top surface 41a, with the pixel substrate 32 and circuit board 41 stacked face-to-back.

The structure of the imaging device 106, from the circuit board 41 to the pixel board 32, is the same as that of the imaging device 100 according to embodiment 1, except that the pixel board 31 is replaced with the pixel board 32. In other words, the structure of the imaging device 106, from the circuit board 41 to the pixel board 32, can be explained by substituting the pixel board 31 for the pixel board 32 in the corresponding parts of the explanation in embodiment 1.

Note that the electrical connection structure from the wiring 61a including the first via 71 to the pad wiring 62p in the imaging device 106 is not limited to the example shown in FIG. 15, and structures such as those shown in any of FIGS. 8 to 12 may also be applied. The imaging device 106 may also further include the above-mentioned circuit board 42 below the circuit board 41.

[Modification 7]
Next, a seventh modification of the first embodiment will be described. The following description will focus on the differences between the seventh modification and the first embodiment and the first to sixth modifications of the first embodiment, and description of commonalities will be omitted or simplified.

Figure 16 is a schematic cross-sectional view showing an example of the device structure of an imaging device 107 according to this modification. As shown in Figure 16, the imaging device 107 according to this modification differs from the imaging device 106 according to Modification 6 of Embodiment 1 mainly in that it does not include a third bonding surface 83 and that it includes wiring layers 176 and 171 instead of wiring layers 66 and 161. The imaging device 107 according to this modification also differs from the imaging device 106 according to Modification 6 of Embodiment 1 in that a transistor Tr11, a charge accumulation region 91, and a plug 92 are arranged on the upper surface 31a of the pixel substrate 31.

The imaging device 107 has a structure in which a circuit board 41, a wiring layer 63, a wiring layer 62, a pixel substrate 32, a wiring layer 171, a pixel substrate 31, a wiring layer 176, an insulating layer 55, and a photoelectric conversion unit 10 are stacked in this order along the Z axis.

In the imaging device 107, the pixel substrates 31 and 32 are stacked using, for example, 3DSI (3D Sequential Integration) technology without using hybrid junctions such as TSV junctions and Cu-Cu junctions. For example, elements such as transistor Tr12 are formed on the pixel substrate 32, and then the pixel substrate 31 is attached to a substrate on which a wiring layer 171 is formed, as if by transfer printing, or the pixel substrate 31 is formed by monolithically depositing a semiconductor layer such as a silicon layer. Then, elements such as transistor Tr11 are formed on the pixel substrate 31, and a wiring layer 176 is formed on top of them. Although not shown, plugs may be formed to electrically connect the elements formed on the pixel substrate 31 and the elements formed on the pixel substrate 32. Furthermore, the pixel substrate 32 and the circuit substrate 41 are stacked via a first bonding surface 81 located between the pixel substrate 32 and the circuit substrate 41. In this modification, the pixel substrate 32 is an example of a first substrate, and the circuit substrate 41 is an example of a second substrate.

The wiring layer 176 is located between the pixel substrate 31 and the photoelectric conversion unit 10. The wiring layer 176 is located closer to the upper surface 31a of the pixel substrate 31 than to the lower surface 31b, and covers the upper surface 31a of the pixel substrate 31. The wiring layer 176 includes multiple wires, an interlayer insulating layer between the wires, and multiple vias that provide electrical connections across the interlayer insulating layer. Furthermore, an MIM capacitor may be formed within the wiring layer 176.

The wiring layer 171 is located between the pixel substrate 31 and the pixel substrate 32. The wiring layer 171 is located closer to the lower surface 31b of the pixel substrate 31 than to the upper surface 31a, and closer to the upper surface 32a of the pixel substrate 32 than to the lower surface 32b, and covers the lower surface 31b of the pixel substrate 31 and the upper surface 32a of the pixel substrate 32. The wiring layer 171 includes multiple wirings including the wiring 61a, an interlayer insulating layer between the wirings, and multiple vias that provide electrical connection across the interlayer insulating layer. Furthermore, an MIM capacitor may be formed within the wiring layer 171.

In the imaging device 107, the wiring 61a is located closer to the upper surface 32a of the pixel substrate 32 than to the lower surface 32b, and closer to the pixel substrate 32 than to the photoelectric conversion unit 10. The wiring 61a electrically connects the first via 71 and the pixel 14. The wiring 61a electrically connects, for example, the first via 71 and the transistor Tr12.

Note that the electrical connection structure from the wiring 61a including the first via 71 to the pad wiring 62p in the imaging device 107 is not limited to the example shown in FIG. 16, and structures such as those shown in any of FIGS. 8 to 12 may also be applied. Furthermore, the imaging device 107 may further include the above-mentioned circuit board 42 below the circuit board 41.

(Embodiment 2)
The following describes an imaging device according to embodiment 2. The following mainly describes differences from embodiment 1 and variations 1 to 7 of embodiment 1, and omits or simplifies descriptions of commonalities.

[composition]
First, the configuration of the imaging device according to this embodiment will be described. Fig. 17 is a schematic cross-sectional view showing an example of the device structure of an imaging device 200 according to this embodiment.

As shown in FIG. 17, the imaging device 200 according to this embodiment differs from the imaging device 100 according to embodiment 1 mainly in that the first via 71, the second via 72, and the third via 73 are located within the pixel array region R1 in a plan view. In other words, in the imaging device 200, a structure similar to that of the imaging device 100 shown in FIG. 3 is formed within the pixel array region R1. This makes it possible to reduce the area of the region surrounding the pixel array region R1, thereby enabling the imaging device 200 to be made more compact.

In the imaging device 200, the first via 71, the second via 72, and the third via 73 overlap with an isolation region 96 formed in the pixel substrate 31 in a planar view. The isolation region 96 is located within the pixel substrate 31 at the boundary between the pixel regions R2 of two adjacent pixels 14, which are examples of a first pixel and a second pixel. The isolation region 96 is a pixel isolation region that separates adjacent pixels 14. The isolation region 96 has, for example, an STI structure. The first via 71, the second via 72, and the third via 73 are the same as those in the imaging device 100 of embodiment 1, except that they are formed in a position that overlaps with the isolation region 96 rather than the isolation region 95 in a planar view. In the example shown in FIG. 17, the first via 71, second via 72, and third via 73 are formed in an isolation region 96 that separates adjacent pixels 14, but the first via 71, second via 72, and third via 73 may also be formed in an intra-pixel isolation region, which is an isolation region that separates elements such as transistors within the pixel 14.

Here, the size of the first via 71 will be explained, giving specific examples of dimensions. Note that the following explanation is intended to illustrate one example of the size of the first via 71 and is not intended to limit the scope of this disclosure.

FIG. 18 is a plan view illustrating the size of the first via 71. FIG. 18 shows the sizes of the first via 71 and the charge storage region 91 in a plan view. Also in FIG. 18, the pixel region R2, which is the region where the pixels 14 are arranged in a plan view, is shown as a rectangle with dashed lines. To give an idea of the size, FIG. 18 also shows a 0.2 μm x 0.5 μm grid with dotted lines, which corresponds to the size of a 22 nm generation SRAM consisting of six transistors. Also, in the example shown in FIG. 18, the size of one pixel region R2 is 1.5 μm x 1.5 μm, which is large enough to fit 18 SRAMs.

In the example shown in FIG. 18, the diameter of the first via 71 is 100 nm. In a plan view, the first via 71 is smaller than, for example, the charge storage region 91. By making the diameter of the first via 71 as small as 100 nm, the first via 71 can be placed within the pixel array region R1 without affecting the size of the pixel region R2, and can be used to connect between the pixel substrate 31 and the circuit board 41.

Note that the structure formed within the pixel array region R1 of the imaging device 200 is not limited to the example shown in FIG. 17, and the structure of an imaging device according to any of the modifications of embodiment 1, such as those shown in any of FIGS. 8 to 16, may be applied within the pixel array region R1. Furthermore, the imaging device 200 may include first vias 71 and the like not only within the pixel array region R1 but also outside the pixel array region R1.

[Flat Layout]
Next, an example of a planar layout of the image pickup device 200 according to the present embodiment will be described. Note that, as long as the image pickup device 200 includes the first via 71 arranged at any position within the pixel array region R1, the planar layout of the image pickup device 200 is not limited to the example described below.

FIG. 19 is a plan view showing a schematic example of a planar layout of an imaging device 200 according to this embodiment. FIG. 19 shows a schematic arrangement of an amplification transistor 11, pad wiring 62p, charge storage region 91, plug 92, first via 71, and isolation region 96 in a planar view. Also, in FIG. 19, pixel regions R2 are shown as rectangles drawn with dashed lines. In FIG. 19, four pixel regions R2 are shown, corresponding to two rows and two columns of pixels 14. This also applies to the planar layout views described below.

Furthermore, Figure 19 shows the arrangement of the amplification transistor 11, pad wiring 62p, charge storage region 91, and plug 92 in the two pixel regions R2 on the left side, and does not show the arrangement of these elements in the other pixel regions R2.

As shown in FIG. 19, the first via 71 is located at the boundary of the pixel region R2 in a planar view. In the example shown in FIG. 19, the first via 71 is located at a side of the outline of the pixel region R2 in a planar view. The first via 71 may also be located at a corner of the outline of the pixel region R2. The first via 71 may also be located within the pixel region R2.

In the example shown in FIG. 19, one first via 71 is arranged for one pixel region R2, but two or more first vias 71 may be arranged for one pixel region R2.

Furthermore, in the arrangement in one pixel region R2, the distance between the plug 92 and the first via 71 in the same pixel region R2 as the amplifier transistor 11 is longer in a planar view than the distance between the first via 71 and the amplifier transistor 11. Further, in the arrangement in one pixel region R2, the distance between the plug 92 and the first via 71 in the same pixel region R2 as the pad wiring 62p is longer in a planar view than the distance between the first via 71 and the pad wiring 62p. Further, in the arrangement in one pixel region R2, the pad wiring 62p is located between the plug 92 and the first via 71 in the same pixel region R2 as the pad wiring 62p in a planar view. Note that in the arrangement in one pixel region R2, the amplifier transistor 11 may be located between the plug 92 and the first via 71 in the same pixel region R2 as the amplifier transistor 11 in a planar view.

In the example shown in FIG. 19, the pitch at which the pixels 14 are arranged is the same as the pitch at which the pad wirings 62p are arranged in a plan view, and one pad wiring 62p is arranged for one pixel region R2. Note that the pitch at which the pixels 14 are arranged may be different from the pitch at which the pad wirings 62p are arranged. Furthermore, if the pitch at which the pad wirings 62p are arranged is greater than the pitch at which the pixels 14 are arranged, one pad wiring 62p may be shared by two or more first vias 71 in the electrical connection between the pad wiring 62p and the first vias 71.

19, in a plan view, the periphery of the pixel region R2 of each pixel 14 is surrounded by an isolation region 96. That is, in a plan view, an isolation region 96 is arranged at all boundaries between two adjacent pixel regions R2. As shown in FIG. 20, an isolation region 96 does not have to be formed on the pixel substrate 31. FIG. 20 is a plan view schematically showing an example of a planar layout when an isolation region 96 is not formed in an imaging device 200 according to this embodiment. FIG. 20 representatively illustrates the arrangement of the amplification transistor 11, pad wiring 62p, charge storage region 91, and plug 92 in the two pixel regions R2 on the left, and does not illustrate the arrangement of these elements in the other pixel regions R2. In another example of a planar layout of the imaging device 200 described below, an isolation region 96 does not have to be formed on the pixel substrate 31.

Next, another example of the planar layout of the imaging device 200 will be described.

First, a first example of a planar layout of the imaging device 200 will be described. Figure 21 is a plan view that schematically shows the first example of a planar layout of the imaging device 200 according to this embodiment.

In the example shown in Figure 21, the arrangement of the amplification transistor 11, pad wiring 62p, charge storage region 91, plug 92, and first via 71 in the pixel regions R2 of two pixels 14 adjacent to each other in the X-axis direction is reversed in the X-axis direction. The X-axis direction is, for example, the row direction, but it may also be the column direction. In other words, Figure 21 shows a planar layout that is line-symmetrical with respect to the boundary line between the pixel regions R2 of two pixels 14 adjacent to each other in the X-axis direction.

In the example shown in FIG. 21, the first via 71 is located at the boundary of the pixel region R2 in a plan view, but it may also be located within the pixel region R2.

In the example shown in FIG. 21, in a plan view, the distance between the plugs 92 in the pixel regions R2 of two pixels 14 adjacent to each other in the X-axis direction is smaller than the distance between the plug 92 and the first via 71. This increases the distance between the first via 71 and the plug 92, making it possible to suppress noise generated in the plug 92 connected to the charge storage region 91 due to interference from the first via 71.

Next, a second example of the planar layout of the imaging device 200 will be described. Figure 22 is a plan view that schematically shows the second example of the planar layout of the imaging device 200 according to this embodiment.

In the example shown in FIG. 22, the arrangements of the amplification transistor 11, pad wiring 62p, and first via 71 are reversed in the X-axis direction in the pixel regions R2 of two pixels 14 adjacent to each other in the X-axis direction. Also, in the example shown in FIG. 22, the two adjacent pixels 14 share a charge storage region 91 and plug 92. No isolation region 96 is arranged at the boundary between the pixel regions R2 of two adjacent pixels 14 in the X-axis direction, and the charge storage region 91 and plug 92 shared by the two pixels 14 are arranged there. Also, the first via 71 is located on the side of the outline of the pixel region R2 that faces the boundary. This makes it possible to increase the distance between the first via 71 and the plug 92.

Next, a third example of the planar layout of the imaging device 200 will be described. Figure 23 is a plan view schematically showing the third example of the planar layout of the imaging device 200 according to this embodiment.

23, four adjacent pixels 14 arranged in two rows and two columns in the row and column directions share a charge storage region 91 and a plug 92. No isolation region 96 is disposed at the boundary between the pixel regions R2 of the four pixels 14, and the charge storage region 91 and plug 92 shared by the four pixels 14 are disposed at the center of the pixel regions R2 of the four pixels 14. In addition, in the example shown in FIG. 23, the first via 71 is located on the outer periphery of the pixel regions R2 of the four pixels 14. This allows the distance between the first via 71 and the plug 92 to be increased. In the example shown in FIG. 23, the first via 71 is located on a side of the outline of the pixel region R2 in a plan view. The first via 71 may also be located at a corner of the outline of the pixel region R2 in a plan view.

In the example shown in FIG. 23, the amplification transistors 11 are arranged in a two-row, two-column array in the row and column directions in a plan view, closer to the periphery than the center of the pixel regions R2 of four adjacent pixels 14, but may also be arranged in a position closer to the center than the periphery of the pixel regions R2 of the four pixels 14.

(Embodiment 3)
Next, a description will be given of embodiment 3. In embodiment 3, a camera system including an imaging device according to the present disclosure will be described.

FIG. 24 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

As shown in FIG. 24, the camera system 400 according to this embodiment includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

Lens optical system 601 focuses light onto the imaging surface of imaging device 602. Lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As imaging device 602, for example, an imaging device according to any of the above-mentioned Embodiment 1, Variations 1 to 7 of Embodiment 1, and Embodiment 2 is used.

The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data from the imaging device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With this configuration, electronic devices that include the imaging device 602 as a part thereof can be made smaller.

(Other embodiments)
While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

For example, in the above embodiment, the first bonding surface 81, the second bonding surface 82, and the third bonding surface 83 are bonded by hybrid bonding, but this is not limited to this. Bonding of at least one of the first bonding surface 81, the second bonding surface 82, and the third bonding surface 83 may be by a method other than hybrid bonding, such as bump bonding.

Furthermore, for example, in the above embodiment, the photoelectric conversion unit 10 includes the pixel electrode 50, the photoelectric conversion layer 51, and the upper electrode 52, but this is not limited to this. The photoelectric conversion unit 10 may also be a photodiode. For example, the photoelectric conversion unit 10 may be a photodiode including an impurity region arranged on the pixel substrate 31. Furthermore, the photoelectric conversion unit 10 may be a stack of a photodiode including an impurity region arranged on the pixel substrate 31 and a photoelectric conversion layer.

Furthermore, for example, in the above-described embodiments, the circuit board may be arranged not only with peripheral circuits, but also with circuits other than peripheral circuits, such as an image signal processor (ISP) and/or a processor for a neural network.

Furthermore, various modifications, substitutions, additions, omissions, etc. may be made to each of the above embodiments within the scope of the claims or their equivalents.

The imaging device and camera system according to the present disclosure are useful, for example, in image sensors and digital cameras. The imaging device and camera system according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like.

4 Peripheral circuit 10 Photoelectric conversion unit 11 Amplifying transistor 12 Reset transistor 13 Address transistor 14 Pixel 14A Pixel array 15 Vertical scanning circuit 16 Counter electrode signal line 17 Vertical signal line 18 Load circuit 19 Column signal processing circuit 20 Horizontal signal readout circuit 21 Power supply line 22 Differential amplifier 23 Feedback line 24 Charge storage node 25 Charge detection circuit 26 Address signal line 27 Reset signal line 28 Horizontal common signal line 30 Voltage control circuit 31, 32 Pixel substrate 31a, 32a, 41a, 42a Upper surface 31b, 32b, 41b Lower surface 31W, 41W Wafer 41, 42 Circuit substrate 50 Pixel electrode 51 Photoelectric conversion layer 52 Upper electrode 53 Shield electrode 55, 62I, 63I Insulating layer 56 Support substrate 61, 62, 62M, 63, 63M, 64, 65, 66, 132, 143, 161, 171, 176 Wiring layers 61a, 62a, 63a, 63b, 64a, 65a, 66a Wirings 61p, 62p, 63p, 64p, 65p, 66p Pad wiring 71 First vias 71a, 72a, 74a, 75a Liner film 71G First via group 72 Second via 73 Third via 74 Fourth via 75 Fifth via 76 Sixth via 81 First bonding surface 81a, 82a, 83a Metal bonding 81b, 82b, 83b Insulating film bonding 82 Second bonding surface 83 Third bonding surface 91 Charge storage region 92 Plugs 95, 96 Isolation region 100 Imaging devices 101, 101A, 102, 103, 103A, 104, 105, 106, 107, 200, 602 Imaging device 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit R1 Pixel array region R2 Pixel regions Tr11, Tr12, Tr21, Tr22 Transistor

Claims (19)

An imaging device,
a first substrate including a first surface and a second surface opposite to the first surface, the first surface being closer to a position where incident light enters the imaging device than the second surface;
a second substrate located closer to the second surface than the first surface of the first substrate, the second substrate including a third surface and a fourth surface facing the third surface, the third surface being closer to the first substrate than the fourth surface;
a first bonding surface located between the first substrate and the second substrate;
a photoelectric conversion unit located closer to the first surface than the second surface of the first substrate and converting the incident light into electric charges;
a first wiring located between the photoelectric conversion unit and the first substrate;
a second wiring located between the second surface of the first substrate and the first bonding surface;
a third wiring located between the third surface of the second substrate and the first bonding surface;
a first via located at least partially within the first substrate;
Equipped with
the first substrate and the second substrate are stacked via the first bonding surface,
The first wiring and the second wiring are electrically connected through the first via.
Imaging device. the first via is a through-silicon via;
The imaging device according to claim 1 . further comprising a second via located in the first substrate;
The first wiring and the first via are electrically connected via the second via.
The imaging device according to claim 1 . Further comprising a third via;
the first wiring and the second via are electrically connected via the third via;
the first via and the second via are directly connected within the first substrate;
the third via and the second via are directly connected within the first substrate;
The imaging device according to claim 3 . Further comprising a third via;
the first wiring and the first via are electrically connected via the third via;
the first via and the third via are directly connected within the first substrate;
The imaging device according to claim 1 . The diameter of the first via is 10 nm or less.
The imaging device according to claim 1 . The first bonding surface includes an insulating film bond and a metal bond.
The imaging device according to claim 1 . a first transistor disposed on the first surface of the first substrate;
a second transistor disposed on the third surface of the second substrate;
Further provided with
The imaging device according to claim 1 . a pixel array including a plurality of pixels arranged in a matrix;
the first via is located within a region in which the pixel array is arranged in a plan view;
The imaging device according to claim 1 . a pixel array including a plurality of pixels arranged in a matrix;
the first via is located outside an area in which the pixel array is arranged in a plan view;
The imaging device according to claim 1 . a third substrate located closer to the fourth surface than the third surface of the second substrate, the third substrate including a fifth surface and a sixth surface opposite to the fifth surface, the fifth surface being closer to the second substrate than the sixth surface;
a second bonding surface located between the second substrate and the third substrate;
a fourth wiring located between the fourth surface of the second substrate and the second bonding surface;
a fifth wiring located between the fifth surface of the third substrate and the second bonding surface;
a fourth via at least partially located within the second substrate;
Furthermore,
the second substrate and the third substrate are stacked via the second bonding surface,
the third wiring and the fourth wiring are electrically connected via the fourth via;
the first via overlaps with the fourth via in a plan view;
The imaging device according to claim 1 . an intra-pixel element;
a charge storage unit that stores the charge;
a plug that electrically connects the photoelectric conversion unit and the charge accumulation unit;
and further comprising a pixel including:
the intra-pixel element is located between the first via and the plug in a plan view;
The imaging device according to claim 1 . a charge storage unit that stores the charge;
a pixel including a plug electrically connecting the photoelectric conversion unit and the charge accumulation unit,
the first bonding surface includes a metal bond located within a region in which the pixel is arranged in a plan view;
the metal junction is located between the first via and the plug in the plan view.
The imaging device according to claim 1 . further comprising an isolation region located within the first substrate;
the isolation region overlaps with the first via in a plan view;
The imaging device according to claim 1 . A first pixel;
a second pixel adjacent to the first pixel;
and a plurality of pixels including:
Each of the plurality of pixels is
a charge storage unit that stores the charge;
a plug that electrically connects the photoelectric conversion unit and the charge accumulation unit;
Including,
the first via is located, in a plan view, within a region in which the first pixel is arranged or at a boundary between a region in which the first pixel is arranged and a region in which the second pixel is arranged;
In the plan view, a distance between the plug of the first pixel and the plug of the second pixel is smaller than a distance between the plug of the first pixel and the first via.
The imaging device according to claim 1 . A first pixel;
a second pixel adjacent to the first pixel;
a pixel isolation region located in the first substrate at a boundary between a region in which the first pixels are arranged in a plan view and a region in which the second pixels are arranged in the plan view;
Furthermore,
the first via overlaps with the pixel isolation region in the plan view;
The imaging device according to claim 1 . the first substrate includes pixel elements;
the second substrate includes a logic transistor;
The imaging device according to claim 1 . The photoelectric conversion unit is
an upper electrode;
A lower electrode;
a photoelectric conversion layer located between the upper electrode and the lower electrode;
The imaging device according to claim 1 . The photoelectric conversion layer contains an organic material.
The imaging device according to claim 18.