WO2025196458A1

WO2025196458A1 - A structure for an electronic device

Info

Publication number: WO2025196458A1
Application number: PCT/GB2025/050612
Authority: WO
Inventors: Vincenzo CURTO
Original assignee: Paragraf Ltd
Current assignee: Paragraf Ltd
Priority date: 2024-03-22
Filing date: 2025-03-21
Publication date: 2025-09-25
Anticipated expiration: 2026-09-22
Also published as: GB202404128D0

Abstract

There is provided a structure (200) for an electronic device, the structure comprising: a patterned two dimensional material layer structure (2101) on a substrate (205); and a patterned dielectric layer (235") having (i) a first portion which is on and/or over the substrate adjacent an edge of the two dimensional material layer structure, and (ii) a second portion which extends from the first portion over the two dimensional material layer structure, and makes resting contact with a surface of the two dimensional material layer structure thereby defining a cavity (245) between at least the dielectric layer and the two dimensional material layer structure; wherein the dielectric layer has a thickness of less than 250 nm.

Description

A structure for an electronic device

The present invention relates to a structure for an electronic device, and to a method for the manufacture of such a structure. More particularly, the structure comprises a patterned two-dimensional material layer structure on a substrate, together with a patterned dielectric layer. The present invention further relates to electronic devices which incorporate such a structure, for example sensors.

Two-dimensional (2D) materials, in particular graphene, and their electronic devices are currently the focus of intense research and development worldwide. 2D-materials have been shown to have extraordinary properties, both in theory and in practice which has led to a deluge of products incorporating such materials which include coatings, batteries and sensors to name but a few. Graphene is most prominent and is being investigated for a range of potential applications. Most notable is the use of graphene in electronic devices and their constituent components which includes transistors, diodes, LEDs, photovoltaic cells, Hall-effect sensors, current sensors, biosensors, gas sensors and the like.

Due to the exceptionally thin nature of two-dimensional materials, and their often minimal interaction with the underlying substrate/wafer generally being based essentially only on weak van der Waals interactions, the inventors have found that such materials are particularly susceptible to delamination. This problem is especially pronounced under solution-based processing and other environments and occasions where the two-dimensional material is exposed to liquids and solutions (i.e. in both device manufacture and use of the final device). One such example of a device having an exposed surface of a two-dimensional material for receiving liquid samples is a biosensor.

As a result, there remains a need in the art for products which incorporate two-dimensional materials which are less susceptible to delamination. Moreover, it is also desirable for such products to be manufactured by methods which do not increase the complexity or the number of process steps so as to maintain an efficient process, but further this is desired so as to mitigate the risk of damaging the two-dimensional material during manufacture by minimising the time and individual steps required for device fabrication.

WO 2023/148149 relates to graphene sensors wherein the graphene layer structure has an exposed sample surface for receiving a sample for testing, particularly graphene biosensors. The sensor comprises first and second electrical contacts in contact with the graphene layer structure, and arranged on opposite sides of the sample surface, and each electrical contact being separated from the sample surface by a directly adjacent metal oxide layer which serves to isolate the electrical contact from the sample surface. WO 2022/246261 relates to field effect transistor arrays, and more particularly relates to an integrated circuit with two dimensional field effect transistors for direct and indirect target signal measurement.

US 2017/0365474 relates to creating wells on a graphene sheet by depositing a passivation layer on top of the graphene sheet.

US 2017/0365477 discloses a method for providing a temporary layer on a graphene sheet comprising: transferring a graphene sheet to a selected wafer; depositing a metal layer to a first surface of the graphene sheet; and removing the metal layer.

US 2017/0365562 discloses a method for patterning graphene comprising: placing a graphene sheet on a wafer; depositing a metal layer on the graphene sheet; depositing a photoresist layer on the metal layer; and etching a pattern on the photoresist layer to expose the metal layer.

GB 2615341 relates to graphene sensors wherein the graphene layer structure has an exposed sample surface for receiving a sample for testing, in particular one in which the sample surface is devoid of photoresist.

US 2018/136266 discloses a resistive environmental sensor including an electrode stack and a sensing layer, the electrode stack comprising a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers, wherein the electrode stack includes a side surface, and the first and second electrode layers are exposed on the side surface.

ON 116799071 relates to a two-dimensional material device structure with an air partition wall and a preparation method thereof, and belongs to the technical field of transistor electronic device preparation.

The present invention aims to overcome, or at least reduce, the aforementioned problems in the prior art, ideally so as to allow for the efficient integration of two-dimensional material into robust electronic devices, or to at least provide a commercially viable alternative thereto.

Thus, a first aspect of the present invention provides a structure for an electronic device, the structure comprising: a patterned two-dimensional material layer structure on a substrate; and a patterned dielectric layer having (i) a first portion which is on and/or over the substrate adjacent an edge of the two-dimensional material layer structure, and (ii) a second portion which extends from the first portion over the two-dimensional material layer structure, and makes resting contact with a surface of the two-dimensional material layer structure thereby defining a cavity between at least the dielectric layer and the two-dimensional material layer structure; wherein the dielectric layer has a thickness of less than 250 nm.

A second aspect therefore provides an electronic device comprising such a structure, and preferably the device is an electrochemical sensor.

A third aspect of the present invention provides a method for the manufacture of the structure described herein, or the electronic device comprising the structure, the method comprising:

(I) providing a layer structure comprising:

(a) a substrate;

(b) a co-patterned stack of a metal layer on a two-dimensional material layer structure on the substrate; and

(c) a patterned dielectric layer having a thickness of less than 250 nm; wherein (i) a first portion of the patterned dielectric layer is on and/or over the substrate adjacent an edge of the co-patterned stack, and (ii) a second portion of the patterned dielectric layer extends from the first portion onto a portion of the stack by a distance of at least 1 pm; and

(II) etching at least a portion of the metal layer to expose a surface of the two-dimensional material layer structure and to undercut the patterned dielectric layer by a distance of at least 1 pm.

The present disclosure will now be described further. In the following passages, different aspects/embodiments of the disclosure are defined in more detail. Each aspect/embodiment so defined may be combined with any other aspect/embodiment or aspects/embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

Consequently, the following features as described herein apply equally to all aspects of the invention, unless the context clearly dictates otherwise. For example, the structure is preferably obtainable by the method described such that any feature described in respect of the method may describe the structure (or any device comprising the structure), and vice versa.

Structure and device

The present invention provides a structure for an electronic device. That is, the present invention provides a structure formed from layers of two-dimensional material and dielectric material, each having been patterned. The structure of these layers is such that a cavity exists therebetween, the cavity being a direct result of the method described herein. This configuration of layers on a substrate (which may, depending on the context, instead be referred to in the art as a wafer) is suitable for integration into electronic devices comprising two-dimensional materials, and indeed, such devices are improved as a result. Thus the present disclosure also provides an electronic device comprising the structure described herein.

The structure comprises a patterned two-dimensional material layer structure on a substrate. Two- dimensional materials per se are well-known, the most preferred for the present invention, in particular subsequent electronic devices, being graphene. Two-dimensional materials include mono-elemental two-dimensional materials such as graphene, silicene, phosphorene, borophene (whether doped or un-doped) as well as hetero-elemental two-dimensional materials such as h-BN and transition metal dichalcogenides (TMDCs) such as M0S2, WS2 and MoSe2 (a monolayer being known in the art to refer to a layer of MX2 stoichiometry). Preferably, the structure comprises a semiconducting/semimetallic two-dimensional material such as graphene, phosphorene, or a TMDC due to the unique electronic properties of such materials being desirable for electronic devices, particularly for at least the uppermost layer of the layer structure. In such embodiments, the structure may be referred to generally as a semiconductor structure. For many devices such as sensors, undoped (e.g. pristine or unintentionally doped) two-dimensional material is preferred.

A two-dimensional material layer (which may be referred to herein as a two-dimensional material layer structure, for example a graphene layer structure) preferably has from 1 to 10 monolayers of two- dimensional material. Preferably the two-dimensional material layer is comprised of a single monolayer. A preferred multilayer structure would have 2 or 3 monolayers. In some embodiments, all of the monolayers are of the same two-dimensional material (e.g. bilayer graphene), though in some preferred embodiments, the multilayer structure may be a heterostructure. By way of example only, the two-dimensional material layer structure may be a sandwich of graphene between two layers of h-BN or a TMDC on graphene.

A monolayer of graphene has a known thickness of about 0.34 nm, that of monolayer phosphorene is about 0.85 nm, and that of a monolayer of TMDC can be in the region of about 0.6 to about 0.7 nm. As described in greater detail herein, the structure of the present invention is particularly resilient to delamination of such thin materials from the surface of the substrate.

The two-dimensional material layer structure is patterned. Patterning is a well-known technique in the art of microfabrication and semiconductor manufacturing (i.e. semiconductor device fabrication). A patterned two-dimensional material layer structure has a shape with one or more edges, typically multiple straight edges defining a polygon (e.g. from four to six outer edges). The patterned two- dimensional material layer structure typically is a “solid” or “filled” shape with only outer edges (that is, the layer structure does not have holes or the like similar to a ring).

Quadrilaterals are preferred (i.e. four straight edges), and the patterned two-dimensional material layer structure may preferably be substantially rectangular, such a shape being simple in design and very suitable for many subsequent device applications, including sensors. Preferably, the corners of the patterned shape are about 90° (such as in a rectangle) or more.

The two-dimensional material layer is provided on a substrate, preferably a non-metallic surface of a substrate, and in some embodiments an insulating surface. The nature of the substrate is not particularly limited. It is known in the art that such substrates or wafers provide a substantially flat upper surface for the fabrication of devices by the growth/deposition and patterning of further layers. Preferably, the non-metallic surface upon which the two-dimensional material layer is provided is silicon (Si), silicon carbide (SiC), silicon nitride (SisN4), silicon dioxide (SiOz), sapphire (AI2O3), aluminium gallium oxide (AGO), hafnium dioxide (HfOz), zirconium dioxide (ZrOz), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAlzO^, yttrium orthoaluminate (YAIO3), strontium titanate (SrTiOs), cerium oxide (CezOs), scandium oxide (SC2O3), erbium oxide (ErzOs), magnesium difluoride (MgFz), calcium difluoride (CaFz), strontium difluoride (SrFz), barium difluoride (BaFz), scandium trifluoride (ScFs), germanium (Ge), cubic boron nitride (c-BN), hexagonal boron nitride (h-BN) and/or a lll/V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN).

In some embodiments, the substrate may consist of one such material. Preferably, the non-metallic surface is silicon, silicon nitride, silicon dioxide, sapphire, aluminium nitride, YSZ, scandium oxide, germanium, calcium difluoride and/or magnesium difluoride. Preferably, the non-metallic surface is sapphire, yttria-stabilised zirconia, scandium oxide, calcium difluoride or magnesium difluoride. In some preferred embodiments, the substrate comprises, or consists of, a first layer which provides the non-metallic surface and a “substrate support” layer, sapphire being a preferred example (such embodiments being particularly suitable for insulative substrates, i.e. typically the oxides, nitrides and fluorides described). In other preferred embodiments, the substrate support layer comprises silicon. A silicon support layer, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry. First layers comprising or consisting of rare earth oxides (which include yttrium and scandium) are particularly preferably provided on a silicon substrate support. Scandium oxide, for example, is particularly preferred. Such substrates are preferred for devices such as gas sensors. A substrate may also comprise one or more layers (for example, regions or channels of embedded waveguide materials such as silicon nitride suitable for electro-optic modulators and photodetectors). The thickness of the substrate support layer is generally much thicker than the thickness of the first layer thereon. Typically, the substrate support layer has a thickness of 250 pm to 1 .5 mm, for example from 400 pm to 1 mm. On the other hand, the thickness of the first layer of such a substrate is substantially thinner and may be formed on the substrate support by epitaxy such as molecular beam epitaxy (MBE) or high temperature sputtering. Preferably, the thickness is at least 2 nm, preferably at least 5 nm and/or less than 500 nm, preferably less than 100 nm. Suitable ranges for the thickness of the first layer are preferably 5 nm to 100 nm, preferably 10 to 50 nm. It is particularly preferred in the present invention that the two-dimensional material layer structure is provided on the surface of the substrate in the first step by directly forming the two-dimensional material layer on the surface by CVD (i.e. a CVD-grown two-dimensional material layer structure grown directly on the surface of the substrate). Forming the two-dimensional material directly on the substrate avoids steps such as physical transfer which can otherwise introduce impurities and/or defects which risks negating the benefit of the invention. For example, direct formation avoids using transfer polymers which are difficult to remove. Forming may be considered synonymous with synthesising, manufacturing, producing and growing. CVD is discussed in greater detail in respect of the method described herein.

A person skilled in the art can readily ascertain whether the two-dimensional material is one has been grown directly on the substrate by CVD. This may be determined using conventional techniques in the art such as atomic force microscopy (AFM) and energy dispersive X-ray (EDX) spectroscopy. The two-dimensional material can be devoid of copper contamination and devoid of organic polymer residues by virtue of the complete absence of contacting these materials with the two-dimensional material in the process (graphene, for example, being commonly grown by CVD indirectly on a sacrificial catalytic copper substrate before transfer to a non-metallic surface). Furthermore, such transfer processes are generally not suitable for large scale manufacture (such as on silicon based substrates in fabrication plants), or at least are not economical.

The structure further comprises a patterned dielectric layer. Suitable dielectric materials are very well- known in the art of microfabrication. The dielectric layer is an inorganic material and may be a metal oxide, nitride and/or fluoride layer, preferably a metal oxide layer such as silicon oxide, aluminium oxide, hafnium oxide, zinc oxide, titanium oxide, magnesium aluminate, yttrium oxide, zirconium oxide and/or YSZ, and/or silicon nitride and/or aluminium nitride, preferably silicon oxide, silicon nitride, aluminium oxide, aluminium nitride and/or hafnium oxide. For the avoidance of doubt, the dielectric layer is not one formed of an organic material such as a photoresist.

As described above, patterning is well-known in the art. A patterned dielectric layer has a shape with one or more edges, often multiple straight edges. As described further below, the end of the second portion of the dielectric layer provides an edge. The dielectric layer may be patterned into more complex geometries than the two-dimensional material layer structure rather than a simple 2D polygon, though as described further herein, typically takes such as shape, e.g. from rectangular to circular.

As described in preferred embodiments herein, the dielectric layer may be provided as a conformal layer across the substrate (and any other layers present on the substrate) during the manufacturing process, and the dielectric layer may preferably be patterned to provide a window (e.g. a hole), to expose the upper surface of the underlying two-dimensional material layer structure. Multiple windows may be provided through to separate patterned two-dimensional material layer structures on the substrate in the production of multiple devices on a common substrate. An electronic device may comprise two or more individual devices (where the individual devices may then be referred to as cells). These may share common device features elsewhere on the substrate (e.g. a common gate contact). The following description will focus on an individual device or cell, though it will be appreciated an array of individual components may be manufactured simultaneously on a common substrate/wafer.

The dielectric layer is formed of (i) a first portion which is on and/or over the substrate adjacent an edge of the two-dimensional material layer structure, and (ii) a second portion which extends from the first portion over the two-dimensional material layer structure, and makes resting contact with a surface of the two-dimensional material layer structure thereby defining a cavity between at least the dielectric layer and the two-dimensional material layer structure.

The dielectric layer is conformal in the sense that the layer is continuous and the first and second portions are used to describe the arrangement of the layer in the structure. The first portion is intended to refer to that portion or region of the dielectric layer that resides outside the perimeter of the two-dimensional material layer structure (and is therefore adjacent an edge of the two- dimensional material layer structure and may optionally be patterned elsewhere on the substrate). The second portion is intended to refer to that portion or region of the dielectric layer that resides within the perimeter of the two-dimensional material layer structure.

As used herein, “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material, and “over” is intended to mean directly “above” without being directly on thereby allowing for other materials therebetween, or a cavity.

The first portion is one which is on and/or over the substrate. As described herein, each of the first and second portions may be formed of sub-portions which may each individually be on or over the substrate or two-dimensional material layer structure such that the first portion may be on the substrate adjacent one edge of the two-dimensional material layer structure, and over the substrate adjacent another edge of the two-dimensional material layer structure (for example, the region in which the dielectric layer is on a metal contact).

The second portion extends from the first portion over the two-dimensional material layer structure. As such, where the first and second portions meet is above the edge of the two-dimensional material layer structure. The second portion extends over the two-dimensional material layer structure (optionally on a support layer, such as a metal contact). The terminal end of the second portion rests on the surface of the two-dimensional material layer structure. As a result, a cavity is defined between at least the second portion of the dielectric layer and the two-dimensional material layer structure.

The dielectric layer has a thickness of less than 250 nm. The inventors unexpectedly found that when a dielectric layer that was sufficiently thin during manufacture (as described herein), the end of the layer would “droop” or “fall” and contact the surface of the two-dimensional material thereby selfsealing the vulnerable edge of the two-dimensional material within a cavity. Such a cavity is the result of the method described herein in which the dielectric layer (at least the second portion) is first formed entirely on an (etchable) metal layer. The metal is then etched to undercut the dielectric layer resulting in the product structure.

Dielectric materials are generally fairly rigid materials, though when the layer has a thickness of less than 250 nm, the layer can deform and bend sufficiently to contact the two-dimensional material. For this reason, thinner layers are preferred, such as less than 150 nm, preferably less than 100 nm. Since the second portion is provided above the edge of the two-dimensional material, in the absence of a support, the dielectric layer folds over the edge to rest on the two-dimensional material surface. The dielectric layer is conformal and thus has a thickness sufficient in order to be so. Preferably the dielectric layer has a thickness of at least 5 nm. Such a thickness may be selected so as to be sufficiently self-supporting over the cavity without collapsing, and be a sufficient barrier to liquid solutions. Whilst the thickness of the dielectric layer can be dependent on the material chosen and its physical properties, at least 5 nm is typical, with 20 to 80 nm preferred.

As described by an embodiment of the method herein, the dielectric layer will have a “vertical” component adjacent the edge of the two-dimensional material as a result of being deposited on the wall of a co-patterned stack formed of the two-dimensional material layer structure and the metal layer, the height of which being substantially equivalent to the height of stack prior to etching (though this may vary slightly due to the deformation of the dielectric layer after metal etching and folding). As such, the substantially vertical component may tilt over the edge of two-dimensional material layer structure and may be formally considered as part of either the first or second portion, and forms a wall of the cavity.

Alternatively, the first portion of the dielectric layer may be on a support and/or a sub-portion of the second portion which extends from the first portion may be on a support. These may be additional to the features above where provided adjacent alternative edges of the two-dimensional material. As described herein, the support is preferably formed of metal, most preferably metal which may be used as an electrical contact to the two-dimensional material. In such embodiments, the metal is typically a portion of that which remains after etching of a metal layer in the method described herein, and therefore on the surface of the two-dimensional material. As a result, a preferred embodiment comprises a sub-portion of the second portion which extends from the first portion that is on a metal support (as such the support is at least adjacent an edge and on the surface of the two-dimensional material layer structure). The difference with whether or not a sub-portion of the second portion is on a support lies essentially with the position at which the dielectric layer is unsupported, whether that be the dielectric layer becoming unsupported directly above the edge of the two-dimensional material extending from a support on the substrate over the edge of the two-dimensional material, or becoming unsupported away from the edge and over the surface of the two-dimensional material (e.g. as viewed in a direction perpendicular to the edge and parallel to the surface).

At least the portion of the support that is on the two-dimensional material layer structure is preferably formed of metal. Preferably the metal comprises or consists essentially of ruthenium, rhodium, palladium, silver, osmium, iridium, platinum and/or gold. Such metals are relatively inert and do not negatively react with the two-dimensional materials such as graphene. These metals have the characteristic property of being resistant to corrosion and oxidation. Gold is particularly suitable.

In the former embodiment in the absence of a support layer, the cavity which forms is defined by the underside of the dielectric layer and the upper surface of the two-dimensional material layer structure. As such, in some preferred embodiments, the first portion of the dielectric layer is on the substrate and the second portion of the dielectric layer extends 20 to 200 nm in height above the surface of the two-dimensional material layer structure, preferably 50 to 150 nm, whereby the cavity is defined between the second portion of the dielectric layer and the two-dimensional material layer structure.

In the latter embodiment comprising a support layer, an edge of the support layer provides a further wall which defines the cavity with the dielectric layer and the two-dimensional material layer structure. Thus, in some embodiments wherein the first portion is on a support layer and the support layer is on the substrate adjacent the edge of the two-dimensional material layer structure, the support layer has a thickness of from 20 to 200 nm, preferably 50 to 150 nm, whereby the cavity is defined between the support layer, the second portion of the dielectric layer and the two-dimensional material layer structure.

As a result, the second portion of the dielectric layer at the point at which it extends from the first portion will be at a corresponding height (e.g. 20 to 200 nm) above the surface of two-dimensional material layer structure.

The cavity may be described as a sealed cavity which protects the edges from being contacted with liquid solutions during subsequent device manufacture (e.g. electrochemical sensor manufacture), and indeed when using the device. The inventors have found that delamination is a particular problem for two-dimensional materials in which the edges are exposed and as a result, the structure described is more robust to delamination. Preferably, the length of the second portion of the dielectric layer that is in contact with the surface of the two-dimensional material layer is at least 500 nm (that is, the length of a sub-portion thereof that is in contact with the surface). The length in contact with the surface is the minimum distance from the terminal end (i.e. edge) of the second portion to the start of the cavity. The inventors have found that this provides a good seal to protect the edge. The length may preferably be at least 1 pm, preferably at least 2 pm, the length being proportional to the etching conditions described herein and the extent of undercut. At least 50% of the length of the second portion may be resting on the surface, and in some embodiments at least 90%.

Preferably the cavity has a width of from 100 nm to 1 pm, preferably from 200 nm to 800 nm. The width of the cavity may depend on the height at which the second portion extends above the two- dimensional material, where a greater height is typically associated with a greater cavity width. The width may be measured with respect to the width of the portion of the two-dimensional material exposed within the cavity (e.g. from the point where the dielectric layer contacts the two-dimensional material and the edge of the two-dimensional material or the support where present).

In particularly preferred embodiments, all edges of the patterned two-dimensional material layer structure are protected in the structure described herein, and preferably combines embodiments with and without a support layer at different edges.

In a preferred embodiment, the first portion of the dielectric layer consists of one or more first subportions, each of the first sub-portions either on or over the substrate adjacent an edge of the two-dimensional material layer structure whereby the first portion completely surrounds all edges of the patterned two-dimensional material layer structure, and wherein the second portion of the dielectric layer consists of one or more corresponding second sub-portions whereby the second subportions define a window to an exposed surface of the two-dimensional material layer structure.

As a result, the edge of the second portion forms a continuous boundary (i.e. a window) and it will be appreciated this excludes the portion of the two-dimensional material surface sealed within the cavity (though the surface is exposed within the cavity). Preferably the exposed surface of the two- dimensional material layer structure has an area of at least 100 pm², preferably at least 1 ,000 pm² (i.e. the window to the two-dimensional material in the product has such an area). Such areas of windows provide a relatively large area particularly suitable for electrochemical sensors, though the inventors have found that the structure described herein may still be manufactured with windows as small as at least 10 pm², for example. The shape of the window may be mathematically similar to the shape of the two-dimensional material layer structure (e.g. substantially rectangular) and the edges can then be aligned parallel with those of the patterned two-dimensional material. The centre of the window can be generally centred over that of the two-dimensional material. Other embodiments may comprise a window in a dielectric layer in which the first portion need not completely surround all edges of the two-dimensional material layer structure. It is generally preferred that such sealed cavities are formed by two opposite metal contacts such that the window may expose the other edges of the graphene (and therefore the adjacent portion of the substrate). The sealing of the graphene at two opposite edges significantly aids in reducing delamination risk, and as described above, it is preferred for all edges to be sealed, significantly reducing this risk further.

The corners of the window may be rounded, though this is not particularly limited. As will be appreciated, a minimum roundedness may result from the practical limits of the resolution associated with photolithographic patterning. The corners may have a radius of curvature of at least 0.5 pm, or even at least 1 .0 pm and/or may have a radius of curvature of at most 10 pm, preferably at most 5 pm, particularly for rectangular or essentially square windows, though there is no specific upper limit for higher order polygons and circular windows except for the intended final device size.

The length of each edge of the window (i.e. the width of the second portion orthogonal to the direction in which the second portion extends from the first portion) may preferably be at least 5 pm, more preferably at least 10 pm, with no particular upper limit except for the intended final device size. For electrochemical sensors, the length of each edge may preferably be at least 25 pm or even at least 50 pm. The length of each edge may be measured to the midpoint of each corner where the corners are rounded. The inventors have found that when the area of the window and/or the length of a window edge is small enough (e.g. less than about 100 pm² and/or less than about 10 pm), a greater undercut may be required in order for the dielectric layer to fold and seal the edges, such as at least 2 pm.

More preferably, at least two first sub-portions of the dielectric layer are each on corresponding subportions of a support layer, each of said sub-portions of the support layer being in the form of a metal contact on portions of the surface of, and adjacent opposite edges of, the two-dimensional material layer structure, and preferably wherein each metal contact extends onto adjacent portions of the surface of the substrate.

Even more preferably, a remainder of the first sub-portions of the dielectric layer are on the substrate each adjacent a remaining edge of the two-dimensional material layer structure. In accordance with the specific embodiments described above, corresponding second sub-portions extending from such first sub-portions will fold over the edge to rest on the two-dimensional material surface.

In exemplary preferred embodiments, such a structure is used in sensors, more preferably electrochemical sensors such as biosensors. The exposed surface of the two-dimensional material layer structure is then preferably functionalised with an analyte-receptor. Suitable receptors for functionalising two-dimensional materials, including graphene, are well-known in the art. An analyte is chemical species of interest to be measured, for example to either detect its presence or more quantitively its concentration in the sample to be tested.

A sensor is a device which generates a signal in response to a biological or chemical interaction with an analyte to be measured. A typical sensor comprises an analyte-receptor (for example a biosensor comprises a bioreceptor), transducer, electronics and a display, so as to measure the analyte. There are many different conventional configurations of such components. In some systems, they may be integrated within a single apparatus, or the biosensor might form part of a system which includes a separate reader that has the display and carries out the diagnosis. Alternatively, in other systems, a cloud-based service is for data analysis/diagnosis and a remote computer provides the diagnosis and display.

A bioreceptor is a molecule or other biological element or species that serves to recognise the analyte. Bioreceptors include, though are not limited to, enzymes, cells, aptamers, DNA, RNA and antibodies. The interaction between the analyte and bioreceptor is also known as biorecognition and the biorecognition event (such as a change of light, heat, pH, charge or mass) is a form of energy which is then converted to a measurable signal by the transducer (i.e. the two-dimensional material layer structure). The electronics serve to process and prepare the transducer signal for display by the display to a user. For example, a processor or a signal processing unit can process a voltage signal generated by the transducer by signal conditioning, such as by amplification and conversion of signals from analogue into the digital form. The processed signals are then quantified by the display unit of the biosensor. Such processing can take place remotely. The user of the biosensor device may be different to the user who analyses the output.

In other technical fields, sensors comprising the structure described herein may be used for gas sensing, pH sensing or ion sensing. As such, the devices find particular application in healthcare and diagnosis, environmental monitoring in agriculture for example, for testing foods, and the presence of heavy metals (and/or their ions).

The sensor comprises first and second electrical contacts provided in contact with the two-dimensional material layer structure, typically arranged on opposite sides of the sample surface (e.g. adjacent opposite parallel edges). Typically, electrical contacts are metallic contacts made of metal, such as chromium, titanium, aluminium, nickel and/or gold, preferably titanium and/or gold. The relative arrangement of such contacts at opposite sides of the sample surface is well-known in the art and serves to define a sample-surface of the transducer for receiving an analyte composition therebetween the contacts. The sensor may also comprise a gate contact as is known for field-effect transistor based sensors. In a further aspect there is provided a method of testing for an analyte (i.e. a method of testing a sample composition for a predetermined analyte), the method comprising applying a sample to the exposed sample surface of the sensor (i.e. contacting the sample surface with a sample composition) and observing an electrical output to determine whether or not the sample contains the intended analyte. The sensor may be used for testing a gaseous sample, though it is preferred that the sample is a liquid sample. In determining whether or not the sample contains the intended analyte, the sensor having increased sensitivity over known sensors allows for either a qualitative determination of the mere presence of the analyte or, preferably, a quantitative determination of the amount, or concentration, of the intended analyte in the sample composition.

A preferred method comprises using a graphene biosensor as described herein which comprises an appropriate analyte-receptor for the biorecognition of a predetermined analyte. The sample composition may be any typical composition for testing. For example, a sample may derive from a human or animal, such as a blood, urine, saliva, sweat, tears, faeces, breath, plasma, or sperm sample. In other embodiments, the sample composition is a food sample, an environmental sample (e.g. river, sea or waste water, ground or soil samples) or may be of plant origin (e.g. tree or crop samples). Preparation of suitable samples is well known; water samples may be used directly, whereas other samples may be dissolved in an appropriate solvent (e.g. water) and filtered as necessary for testing.

The composition is contacted with the sample-surface of the graphene layer structure so that, upon interaction with the analyte, if present in the sample composition, an electrical current provided by the contacts and through the graphene will be modulated. Thus, by observing an electrical output between the contacts, a user may determine whether the predetermined analyte (as determined by the nature of the analyte-receptor of the sensor device) is present in the sample composition. For example, a positive or negative result may be determined by the conductance of the graphene exceeding a predetermined threshold.

Method

The method for forming the structure described herein comprises providing a layer structure comprising:

(a) a substrate;

(c) a patterned dielectric layer having a thickness of less than 250 nm; wherein (i) a first portion of the patterned dielectric layer is on and/or over the substrate adjacent an edge of the co-patterned stack, and (ii) a second portion of the patterned dielectric layer extends from the first portion onto a portion of the stack by a distance of at least 1 pm. Various features of the substrate, patterned two-dimensional material layer structure, and patterned dielectric layer are described above in respect of the product. The layer structure used in the present method is a precursor to the product, the method further comprising etching as described below. The layer structure comprises a co-patterned stack of a metal layer on a two-dimensional material layer structure, the two-dimensional material layer structure being on the substrate.

By co-patterned, it is meant that the metal layer and the two-dimensional material layer structure have coincident shapes with aligned edges. Preferably, providing the layer structure comprises depositing the metal layer on and across the two-dimensional material layer structure, and then patterning the two-dimensional material layer structure and the metal layer simultaneously to form the stack. The metal layer will be substantially flat and parallel to the two-dimensional material surface such that the second portion of the dielectric layer will also be substantially flat and parallel thereto.

It is also particularly preferred that the method comprises directly forming the two-dimensional material layer structure on a growth surface of the substrate by CVD.

CVD refers generally to a range of chemical vapour deposition techniques, each of which involve deposition to produce thin film materials such as two-dimensional crystalline materials like graphene, optionally under vacuum/reduced pressure. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. The description herein for the CVD of graphene may be modified accordingly to produce other two-dimensional materials.

CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor. A CVD layer formed directly on a surface can be distinguished from one transferred, either due to impurities or other defects such as cracks and wrinkles.

Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating the carbon-containing precursor. Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on the materials described herein by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber.

In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface.

Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface (i.e. the growth surface).

The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber.

Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017/029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform two-dimensional material layers directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor.

Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017/029470, forming a graphene layer structure directly on a substrate by CVD comprises: providing the growth substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; cooling the inlets to less than 100°C (i.e. so as to ensure that the precursor is cool as it enters the reaction chamber); introducing a carbon-containing precursor in a gas phase and/or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the substrate surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm. The rotation rate of the heated susceptor in a close-coupled reaction chamber is typically less than 300 rpm, or even less than 200 rpm.

In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019/138231 , forming a graphene layer structure directly on a substrate by CVD comprises: providing the growth substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and/or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm.

The most common carbon-containing precursor in the art for graphene growth is methane (CF ). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and/or bromine, even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Suitable precursors for other two-dimensional materials are known. TMDCs may be grown by a combination of metal precursor and chalcogenide precursor (introduced into the reaction chamber simultaneously or sequentially). The high quality material produced by such CVD methods also has fewer and weaker interactions with the substrate as a result of there being fewer defects in the two-dimensional material layer (in particular when compared to transferred materials or graphene grown by sublimation of silicon from silicon carbide). This is beneficial is terms of the unique electronic properties of the two-dimensional material, and as such, the directly grown material can be more susceptible to delamination. Therefore, there is a synergistic benefit associated with such combinations.

Depositing the metal layer on and across the two-dimensional material layer structure may be achieved by conventional techniques, for example sputtering, thermal evaporation or e-beam evaporation. The metal layer is preferably deposited with a thickness of from 20 to 200 nm and is generally deposited across the whole surface.

Patterning the two dimensional material layer structure and the metal layer simultaneously to form the stack may be performed using conventional techniques such as photolithography and etching. Typically, a mask is patterned onto the surface of the stack using a photoresist and both layers of the stack may be etched in a single step, or two steps with one for each layer. The patterned photoresist may be heated (which may be referred to as “curing” or “baking”) to improve adhesion to the gold layer prior to the etching step. Such a heating step to cure the photoresist is well-known in the art and can include heating up to about 180°C, or up to 160°C, for example from 80°C to 140°C and up 10 minutes, for example from 1 to 3 minutes. The cured photoresist may be washed away following etching using an appropriate solvent.

Further layers may be deposited at this stage, for example further metal may be formed in contact with the metal layer and an edge of the two-dimensional material layer structure. This further metal layer may provide the desired circuitry for a final device. That is, the further metal may be used to provide circuit “tracks” and preferably, a gate contact on the substrate, again using conventional techniques such as photolithography. One preferred stack of further metal for contacting the metal layer is a stack of first, second and third metal layers, wherein the first metal is selected from the group consisting of titanium and/or chromium, the second metal is selected from the group consisting of aluminium, copper, gold, nickel and/or palladium, and the third metal is selected from the group consisting of cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride and/or tungsten. Whilst a ceramic material, titanium nitride, particularly thin layers, is a known conductive ceramic nitride often referred to in the art as a barrier metal to chemically isolate semiconductors from soft metal interconnects whilst maintaining electrical connection between them. As such, a skilled person would readily recognise titanium nitride as a suitable metal in the context of a contact-stack.

In one particularly preferred embodiment, the first, second and third metals are titanium and/or chromium, gold, and platinum, respectively. In preferred embodiments, the first metal layer has a thickness of less than 15 nm, the second metal layer has a thickness of from 50 to 100 nm, and the third metal layer has a thickness of less than 35 nm.

The first metal layer is an adhesion promoter facilitating adhesion of the second metal to the substrate surface. The second metal layer is generally thicker and provides the desired electrical conductivity whilst being stress relieving compared to the third metal layer. However, the third metal layer is resistant to etching solutions, in particular gold etchants. Consequently, the dielectric layer may be patterned simultaneously to provide a window to the metal layer on the two-dimensional material and a window to the further metal stack (e.g. a gate contact), such that the metal layer may then be etched to expose the surface of the two-dimensional material layer structure with the gate contact having already been exposed. The inventors have found that such a selection of metals can also address problems of delamination during manufacture, particularly at the thicknesses described. The layer typically has internal stresses at greater thicknesses following metal deposition, which if too large can propagate through the layers. If this is greater than the adhesion of the two-dimensional material layer structure on the substrate surface, this leads to delamination. Preferably, the third metal layer has a thickness of from 15 to 30 nm.

A layer of dielectric material is then deposited on and across the substrate and the stack and any other layers that may be present. ALD is a particularly suitable method for the deposition of conformal layers of dielectric material, though other methods such as sputtering, thermal evaporation or e-beam evaporation may also be used. The dielectric layer may then be patterned, again using conventional techniques such as photolithography. The dielectric layer, generally being formed of metal oxide, nitride or fluoride, is preferably dry-etched in the patterning step, for example by plasma or reactive ion etching. A dielectric layer may instead be deposited directly in a pattern using physical vapour deposition techniques, for example using a shadow mask.

The dielectric layer is patterned in which (i) a first portion is on and/or over the substrate adjacent an edge of the co-patterned stack, and (ii) a second portion extends from the first portion onto a portion of the stack by a distance of at least 1 pm (i.e. a minimum of at least 1 pm). For example, the dielectric layer may be patterned to provide windows above and within the perimeter of each copatterned stack so as to cover only a portion of the stack (i.e. the second portion). The second portion extends a minimum distance of at least 1 pm in a direction parallel to the plane of the substrate from the first portion (i.e. the edge of the stack) onto the stack. The remainder of the dielectric layer (i.e. the first portion) may remain unpatterned, coating the rest of the substrate and any other layers present.

The method then comprises etching at least a portion of the metal layer to expose a surface of the two-dimensional material layer structure and to undercut the patterned dielectric layer by a distance of at least 1 pm. The inventors have advantageously found that the combination of a sufficiently thin dielectric layer (i.e. less than 250 nm) with an undercut etch of at least 1 gm allows for the self-sealing by the dielectric layer (such a length may be considered equivalent to the combined length of the dielectric resting on the surface of the two-dimensional material and the width of the cavity in the resulting product). The inventors were surprised to find that the dielectric layer may fold under such conditions whilst retaining structural integrity to protect the edges of the underlying two-dimensional material layer structure, which in turn provided a more robust product to delamination. The inventors found that thicker layers, such as those above 500 nm, would not seal. Similarly, the inventors found that for etch distances of less than 1 pm the dielectric layer would also not form a seal. Furthermore, the inventors have found a metal layer having a thickness of from 20 to 200 nm as described hereinabove is particularly suitable for the combination of dielectric layer parameters in order to provide selfsealing and the product structure described. The presence of a cavity in the product is characteristic of such a method of manufacture.

Preferably the metal layer consists essentially of ruthenium, rhodium, palladium, silver, osmium, iridium, platinum and/or gold, preferably gold. Due to gold's characteristically inert qualities, the temporary gold layer on the surface of the two-dimensional material layer structure may further provide thermal protection and prevent oxidation, especially when the two-dimensional material layer structure is exposed to high temperature treatments during epoxy curing, oven baking, and/or burn testing. Furthermore, the temporary gold coating may also protect the two-dimensional material layer structure from potentially being contaminated during wire bonding, encapsulation, wafer dicing, and cleaning. Thus, this allows the two-dimensional material layer structure to be handled in a factory setting for large manufacturing production.

Etching the metal layer is preferably performed by a wet-etching method. Metals are typically readily etchable and suitable methods for etching, and etching solutions for wet-etching are well-known, particularly for the preferred metals described herein. Gold is particularly preferred in this regard since gold may be etched with a relatively mild solution. Most common is a solution of potassium iodide and/or iodine. However, it should be noted that the etchant solution need not be limited to a potassium iodide solution, but instead, may also include sodium and/or potassium cyanide, or an aqua regia solution with a mixture of nitric and hydrochloric acids. Various commercial etchants (sometimes referred to as developing solutions) are also readily available for the metals described herein. Preferably, the etching solution has a pH of greater than 5 and/or less than 9, such as about 7 to about 8.

The etching of the metal layer occurs isotopically so as to undercut the dielectric layer. The etching conditions may be selected and controlled to achieve the desired extent of undercut. For example, etching time and temperature may be varied to control the degree of etching. Typically, a wet-etch may take up to 30 minutes, such as from 1 to 10 minutes, or even from 2 to 5 minutes. That is, wet- etching may take place by submerging the entire substrate in an etchant solution for such time. By way of example, the inventors have found that the etching of a gold layer as described herein for about 1 minute can provide an undercut of about 3 to 5 pm, 2 minutes can provide an undercut of about 7 to 8 pm, and 4 minutes can provide an undercut of about 9 to 11 pm.

The etching may be performed at room temperature (e.g. about 15°C to about 25°C), or may be gently heated, such as up to 50°C. The etching solution is then washed away and the structure rinsed, such as with deionised water, and the structure is dried. Drying may be accelerated with gentle heating (e.g. up to 50°C) and/or a flow of dry inert gas such as nitrogen. The inventors have found that the extent of etching may be controlled and therefore it is believed that the dielectric layer seals on the two-dimensional material surface to leave a cavity during and following drying.

Such a method is especially advantageous because the method uses fewer process steps and therefore provides a simpler, quicker and more efficient route to a product suitable for a device with protected edges since the dielectric (or support where present) on the substrate is formed in the same step as the dielectric which subsequently is used to seal on the surface. In the present invention, the metal, such as gold, does not need to be patterned away from the edge(s) after patterning the two-dimensional material to allow for dielectric material to be deposited across the edge and adjacent substrate. Instead, a single dielectric layer can be immediately patterned onto the metal to the desired/necessary length and thickness before etching and sealing in a single step.

The method comprises etching at least a portion of the metal layer. That is, all of the metal layer may be etched away leaving no support and a cavity between the dielectric layer and the two-dimensional material layer structure. In other embodiments, only a portion is etched to leave a portion of the metal layer adjacent the edge of the two-dimensional material layer structure, such support providing a wall to the cavity. In a preferred embodiment, a combination may be relied upon to prepare the structure described herein in which two portions of metal support are left behind along two edges (e.g. two opposite edges of a rectangle), and the metal is completely removed along the other edges. The two portions of the metal support may be used as electrical contacts in a subsequent device. The combination may be achieved by appropriate patterning of the window in the dielectric layer and the distance of each second sub-portion portion over the stack from each edge of the stack.

Such a method may be used to form an electronic device as described herein. The method may further comprise functionalising the exposed surface of the two-dimensional material layer structure with an analyte-receptor. Especially for a biosensor, a functionalised sample surface may comprise an organic linker moiety which comprises two functional groups, a first of which serves to immobilise the analyte-receptor to the surface. For example, this may comprise non-covalent immobilisation through a pyrene functional group or covalent immobilisation through diazonium binding or alkylation of dopant atoms. One of the most common methods, at least for graphene, is based on the reliable TT-TT stacking which utilises 1 -pyrenebutyric acid N-hydroxysuccinimide ester (PBASE). The second functional group may comprise a thiol, amine or carboxylic acid functional group which is used to attach receptors, for example, biomolecules such as antibodies and aptamers as described above. Many other variations are known in the art and may be used to functionalise the device described herein for the desired application.

Figures

The present invention will now be described further with reference to the following non-limiting exemplary Figures, in which:

Figures 1A to 1 C illustrate, in cross-section, an embodiment of the method of the present invention.

Figure 2 illustrates, in cross-section, a further embodiment of the method of the present invention.

Figure 3 illustrates a plan view of an individual device in accordance with the present invention.

Figure 4 is an image of an individual device in accordance with the present invention.

Figure 5 is an image of a further individual device in accordance with the present invention.

Figure 6 is an image of a comparative device.

Figure 7 is an image of a device precursor.

Figure 8 is an image of a device, obtained by etching the device precursor shown in Figure 7.

Figure 9 is an image of a further device precursor.

Figure 10 is an image of a device, obtained by etching the device precursor shown in Figure 9.

Figure 11 is the outline of an image of an electrochemical sensor comprising three individual devices (cells) in accordance with the present invention.

Figure 12 is an image of a further individual device in accordance with the present invention. Figures 1 to 3 are schematics illustrating the present invention and the relative dimensions and shapes of some features/layers may be exaggerated and/or simplified and not presented to scale to improve the clarity of the drawing. The relative dimensions and sizes do not necessarily correspond to those of practical embodiments of the invention.

Figures 1 A to 1 C illustrate, in cross-section, an exemplary method in accordance with the present invention for the manufacture of structure 200. A two-dimensional material layer structure such as a monolayer of graphene 210 is provided on and across the surface of a substrate 205 (for example, sapphire). The graphene monolayer 210 may be formed by CVD directly on the substrate 205 avoiding the need for physical transfer.

In a first step 100, a metal layer such as a gold layer 215 is deposited on and across the entire surface of the graphene 210, for example to a thickness of about 60 nm. A photoresist 220 is then coated on and across the gold layer 215 in step 105, before patterning into a patterned photoresist 220’ in step 110 and subsequently baking. Photoresist 220 can be patterned by conventional photolithography techniques thereby exposing portions of the underlying gold layer 215. In step 115, the exposed portion of the gold layer 215 and the corresponding underlying portion of the graphene 210 are then etched away to leave a co-patterned stack of the gold layer 215’ and the graphene 210’ having opposite edges (210a’, 210b’). Finally in Figure 1A, the patterned photoresist 220’ is washed away in step 120 to leave the co-patterned stack (210’, 215’) whereby the patterned gold layer 215’ has the same shape with coincident edges as the patterned graphene 21 O’.

As shown in Figure 1 B, the stack on the substrate 205 is then coated with a further photoresist 225 in step 125 which is then patterned in step 130 to expose portions of the underlying patterned gold layer 215’ adjacent the edges of the stack leaving a patterned further photoresist layer 225’. As shown in the specific cross-section of Figures 1 A to 1 C, opposite edges of the stack comprising the patterned graphene 210’ are exposed.

In step 135, further metal 230 for electrical contacts is subsequently deposited. Such further metal 230 may be formed of chromium, titanium, aluminium, nickel, platinum and/or gold. The patterned further photoresist layer 225’ is then removed in a conventional “lift-off” step 140 thereby removing the metal layer deposited on the patterned further photoresist layer 225’ so as to leave portions of the patterned further metal layer 230’, each in contact with opposite edges of the stack and on the substrate 205. Elsewhere on the substrate 205, the patterned further metal layer 230’ may itself provide the desired circuitry to integrating the structure 200 into a larger device.

As continued in Figure 1 C, a layer of dielectric material 235 is then deposited on and across the patterned gold layer 215’ and the patterned further metal layer 230’ in step 145. The layer of dielectric material 235 has a thickness of less than 100 nm. A further photoresist is then deposited and patterned to provide yet another patterned further photoresist 240’ which is patterned to expose a portion of the patterned gold layer 215’ in an area entirely above the patterned graphene 210’. More specifically, the layer of dielectric material 235 extends a minimum of 1 pm over the patterned graphene 210’ as measured parallel to the plane of the substrate 205 from the edge of the stack.

In step 155, the exposed portion of the dielectric layer 235 is etched to provide a corresponding window to the underlying patterned gold layer 215’ leaving a patterned dielectric layer 235’, and the patterned further photoresist 240’ is then also washed away.

Finally, the patterned gold layer 215’ is etched in step 160 using a gold etching solution, such as one of potassium iodide and iodine in water. Such wet-etching occurs isotopically to undercut the patterned dielectric layer 235’ by a distance of at least 1 pm, such as about 3 pm to about 5 pm, depending on the etching time, temperature and etchant concentration, for example. As shown in Figure 1 C, etching of the patterned gold layer 215’ occurs to an extent such that a portions of the gold layer 215” remain. By undercutting such a thin dielectric layer 235’ to such an extent, the patterned dielectric layer 235” folds and contacts the surface of the patterned graphene 21 O’, thereby forming structure 200. The folding of the patterned dielectric layer 235” creates a cavity 245 between the patterned dielectric layer 235”, the patterned graphene 21 O’, and the “support” portion of the gold layer 215” (which itself serves as an electrical contact together with the patterned further metal layer 230’). The cavity may have a width of about 500 nm (as measured with respect to the width of the portion of the exposed surface of the graphene 210’ within the cavity). This occurs on both sides of the window to form two sealed-edges in the cross-section as illustrated. This is particularly beneficial for devices used with liquid solutions for functionalisation and/or subsequent use (e.g. biosensors) since the electrical contacts are electrically isolated from the exposed surface of the patterned graphene 210’ using fewer processing steps than would be required by known processes.

Figure 2 illustrates, in cross-section, a further embodiment of the method of the present invention in the manufacture of structure 400. Figure 2 may represent an alternative cross-section in the manufacture of structure 200 as shown in Figures 1 A to 1 C.

A co-patterned stack of a patterned graphene 410’ having opposite edges (410a’, 41 Ob’) and patterned gold layer 415’ are provided on a substrate 405 (such as by the method of Figure 1A). In step 345 (which may be equivalent to step 145), a layer of dielectric material 435 is deposited on and across the patterned gold layer 415’, as well as the exposed surface of the substrate 405, to a thickness of less than 100 nm. In step 355, the dielectric material 435 is patterned to expose a portion of the patterned gold layer 415’ in an area entirely above the patterned graphene 410’, such as by photolithography, whereby the patterned layer of dielectric material 435’ extends a minimum of 1 pm over the patterned graphene 410’ as measured parallel to the plane of the substrate 405 from the edge of the stack. In step 360, the patterned gold layer 415’ is etched using a gold etching solution, such as one of potassium iodide and iodine in water. Such wet-etching occurs isotopically to undercut the patterned dielectric layer 435’ by a distance of at least 1 pm. More specifically, the entirety of the patterned gold layer 415’ is etched in the cross-section illustrated. The patterned layer of dielectric material 435” folds to contact the surface of the patterned graphene 410’ creating a cavity 445 between patterned dielectric layer 435” and the patterned graphene 410’, affording structure 400. The resulting product has “sealed edges” in which the edges (410a’, 410b’) of the patterned graphene 410’ are protected from ingress of liquid solutions which can otherwise lead to delamination of the two-dimensional material. Whilst a dielectric layer could be deposited with photolithography across the edge of the two- dimensional material, the present embodiment achieves such a result in combination with the need to keep the surface of the two-dimensional material protected during processing. That is, whilst a photoresist could be patterned onto the surface of the two-dimensional material, this is difficult to remove affecting the performance of subsequent devices, whereas metal does not interact negatively with the two-dimensional material and can be easily etched away.

As described herein, one embodiment of the present invention is a combination of the methods illustrated in Figures 1 A to 1 C and Figure 2. An example of a resulting structure is that shown in Figure 3. Figure 3 illustrates a plan view of an individual device in accordance with the present invention with various layers illustrated with semi-transparency in order to show the layers beneath. Structure 500 when viewed in one cross-section (A-A) comprises structure 200 as shown in Figure 1 C. When view in an orthogonal cross-section (B-B), structure 500 comprises structure 400 as shown in Figure 2. Equivalent features have been given equivalent labels across the Figures.

Structure 500 comprises an underlying substrate (not shown), a rectangular patterned graphene monolayer 510’ thereon with a window to an exposed surface thereof provided by a rectangular window in a patterned dielectric layer 535”. Over two opposite edges of the patterned graphene 510’ in the B-B direction, cavity 545 may be found. The cavity 545 is also found in the orthogonal direction adjacent the support portions of the gold layer 515” which remained following etching in the A-A direction. Further in the A-A direction, a patterned further metal layer 230’ in provided in contact with and on the patterned gold layer 515” (and therefore a portion is over the patterned graphene 510’). In a “first portion” outside the area of the patterned graphene 510’ the patterned dielectric layer 535” coats the substrate and the corresponding portions of the patterned further metal layer 230’ - a “second portion” of the patterned dielectric layer 535” being that within the perimeter of the patterned graphene 510’. As such, the dielectric layer 535” surrounds all edges of the patterned two-dimensional material layer structure 510’.

Each of Figures 4 to 10 and 12 are images of structures and devices taken using an optical microscope. For clarity and reproduction, the dark background of each image (e.g. the substrate outside of the active channel region) has been removed. Figure 4 is an image of an individual device in accordance with the schematic in Figure 3 with a rectangular window with edges have a length of about 90 gm. The experimental results clearly show a cavity and a region of the dielectric layer which rests on the surface of the graphene creating a window to an exposed upper surface of the graphene.

Figure 5 is a further individual device in which a window in the patterned dielectric layer 635” exposes a surface of the patterned graphene 610’ and two opposite edges thereby exposing the adjacent surface of the substrate 605 (the window having been patterned beyond the area of the underlying graphene during manufacture exposing the substrate 605 prior to the gold metal etch). Nevertheless, gold contacts are provided at the other two opposite edges forming a cavity 645 between the patterned dielectric 635” and the patterned graphene 610’.

Figure 6 is an image of a comparative device in which the thickness of the dielectric layer deposited during manufacture was about 500 nm. Similar to the device in Figure 5, the window in the dielectric layer was patterned beyond the area, i.e. beyond two opposite edges, of the graphene). Accordingly, following etching of the gold metal layer exposing the surface of the patterned graphene 710’ and portions of the substrate 705 adjacent two opposite edges of the graphene 71 O’, the patterned dielectric layer 735” was too rigid and was not observed to fold and contact the graphene 710’. As a result, no cavity is observed and the gold remains exposed which is not suitable for a device.

Figure 7 is an image of a device precursor. Specifically, Figure 7 is an image of a precursor to the product shown in Figure 8 prior to the gold etching step and the formation of the cavity (i.e. a layer structure as described in respect of the method).

Figure 8 is an image of a further device in accordance with the present invention, the device having been obtained by etching the device precursor shown in Figure 7. The reference length scale in the bottom right reads 20 pm.

Figure 9 is an image of a further device precursor (i.e. layer structure). However, along one edge the length of the second portion of the dielectric layer over the graphene is less than 1 pm.

Figure 10 is an image of a further device, the device having been obtained by etching the device precursor shown in Figure 9. However, along the one edge in which the dielectric layer did not extend far enough, no cavity is observed. Figure 10 shows that the dielectric layer adjacent the right hand side edge orthogonal to each of the two electrical contacts does not fold to contact the graphene surface, but remains “floating” leaving the edge of the graphene exposed and potentially vulnerable. However, by sealing two or more other edges of the rectangular graphene layer, a relatively robust device is still provided, though ideally all edges are sealed in accordance with Figure 8. Figure 11 is the outline of an image of an electrochemical sensor comprising three individual devices (cells) in accordance with the present invention, each cell connected via the further metal circuitry to provide the necessary source and drain. More individual cells may be incorporated into the device. Each cell may have the same functionalisation (to improve accuracy of results and elimination of false positives) or may have different functionalisations in order to provide a device capable of detecting multiple analytes simultaneously. In other embodiments, some cells may not have any functionalisation and used as a reference, for example. The sensor further comprises a common gate contact (the circular pad) on the substrate. In use, a liquid sample may be applied to the sensor coating the exposed surfaces of each cell and the common gate contact simultaneously. Whilst the present embodiment comprises three cells, the device can be manufactured to include any desired number of cells, which may depend on the intended final application. The reference length scale in the bottom right reads 500 pm.

Figure 12 is an image of a further individual device, substantially in accordance with the schematic in Figure 3 with the exception that the dielectric layer was patterned to comprise a small circular window having a diameter of about 4 pm. For such a small window, an undercut of at least about 2 pm allowed for the sealing of the edges by the dielectric layer and the concomitant formation of a cavity. The two lengths of the second portion of the dielectric layer displayed in Figure 12 read 1 .85 pm and 2.71 pm, and the diameter of the window 4.44 pm.

1 . Monolayer graphene was grown on a sapphire substrate in an MOCVD reactor in accordance with the process in WO 2017/029470.

2. Gold was evaporated onto the graphene using e-beam evaporation to form a fully conformal layer. The thickness of the evaporated gold was 100 nm.

3. A positive photoresist was spin coated for 30 s at 1500 rpm to attain a resist film thickness of 1 pm. A mask aligner was used to expose the positive photoresist for 10 seconds through a chrome quartz mask designed with the final patterns of a GFET channel. Positive photoresist was then developed in the resist developer for one minute.

4. Gold was then wet etched using a potassium iodide and iodine solution to completely remove the gold from the portions of the wafers free of positive photoresist. The graphene in areas where it remained exposed was removed via plasma etching. The setting used for this were 40% power (on a 100 W device) with 6 seem oxygen flow rate for 1 minute. Positive photoresist was then removed by immersing the wafer in a photoresist stripper, i.e. SVC-14, for 20 minutes. A DI water bath was also used to rinse any excess of the photoresist stripper adhering to the wafer. 5. A second photolithography process was used to define the metal traces, contact pads and inplane gate electrode. Similar to step 3, a positive photoresist was spin coated, baked, exposed and developed. Such a positive photoresist presents a negative sidewall profile to facilitate the lift-off process. A metal stack comprising 10 nm titanium, 60 nm gold and 30 nm platinum was evaporated using e-beam evaporation. Lift-off of the resist was performed in a heated resist stripper bath at 80°C for 30 min. Following a DI water rinse step, the wafer was dried with a nitrogen gun and then plasma cleaned (40% power, 6 seem oxygen flow rate for 1 minute) to remove any possible residue of photoresist still present on the wafer.

6. AI2O3 was evaporated onto the wafer using a thermal evaporator to form a blanket passivation layer. A third photolithography process was used to define windows on the graphene GFET channels, contact pads and in-plane gate electrode. Similar to steps 3 and 5, a positive photoresist was spin coated, baked, exposed and developed. Concentrated phosphoric acid was then used to wet etch AI2O3 through the windows of the photoresist. Positive photoresist was removed by immersing the wafer in a photoresist stripper for 20 minutes. A DI water bath was also used to rinse any excess of the photoresist stripper adhering to the wafer.

7. Finally, the gold layer protecting the graphene channel was fully etched in a potassium iodide and iodine solution for 1 minute. The wafer was then rinse in DI water and dried using a nitrogen gun.

Various devices manufactured by such a method are shown in Figures 4 to 12.

As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of” (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of” (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe, for example, various elements, layers, portions and/or sub-portions, the elements, layers, portions and/or sub-portions should not be limited by these terms. These terms are only used to distinguish one element, layer, portion or sub-portion from another, or a further, element, layer, portion or sub-portion. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

Numerical lower and upper limits of features described herein may preferably be combined to provide a closed range.

The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.

For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference.

Claims

Claims:

1 . A structure for an electronic device, the structure comprising: a patterned two-dimensional material layer structure on a substrate; and a patterned dielectric layer having (i) a first portion which is on and/or over the substrate adjacent an edge of the two-dimensional material layer structure, and (ii) a second portion which extends from the first portion over the two-dimensional material layer structure, and makes resting contact with a surface of the two-dimensional material layer structure thereby defining a cavity between at least the dielectric layer and the two-dimensional material layer structure; wherein the dielectric layer has a thickness of less than 250 nm.

2. The structure according to claim 1 , wherein the length of the second portion of the dielectric layer that is in contact with the surface of the two-dimensional material layer is at least 500 nm, preferably at least 1 pm.

3. The structure according to claim 1 or claim 2, wherein the dielectric layer has a thickness of at least 5 nm.

4. The structure according to any preceding claim, wherein the dielectric layer has a thickness of less than 150 nm, preferably less than 100 nm.

5. The structure according to any preceding claim, wherein the first portion of the dielectric layer is on the substrate and the second portion of the dielectric layer extends 20 to 200 nm in height above the surface of the two-dimensional material layer structure, preferably 50 to 150 nm, whereby the cavity is defined between the second portion of the dielectric layer and the two-dimensional material layer structure.

6. The structure according to any preceding claim, wherein the first portion is on a support layer and the support layer is on the substrate adjacent the edge of the two-dimensional material layer structure, the support layer having a thickness of from 20 to 200 nm, preferably 50 to 150 nm, whereby the cavity is defined between the support layer, the second portion of the dielectric layer and the two-dimensional material layer structure.

7. The structure according to claim 6, wherein the support layer is formed of metal.

8. The structure according to claim 7, wherein the metal comprises ruthenium, rhodium, palladium, silver, osmium, iridium, platinum and/or gold, preferably gold.

9. The structure according to any preceding claim, wherein the cavity has a width of from 100 nm to 1 pm, preferably from 200 nm to 800 nm.

10. The structure according to any preceding claim, wherein the dielectric layer is formed of an inorganic oxide or nitride, preferably silicon oxide, silicon nitride, aluminium oxide, aluminium nitride and/or hafnium oxide.

11 . The structure according to any preceding claim, wherein the two-dimensional material layer structure is provided on a non-metallic surface of the substrate, preferably wherein the substrate is sapphire or a rare earth oxide on silicon.

12. The structure according to any preceding claim, wherein the two-dimensional material layer structure is a two-dimensional material monolayer.

13. The structure according to any preceding claim, wherein the patterned two-dimensional material layer structure is substantially rectangular.

14. The structure according to any preceding claim, wherein the first portion of the dielectric layer consists of one or more first sub-portions, each of the first sub-portions either on or over the substrate adjacent an edge of the two-dimensional material layer structure whereby the first portion completely surrounds all edges of the patterned two-dimensional material layer structure, and wherein the second portion of the dielectric layer consists of one or more corresponding second sub-portions whereby the second sub-portions define a window to an exposed surface of the two-dimensional material layer structure.

15. The structure according to claim 14, wherein the exposed surface of the two-dimensional material layer structure has an area of at least 100 pm², preferably at least 1 ,000 pm².

16. The structure according to claim 14 or claim 15, wherein at least two first sub-portions of the dielectric layer are each on corresponding sub-portions of a support layer, each of said sub-portions of the support layer being in the form of a metal contact on portions of the surface of, and adjacent opposite edges of, the two-dimensional material layer structure, and preferably wherein each metal contact extends onto adjacent portions of the surface of the substrate.

17. The structure according to claim 16, wherein a remainder of the first sub-portions of the dielectric layer are on the substrate each adjacent a remaining edge of the two-dimensional material layer structure.

18. The structure according to any of claims 14 to 17, wherein the exposed surface of the two- dimensional material layer structure is functionalised with an analyte-receptor, preferably a bioreceptor.

19. An electronic device comprising the structure according to any preceding claim, preferably wherein the electronic device is a biosensor comprising the structure according to claim 18.

20. A method for forming the structure according to any of claims 1 to 18, or the electronic device according to claim 19, the method comprising:

(I) providing a layer structure comprising:

(a) a substrate;

21 . The method according to claim 20, wherein the step of etching comprises wet-etching.

22. The method according to claim 20 or claim 21 , wherein the metal layer consists essentially of ruthenium, rhodium, palladium, silver, osmium, iridium, platinum and/or gold, preferably gold.

23. The method according to any of claims 20 to 22, wherein providing the layer structure comprises depositing the metal layer on and across the two-dimensional material layer structure, and then patterning the two-dimensional material layer structure and the metal layer simultaneously to form the stack.

24. The method according to any of claims 20 to 23, wherein providing the layer structure comprises directly forming the two-dimensional material layer structure on the substrate by CVD.

25. The method according to any of claims 20 to 24 for forming the electronic device according to claim 19, the method further comprising functionalising the exposed surface of the two-dimensional material layer structure with an analyte-receptor.