WO2025195208A1 - Access method, related devices, and storage medium - Google Patents

Abstract

The embodiments of the present application provide an access method, related devices, and a storage medium, which can present capabilities of an aggregation device on a device, the capabilities of the aggregation device comprising a capability of a first device and a capability of a second device, so that an application program run by the device directly uses the capabilities of the aggregation device to meet a requirement of the application program for executing a service, thereby reducing the complexity of the application program for executing the service, and reducing device performance loss. The access method comprises: obtaining an access request, the access request carrying a logical address for accessing the aggregation device; according to the access request, sending a first access request to a first network address, and sending a second access request to a second network address, wherein the first network address is a network address of the first device, the second network address is a network address of the second device, and the logical address is used for corresponding to the first network address and the second network address.

Description

An access method, related device and storage medium

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 22, 2024, with application number 202410342563.2 and invention name “An access method, related equipment and storage medium”, the entire contents of which are incorporated by reference into this application.

Technical Field

The embodiments of the present application relate to the field of communication technologies, and in particular to an access method, related equipment, and storage medium.

Background Art

With the development of fields such as artificial intelligence and cloud computing, the requirements for network bandwidth, storage, computing power, etc. of equipment are constantly increasing.

However, the capabilities of a single bus device within a device are limited. For example, suppose an application running on the device requires 800 gigabits per second (Gbps), but a single bus device (such as a network interface card) provides 400 Gbps of network bandwidth. This single network interface card cannot meet the application's requirements. Therefore, the application must use two network interfaces and, at the application layer, allocate the 800 Gbps of network bandwidth to both. Allocating services across multiple network interfaces increases complexity and reduces device performance.

Summary of the Invention

An embodiment of the present application provides an access method, related devices, and storage media, which can present the capabilities of an aggregate device on a device. The capabilities of the aggregate device include the capabilities of a first bus device and the capabilities of a second bus device. Then, the application running on the device directly uses the capabilities of the aggregate device to meet the needs of the application to perform business, without the need to distribute the business performed by the application to multiple different bus devices, thereby reducing the complexity of the application's business execution and reducing the loss of device performance.

In a first aspect, an embodiment of the present application provides an access method, which is applied to a device, and the device may be a device having both computing and storage capabilities, including but not limited to desktop computers, computing devices, servers, laptop computers, and mobile devices. The device includes a processing device and an aggregation device, and the aggregation device is associated with a first bus device and a second bus device, wherein the device includes a host and a bus, and the first bus device and the second bus device are both connected to the bus. The processing device may be a host included in the device, a logic module run by a processor of the host, software, or a device running an operating system, and the processing device may be a fabric manager (FM) on a processor. The processing device may also be a component or device of the device (such as a processor, a core of a processor, a chip, etc.). The first device and the second device refer to devices connected to the bus. Hereinafter, the first device is referred to as the first bus device, and the second device is referred to as the second bus device. Taking the first bus device as an example, the first bus device may be a network card, a hard drive, a keyboard, a printer, a sound card, an artificial intelligence (AI) device, a virtual reality (VR), a graphics processing unit (GPU) for accelerating computing and graphics processing, a computing card for accelerating specific algorithms and data processing, an accelerator card for accelerating specific computing tasks, etc., so that the first bus device can be applied to applications in the computer, cloud computing, artificial intelligence, and virtual reality fields. For a description of the second bus device, please refer to the description of the first bus device, and the details are not repeated here. The capabilities of the aggregation device include the capabilities of the first bus device and the capabilities of the second bus device. Taking the capabilities of the first bus device as an example, the capabilities of the first bus device may include the supported network bandwidth, the size of the resource space, the number of supported interrupt vectors, and the number of supported task queues. The method includes: first, a processing device obtains an access request, wherein the access request carries a logical address for accessing the aggregation device. Secondly, the processing device sends a first access request to a first network address and a second access request to a second network address based on the access request, wherein the first network address is the network address of the first bus device, the second network address is the network address of the second bus device, and the logical address is used to correspond to the first network address and the second network address.

Using the method described in the first aspect, a processing device can aggregate a first bus device and a second bus device into a single aggregate device. This allows the device's operating system to present the capabilities of the aggregate device. For example, the aggregate device's network bandwidth is the sum of the first bus device's network bandwidth and the second bus device's network bandwidth. Another example is the size of the aggregate device's resource space, which is the sum of the first bus device's resource space and the second bus device's resource space. Another example is the number of interrupt vectors for the aggregate device, which is the sum of the first bus device's interrupt vectors and the second bus device's interrupt vectors. Another example is the number of task queues for the aggregate device, which is the sum of the first bus device's task queues and the second bus device's task queues. If an application program on the processing device initiates an access request requiring the use of multiple bus devices, and this aspect aggregates the first and second bus devices into a single aggregate device, then access requests initiated by the application program only need to use this single aggregate device. Access requests no longer need to be allocated to different bus devices at the application layer. Instead, access requests are allocated to a single aggregate device. This effectively reduces the complexity of executing services for applications running on the device and minimizes device performance losses. Furthermore, since the first access request and the second access request are sent to the first bus device and the second bus device respectively, the delay of sending the access request to each bus device included in the aggregation device is reduced.

Based on the first aspect, in an optional implementation, before sending a first access request to a first network address and sending a second access request to a second network address according to the access request, the method further includes: a processing device converting the logical address into a physical address; obtaining the first network address corresponding to the physical address; and the processing device obtaining the second network address corresponding to the first network address based on a pre-created correspondence between the first network address and the second network address.

By adopting this implementation method, the processing device can directly divide the access request issued by the application into a first access request and a second access request. Then, the business run by the application can directly use the aggregation device, effectively reducing the complexity of the business execution of the application run by the device and reducing the loss of device performance.

Based on the first aspect, in an optional implementation, obtaining the second network address corresponding to the first network address includes: obtaining the second network address corresponding to the first network address according to an aggregation list, wherein the aggregation list includes the first network address and the second network address.

In this implementation, the processing device pre-creates an aggregation list that includes the first network address and the second network address. The aggregation list then includes a correspondence between the first network address and the second network address. Based on the access request and the aggregation list, the processing device can directly query the first network address and the second network address, thereby enabling the logical address of the aggregation device carried in a single access request to access multiple bus devices (i.e., the first bus device and the second bus device).

Based on the first aspect, in an optional implementation, before obtaining the access request, the method further includes: sending a scan request message to the first bus device and the second bus device respectively; receiving a first response message from the first bus device, the first response message carrying the first network address; receiving a second response message from the second bus device, the second response message carrying the second network address; and obtaining a correspondence between the first network address and the second network address based on the first response message and the second response message.

Using this implementation method, a correspondence between the first network address and the second network address is created based on the first response message and the second response message (for example, an aggregation list is created). The aggregation list ensures that the first network address and the second network address are successfully obtained, and ensures the success rate of sending the first access request to the first bus device and sending the second access request to the second bus device.

Based on the first aspect, in an optional implementation, the first response message also carries first model indication information and first indication information, and the second response message also carries second model indication information and second indication information, the first indication information is used to indicate that the first bus device supports aggregation into the aggregate device, and the second indication information is used to indicate that the second bus device supports aggregation into the aggregate device, and the model of the first bus device indicated by the first model indication information is the same as the model of the second bus device indicated by the second model indication information.

By adopting this implementation, it is possible to determine to aggregate the first bus device and the second bus device into an aggregate device based on the first response message and the second response message, so as to ensure that the aggregate device can successfully respond to the access request issued by the application.

Based on the first aspect, in an optional implementation, the first network address also corresponds to quantity indication information, enable indication information, first resource indication information, and second resource indication information. For example, the aggregation list includes the first network address, the second network address, quantity indication information, enable indication information, first resource indication information, and second resource indication information. The quantity indication information is used to indicate the number of the first bus devices and/or the number of the second bus devices, the enable indication information is used to indicate that the first bus device and the second bus device have the ability to be aggregated into the aggregate device, the first resource indication information is used to indicate the size of the resource space of the first bus device, and the second resource indication information is used to indicate the size of the resource space of the second bus device. The resource space of the first bus device is used to respond to the first access request, and the resource space of the second bus device is used to respond to the second access request.

With this implementation, the aggregation list ensures that the first bus device can successfully respond to the first access request, and ensures that the second bus device can successfully respond to the second access request.

Based on the first aspect, in an optional implementation, before obtaining the access request, the method further includes: sending first configuration information and second configuration information to the first bus device, the first bus device being used to forward the second configuration information to the second bus device, the first configuration information being used to configure the first bus device so that the configured first bus device responds to the first access request, and the second configuration information being used to configure the second bus device so that the configured second bus device responds to the second access request.

With this implementation, the first bus device forwards the second configuration message to the second bus device. Then, the process of the processing device sending the second configuration message to the second bus device does not need to occupy the data path between the processing device and the second bus device.

Based on the first aspect, in an optional implementation, when the second bus device successfully receives the second configuration message and stores the second configuration message in a register, the second bus device sends a second success response message to the first bus device. When the first bus device stores the first configuration message in the register, the first bus device sends a first success response message to the processing device, and the first bus device also forwards the second success response message to the processing device, so that the processing device determines that both the first bus device and the second bus device are successfully configured based on the first success response message and the second success response message, and then both the first bus device and the second bus device can respond to the access request.

With this implementation, when the processing device receives the first success response message and the second success response message, it creates an aggregation list to ensure that the first bus device can successfully respond to the first access request and the second bus device can successfully respond to the second access request.

Based on the first aspect, in an optional implementation, the first configuration information includes an identifier of a first task queue, the second configuration information includes an identifier of a second task queue, the first task queue is used to access the first bus device, and the second task queue is used to access the second bus device.

Using this implementation, the processing device can configure a first task queue for a first bus device using first configuration information, and a second task queue for a second bus device using second configuration information. The first bus device can then respond to a first access request based on the first task queue, and the second bus device can respond to a second access request based on the second task queue. Applications running on these devices can then directly use the aggregation device to call the first and second task queues, eliminating the need to allocate services to the task queues supported by different bus devices at the application layer.

Based on the first aspect, in an optional implementation, the first configuration information includes the correspondence between the first task queue and the first interrupt vector, the second configuration information includes the correspondence between the second task queue and the second interrupt vector, the first interrupt vector is used to indicate the data accessed by the first task queue interrupt, and the second interrupt vector is used to indicate the data accessed by the second task queue interrupt.

Using this implementation, the processing device can configure the correspondence between the first task queue and the first interrupt vector for the first bus device using first configuration information, and the processing device can configure the correspondence between the second task queue and the second interrupt vector for the second bus device using second configuration information. The first bus device can then respond to the first access request based on the correspondence between the first task queue and the first interrupt vector, and the second bus device can respond to the second access request based on the correspondence between the second task queue and the second interrupt vector.

Based on the first aspect, in an optional implementation, before obtaining the first network address corresponding to the physical address, the method further includes: establishing a correspondence between the physical address of the aggregation device and the first network address.

By adopting this implementation method, the processing device can successfully divide the access request into the first access request and the second access request. Then, the business run by the application can directly use the aggregation device, effectively reducing the complexity of the business execution of the application run by the device and reducing the loss of device performance.

Based on the first aspect, in an optional implementation, after creating the aggregation list, the method further includes: creating an address lookup list, the address lookup list including the correspondence between the physical address of the aggregation device and the first network address; obtaining the first network address corresponding to the physical address includes: obtaining the first network address corresponding to the physical address according to the address lookup list.

Using this implementation method, the address lookup list created by the processing device can successfully divide the access request into the first access request and the second access request. Then, the business run by the application can directly use the aggregation device, effectively reducing the complexity of the business execution of the application run by the device and reducing the loss of device performance.

Based on the first aspect, in an optional implementation, the capabilities of the aggregation device include capabilities of the first device and capabilities of the second device.

In this implementation, when a processing device aggregates a first bus device and a second bus device into a single aggregate device, the capabilities of the aggregate device are presented to the operating system (OS). Furthermore, the capabilities of the aggregate device include the capabilities of the first bus device and the second bus device. The capabilities of the bus devices may include network bandwidth, resource space, interrupt vectors, task queues, and the like.

In a second aspect, an embodiment of the present application provides an access method, applied to an aggregation device, wherein the aggregation device is associated with a first bus device and a second bus device. The method comprises: the first bus device receives a first access request; the first bus device responds to the first access request; the second bus device receives a second access request; and the second bus device responds to the second access request, wherein the first access request and the second access request are used to execute the access request received by a device, the device including the aggregation device, and the access request carries a logical address for accessing the aggregation device. For a description of the beneficial effects of this aspect, please refer to the first aspect and are not further elaborated upon.

Based on the second aspect, in an optional implementation, before the first bus device receives the first access request and the second bus device receives the second access request, the method further includes: the first bus device receives a first scan request message; and based on the first scan request message, sends a first response message, the first response message carrying the first network address of the first bus device; the second bus device receives a second scan request message; and based on the second scan request message, sends a second response message, the second response message carrying the second network address of the second bus device, the first response message and the second response message being used to establish a correspondence between the first network address and the second network address.

Based on the second aspect, in an optional implementation, the first response message also carries first model indication information and first indication information, and the second response message also carries second model indication information and second indication information, the first indication information is used to indicate that the first bus device supports aggregation into the aggregate device, and the second indication information is used to indicate that the second bus device supports aggregation into the aggregate device, and the model of the first bus device indicated by the first model indication information is the same as the model of the second bus device indicated by the second model indication information.

Based on the second aspect, in an optional implementation, before the first bus device receives the first access request and the second bus device receives the second access request, the method further includes: the first bus device receives first configuration information and second configuration information; the first bus device forwards the second configuration information to the second bus device; the first bus device responds to the first access request including: the first bus device responds to the first access request according to the first configuration information; the second bus device responds to the second access request including: the second bus device responds to the second access request according to the second configuration information.

Based on the second aspect, in an optional implementation, the first configuration information includes an identifier of a first task queue, the second configuration information includes an identifier of a second task queue, the first task queue is used to access the first bus device, and the second task queue is used to access the second bus device.

Based on the second aspect, in an optional implementation, the first configuration information includes the correspondence between the first task queue and the first interrupt vector, the second configuration information includes the correspondence between the second task queue and the second interrupt vector, the first interrupt vector is used to indicate the data accessed by the first task queue interrupt, and the second interrupt vector is used to indicate the data accessed by the second task queue interrupt.

Based on the second aspect, in an optional implementation, the capabilities of the aggregation device include capabilities of the first device and capabilities of the second device.

In a third aspect, an embodiment of the present application provides a device comprising a processor and a memory, wherein the device is connected to an external aggregation device, wherein the aggregation device associates the first bus device with the second bus device, the processor is connected to the first bus device and the second bus device, the memory is used to store program code, and the processor is used to call the program code in the memory to enable the processor to execute a method as described in any one of the above-mentioned first aspects.

In a fourth aspect, an embodiment of the present application provides a device comprising a processor, a memory, and an aggregation device, wherein the aggregation device is associated with a first bus device and a second bus device, the processor is connected to the memory, and the processor is connected to the first bus device and the second bus device respectively; the memory is used to store program code, and the processor is used to call the program code in the memory to enable the processor to execute the method described in any one of the first aspects above.

In a fifth aspect, an embodiment of the present application provides an aggregation device, comprising a first bus device and a second bus device, wherein the first bus device comprises a first processor and a first memory connected to the first processor, and the second bus device comprises a second processor and a second memory connected to the second processor; the first memory is used to store program code, and the first processor is used to call the program code in the first memory so that the first processor executes the method executed by the first bus device as in any one of the second aspects; the second memory is used to store program code, and the second processor is used to call the program code in the second memory so that the second processor executes the method executed by the second bus device as in any one of the second aspects.

In a sixth aspect, an embodiment of the present application provides a chip system, the chip system comprising a processor and an input/output interface, the input/output interface being used to receive data and transmit it to the processor, or to send data from the processor to another chip system, the processor being used to execute the method as described in any one of the first aspects above, or the method as described in any one of the second aspects above.

In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium comprising computer program instructions. When the computer program instructions are executed by a processor, the processor executes the method as described in any one of the first aspect or the method as described in any one of the second aspect.

In an eighth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed by a computer, implement the method described in any one of the first or second aspects above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of an embodiment of the device provided in this application;

FIG2 is a flow chart of the registration steps in the access method provided in an embodiment of the present application;

FIG3 is a diagram illustrating an example of executing the registration step flowchart shown in FIG2 in a device;

FIG4 is another example diagram of the registration step flowchart shown in FIG2 being executed in a device;

FIG5 is an example diagram of the configuration information shown in FIG2 ;

FIG6 a shows an example of an address lookup list corresponding to existing bus devices;

FIG6 b is an example diagram of an address lookup list corresponding to a bus device according to an embodiment of the present application;

FIG7 is a flowchart of the steps of the access method provided in an embodiment of the present application;

FIG8 is a diagram illustrating an example of executing the access method shown in FIG7 in a device;

FIG9 is a structural diagram of a bus device provided in an embodiment of the present application;

FIG10 is a diagram illustrating an exemplary structure of a node provided in an embodiment of the present application;

FIG11 is a structural example diagram of a chip system provided in an embodiment of the present application.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

An embodiment of the present application provides an access method. First, FIG1 illustrates a device 100 to which the method of the embodiment of the present application is applied. FIG1 is a structural diagram of an embodiment of the device provided by the present application. The device may be a device having both computing and storage capabilities, including but not limited to a desktop computer, a server, a computing device, a laptop computer, and a mobile device. The device 100 includes at least a host 120, N network cards, and M hard disks. The host 120 includes a processor 101 and a memory 102. This embodiment does not limit the values of N and M. For example, the N network cards specifically include network cards 111 to 11N, and the M hard disks specifically include hard disks 121 to 12M. The host 120, the N network cards, and the M hard disks are each connected to a bus 130. The processor 101, the memory 102, the N network cards, and the M hard disks are each connected to the bus 130. The processor 101 can access the N network cards and the M hard disks via the bus 130, and the processor 101 is also connected to the memory 102 via the bus 130. For example, the processor 101 can read and write data or execute code in the memory 102 through a bus. The bus 130 can be, for example, a quick path interconnect (QPI) or an ultra path interconnect (UPI). The bus 130 is divided into an address bus, a data bus, a control bus, etc. The function of the processor 101 is mainly to interpret the instructions (or code) of the computer program and process the data in the computer software. The instructions of the computer program and the data in the computer software can be stored in the memory 102. The processor 101 is a central processing unit (CPU). Exemplarily, when the processor 101 receives a write data request (from an external device or generated by the processor 101 itself), it temporarily stores the data in the write data request in the memory 102. When the total amount of data in the memory 102 reaches a certain threshold, the processor 101 sends the data stored in the memory 102 to the hard disk for persistent storage. In addition, the processor 101 is also used for computing or processing data, such as metadata management, data deduplication, data compression, data verification, virtualized storage space, and address translation. FIG1 shows only one processor 101. In actual applications, there are often multiple processors 101, wherein one processor 101 has one or more CPU cores. This embodiment does not limit the number of CPUs or the number of CPU cores. The description of the type of processor 101 in this embodiment is an optional example and is not limited. For example, the processor 101 may include one or more chips, or one or more integrated circuits. For another example, the processor 101 may include one or more neural processing units (NPUs), optical digital signal processors (oDSPs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chips (SoCs), network processors (NPs), microcontroller units (MCUs), programmable logic devices (PLDs), network card chips, storage interface chips, or other integrated chips. The details are not described in detail. Optionally, the host 120 and the N network cards, as well as the host 120 and the M hard disks shown in this example, can be connected via a switch.

Memory 102 refers to memory that directly exchanges data with processor 101. It can read and write data at any time and at a high speed, and serves as temporary data storage for the operating system or other running programs. Memory includes at least two types of memory. For example, memory can be either random access memory or read-only memory (ROM). For example, random access memory is dynamic random access memory (DRAM) or storage class memory (SCM). DRAM and SCM are merely exemplary in this embodiment. Memory can also include other random access memories, such as static random access memory (SRAM). As for read-only memory, for example, it can be programmable read-only memory (PROM) or erasable programmable read-only memory (EPROM). In addition, the memory 102 may also be a dual in-line memory module or a dual-line memory module (DIMM), that is, a module composed of dynamic random access memory (DRAM), or a solid state disk (SSD). In actual applications, multiple memories 102 and different types of memories 102 may be configured in the device 100. This embodiment does not limit the number and type of memories 102. In addition, the memory 102 may be configured to have a power-saving function. The power-saving function means that when the system loses power and then powers on again, the data stored in the memory 102 will not be lost. A memory with a power-saving function is called a non-volatile memory.

Each of the M hard drives is used to provide storage resources, such as storing data. It can be a disk or other type of storage medium, such as a solid-state drive or a shingled magnetic recording hard drive. Each of the N network cards is used to communicate with other devices. Optionally, taking network card 111 as an example, the network card can be an intelligent network card, including a processor and memory. The network card 111 can perform data reading and writing, address conversion, and other computing functions. In certain application scenarios, the network card 111 may also have a persistent memory medium, such as persistent memory (PM), non-volatile random access memory (NVRAM), or phase change memory (PCM). The processor is used to perform operations such as address conversion and reading and writing data. The memory is used to temporarily store data to be written to the hard drive, or data read from the hard drive to be sent to the processor. For a description of the processor type included in the network card 111, please refer to the description of the processor type 101, and the details are not repeated here. The network card 111 is connected to the bus 130 via an interface. The interface may be, for example, a peripheral component interface express (PCIE) interface.

In this embodiment, the types of bus devices connected to the bus 130 (such as hard disks and network cards) are used as examples and are not limited thereto. In other examples, the bus devices connected to the bus 130 may also be keyboards, printers, sound cards, artificial intelligence (AI) devices, virtual reality (VR), graphics processing units (GPUs) for accelerating computing and graphics processing, computing cards (such as FPGAs) for accelerating specific algorithms and data processing, accelerator cards for accelerating specific computing tasks, etc., so that the device can be applied to applications in the fields of cloud computing, artificial intelligence, and virtual reality.

Based on FIG1 , the execution process of the access method provided in the embodiment of the present application is described below in conjunction with FIG2 and FIG3 . FIG2 is a flowchart of the registration steps in the access method provided in the embodiment of the present application, and FIG3 is an example diagram of an execution of the registration step flowchart shown in FIG2 in a device. In this embodiment, the protocol type used by the bus shown in FIG1 is taken as the unified bus (UB) protocol, without limitation. For example, remote direct memory access (RDMA), serial advanced technology attachment (SATA), peripheral component interconnect express (PCle), etc. may also be used. In this embodiment, the processing device used to execute the method shown in FIG2 may be a host included in the device, a logic module running on the host's processor 101, software, or a device running an operating system. For example, the processing device may be a fabric manager (FM) on the processor. The processing device may also be a component or device of the device (such as a processor, CPU core, chip, etc.). The embodiments shown in FIG. 2 and FIG. 3 can aggregate multiple bus devices into one aggregate device.

Step 201: The processing device sends multiple scan request messages to the bus.

Based on the UB protocol, the processing device can send multiple scan request messages to the bus in parallel. The scan request message is used to scan and discover each bus device connected to the bus. For the description of the bus device, please refer to the corresponding description of Figure 1, and the details will not be repeated here.

Step 202: The processing device receives a first response message from a first bus device.

Step 203: The processing device receives a second response message from the second bus device.

This embodiment takes the example that both the first bus device and the second bus device are network cards connected to the bus. It should be noted that this embodiment does not limit the description of the device types of the first bus device and the second bus device.

Taking the first bus device as an example, after receiving the scan request message, the first bus device sends a first response message to the processing device via the bus. The first response message specifically carries the first indication information, the first network address, the first type indication information, and the first resource space indication information. The contents of each field carried by the first response message are shown in Table 1:

Table 1

The first indication information is used to indicate whether the first bus device supports aggregation. The first indication information may be the Supported field of the aggregation device table (ADT). If the value of the ADT Supported field is 1, it indicates that the first bus device supports aggregation. If the value of the ADT Supported field is 0, it indicates that the first bus device does not support aggregation. The first network address is used to identify the address of the physical port of the first bus device. The first network address may be a network address (network address) or a destination network address (CNA). In the example shown in Table 1, the first network address may be the Device CNA field, and the value of the Device CNA field is used to identify the address of the physical port of the first bus device. The first type indication information is used to indicate the model of the first bus device. For example, the first type indication information may be an entity ID (EID), a globally unique identifier (GUID), a universally unique identifier (UUID), etc., without limitation. The first type of indication information may also indicate information such as the bus device type and device manufacturer, without specific limitation. In the example shown in Table 1, the first type of indication information may be the Device GUID field. The first resource space indication information is the Device resource space size (RSSZ) field. The value of the Device RSSZ field indicates the size of the resource space of the first bus device. The resource space may include memory resource size, storage space size, processor resources, network bandwidth, input/output (I/O) resources, software resources, etc. Processor resources indicate the execution time and computing power of the processor used to perform various tasks on the device. It should be noted that the description of the resource space in this embodiment is an optional example and is not limiting. As long as the resource space is related to the resources used to run the services of the first bus device, it is sufficient. The second response message specifically carries the second indication information, the second network address, the second type indication information, and the second resource space indication information. For a description of the second response message, please refer to the description of the first response message and will not be repeated here. It should be noted that the description of the names and values of each field in this embodiment is an optional example and is not limiting.

Step 204: The processing device aggregates the first bus device and the second bus device into an aggregated device.

In this embodiment, when the processing device determines that the first response message and the second response message meet the preset conditions, the first bus device and the second bus device are aggregated into an aggregate device. It can be understood that the aggregate device is associated with the first bus device and the second bus device. The preset conditions refer to that both the first bus device and the second bus device support aggregation, and the device model of the first bus device is the same as the device model of the second bus device. Specifically, the first response message carries first type indication information and first indication information, and the second response message carries second type indication information and second indication information. The first indication information is used to indicate that the first bus device supports aggregation, and the second indication information is used to indicate that the second bus device supports aggregation. The model indicated by the first type indication information is the same as the model indicated by the second type indication information. As shown in Table 1, when the first response message and the second response message meet the preset conditions, in the first response message and the second response message, the value of the ADT Supported field is 1, and the value of the Device GUID field is the same. In this embodiment, the preset condition includes the model of the first bus device being the same as the model of the second bus device as an example. In other examples, the preset condition may include the device type of the first bus device being the same as the device type of the second bus device, for example, the first bus device and the second bus device are both network cards, or the first bus device and the second bus device are both hard disks, etc.

The processing device aggregates the first bus device and the second bus device into an aggregate device by creating an aggregation list as shown in Table 2. The aggregation list is shown in Table 2: It should be noted that the fields and values of each field shown in Table 2 are optional examples and are not limited. In other examples, the aggregation list can adopt any value of any field, at least indicating the network address of the first bus device, the network address of the second bus device, the model of the first bus device, and the model of the second bus device.

Table 2

When the processing device aggregates the first bus device and the second bus device into the same aggregate device, the processing device selects one bus device from the first bus device and the second bus device as the primary device and selects the other bus devices as slave devices. This embodiment takes the example of the processing device selecting the first bus device as the primary device and the second bus device as the secondary device. It should be understood that in other examples, the processing device can also obtain a response message from the third bus device, and so on, obtain a response message from the Nth bus device, and aggregate the N bus devices into the same aggregate device to create an aggregate list as shown in Table 2. This embodiment does not limit the number of bus devices included in the aggregate list.

The aggregate list includes the Supported ADT Number field, quantity indication information, enable indication information, device mode indication information, the first network address of the first bus device, the second network address of the second bus device, first resource indication information, second resource indication information, first type indication information, and second type indication information. For descriptions of the first network address, the second network address, the first type indication information, and the second type indication information, please refer to the corresponding descriptions in Table 1 and are not further described here.

Among them, the Supported ADT Number field is used to indicate the number of aggregation lists supported by the processing device. The quantity indication information may be the Supported Secondary Device Number field. The Supported Secondary Device Number field is used to indicate the number of supported slave devices in the aggregation list. In other examples, the data indication information may be used to indicate the number of all bus devices included in the aggregation list, or the quantity indication information may be used to indicate the number of master devices included in the aggregation list, etc., without specific limitation. The enable indication information may be the ADT Enable field, which is used to indicate that the first bus device and the second bus device have the ability to aggregate into an aggregation device. The device mode indication information may be the Device Mode field, and the value of the Device Mode field is used to indicate that the first bus device is a master device and the second bus device is a slave device. This embodiment does not limit the number of fields included in the Device Mode field and the specific value of each field, as long as the Device Mode field can indicate that the first bus device is a master device and the second bus device is a slave device. The value of Primary Device CNA is the first network address of the first bus device that serves as the master device. The value of Secondary Device CNA is the second network device of the second bus device that serves as the slave device. The first resource indication information may be the Primary Device RSSZ field. The value of the Primary Device RSSZ field is used to indicate the size of the resource space of the first bus device that serves as the master device. The second resource indication information may be the Secondary Device RSSZ field. The value of the Secondary Device RSSZ field is used to indicate the size of the resource space of the second bus device that serves as the slave device.

It should be clarified that the method of creating an aggregation list shown in this embodiment is to achieve the aggregation of the first bus device and the second bus device into an aggregate device as an example, and is not limited. As long as the processing device at least creates the corresponding relationship between the network address of each bus device included in the aggregate device, the resource space size of each bus device, and the GUID of each bus device, the specific method of creating the corresponding relationship is not limited.

When the processing device aggregates the first bus device and the second bus device into the same aggregate device (i.e., creates an aggregate list as shown in Table 2), the capabilities of the aggregate device are presented to the operating system (OS). The capabilities of the aggregate device include the capabilities of the first bus device and the capabilities of the second bus device. The capabilities of the bus devices may include network bandwidth, resource space, interrupt vectors, task queues, etc., which are not specifically limited. For example, as shown in Table 3:

Table 3

For example, if the network bandwidth supported by the first bus device is A1 and the network bandwidth supported by the second bus device is A2, then the network bandwidth supported by the aggregation device is A1+A2. Specifically, if A1 and A2 are both 400 Gbps, then the network bandwidth supported by the aggregation device is 800 Gbps. For another example, if the size of the resource space supported by the first bus device is B1 and the size of the resource space supported by the second bus device is B2, then the size of the resource space supported by the aggregation device is B1+B2. Specifically, if B1 and B2 are both 10 megabytes (M), then the size of the resource space supported by the aggregation device is 20M. For another example, if the first bus device supports C1 interrupt vectors and the second bus device supports C2 interrupt vectors, then the aggregation device supports C1+C2 interrupt vectors. An interrupt vector refers to the entry address of a service routine in a task queue of a processing device, so that the processing device can respond to and process the corresponding task queue. Each interrupt vector includes a segment address and an offset, which are used to uniquely identify the entry address of an interrupt service routine. If the first bus device supports D1 task queues and the second bus device supports D2 task queues, then the aggregation device supports D1+D2 task queues. A task queue means that the processing device divides the data to be sent to the first bus device into D1 independent sub-data streams, and places the D1 sub-data streams into D1 task queues respectively. The task queues process and send the sub-data streams. It is understood that if the first bus device supports 10 task queues and the second bus device supports 10 task queues, and the aggregation device supports 20 task queues, then when the processing device sends a data stream to the aggregation device, it can divide the data stream into 20 sub-data streams and place the 20 sub-data streams into the 20 task queues supported by the aggregation device.

For example, as shown in FIG3 , a processing device aggregates a first bus device and a second bus device into a single aggregate device and registers the aggregate device with the bus. FIG4 illustrates another example of aggregation. FIG4 is another example diagram of executing the registration step flowchart shown in FIG2 in a device. For example, a first bus device and a second bus device are both network cards. First bus device 401 includes multiple functional entities or service entities (FEs). For example, first bus device 401 includes FE 411 and FE 412. Each FE included in first bus device 401 is responsible for processing various functional modules for network communications, such as modules for sending and receiving data and modules for processing network protocols. The first resource space indication information sent by first bus device 401 to the processing device includes resource space indication information for FE 411 and resource space indication information for FE 412. The resource space indication information for FE 411 is specifically used to indicate the resource space of FE 411 (for example, the network bandwidth of FE 411, the size of the resource space, the number of interrupt vectors, the number of task queues, etc.). The resource space indication information of FE411 is specifically used to indicate the resource space of FE412. Similarly, the second bus device 402 includes FE421 and FE422. Then, the second resource space indication information sent by the second bus device 402 to the processing device includes the resource space indication information of FE421 and the resource space indication information of FE422. For details, please refer to the description of the resource space indication information of FE411 and the resource space indication information of FE412. The details are not repeated here. The processing device can aggregate FE411 of the first bus device 401 and FE421 of the second bus device 402 into the same aggregated device. For a detailed description of the aggregation, please refer to step 204. The details are not repeated here.

Step 205: The processing device sends a first configuration message and a second configuration message to the first bus device.

When the processing device has successfully aggregated the first bus device and the second bus device into a single aggregated device, the processing device sends a first configuration message and a second configuration message to the first bus device, which serves as the master device. For example, as shown in FIG3 , taking the processing device as the host CPU as an example, the CPU sends the first configuration message and the second configuration message to the first bus device via the host port. The first configuration message includes a first network address, first device mode indication information, and first configuration information. The second configuration message includes a second network address, second device mode indication information, and second configuration information. The first configuration message is used to configure the first bus device so that the configured first bus device can respond to access requests from the processing device. The second configuration message is used to configure the second bus device so that the configured second bus device can respond to access requests from the processing device. For a description of the first network address and first device mode indication information included in the first configuration message, and a description of the second network address and second device mode indication information included in the second configuration message, please refer to the corresponding descriptions in Table 1, and the details are not repeated here. It can be seen that the first device mode indication information is used to indicate that the first bus device serves as the master device. The second device mode indication information is used to indicate that the second bus device functions as a slave device. The first configuration information is shown in the following example. It should be noted that the description of the first configuration information in this embodiment is an optional example and is not limiting. As long as the first bus device is configured according to the first configuration information, it can respond to access requests from the processing device.

Example 1: The first configuration information includes an identifier of a first task queue, and the first task queue is used to access the first bus device.

Referring to FIG. 5 , FIG. 5 is an example diagram of the configuration information shown in FIG. A processing device activates N first task queues for a first bus device. This embodiment does not limit the specific value of N. This example uses N as 4 as an example. Then, the processing device activates four first task queues for the first bus device, each with identifiers Q P1, Q P2, Q P3, and Q P4. The first configuration information includes the identifiers of the four first task queues, namely, Q P1, Q P2, Q P3, and Q P4.

Example 2: The first configuration information includes a correspondence between the first task queue and the first interrupt vector.

Continuing with FIG. 5 , each first task queue may correspond to one or more first interrupt vectors, enabling the processing device to process or respond to services in the corresponding task queue based on the first interrupt vectors. The processing device can then interrupt the data accessed by the first task queue based on the instructions of the first interrupt vectors. This example uses two interrupt vectors corresponding to each first task queue as an example. It should be noted that this embodiment does not limit the number of interrupt vectors corresponding to each first task queue. For example, the two first interrupt vectors corresponding to the first task queue Q P1 are P11 and P12, respectively. The first interrupt vector P11 can be used to indicate a first interrupt event. Specifically, when the first bus device successfully completes the transmission of the sub-data stream corresponding to the first task queue Q P1, the first interrupt vector P11 is the entry address of the interrupt service routine indicating the completion of the transmission of the sub-data stream corresponding to the first task queue Q P1, enabling the processing device to determine that the transmission of services in the first task queue Q P1 is complete. The first interrupt vector P12 can be used to indicate a second interrupt event. Specifically, if the first bus device has not completed transmission of the sub-data stream corresponding to the first task queue Q P1, the first interrupt vector P12 is the entry address of the interrupt service routine indicating that the sub-data stream corresponding to the first task queue Q P1 has not been fully transmitted, so that the processing device can determine that the service in the first task queue Q P1 has been interrupted due to the incomplete transmission. For the description of the two first interrupt vectors P21 and P22 corresponding to the first task queue Q P2, the two first interrupt vectors P31 and P32 corresponding to the first task queue Q P3, and the two first interrupt vectors P41 and P42 corresponding to the first task queue Q P4, please refer to the description of the first interrupt vectors P11 and P12 corresponding to the first task queue Q P1, and the details are not repeated here.

The first configuration information shown in this embodiment may include at least one of the identifier of the first task queue and the correspondence between the first task queue and the first interrupt vector. For the description of the second configuration message, please refer to the description of the first configuration message, and the details are not repeated here. For example, the second configuration message includes the identifiers of four second task queues, for example, Q S1, Q S2, Q S3 and Q S4, two second interrupt vectors S11 and S12 corresponding to the second task queue Q S1, two second interrupt vectors S21 and S22 corresponding to the second task queue Q S2, two second interrupt vectors S31 and S32 corresponding to Q S3, and two second interrupt vectors S41 and S42 corresponding to Q S4.

Step 206: The first bus device sends a second configuration message to the second bus device.

In this embodiment, when a first bus device receives a first configuration message and a second configuration message, it determines that the first bus device is the master device based on the first device mode indication information included in the first configuration message. The first bus device then performs two actions. First, the first bus device stores the first configuration message to implement the configuration of the first bus device, ensuring that the first bus device can respond to access requests from the processing device. This embodiment uses the example of the first bus device storing the first configuration message in a register, but this is not limiting. The first bus device may store the first configuration message in any storage medium within the first bus device. Second, since the first bus device has determined that it is the master device, the first bus device forwards the second configuration message to the second bus device based on the second network address carried in the second configuration message.

Step 207: The second bus device receives the second configuration message.

In this embodiment, when the second bus device receives the second configuration message, it determines that the second bus device is a slave device based on the second device mode indication information included in the second configuration message. The second bus device then performs one action: the second bus device stores the second configuration message to implement the second bus device configuration, thereby ensuring that the second bus device can respond to access requests from the processing device. This embodiment uses the example of the second bus device storing the second configuration message in a register, but this is not limiting. The second bus device may store the second configuration message in any storage medium within the second bus device.

This embodiment takes the forwarding of the second configuration message from the first bus device to the second bus device as an example. Therefore, the process of the processing device sending the second configuration message to the second bus device does not need to occupy the data path between the processing device and the second bus device.

This embodiment takes as an example that there is only one second bus device serving as a slave device. In other examples, there may be multiple second bus devices serving as slave devices. In this case, the first bus device sends a second configuration message to each second bus device, so that each second bus device can be configured according to the second configuration message.

Optionally, in the embodiment shown in FIG. 1 , when the second bus device successfully receives the second configuration message and stores the second configuration message in a register, the second bus device may send a second success response message to the first bus device. When the first bus device stores the first configuration message in a register, the first bus device may send a first success response message to the processing device. Furthermore, the first bus device may forward the second success response message to the processing device, so that the processing device determines, based on the first success response message and the second success response message, that both the first bus device and the second bus device are successfully configured. Consequently, both the first bus device and the second bus device can respond to the access request.

The processing device shown in this embodiment can implement the above steps 201, 202, 203, 204 and 205 through at least one communication interface of the device host to realize the sending and receiving of messages and configuration messages.

Step 208: The processing device obtains an address lookup list.

The processing device registers the aggregation device on the bus of the OS. The processing device generates an address lookup list as shown in Table 4 for the registered aggregation device: It should be noted that the address lookup list shown in this embodiment is an optional example, as long as the processing device can establish a correspondence between the HPA and the first network address.

Table 4

The registration list shown in this embodiment includes the correspondence between the first network address of the master device (i.e., the first bus device shown above) and the host physical address (HPA) of the master device.

For a better understanding, see Figures 6a and 6b. Figure 6a shows an example of an address lookup table corresponding to existing bus devices. In existing solutions, if a first bus device successfully registers with the bus, the physical address of the memory segment allocated to the first bus device by the processing device is HPA1. Therefore, the address lookup table created for the first bus device includes the correspondence between HPA1 and the first network address. If a second bus device successfully registers with the bus, the physical address of the memory segment allocated to the second bus device by the processing device is HPA2. Therefore, the address lookup table created for the second bus device includes the correspondence between HPA2 and the second network address. In a specific application process, if the application running on the host cannot be satisfied by one bus device, the processing device needs to call the first bus device and the second bus device, and allocate the business running by the application to the first bus device and the second bus device based on complex calculations, and after multiple address queries, such as querying the first network address through address lookup list 1, and querying the second network address through address lookup list 2, and then allocating the business to the first network address and the second network address. The business execution will bring extremely high complexity and lose the performance of the device.

Figure 6b is an example diagram of the address lookup list corresponding to the bus device shown in the embodiment of the present application. In this embodiment, the processing device aggregates the first network device and the second network device into an aggregate device, then the physical address of the memory at one end allocated by the processing device to the aggregate device is HPA. The address query list created for the aggregate device includes the correspondence between HPA and the first network address (i.e., the network address of the main device). In a specific application process, if the application running on the host cannot be satisfied by one bus device, but the aggregate device that aggregates multiple bus devices can meet the needs of the application running, the processing device directly calls the aggregate device to respond to the business performed by the application, without going through a complex business allocation process and multiple complex address query processes, thereby reducing the complexity of business execution and reducing the performance loss of the device running the application.

This embodiment does not limit the execution sequence of step 208 , step 205 , step 206 , and step 207 .

By adopting the method shown in this embodiment, the processing device can aggregate the first bus device and the second bus device into the same aggregate device, so that the capabilities of the aggregate device are presented on the OS. Moreover, the capabilities of the aggregate device include the capabilities of the first bus device and the capabilities of the second bus device. For example, the network bandwidth of the aggregate device is the sum of the network bandwidth of the first bus device and the network bandwidth of the second bus device. For another example, the resource space size of the aggregate device is the sum of the resource space size of the first bus device and the resource space size of the second bus device. For another example, the number of interrupt vectors of the aggregate device is the sum of the number of interrupt vectors of the first bus device and the number of interrupt vectors of the second bus device. For another example, the number of task queues of the aggregate device is the sum of the number of task queues of the first bus device and the number of task queues of the second bus device. Then, the processing device only registers the first bus device in the first bus device and the second bus device. It can be understood that if the application of the device initiates an access request, it needs to use at least two bus devices (for example, two network cards), and this embodiment has aggregated at least two bus devices into one aggregate device. Then, the access request initiated by the application only needs to use this one aggregate device. There is no need to allocate the access request to two different bus devices at the application layer. The access request only needs to be allocated to one aggregate device, which effectively reduces the complexity of the business execution of the application running on the device and reduces the loss of device performance.

FIG2 illustrates the process of registering only the aggregate device in the first and second bus devices. The following, in conjunction with FIG7 and FIG8 , illustrates the process of a processing device accessing the first and second bus devices. FIG7 is a flowchart of the steps of the access method provided in an embodiment of the present application. For a description of the processing device shown in this embodiment, please refer to the description of the processing device corresponding to FIG2 , and detailed description is omitted here.

Step 701: The processing device obtains an access request.

In this embodiment, an application is run on the device, for example, the access request is issued by a virtual machine (VM) running on the device. The access request may include a write command or a read command. If the access request is a write command, and each bus device associated with the aggregate device is a network card, for example, then the aggregate device is used to write the data carried by the write command to another device. For another example, if the access request is a read command, and each bus device associated with the aggregate device is a network card, for example, then the aggregate device is used to obtain data from another device and send it to the host. In this embodiment, taking the access request as a write command as an example, in order to achieve the purpose of writing data to another device, the write command carries the logical address (or virtual address) of the aggregate device.

Step 702: The processing device obtains a physical address according to the access request.

When the processing device obtains the logical address of the aggregation device carried in the access request, the processing device converts the logical address of the aggregation device to obtain the physical address of the aggregation device. For example, as shown in Figure 6b, the processing device obtains the physical address HPA of the aggregation device based on the logical address carried in the access request.

Step 703: The processing device obtains the network address of the aggregation device according to the physical address.

When the processing device obtains the physical address of the aggregation device, the processing device queries the address query table to obtain the network address corresponding to the physical address of the aggregation device. The address query table is shown in Table 4. Then, the processing device obtains the network address of the aggregation device corresponding to the physical address (HPA) of the aggregation device (i.e., the first network address of the first network device serving as the master device) based on the address query table shown in Table 4.

Step 704: The processing device obtains the first network address and the second network address according to the aggregation list.

When the processing device retrieves the first network address, it obtains an aggregation list that includes the first network address. For example, the processing device can obtain the aggregation list shown in Table 2, and then obtain all network addresses included in the aggregation list, namely, the first network address and the second network address. It will be understood that the first network address and the second network address shown in this embodiment are in the same aggregation list, and the physical address of the aggregation device is used to correspond to the aggregation list.

The processing device also obtains a first offset address and a second offset address according to the access request. The first offset address refers to an offset within the first network address relative to the first address of the first network address. The second offset address refers to an offset within the second network address relative to the first address of the second network address.

Step 705: The processing device sends a first access request to the first network address.

Step 706: The processing device sends a second access request to the second network address.

In this embodiment, after the processing device obtains the first network address and the second network address, the processing device directly sends a first access request to the first network address. The processing device directly sends a second access request to the second network address. The first access request includes the first network address and the first offset address. The second access request includes the second network address and the second offset address. It can be understood that the processing device shown in this embodiment sends access requests to the first bus device and the second bus device, respectively. For example, as shown in Figure 8 , taking the processing device as a CPU as an example, the device host includes two communication interfaces, namely, communication interface 801 and communication interface 802. The CPU sends a first access request to communication interface 801 and a second access request to communication interface 802. Communication interface 801 sends the first access request to the first bus device, and communication interface 802 sends the second access request to the second bus device. Because the processing device shown in this embodiment sends the first access request and the second access request to the first bus device and the second bus device, respectively, the latency of the processing device sending access requests to each bus device included in the aggregate device is reduced.

If the processing device receives an access request from an application and needs to write 800 gigabytes (GB) of data to the aggregation device, the processing device allocates the 800GB of data based on the resource space size of the first bus device associated with the aggregation device and the resource space size of the second bus device. Then, the processing device allocates the first data volume to the first bus device and the second data volume to the second bus device, and the sum of the first data volume and the second data volume is 800GB. For example, if the resource space of the first bus device is larger than the resource space of the second bus device, the first data volume is larger than the second data volume. For another example, if the resource space of the first bus device is equal to the resource space of the second bus device, the first data volume is equal to the second data volume. The first access request includes a first network address, a first offset, and a first data volume, and the second access request includes a second network address, a second offset, and a second data volume. It can be understood that because the first access request includes the first network address and the first offset, the first bus device can write the first data volume to the storage space identified by the first network address and the first offset. Since the second access request includes the second network address and the second offset, the second bus device can write the second amount of data into the storage space identified by the second network address and the second offset.

If the access request sent by the application running on the device to the processing device is a read command, then the first access request is used to read data in the storage space identified by the first network address and the first offset, and the second access request is used to read data in the storage space identified by the second network address and the second offset.

Using the method described in this embodiment, since the device OS presents an aggregate device, applications running on the device select the aggregate device based on its capabilities. The aggregate device's capabilities include the capabilities of the first bus device and the capabilities of the second bus device. Therefore, if a single bus device cannot meet the application's operational requirements, the aggregate device can. Applications use the aggregate device to execute corresponding services, such as writing data to or reading data from the aggregate device. Because the aggregate device presents the capabilities of multiple bus devices, even when applications use multiple bus devices, there's no need to partition services at the application layer based on the capabilities of the different bus devices. Instead, applications directly call the aggregate device to execute the services they're running. This reduces the complexity of running services across multiple bus devices and improves device performance. For example, the aggregate device aggregates N bus devices with the same capabilities, each supporting M capabilities. Specifically, the bus devices are network cards, each supporting 400 Gbps network bandwidth. The device OS then presents an aggregate device with N*M capabilities. For example, if N is 4, the capacity supported by the aggregation device is 400 * 4 = 1600 Gbps. If a device application requires 1000 Gbps of network bandwidth to run a service, and the aggregation device presented by the device's OS supports 1600 Gbps of network bandwidth, then the aggregation device meets the application's service requirements. Access requests from the application can directly request access to the aggregation device, eliminating the need to partition the application's services based on the capabilities of different bus devices.

Regarding the above method embodiment, it should be noted that:

(1) The step numbers in the flowcharts described in the embodiments are merely examples of the execution process and do not limit the order in which the steps are executed. In the embodiments of the present application, there is no strict execution order for steps that have no temporal dependencies. Furthermore, not all steps shown in the flowcharts are mandatory steps, and steps may be added or deleted based on actual needs.

(2) In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

The above describes in detail the methods provided by the embodiments of the present application. Below, the related devices and chip systems provided by the embodiments of the present application for executing the above-mentioned method embodiments are described in detail. It should be understood that the description of the related device embodiments corresponds to the description of the method embodiments. Therefore, for matters not described in detail, please refer to the above method embodiments. For the sake of brevity, they are not repeated here.

The above method embodiments are mainly introduced from the perspective of the interaction between the processing device and the bus device. It can be understood that, in order to realize the above functions, the processing device and the bus device include hardware structures and/or software modules corresponding to the execution of each function. In order to realize the functions in the above embodiments, the processing device and the bus device include hardware structures and/or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

The embodiment of the present application provides a device. For a detailed description of the device, please refer to the description corresponding to Figure 1, and the details will not be repeated here. In conjunction with the above-mentioned method embodiment, taking the processor 101 included in the host 120 as an example, the processor 101 calls the program code in the memory 102, so that in the embodiment corresponding to Figure 2, the processor 101 executes steps 201, step 202, executes step 203 to receive the second response message, step 204, step 205, and step 208. In the embodiment corresponding to Figure 7, the processor 101 executes steps 701, step 702, step 703, step 704, step 705, and step 706.

An embodiment of the present application provides a bus device. Figure 9 is a structural example diagram of the bus device provided in an embodiment of the present application. For an explanation of the bus device type, please refer to the corresponding explanation of Figure 1, and no further details are given. The bus device 900 specifically includes a processor 901, a memory 902, a bus 904, and a communication interface 903. For an explanation of the processor 901, the memory 902, and the bus 904 of the bus device 900, please refer to the corresponding explanation of Figure 1, and no further details are given. The bus device 900 communicates with external devices through the communication interface 903. If the bus device acts as a first bus device, then, when the processor 901 calls the program code in the memory 902, in the embodiment corresponding to Figure 2, the processor 901 is used to execute step 201 to receive a scan request message, execute step 202, execute step 205 to receive a first configuration message and a second configuration message, and execute step 206. In the embodiment corresponding to Figure 7, the processor 901 is used to execute step 705 to receive a first access request.

If the bus device serves as the second bus device, then, when the processor 901 calls the program code in the memory 902, in the embodiment corresponding to FIG2 , the processor 901 is configured to execute step 201 to receive the scan request message, execute step 203, execute step 206 to receive the second configuration message, and execute step 207. In the embodiment corresponding to FIG7 , the processor 901 is configured to execute step 706 to receive the second access request.

Figure 10 is a diagram illustrating an exemplary structure of a node provided in an embodiment of the present application. Specifically, node 1000 includes a transmitting module 1001, a processing module 1002, and a receiving module 1003. Transmitting module 1001 may also be referred to as a transmitter, a transmitting unit, a transmitting device, etc. Receiving module 1003 may also be referred to as a receiver, a receiving unit, a receiving device, etc. Processing module 1002 is used to implement corresponding processing functions. Transmitting module 1001 and receiving module 1003 may also be referred to as communication interfaces or communication units.

Optionally, the node 1000 further includes a storage unit, which can be used to store instructions and/or data. The processing module 1002 can read the instructions and/or data in the storage unit to perform corresponding processing control actions.

For example, node 1000 may be a processing device for executing the method embodiment shown in FIG2 . In this case, sending module 1001 is configured to execute steps 201 and 205. Receiving module 1003 is configured to execute steps 202 and 203, and processing module 1002 is configured to execute steps 204 and 208. For example, node 1000 may be a processing device for executing the method embodiment shown in FIG7 . In this case, processing module 1002 is configured to execute steps 701, 702, 703, and 704. Sending module 1001 is configured to execute steps 705 and 706.

For example, node 1000 may be a first bus device for executing the method embodiment shown in FIG2 . In this case, receiving module 1003 is configured to execute step 201 to receive a scan request message and step 205 to receive a first configuration message and a second configuration message. Sending module 1001 is configured to execute step 202 to send a first response message and step 206. For example, node 1000 may be a first bus device for executing the method embodiment shown in FIG7 . In this case, receiving module 1003 is configured to execute step 705 to receive a first access request.

For example, node 1000 may be a second bus device for executing the method embodiment shown in FIG2 . In this case, receiving module 1003 is configured to execute step 201 to receive a scan request message and to execute step 206. Sending module 1001 is configured to execute step 203. Processing module 1002 is configured to execute step 207. For example, node 1000 may be a second bus device for executing the method embodiment shown in FIG7 . In this case, receiving module 1003 is configured to execute step 706 to receive a second access request.

It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

FIG11 is a diagram illustrating a structure of a chip system according to an embodiment of the present application. The chip system 1100 (or processing system) includes a processor 1110 and an input/output interface 1120.

The processor 1110 may be a processing circuit in the chip system 1100. The processor 1110 may be coupled to a storage unit and call instructions in the storage unit so that the chip system 1100 can implement the methods and functions of the various embodiments of the present application. The input/output interface 1120 may be an input/output circuit in the chip system 1100, outputting information processed by the chip system 1100 or inputting data or signaling information to be processed into the chip system 1100 for processing.

Optionally, the processor 1110 may be implemented by one or more processors, including the one or more processors or a processing portion in the one or more processors.

Optionally, the input/output interface 1120 may include a transceiver circuit, an input/output circuit, or a communication interface.

As a solution, the chip system 1100 is used to implement the operations performed by the source node or the target node in the above various method embodiments.

Specifically, the processor 1110 is used to implement the processing-related operations performed by the processing device or bus device in the above method embodiment; the input/output interface 1120 is used to implement the sending and/or receiving-related operations performed by the processing device or bus device in the above method embodiment.

An embodiment of the present application also provides a computer-readable storage medium on which computer instructions for implementing the methods executed by the source node or the target node in the above-mentioned method embodiments are stored.

For example, when the computer program is executed by a computer, the computer can implement the method performed by the processing device or bus device in each embodiment of the above method.

An embodiment of the present application further provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by the processing device or bus device in the above-mentioned method embodiments.

An embodiment of the present application further provides a communication system, which includes the device in the above embodiments and multiple bus devices.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)). For example, the aforementioned available medium includes, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims (23)

An access method, characterized in that the method is applied to a device, and the method comprises: Obtaining an access request, the access request carrying a logical address for accessing an aggregation device, wherein the aggregation device is associated with a first device and a second device; According to the access request, a first access request is sent to a first network address, and a second access request is sent to a second network address, where the first network address is the network address of the first device, the second network address is the network address of the second device, and the logical address is used to correspond to the first network address and the second network address. The method according to claim 1, characterized in that before sending the first access request to the first network address and sending the second access request to the second network address according to the access request, the method further comprises: Converting the logical address into a physical address; Obtaining the first network address corresponding to the physical address; Obtain the second network address corresponding to the first network address. The method according to claim 2, wherein obtaining the second network address corresponding to the first network address comprises: The second network address corresponding to the first network address is obtained according to the aggregation list, wherein the aggregation list includes the first network address and the second network address. The method according to claim 2 or 3, characterized in that, before obtaining the access request, the method further comprises: Sending a scan request message to the first device and the second device respectively; receiving a first response message from the first device, where the first response message carries the first network address; receiving a second response message from the second device, where the second response message carries the second network address; A correspondence between the first network address and the second network address is obtained according to the first response message and the second response message. The method according to claim 4 is characterized in that the first response message also carries first model indication information and first indication information, the second response message also carries second model indication information and second indication information, the first indication information is used to indicate that the first device supports aggregation into the aggregated device, the second indication information is used to indicate that the second device supports aggregation into the aggregated device, and the model of the first device indicated by the first model indication information is the same as the model of the second device indicated by the second model indication information. The method according to any one of claims 1 to 5, characterized in that the first network address further corresponds to quantity indication information, enable indication information, first resource indication information, and second resource indication information; Among them, the quantity indication information is used to indicate the number of the first devices and/or the number of the second devices, the enable indication information is used to indicate that the first device and the second device have the ability to be aggregated into the aggregated device, the first resource indication information is used to indicate the size of the resource space of the first device, and the second resource indication information is used to indicate the size of the resource space of the second device. The resource space of the first device is used to respond to the first access request, and the resource space of the second device is used to respond to the second access request. The method according to any one of claims 1 to 6, characterized in that before obtaining the access request, the method further comprises: First configuration information and second configuration information are sent to the first device, and the first device is used to forward the second configuration information to the second device. The first configuration information is used to configure the first device so that the configured first device responds to the first access request, and the second configuration information is used to configure the second device so that the configured second device responds to the second access request. The method according to claim 7 is characterized in that the first configuration information includes an identifier of a first task queue, the second configuration information includes an identifier of a second task queue, the first task queue is used to access the first device, and the second task queue is used to access the second device. The method according to claim 7 or 8 is characterized in that the first configuration information includes the correspondence between the first task queue and the first interrupt vector, the second configuration information includes the correspondence between the second task queue and the second interrupt vector, the first interrupt vector is used to indicate the data accessed by the first task queue interrupt, and the second interrupt vector is used to indicate the data accessed by the second task queue interrupt. The method according to any one of claims 2 to 6, characterized in that before obtaining the first network address corresponding to the physical address, the method further comprises: A correspondence between the physical address of the aggregation device and the first network address is created. The method according to any one of claims 1 to 10, characterized in that the capabilities of the aggregate device include capabilities of the first device and capabilities of the second device. An access method, characterized in that the method is applied to an aggregation device, the aggregation device is associated with a first device and a second device, and the method includes: The first device receives a first access request; The first device responds to the first access request; The second device receives a second access request; The second device responds to the second access request, the first access request and the second access request are used to execute an access request received by a device, the device includes the aggregation device, and the access request carries a logical address for accessing the aggregation device. The method according to claim 12, wherein before the first device receives the first access request and before the second device receives the second access request, the method further comprises: The first device receives a first scan request message; Sending a first response message according to the first scan request message, where the first response message carries a first network address of the first device; The second device receives a second scanning request message; According to the second scan request message, a second response message is sent, where the second response message carries the second network address of the second device. The first response message and the second response message are used to establish a correspondence between the first network address and the second network address. The method according to claim 13 is characterized in that the first response message also carries first model indication information and first indication information, the second response message also carries second model indication information and second indication information, the first indication information is used to indicate that the first device supports aggregation into the aggregated device, the second indication information is used to indicate that the second device supports aggregation into the aggregated device, and the model of the first device indicated by the first model indication information is the same as the model of the second device indicated by the second model indication information. The method according to any one of claims 12 to 14, wherein before the first device receives the first access request and the second device receives the second access request, the method further comprises: The first device receives first configuration information and second configuration information; forwarding, by the first device, the second configuration information to the second device; The first device responding to the first access request includes: The first device responds to the first access request according to the first configuration information; The second device responding to the second access request includes: The second device responds to the second access request according to the second configuration information. The method according to claim 15 is characterized in that the first configuration information includes an identifier of a first task queue, the second configuration information includes an identifier of a second task queue, the first task queue is used to access the first device, and the second task queue is used to access the second device. The method according to claim 15 or 16 is characterized in that the first configuration information includes a correspondence between a first task queue and a first interrupt vector, the second configuration information includes a correspondence between a second task queue and a second interrupt vector, the first interrupt vector is used to indicate data accessed by an interrupt of the first task queue, and the second interrupt vector is used to indicate data accessed by an interrupt of the second task queue. The method according to any one of claims 12 to 17, characterized in that the capabilities of the aggregate device include capabilities of the first device and capabilities of the second device. A device, comprising a processor and a memory, wherein the processor is configured to connect to a first device and a second device respectively, and an aggregation device associates the first device and the second device; The memory is used to store program codes, and the processor is used to call the program codes in the memory so that the processor executes the method according to any one of claims 1 to 11. A device, comprising a processor, a memory, and an aggregation device, wherein the aggregation device is associated with a first device and a second device, the processor is connected to the memory, and the processor is connected to the first device and the second device respectively; The memory is used to store program codes, and the processor is used to call the program codes in the memory so that the processor executes the method according to any one of claims 1 to 11. An aggregation device, comprising a first device and a second device, wherein the first device comprises a first processor and a first memory connected to the first processor, and the second device comprises a second processor and a second memory connected to the second processor; The first memory is used to store program code, and the first processor is used to call the program code in the first memory to enable the first processor to execute the method performed by the first device according to any one of claims 12 to 18; The second memory is used to store program codes, and the second processor is used to call the program codes in the second memory so that the second processor executes the method executed by the second device as claimed in any one of claims 12 to 18. A chip system, characterized in that the chip system includes a processor and an input/output interface, the input/output interface is used to receive data and transmit it to the processor, or to send data from the processor to another chip system, and the processor is used to execute the method according to any one of claims 1 to 11, or the method according to any one of claims 12 to 18. A computer-readable storage medium, characterized in that it includes computer program instructions, when the computer program instructions are executed by a processor, the processor executes the method according to any one of claims 1 to 18.