WO2025195168A1 - Back contact battery and manufacturing method therefor - Google Patents

Abstract

The present application discloses a back contact battery and a manufacturing method therefor, relates to the technical field of photovoltaics, and reduces the carrier recombination rate on one side of a first surface in a back contact battery. The back contact battery comprises: a semiconductor substrate, a first doped semiconductor layer, and a second doped semiconductor layer. In a direction from a second surface to a first surface, a surface of a second region is lower than a surface of a first region, forming a recess structure. Along the arrangement direction of the first region and the second region, a side face of the recess structure is provided with a first sub-region and a second sub-region which are continuously distributed, and the second sub-region is close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of a part of the first sub-region of the recess structure gradually increases in the direction away from the first surface. The surface of the second sub-region is a plane. The first doped semiconductor layer is located on at least part of the first region. The second doped semiconductor layer is located on the second region, and extends to above a part of the first region.

Description

Back contact battery and manufacturing method thereof

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and benefits of Chinese patent application No. 202410323797.2 filed on March 20, 2024, Chinese patent application No. 202411231888.X filed on September 3, 2024, and Chinese patent application No. 202411413821.8 filed on October 10, 2024, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same.

Background Art

A solar cell is a device that can convert the above-mentioned solar light energy into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the p-n junction, the photogenerated holes flow to the p region and the photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

With the continuous development of the photovoltaic industry, reducing the cost of power generation is an issue that must be faced, and improving the photoelectric conversion efficiency of the above-mentioned back-contact cells is a key measure to reduce costs.

Summary of the Invention

The purpose of this application is to provide a back-contact battery and a manufacturing method thereof, which are used to reduce the carrier recombination rate on the first side of the back-contact battery, thereby improving the photoelectric conversion efficiency of the back-contact battery.

In order to achieve the above-mentioned objectives, the present application provides a back-contact battery, which includes: a semiconductor substrate, a first doped semiconductor layer and a second doped semiconductor layer. The semiconductor substrate has a first surface and a second surface relative to each other. The first surface has a first region and a second region that are alternately distributed. Along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region to form a groove structure. Along the arrangement direction of the first region and the second region, the side surface of the groove structure has a first sub-region and a second sub-region that are continuously distributed, and the second sub-region is close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of the portion of the first sub-region of the groove structure gradually increases in the direction away from the first surface. The surface of the second sub-region is flat. The first doped semiconductor layer is located on at least a portion of the first region. The second doped semiconductor layer is located on the second region and extends above a portion of the first region. The conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.

Using the above technical solution, in the back-contact cell provided in this application, the first surface of the semiconductor substrate has alternating first and second regions. Along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region, forming a groove structure. The presence of this groove structure can at least partially offset the first doped semiconductor layer located on at least a portion of the first region and the portion of the second doped semiconductor layer located on the second region along the thickness direction of the semiconductor substrate. This further facilitates at least partially offsetting the electrode structures that make ohmic contact with the first and second doped semiconductor layers of opposite conductivity types along the thickness direction of the semiconductor substrate, thereby reducing the risk of leakage.

In addition, the side surface of the groove structure comprises a first sub-region and a second sub-region that are continuously distributed, with the second sub-region being adjacent to the first region. Furthermore, the surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of the portion of the first sub-region of the groove structure gradually increases in a direction away from the first side. In other words, the portion of the side surface of the groove structure corresponding to the first sub-region gradually increases in height as it approaches the first region, which facilitates a smoother transition in height from the bottom of the groove structure (with a lower surface) to the first region (with a higher surface) on the first side of the semiconductor substrate. This facilitates better coverage of the portion of the second doped semiconductor layer extending from the second region to above a portion of the first region on the side surface of the groove structure during formation, preventing unfilled gaps in the second doped semiconductor layer at the boundary between the first region and the second region with a surface height difference. This reduces the number of defects on the first side of the back-contact cell and improves the formation quality of the second doped semiconductor layer at the boundary between the first region and the second region, thereby enhancing the field passivation effect of the second doped semiconductor layer at the boundary between the first region and the second region, reducing the carrier recombination rate there, and improving the photoelectric conversion line efficiency of the back-contact cell.

Furthermore, compared to a surface with a textured structure, when the surface of the second sub-region, which is continuous with the first sub-region, is planar, the second sub-region's surface is smoother and has a smaller specific surface area. Under certain conditions, the thickness of a film deposited is inversely proportional to the specific surface area of the surface on which it is deposited. Therefore, when the surface of the second sub-region is planar, it is more conducive to increasing the thickness of the second doped semiconductor layer formed on the second sub-region, thereby enhancing the field passivation effect of the second doped semiconductor layer in the second sub-region, further reducing the carrier recombination rate in the second sub-region, and improving the photoelectric conversion efficiency of the back-contact cell.

As a possible implementation solution, along the arrangement direction of the first region and the second region, the ratio of the width of the groove bottom surface of the groove structure to the total width of the second region is greater than or equal to 50% and less than or equal to 99.9%.

When employing the above technical solution, it can be understood that, because the surface of the groove structure has a height difference with the surface of the first region, and compared to the height variation of the side surfaces of the groove structure, the surface height variation of the groove bottom surface of the groove structure is smaller and flatter, thereby facilitating improved formation quality of the second doped semiconductor layer and improved carrier collection efficiency of the second doped semiconductor layer. Based on this, the ratio of the width of the groove bottom surface of the groove structure to the total width of the second region is within the above range, which can prevent the second doped semiconductor layer from being formed on the relatively flat groove bottom surface due to the small proportion of the groove bottom surface width, thereby ensuring that the second doped semiconductor layer has higher carrier diversion and collection energy.

As a possible implementation solution, along the arrangement direction of the first region and the second region, a ratio of the width of the first sub-region to the total width of the second region is greater than or equal to 0.1% and less than or equal to 5%.

In the case of adopting the above technical solution, it can be understood that when other factors (including the height difference between the first region and the bottom surface of the groove of the groove structure) are the same, the larger the width of the first sub-region, the smaller the inclination rate of the first sub-region. And the smaller the width of the first sub-region, the larger the inclination rate of the first sub-region. Based on this, the ratio between the width of the first sub-region and the total width of the second region is within the above range, which can prevent the second doped semiconductor layer from having a smaller coating effect at the junction of the first region and the second region due to the smaller proportion of the width of the first sub-region, resulting in a larger inclination rate (i.e., a lower height transition smoothness), thereby ensuring that the second doped semiconductor layer has good formation quality at the junction of the first region and the second region. In addition, it can also prevent the groove bottom surface of the groove structure from having a smaller proportion due to the larger proportion of the width of the first sub-region. To prevent the effect of the groove bottom surface of the groove structure from having a smaller proportion, please refer to the previous text and will not be repeated here.

As a possible implementation solution, along the arrangement direction of the first region and the second region, the width of the second sub-region is greater than or equal to 100 nm and less than or equal to 600 nm.

When the above technical solution is adopted, in the actual manufacturing process, after the first doped semiconductor layer is formed as a whole layer on the first surface, it is necessary to remove the portion of the first doped semiconductor layer located on most of the second region under the masking action of the mask layer. Then, under the masking action of the mask layer, the portion of the semiconductor substrate exposed outside the mask layer is etched to form the above-mentioned groove structure. In particular, when etching the semiconductor substrate, the etchant can not only etch the portion of the semiconductor substrate exposed outside the masking action along the thickness direction of the semiconductor substrate, but also has a certain etching effect on the first doped semiconductor layer and the portion of the semiconductor substrate located below the edge region of the mask layer along the direction parallel to the second surface, thereby forming the above-mentioned groove structure under the partial isotropic etching action of the etchant, so that the surface of the second sub-region in the groove structure is flat and lower than the surface of the first region, and the portion of the first doped semiconductor layer remaining on the second region is removed. Based on this, the width of the second sub-region within the above-mentioned range can prevent the second doped semiconductor layer from occupying a small portion of the flat surface portion of the side surface of the recessed structure due to the smaller width of the second sub-region, thereby ensuring good formation quality and field passivation effect of the second doped semiconductor layer at the junction of the first and second regions. This also prevents the shorter etching time of the etchant due to the smaller width of the second sub-region, which results in a smaller recessed structure depth. This ensures that electrodes of opposite conductivity types on one side of the first surface can be staggered a certain distance along the thickness direction of the semiconductor substrate, further reducing the risk of leakage. Furthermore, this can prevent the longer etching time of the etchant due to the larger width of the second sub-region, which results in an excessively large recessed structure depth and the need for a thicker semiconductor substrate, thereby facilitating the thin-film production of back-contact cells.

As a possible implementation solution, the height difference between the surface of the second sub-region and the surface of the first region is greater than or equal to 5 nm and less than or equal to 40 nm.

When the above technical solution is adopted, the height difference between the surface of the second sub-region and the surface of the first region is within the above range, which can prevent the etching time of the etchant from being too short due to the small height difference, resulting in a small depth of the groove structure. In addition, it can also prevent the etching time of the etchant from being too long due to the large height difference, resulting in a large depth of the groove structure. The effect of preventing the depth of the groove structure from being small or large can be referred to the above. Secondly, it can also prevent the coating effect of the second doped semiconductor layer at the junction of the second sub-region and the first region from being too small due to the large height difference, thereby ensuring the formation quality of the second doped semiconductor layer at the junction of the second sub-region and the first region.

As a possible implementation solution, a texture structure is formed on the bottom surface of the groove structure.

When the above technical solution is adopted, the texture structure has an uneven feature. When the texture structure is formed on the bottom surface of the groove structure, it is beneficial to increase the surface area of the groove bottom surface of the groove structure, improve the light trapping effect of the groove structure, and facilitate more light to be refracted through the groove bottom surface of the groove structure into the semiconductor substrate and utilized by the semiconductor substrate. In addition, the portion of the second doped semiconductor layer corresponding to the second region includes a portion located on the bottom surface of the groove structure, and the side of the portion of the second doped semiconductor layer formed on the bottom surface of the groove by deposition and other processes that is away from the semiconductor substrate will also fluctuate along with the undulations of the bottom surface of the groove, that is, the side of the portion of the second doped semiconductor layer formed on the bottom surface of the groove that is away from the semiconductor substrate also has roughly the same undulating morphology as the bottom surface of the groove of the groove structure. Therefore, when a texture structure is formed on the bottom surface of the groove of the groove structure, the side of the portion of the second doped semiconductor layer formed on the bottom surface of the groove that is away from the semiconductor substrate also has corresponding uneven features, which is beneficial to increasing the surface area of the side of the portion of the second doped semiconductor layer formed on the bottom surface of the groove that is away from the semiconductor substrate, and further beneficial to increasing the contact area between the second doped semiconductor layer and the corresponding electrode, and beneficial to reducing the contact resistance between the second doped semiconductor layer and the corresponding electrode, and further improving the working performance of the back contact battery.

As a possible implementation solution, a texture structure is formed on the surface of the first sub-region, which has similar beneficial effects to the beneficial effects of forming a texture structure on the bottom surface of the groove structure described above, and will not be described in detail here.

As a possible implementation solution, the surface of the second sub-region is parallel to the surface of the first region.

When using the above technical solution, the second subregion is distributed continuously with the first subregion and is closer to the first region. At the same time, the surface of the second subregion is parallel to the surface of the first region. This further reduces the variation in surface height of the second subregion, facilitating a smoother transition in height from the bottom of the groove structure (with a lower surface) to the first region (with a higher surface) on the first surface of the semiconductor substrate. Furthermore, the surface of the second subregion of the groove structure is lower than that of the first region, so that the portion of the semiconductor substrate corresponding to the second subregion not only has a partial surface parallel to the second subregion and the second surface, but also has a partial surface connecting the second subregion and the first region. This increases the surface area of the portion of the semiconductor substrate corresponding to the second subregion, thereby increasing the contact area between the second doped semiconductor layer and the portion of the semiconductor substrate corresponding to the second subregion, improving the field passivation effect of the second doped semiconductor layer in the portion of the semiconductor substrate corresponding to the second subregion, and further improving the photoelectric conversion efficiency of the back-contact cell.

As a possible implementation, a textured structure is formed on the surface of the first sub-region. Along the arrangement direction of the first and second regions, the first sub-region comprises a first roughness zone and a second roughness zone, with the second roughness zone being adjacent to the second sub-region. The surface roughness of the second roughness zone is less than that of the first roughness zone.

When the above-mentioned technical solution is adopted, when a texture structure is formed on the surface of the first sub-region, the surface roughness of the first roughness zone of the first sub-region is smaller than the surface roughness of the second roughness zone along the direction close to the first region, which is conducive to making the part of the second doped semiconductor layer refracted from the second region to the first region transition from a large roughness surface to a small roughness surface, further improving the smooth transition of the second doped semiconductor layer at the junction of the second region and the first region, and further improving the coating effect of the second doped semiconductor layer at the junction of the second region and the first region.

As a possible implementation solution, a texture structure is formed on the surface of the first region. The texture structure on the surface of the first region has a square shape on a side facing away from the semiconductor substrate.

When the above technical solution is adopted, when a texture structure is formed on the surface of the first region, it is beneficial to increase the specific surface area of the first region. Secondly, the first doped semiconductor layer formed on at least part of the first region has a undulating feature on the side away from the semiconductor substrate that is substantially the same as that of the surface of the first region. Therefore, when the first region has a larger specific surface area, it is also beneficial to increase the specific surface area of the first doped semiconductor layer on the side away from the semiconductor substrate, thereby increasing the contact area between the first doped semiconductor layer and the corresponding electrode, and reducing the contact resistance. At the same time, compared with pyramid-shaped and other texture structures, when the texture structure on the surface of the first region is square on the side away from the semiconductor substrate, it is beneficial to make the surface of the first region have a relatively low surface roughness, which is beneficial to improving the formation quality of the above-mentioned first doped semiconductor layer and ensuring that the first doped semiconductor layer has a higher carrier collection ability and field passivation effect.

As a possible implementation, the morphology of the textured structure formed on the first roughness region is different from the morphology of the textured structure formed on the second roughness region. In this case, it is advantageous to form a textured structure with corresponding morphologies based on the surface roughness requirements of the first and second roughness regions in actual application scenarios, ensuring a smooth transition of the second doped semiconductor layer at the junction of the second and first regions.

As a possible implementation solution, the texture structure formed on the second roughness area is a ridge structure, and the extension direction of the ridge structure is parallel to the inclination direction of the first sub-area. The texture structure formed on the first roughness area is a suede structure.

When using the above technical solution, with other factors remaining the same, the ridgeline structure has a lower degree of undulation compared to the velvet structure, which helps reduce the specific surface area of the second roughness region, ensuring that the second roughness region has a lower surface roughness, thereby improving the coating effect of the second doped semiconductor layer on the second roughness region. In addition, when the texture structure on the first roughness region is a velvet structure, the texture structure on the first roughness region can be formed using a relatively mature velvet-forming process, which helps reduce the manufacturing difficulty of back-contact solar cells and improve the manufacturing efficiency of back-contact solar cells.

As a possible implementation solution, along the inclined direction of the first sub-region, the length of the second roughness area is greater than 0 and less than or equal to 3 μm.

When the above technical solution is adopted, the length of the second roughness zone is within the above range, which can prevent the side width of the groove structure from accounting for a larger proportion in the second area due to the larger length of the second roughness zone, resulting in a smaller proportion of the width of the groove bottom surface with a flat surface, thereby ensuring that at least most areas in the second doped semiconductor layer are formed on a flat surface, thereby improving the field passivation effect of the second doped semiconductor layer on the corresponding area of the first surface of the semiconductor substrate.

As a possible implementation, along the direction from the second surface to the first surface of the semiconductor substrate, the minimum distance from the boundary between the first roughness area and the second roughness area to the bottom of the groove structure is greater than or equal to 1 μm and less than or equal to 8 μm.

When adopting the above technical solution, it can be understood that when the width of the first roughness zone is a constant value along the direction from the first area to the second area, the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure is proportional to the inclination rate of the first sub-area. Based on this, the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure is within the above range, which can prevent the inclination rate of the first sub-area from being larger due to the larger minimum distance. In addition, it can also prevent the inclination rate of the first sub-area from being smaller due to the smaller minimum distance. The effect of preventing the inclination rate of the first sub-area from being larger or smaller can be referred to the above and will not be repeated here.

As a possible implementation scheme, when texture structures are formed on the surface of the first sub-region and on the bottom surface of the groove structure, the morphology of the texture structure formed on the surface of the first sub-region is different from the morphology of the texture structure formed on the bottom surface of the groove structure.

When the above technical solution is adopted, the bottom surface of the groove structure is approximately parallel to the second surface, while the surface of the first sub-region is inclined relative to the surface of the first region. It can be seen that the relative positional relationship between the bottom surface of the groove structure and the second surface is different from the relative positional relationship between the surface of the first sub-region and the second surface. Therefore, the bottom surface of the groove structure and the surface of the first sub-region have different crystal orientations. It can be understood that the surface treatment to form the texture structure is based on the different etching rates of the etchant on portions of the semiconductor substrate along different crystal orientations. Therefore, when the bottom surface of the groove structure and the surface of the first sub-region have different crystal orientations, the morphology of the texture structure formed by the etchant on the first sub-region is different from the morphology of the texture structure formed on the bottom surface of the groove structure. In this case, when the morphology of the texture structure on the surface of the first sub-region in the back-contact battery provided by the present application is different from the morphology of the texture structure on the bottom surface of the groove structure, there is no need to perform additional operations to form a texture structure with approximately the same morphology on the bottom surface of the groove structure and the surface of the first sub-region, which reduces the manufacturing difficulty of the back-contact battery and also helps to simplify the manufacturing process of the back-contact battery.

As a possible implementation scheme, the longitudinal section of at least part of the surface of the above-mentioned first sub-region is serrated. In this case, the serrations have multiple sharp corners. Based on this, when other factors are the same, the specific surface area of the serrated morphology is larger than that of the planar morphology. Therefore, when the longitudinal section of at least part of the surface of the first sub-region is serrated, it is beneficial for the surface of the first sub-region to have a good light-trapping effect, further improving the utilization rate of light by the back-contact battery. In addition, when other factors are the same, the surface of the serrated morphology has lower roughness than the surface of the pyramid-shaped velvet morphology, and its surface is relatively smooth, which is beneficial to improving the coating effect of the second doped semiconductor layer on the first sub-region.

As one possible implementation, the textured structure formed on at least a portion of the surface of the first sub-region is a triangular prism-like structure. This embodiment provides similar benefits to those described above where at least a portion of the surface of the first sub-region has a serrated longitudinal cross-section, and will not be further elaborated here. Furthermore, the triangular prism-like structure is a polyhedron, which helps increase the specific surface area of the first sub-region and further reduce the surface reflectivity of the first sub-region.

As a possible implementation solution, the texture structure formed on the bottom surface of the groove structure is a pyramid-shaped velvet structure.

When adopting the above technical solution, the pyramid-shaped velvet structure is a pentahedral structure. Compared with texture structures with a smaller number of surfaces such as V-shaped grooves, when the texture structure on the bottom surface of the groove structure is a pyramid-shaped velvet structure, it is beneficial to increase the specific surface area of the bottom surface of the groove structure.

As a possible implementation solution, the above-mentioned back-contact battery further includes a first passivation layer, and the first passivation layer is at least located between the first doped semiconductor layer and the first region.

When adopting the above-mentioned technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the first region of the first surface of the semiconductor substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on one side of the first surface, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

As a possible implementation, the back-contact cell further includes a second passivation layer, which is located between the second doped semiconductor layer and the second region and extends over a portion of the first region. The portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second passivation layer corresponding to the first region.

When the above-mentioned technical solution is adopted, the second passivation layer and the second doped semiconductor layer can form a selective contact structure to achieve chemical passivation of at least the second region of the first surface of the semiconductor substrate, and to achieve selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on one side of the first surface, and facilitating improvement of the photoelectric conversion efficiency of the back-contact battery.

As a possible implementation, the back-contact cell further includes an intrinsic semiconductor layer. The intrinsic semiconductor layer is formed parallel to the first surface on a portion of the first region excluding the first doped semiconductor layer. A portion of the second doped semiconductor layer corresponding to the first region overlies a portion of the intrinsic semiconductor layer facing away from the semiconductor substrate. The intrinsic semiconductor layer serves to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer.

When using the above technical solution, the first doped semiconductor layer and the second doped semiconductor layer are both formed on one side of the first surface of the semiconductor substrate, and the two have opposite conductivity types. Based on this, when the back-contact cell is in operation, the electrons and holes generated by the semiconductor substrate absorbing photons move toward the first doped semiconductor layer and the second doped semiconductor layer, respectively, and are collected and discharged by the two layers to form a photocurrent. Because the intrinsic semiconductor layer is non-conductive, the presence of the intrinsic semiconductor layer can electrically isolate the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, suppressing leakage, further reducing the carrier recombination rate on the first surface, and improving the photoelectric conversion efficiency of the back-contact cell.

As a possible implementation, the first doped semiconductor layer overlies the first region, and the doping concentration of impurities in the first doped semiconductor layer is less than or equal to 6E19 cm ³ . Furthermore, the back-contact cell further includes a second passivation layer, which is located between the second doped semiconductor layer and the second region and extends over a portion of the first region. The portion of the second doped semiconductor layer corresponding to the first region is located over the portion of the second passivation layer corresponding to the first region.

When the above technical solution is adopted, the first doped semiconductor layer can be formed on various parts of the first region, thereby increasing the formation range of the first doped semiconductor layer and further increasing the carrier collection range of the first doped semiconductor layer. Secondly, the doping concentration of impurities in the first doped semiconductor layer is less than or equal to 6E19cm ^3. At this time, the doping concentration of impurities in the first doped semiconductor layer is relatively low, which makes its own conductivity relatively weak, which is conducive to reducing the leakage current between the first doped semiconductor layer and the second doped semiconductor layer. In addition, the back contact battery also includes a second passivation layer between the second doped semiconductor layer and the second region and extending to above part of the first region. The second passivation layer can separate the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, further suppressing leakage current, and also providing another possible implementation scheme for the structure of the back contact battery, which is conducive to improving the applicability of the back contact battery provided in this application in different application scenarios.

As a possible implementation, when the back-contact cell further includes an intrinsic semiconductor layer, the impurity doping concentration within the first doped semiconductor layer is greater than or equal to 4E20 cm ³ and less than or equal to 6E20 cm ³ . In this case, as described above, the intrinsic semiconductor layer can electrically isolate the first doped semiconductor layer from the second doped semiconductor layer of opposite conductivity types. In this case, there is no need to reduce the impurity doping concentration within the first doped semiconductor layer to suppress leakage from the first doped semiconductor layer and the second doped semiconductor layer. Based on this, the impurity doping concentration within the first doped semiconductor layer is within the above-mentioned range, which can prevent the low impurity doping concentration within the first doped semiconductor layer from resulting in low conductivity and carrier collection ability. In addition, because the impurity doping concentration within the semiconductor material is limited by the solid concentration, the impurity doping concentration within the first doped semiconductor layer is within the above-mentioned range, which can also prevent the difficulty of impurity doping in the first doped semiconductor layer due to a high impurity doping concentration within the first doped semiconductor layer.

As a possible implementation solution, the first doped semiconductor layer includes a doped crystalline silicon layer.

When the above technical solution is adopted, the doped crystalline silicon layer has higher carrier transport characteristics than the doped amorphous silicon layer. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

As a possible implementation solution, the conductivity type of the first doped semiconductor layer is N-type, and the conductivity type of the second doped semiconductor layer is P-type.

As a possible implementation solution, the second doped semiconductor layer includes a doped amorphous silicon layer and/or a doped microcrystalline silicon layer.

As a possible implementation, a mask layer is provided between the second doped semiconductor layer extending above the first region and the first doped semiconductor layer, and a gap open toward the second region is provided between a portion of the mask layer close to the second region and the first doped semiconductor layer.

When the above technical solution is adopted, the above-mentioned mask layer can not only include the portion of the first doped semiconductor layer located in the first region during the selective etching of the entire first doped semiconductor layer, but also separate the second doped semiconductor layer extending above the first region from the first doped semiconductor layer of opposite conductivity type, thereby reducing the risk of leakage between the two. Secondly, a gap open to the second region is provided between the portion of the mask layer near the second region and the first doped semiconductor layer. In this case, the portion of the second passivation layer or other passivating film layer extending above the first region can also be filled in the gap, thereby increasing the contact area between the second passivation layer or other passivating film layer and the first doped semiconductor layer, improving the passivation effect, and thereby facilitating the improvement of the conversion efficiency of the back-contact battery.

As a possible implementation solution, a recessed structure recessed into the first doped semiconductor layer is provided in a portion close to the second region on a side of the first doped semiconductor layer facing away from the semiconductor substrate, and a gap is formed between the mask layer and the recessed structure.

When the above-mentioned technical solution is adopted, the existence of the above-mentioned recessed structure ensures that the surface of the portion of the first doped semiconductor layer close to the second region on the side facing away from the semiconductor substrate does not contact the mask layer, but is exposed to the outside through the gap, which is beneficial for the portion of the second passivation layer or other film layers with passivation effect formed later that fills the gap to be in passivation contact with the first doped semiconductor layer, thereby enhancing the passivation effect of the portion of the first doped semiconductor layer close to the second region on the side facing away from the semiconductor substrate.

As a possible implementation solution, in a longitudinal section of the back-contact cell, a side edge of the first doped semiconductor layer close to the second region is bent inwardly of the first doped semiconductor layer.

When the above-mentioned technical solution is adopted, compared with the side edge of the first doped semiconductor layer close to the second region being arranged perpendicular to the first surface, when the side edge of the first doped semiconductor layer close to the second region is bent inward of the first doped semiconductor layer, the side edge of the first doped semiconductor layer close to the second region has a larger side surface area, which is beneficial to enhancing the passivation contact area between the second passivation layer and other film layers with passivation effect and the side edge of the first doped semiconductor layer close to the second region. Secondly, the side edge of the first doped semiconductor layer near the second region is bent inward of the first doped semiconductor layer, which can also reduce the height variation of the side edge of the first doped semiconductor layer near the second region, which is beneficial for the second doped semiconductor layer (which may also include a second passivation layer or other film layer with a passivation effect) to better cover the side edge of the first doped semiconductor layer near the second region, preventing the second doped semiconductor layer from having unfilled gaps at the boundary between the first region and the second region with a surface height difference, further reducing the number of defects on the first side of the back contact battery, and also helping to improve the formation quality of the second doped semiconductor layer at the boundary between the first region and the second region, thereby improving the field passivation effect of the second doped semiconductor layer at the boundary between the first region and the second region, reducing the carrier recombination rate here, and helping to improve the photoelectric conversion line efficiency of the back contact battery.

As a possible implementation, a recessed structure recessed into the first doped semiconductor layer is provided in a portion of the first doped semiconductor layer near the second region on a side of the first doped semiconductor layer away from the semiconductor substrate. The beneficial effects of this embodiment can be found in the previous text and will not be elaborated on here.

As a possible implementation scheme, the side edge of the first doped semiconductor layer near the second region is inclined. The height of the inclined surface gradually decreases along the direction from the first region to the second region. In this case, reducing the height variation of the side edge of the first doped semiconductor layer near the second region is conducive to better covering the side edge of the first doped semiconductor layer near the second region (which may also include a second passivation layer or other film layer with a passivation effect), preventing the second doped semiconductor layer from having unfilled gaps at the boundary between the first region and the second region with a surface height difference, further reducing the number of defects on the first side of the back contact battery, and also helping to improve the formation quality of the second doped semiconductor layer at the boundary between the first region and the second region, thereby improving the field passivation effect of the second doped semiconductor layer at the boundary between the first region and the second region, reducing the carrier recombination rate there, and helping to improve the photoelectric conversion line efficiency of the back contact battery.

As a possible implementation solution, the back-contact cell further includes a first passivation layer, wherein the first passivation layer is at least located between the first doped semiconductor layer and the first region;

The back-contact cell further includes a second passivation layer, the second passivation layer being located between the second doped semiconductor layer and the second region and extending over a portion of the first region; a portion of the second doped semiconductor layer corresponding to the first region being located on a portion of the second passivation layer corresponding to the first region;

A texture structure is formed on the bottom surface of the groove structure, a square structure is formed on the surface of the first region, and in the second passivation layer and the second doping layer, the sum of the thicknesses of the second passivation layer and the second doping layer located at the bottom of the groove structure is less than the sum of the thicknesses of the second passivation layer and the second doping layer located in the second sub-region.

When using the above technical solution, the second passivation layer has a smaller thickness at the bottom of the groove structure, which helps to achieve lower tunneling resistance in this portion and higher carrier collection efficiency for the second doped semiconductor layer. The second passivation layer has a greater thickness in the second subregion, which helps to enhance the passivation effect in this portion. Furthermore, the second subregion is closer to the first region on which the first doped semiconductor layer is disposed. Therefore, when the second passivation layer has a greater thickness in the second subregion, it helps to achieve a higher isolation effect in the portion of the second passivation layer located in the second subregion, further reducing the risk of leakage between the second doped semiconductor layer and the first doped semiconductor layer.

As a possible implementation, when a textured structure is formed on the bottom surface of the groove structure and a textured structure is formed on the surface of the first sub-region, the size of the textured structure formed on the surface of the first sub-region is larger than the size of the textured structure formed on the bottom surface of the groove structure. In this case, it can be understood that within the same range, the number of textured structures formed on the surface of the region with the larger textured structure is relatively small, which helps to reduce the surface roughness of this region. Based on this, when the size of the textured structure formed on the surface of the first sub-region is larger than the size of the textured structure formed on the bottom surface of the groove structure, it helps to reduce the surface roughness of the first sub-region, improve the formation quality of the second doped semiconductor layer in the first sub-region, and enhance the field passivation effect of the second doped semiconductor layer in the first sub-region.

As a possible implementation scheme, the distance between the bottom surface of the groove of the groove structure and the first surface is greater than 5μm. In this case, it can be understood that the distance between the bottom surface of the groove of the groove structure and the first surface will affect the distance between the portion of the second doped semiconductor layer arranged on the bottom surface of the groove of the groove structure and the portion of the first doped semiconductor layer arranged in the first region along the thickness direction of the semiconductor substrate. Based on this, when the distance between the bottom surface of the groove of the groove structure and the first surface is within the above range, it is beneficial to increase the distance between the portion of the second doped semiconductor layer arranged on the bottom surface of the groove structure and the portion of the first doped semiconductor layer arranged in the first region along the thickness direction of the semiconductor substrate, further reducing the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer.

As a possible implementation scheme, the bottom of the groove structure has a pyramid-shaped velvet surface. Along the thickness direction of the semiconductor substrate, the surface of the second doped semiconductor layer at the top of the pyramid at the bottom of the groove facing away from the semiconductor substrate is at a distance h0 from the surface of the first doped semiconductor layer facing away from the semiconductor substrate, and 292nm≤h0≤15288nm.

In the preparation process of the back contact battery, after the second doped semiconductor layer is made, the semiconductor substrate with the second doped semiconductor layer formed thereon needs to be cleaned. During the cleaning, the semiconductor substrate is conveyed forward by a roller. On the one hand, if h0 is too small, the teeth of the roller will easily contact and scratch the second doped semiconductor layer at the bottom of the groove after extending into the groove structure. The second doped semiconductor layer at the bottom of the groove is used for passivation and carrier collection. If the second doped semiconductor layer is scratched or damaged, it will greatly affect the passivation effect and the effect of carrier collection, thereby affecting the photoelectric conversion efficiency of the back contact battery. The impact is relatively large; on the other hand, if h0 is too large, the depth of the groove structure needs to be set deeper, that is, more parts of the semiconductor substrate need to be removed, which will reduce the overall mechanical strength of the cell. In addition, the back contact cell uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If too much of the semiconductor substrate is removed, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of the semiconductor substrate will be reduced. In this way, the number of photogenerated carriers, that is, holes and electrons, generated by irradiation on the semiconductor substrate will be reduced, thereby reducing the photoelectric conversion rate of the back contact cell. Taking the above two aspects into consideration, in the back contact cell provided by the embodiment of the present invention, h0 is set within a reasonable range to reduce the situation where the teeth of the roller extend into the groove structure and scratch the second doped semiconductor layer at the bottom of the groove, while ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact cell will not be reduced, and it also ensures that the cell has sufficient mechanical strength.

As a possible implementation scheme, the bottom of the groove structure has a pyramid-shaped velvet surface. Along the thickness direction of the semiconductor substrate, the surface of the second doped semiconductor layer at the top of the pyramid at the bottom of the groove structure that is away from the semiconductor substrate is at a distance h1 from the surface of the second doped semiconductor layer covering the first doped semiconductor layer that is away from the semiconductor substrate, and 312nm≤h1≤15348nm.

Setting h1 within a reasonable range can reduce the risk of the roller teeth protruding into the groove structure and scratching the second doped semiconductor layer at the bottom of the groove, while ensuring that the light absorbency of the second doped semiconductor layer within the groove structure and the photoelectric conversion efficiency of the back-contact battery are not reduced, and also ensure that the battery cell has sufficient mechanical strength. In the case where the second doped semiconductor layer extends to the side of the first doped semiconductor layer facing away from the semiconductor substrate, the second doped semiconductor layer disposed on the side of the first doped semiconductor layer facing away from the semiconductor substrate can increase the distance between the roller teeth and the second doped semiconductor layer at the top of the pyramid covering the bottom of the groove. Therefore, h1 can be set within the range of 312nm≤h1≤15348nm, which can further prevent the roller teeth from protruding into the groove structure and scratching the second doped semiconductor layer at the bottom of the groove.

As a possible implementation scheme, the bottom of the groove structure has a pyramid-shaped velvet surface. Along the thickness direction of the semiconductor substrate, the distance between the pyramid top of the bottom of the groove structure of the semiconductor substrate and the surface of the first doped semiconductor layer away from the semiconductor substrate is h2, 330nm≤h2≤15300nm.

In this technical solution, h2 is set within a reasonable range, thereby further preventing the teeth of the roller from extending into the groove structure and scratching the pyramid at the bottom of the groove structure during the cleaning process, and further ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact battery will not decrease, and the battery cell has sufficient mechanical strength.

As a possible implementation, the groove structure has a pyramid-shaped velvet surface at its bottom. Along the thickness direction of the semiconductor substrate, the distance from the pyramid tip at the groove structure bottom to the surface of the first surface excluding the groove structure is h3, where 300 nm ≤ h3 ≤ 15000 nm. In this case, maintaining the groove structure depth within a reasonable range ensures that the light absorption rate of the semiconductor substrate and the photoelectric conversion efficiency of the back-contact cell are not reduced, while also ensuring that the cell has sufficient mechanical strength. Furthermore, after other film layers are formed on the semiconductor substrate, when the semiconductor substrate is cleaned, the teeth of the roller extending into the groove structure will not contact the pyramid at the bottom of the groove structure, or the film layers deposited on the pyramid at the bottom of the groove structure, such as the second doped semiconductor layer. This ensures that the teeth of the roller will not scratch the pyramid at the bottom of the groove structure, or the film layers formed on the pyramid at the bottom of the groove structure.

As a possible implementation, the groove bottom of the groove structure has a pyramid-shaped velvet surface, and the pyramid base size of the pyramid at the groove bottom of the semiconductor substrate ranges from 500nm to 7000nm, and the pyramid height ranges from 300nm to 6000nm. The pyramid base size and pyramid height are set within a reasonable range, so that the groove bottom of the groove structure can ensure the light trapping effect while the pyramid height of the groove bottom is appropriately reduced, thereby making the pyramid tip at the groove bottom further away from the surface of the first doped semiconductor layer that is away from the semiconductor substrate. This can further ensure that other film layers disposed at the pyramid tip at the groove bottom, such as but not limited to the second doped semiconductor layer or the transparent conductive layer, are also further away from the surface of the first doped semiconductor layer that is away from the semiconductor substrate, thereby preventing the teeth of the roller from extending into the groove structure and scratching the second doped semiconductor layer or the transparent conductive layer at the groove bottom. Furthermore, during the cleaning of the semiconductor substrate after the texturing process is completed, the teeth of the roller can be prevented from contacting the pyramid at the groove bottom of the groove structure after extending into the groove structure, thereby ensuring that the teeth of the roller will not scratch the pyramid tip at the groove bottom of the groove structure.

As a possible implementation, the spacing L between adjacent first doped semiconductor layers is 200 μm ≤ L ≤ 800 μm. In this technical solution, the spacing L between adjacent first doped semiconductor layers is set within a reasonable range. As the teeth of the roller extend into the groove structure, the side walls of the groove structure can abut against the tapered teeth, limiting the length of the roller teeth's extension into the groove structure, thereby appropriately increasing the distance between the roller teeth and the pyramidal tip at the groove bottom. This further ensures that the distance between the second doped semiconductor layer at the pyramidal tip at the groove bottom and the surface of the first doped semiconductor layer facing away from the semiconductor substrate is appropriately increased, further preventing the roller teeth from extending into the groove structure and scratching the second doped semiconductor layer at the groove bottom. Furthermore, setting the spacing L between adjacent first doped semiconductor layers within a reasonable range prevents the roller teeth from extending into the groove structure and scratching the pyramid at the groove bottom, the second doped semiconductor layer at the groove bottom, or the transparent conductive layer at the groove bottom. This also prevents the width of the second doped semiconductor layer from being too small, thereby affecting carrier collection by the second doped semiconductor layer.

As a possible implementation, the groove bottom width of the groove structure is L1, 170 μm ≤ L1 ≤ 790 μm. In this technical solution, the groove bottom width L1 is set within a reasonable range to prevent the teeth of the roller from extending into the groove structure and scratching the pyramid at the bottom of the groove structure, the second doped semiconductor layer disposed at the bottom of the groove, or the transparent conductive layer disposed at the bottom of the groove. At the same time, the width of the second doped semiconductor layer is prevented from being too small, which would affect the second doped semiconductor layer's collection of carriers.

In one implementation, 0.36≤h0/L≤76.4. It can be understood that if the depth of the groove structure is deeper, the length of the roller teeth allowed to extend into the groove structure is greater, while ensuring that the pyramid tip at the bottom of the groove, the second doped semiconductor layer located on the pyramid tip at the bottom of the groove, and the transparent conductive layer located on the pyramid tip at the bottom of the groove are not scratched. In this way, when the depth of the groove structure is deeper, the opening width of the groove structure can be appropriately increased, and the opening width of the groove structure is roughly equal to the spacing L between adjacent first doped semiconductor layers. Based on this, the embodiment of the present application sets the ratio of h0/L within a reasonable range to ensure that the roller teeth extend into the groove structure without scratching the pyramid tip at the bottom of the groove, the second doped semiconductor layer located on the pyramid tip at the bottom of the groove, and the transparent conductive layer located on the pyramid tip at the bottom of the groove, and to increase the width of the second doped semiconductor layer, thereby improving the carrier collection efficiency of the second doped semiconductor layer.

As a possible implementation, the sidewalls of the groove structure include an inclined surface that slopes away from the second surface, away from the central region of the groove bottom. The width of the inclined surface is L2, with 5μm≤L2≤15μm. In this technical solution, the width L2 of the inclined surface is set within a reasonable range to prevent the teeth of the roller from scratching the inclined surface or the film deposited on the inclined surface after entering the groove structure. At the same time, it ensures that the formation quality of the second doped semiconductor layer on the sidewalls of the groove structure is improved, thereby improving the carrier collection efficiency of the second doped semiconductor layer.

As a possible implementation scheme, the bottom of the groove structure has a pyramid-shaped velvet surface, and the top of the pyramid of the groove bottom of the semiconductor substrate is arc-shaped; in this case, compared with the pyramid with a pointed top, the height of the pyramid with an arc-shaped top is appropriately reduced, thereby increasing the distance between the top of the pyramid at the groove bottom and the surface of the first doped semiconductor layer away from the semiconductor substrate, and also increasing the distance between the second doped semiconductor layer located at the top of the pyramid at the groove bottom and the surface of the first doped semiconductor layer away from the semiconductor substrate, further reducing the probability that the teeth of the roller extend into the groove structure and scratch the pyramid at the bottom of the groove structure, the second doped semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer arranged at the bottom of the groove.

The radius of curvature of the arc-shaped pyramid tip is 70nm to 150nm; and/or the curvature of the arc-shaped pyramid tip is 30° to 150°. Setting the radius of curvature and curvature of the arc-shaped pyramid tip within an appropriate range can both appropriately reduce the height of the pyramid and thus reduce the risk of scratches on the pyramid at the bottom of the groove, while ensuring the light trapping effect of the groove structure.

As a possible implementation solution, the back-contact cell further includes a transparent conductive layer, the transparent conductive layer being disposed on a side of the first doped semiconductor layer and the second doped semiconductor layer away from the semiconductor substrate, and the transparent conductive layer being provided with an opening extending through the thickness thereof;

Along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer arranged at the top of the pyramid at the bottom of the groove and the surface of the transparent conductive layer arranged on the first doped semiconductor layer and facing away from the semiconductor substrate is greater than or equal to 316 nm and less than or equal to 15385 nm.

In this case, after the transparent conductive layer is formed, during the cleaning of the semiconductor substrate, the teeth of the roller, after extending into the groove structure, will not come into contact with the transparent conductive layer at the bottom of the groove structure, thereby preventing the teeth of the roller from scratching the transparent conductive layer at the top of the pyramid at the bottom of the groove structure. This also ensures a high light absorption rate of the semiconductor substrate, does not reduce the photoelectric conversion efficiency of the back-contact solar cell, and ensures sufficient mechanical strength of the solar cell.

As a possible implementation solution, the thickness of the second doped semiconductor layer at the bottom of the groove structure is smaller than the thickness of the second doped semiconductor layer at the sidewall of the groove structure and/or covering the first doped semiconductor layer.

With this arrangement, the second doped semiconductor layer covering the first doped semiconductor layer is thicker. When the second doped semiconductor layer covering the first doped semiconductor layer supports the roller, the teeth on the roller can be further away from the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer disposed on the second doped semiconductor layer. At the same time, the second doped semiconductor layer at the bottom of the groove structure is thinner, which can also make the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer disposed on the second doped semiconductor layer farther away from the teeth on the roller. In summary, when the thickness of the second doped semiconductor layer at the bottom of the groove structure is less than the thickness of the second doped semiconductor layer covering the first doped semiconductor layer, the distance between the teeth on the roller and the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer disposed on the second doped semiconductor layer is further increased, further reducing the possibility that the teeth of the roller extend into the groove structure and scratch the second doped semiconductor layer at the bottom of the groove or the transparent conductive layer disposed on the second doped semiconductor layer.

In a second aspect, the present application provides a method for manufacturing a back-contact battery, comprising: first, providing a semiconductor substrate having a first surface and a second surface opposite to each other; the first surface having alternating first and second regions. Next, forming at least a first doped semiconductor layer on the first region of the first surface. Next, selectively etching a portion of the second region of the semiconductor substrate so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure. Along the arrangement direction of the first and second regions, the side surface of the groove structure has continuously distributed first and second sub-regions, and the second sub-region is close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of the portion of the first sub-region of the groove structure gradually increases in a direction away from the first surface. The surface of the second sub-region is planar. Next, forming a second doped semiconductor layer covering the second region and extending above a portion of the first region. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types.

As a possible implementation, forming at least the first doped semiconductor layer on the first region of the first surface includes: forming a layer of intrinsic semiconductor material disposed entirely on the first surface. Next, selectively doping the portion of the intrinsic semiconductor material layer located on at least a portion of the first region to form the first doped semiconductor layer. Next, forming a mask layer covering the first region. Then, under the masking action of the mask layer, removing the portion of the intrinsic semiconductor material layer located on the second region.

As a possible implementation, forming at least the first doped semiconductor layer on the first region of the first surface includes forming the first doped semiconductor layer and an intrinsic semiconductor layer on the first region of the first surface. The intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer.

As a possible implementation scheme, the above-mentioned selective etching of part of the second region of the semiconductor substrate so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface comprises: under the masking action of the mask layer and using a wet chemical process to etch part of the second region of the semiconductor substrate so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure.

As a possible implementation scheme, after selectively etching part of the second region of the semiconductor substrate so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface to form a groove structure, and before forming a second doped semiconductor layer covering the second region and extending to above part of the first region, the manufacturing method of the back contact battery also includes: performing a texturing treatment on the bottom surface of the groove structure and at least part of the first sub-region.

As a possible implementation solution, after providing a semiconductor substrate and before forming at least a first doped semiconductor layer on a first region of a first surface, the method for manufacturing a back contact battery further includes: forming a first passivation layer on the first region.

As a possible implementation scheme, after selectively etching part of the second region of the semiconductor substrate so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface to form a groove structure, and before forming a second doped semiconductor layer covering the second region and extending to above a portion of the first region, the manufacturing method of the back contact battery also includes: forming a second passivation layer covering the second region and extending to above a portion of the first region.

The beneficial effects of the second aspect and its various implementations in this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a schematic longitudinal cross-sectional view of a back-contact battery according to an embodiment of the present application;

FIG2 is a SEM image 1 of a portion of the structure of a back-contact battery provided in an embodiment of the present application at the junction of the first region and the second region;

FIG3 is a second SEM image of a portion of the structure of a back-contact battery provided in an embodiment of the present application at the junction of the first region and the second region;

FIG4 is a third SEM image of a portion of the structure of a back-contact battery provided in an embodiment of the present application at the junction of the first region and the second region;

FIG5 is a fourth SEM image of a portion of the structure of a back-contact battery provided in an embodiment of the present application at the junction of the first region and the second region;

FIG6 is a fifth SEM image of a portion of the structure at the junction of the first region and the second region of the back contact battery provided in an embodiment of the present application;

FIG7 is a sixth SEM image of a portion of the structure at the junction of the first region and the second region of the back contact battery provided in an embodiment of the present application;

FIG8 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

FIG9 is a third schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

FIG10 is a first schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

FIG11 is a second schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

FIG12 is a third schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

FIG13 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

FIG14 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

FIG15 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

FIG16 is a seventh schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

FIG17 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

FIG18 is a ninth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

FIG19 is a ninth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

FIG20 is a schematic diagram of a longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process.

FIG21 is a schematic diagram of a photovoltaic module provided in an embodiment of the present application;

FIG22 is a partial cross-sectional view of a back-contact battery provided in an embodiment of the present application;

FIG23 is a schematic diagram of a semiconductor substrate having a first semiconductor layer formed thereon by roller transfer according to an embodiment of the present application;

FIG24 is a first SEM image of a portion of the structure of the back contact battery provided in an embodiment of the present application at the sidewall of the groove structure;

FIG25 is a second SEM image of a portion of the structure of the back contact battery provided in an embodiment of the present application at the sidewall of the groove structure;

FIG26 is a top-view SEM image of a portion of the structure of the back-contact battery provided in an embodiment of the present application at the sidewall of the groove structure;

FIG27 is a cross-sectional view of a semiconductor substrate provided in an embodiment of the present application;

FIG28 is a first schematic diagram of the opening positions of the transparent conductive layer of the back contact battery provided in an embodiment of the present application;

FIG29 is a second schematic diagram of the opening positions of the transparent conductive layer of the back contact battery provided in an embodiment of the present application;

FIG30 is a third schematic diagram of the opening positions of the transparent conductive layer of the back contact battery provided in an embodiment of the present application;

FIG31 is a fourth schematic diagram of the opening positions of the transparent conductive layer of the back contact battery provided in an embodiment of the present application;

Figure numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is a groove structure, 15 is a first sub-region, 16 is a second sub-region, 17 is a first doped semiconductor layer, 18 is a second doped semiconductor layer, 19 is a groove bottom surface, 20 is a first roughness region, 21 is a second roughness region, 22 is a first passivation layer, 23 is a second passivation layer, 24 is an intrinsic semiconductor layer, 25 is an intrinsic semiconductor material layer, 26 is a mask layer, 27 is a recessed structure, 6b-inclined surface, 7-roller, 7a-teeth, 8-transparent conductive layer, 8a-opening.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions/layers with different shapes, sizes, and relative positions as needed.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be an intervening layer/element between them. Furthermore, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element may be "below" the other layer/element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

When both the positive and negative electrodes of a solar cell are located on the back side of the solar cell, the solar cell is called a back-contact cell. The most significant feature of a back-contact cell is that it has no metal electrode blocking the front side, resulting in a higher short-circuit current (Isc). This makes back-contact cells one of the current technological advancements in achieving high-efficiency crystalline silicon cells.

Specifically, the above-mentioned back-contact battery generally includes a semiconductor substrate, a first doped semiconductor layer and a second doped semiconductor layer. Among them, the first doped semiconductor layer is formed on a partial area of the backlight surface of the semiconductor substrate in a direction parallel to the surface of the semiconductor substrate. A groove structure is formed on the portion of the backlight surface of the semiconductor substrate exposed outside the first doped semiconductor layer. The above-mentioned second doped semiconductor layer covers the surface of the groove structure and extends to above the portion of the first doped semiconductor layer facing away from the semiconductor substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, so as to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. The presence of the above-mentioned groove structure can at least partially stagger the electrode structures that are electrically in contact with the first doped semiconductor layer and the second doped semiconductor layer respectively along the thickness direction of the semiconductor substrate, which is conducive to suppressing leakage.

However, in the process of manufacturing the above-mentioned back-contact battery, the height difference and height change trend between the bottom of the groove structure and the first doped semiconductor layer are large, resulting in the second doped semiconductor layer being difficult to cover the various areas of this part when it is deposited on the surface between the bottom of the groove structure and the first doped semiconductor layer, resulting in unfilled gaps between the part of the second doped semiconductor layer between the bottom of the groove structure and the first doped semiconductor layer and the semiconductor substrate, which in turn results in a large number of defects on the backlight side of the back-contact battery, and a large carrier recombination rate here, resulting in a decrease in the photoelectric conversion efficiency of the back-contact battery.

To address the above technical issues, in a first aspect, embodiments of the present application provide a back-contact battery. As shown in FIG1 , the back-contact battery comprises: a semiconductor substrate 11, a first doped semiconductor layer 17, and a second doped semiconductor layer 18. The semiconductor substrate 11 has a first and second opposing surfaces. The first surface has alternating first and second regions 12, 13. Along the direction from the second surface to the first surface, the surface of the second region 13 is lower than the surface of the first region 12, forming a groove structure 14. Along the arrangement direction of the first and second regions 12, the side surfaces of the groove structure 14 have continuously distributed first and second sub-regions 15, 16, with the second sub-region 16 adjacent to the first region 12. The surface of the first sub-region 15 is inclined relative to the surface of the first region 12, and the cross-sectional area of the portion of the first sub-region 15 of the groove structure 14 gradually increases in a direction away from the first surface. The surface of the second sub-region 16 is planar. The first doped semiconductor layer 17 is located on at least a portion of the first region 12. The second doped semiconductor layer 18 is located on the second region 13 and extends above a portion of the first region 12. The second doped semiconductor layer 18 and the first doped semiconductor layer 17 have opposite conductivity types.

It should be noted that, as shown in FIG1 , the cross-sectional area of the first subregion 15 of the groove structure 14 is the corresponding cross-sectional area when the first subregion 15 of the groove structure 14 is cut transversely along a direction parallel to the second surface. Furthermore, the surface of the first region 12 and the surfaces of the first subregion 15 and the second subregion 16 included in the second region 13 are all surfaces of the semiconductor substrate 11 itself.

Using the above technical solution, as shown in FIG1 , in a back-contact cell provided in an embodiment of the present application, the first surface of the semiconductor substrate 11 has alternating first and second regions 12, 13. Along the direction from the second surface to the first surface, the surface of the second region 13 is lower than the surface of the first region 12, forming a groove structure 14. The presence of this groove structure 14 can at least partially offset the first doped semiconductor layer 17 located on at least a portion of the first region 12 and the portion of the second doped semiconductor layer 18 located on the second region 13 along the thickness direction of the semiconductor substrate 11. This facilitates at least partially offsetting the electrode structures that make ohmic contacts with the first and second doped semiconductor layers 17, 18, of opposite conductivity types, along the thickness direction of the semiconductor substrate 11, thereby reducing the risk of leakage. Furthermore, the side surfaces of the groove structure 14 have continuously distributed first and second sub-regions 15, 16, with the second sub-region 16 adjacent to the first region 12. Furthermore, the surface of the first sub-region 15 is inclined relative to the surface of the first region 12, and the cross-sectional area of the first sub-region 15 portion of the groove structure 14 gradually increases in a direction away from the first surface. In other words, the portion of the side surface of the groove structure 14 corresponding to the first sub-region 15 gradually increases in height in the direction approaching the first region 12, which is beneficial to making the height transition trend from the bottom of the groove structure 14 with a lower surface to the first region 12 with a higher surface in the first surface of the semiconductor substrate 11 relatively gentle, thereby facilitating that when the second doped semiconductor layer 18 is formed, the portion of the second doped semiconductor layer 18 extending from the second region 13 to above part of the first region 12 is better covered on the side surface of the groove structure 14, preventing the second doped semiconductor layer 18 from having unfilled gaps at the boundary between the first region 12 and the second region 13 with a surface height difference, reducing the number of defects on the first side of the back contact battery, and also helping to improve the formation quality of the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13, thereby improving the field passivation effect of the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13, reducing the carrier recombination rate here, and helping to improve the photoelectric conversion line efficiency of the back contact battery. Furthermore, compared to a surface with a textured structure, when the surface of the second sub-region 16, which is continuous with the first sub-region 15, is planar, the surface of the second sub-region 16 is smoother and has a smaller specific surface area. Under certain conditions, the thickness of a film deposited is inversely proportional to the specific surface area of the surface on which it is deposited. Therefore, when the surface of the second sub-region 16 is planar, it is more conducive to increasing the thickness of the second doped semiconductor layer 18 formed on the second sub-region 16, thereby enhancing the field passivation effect of the second doped semiconductor layer 18 in the second sub-region 16, further reducing the carrier recombination rate in the second sub-region 16, and improving the photoelectric conversion efficiency of the back-contact cell.

In actual application, the embodiment of the present application does not specifically limit the material of the semiconductor substrate. The semiconductor substrate can be a substrate made of any semiconductor material such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

It is understood that the first surface of the semiconductor substrate corresponds to the backlight side of the back-contact cell, and the second surface of the semiconductor substrate corresponds to the light-facing side of the back-contact cell. Based on this, the light-facing side of the semiconductor substrate can be a flat surface, or, as shown in FIG1 , the light-facing side of the semiconductor substrate 11 can also be a velvet surface. Because velvet traps light, when the light-facing side of the semiconductor substrate 11 is a velvet surface, the reflectivity of the light-facing side can be reduced, allowing more light to be refracted from the light-facing side into the semiconductor substrate 11 and absorbed and utilized by the semiconductor substrate 11, thereby improving the photoelectric conversion efficiency of the back-contact cell.

In terms of scope, the boundaries between the first and second regions on the first surface of the semiconductor substrate, as well as the first and second sub-regions on the side of the groove structure, are virtual boundaries. As shown in FIG1 , the first doped semiconductor layer 17 is formed on at least a portion of the first region 12. Therefore, the scope of the first region 12 on the first surface of the semiconductor substrate 11 can be determined based on the actual application scenario's requirements for the formation scope of the first doped semiconductor layer 17 and the leakage protection requirements between the first and second doped semiconductor layers 17 and 18. Furthermore, it is understood that once the scope of the first region 12 is determined, the scope of the second region 13 on the first surface can also be determined. As for the scope of the first sub-region 15 and the second sub-region 16 on the side of the groove structure 14, since the surface of the first sub-region 15 is inclined relative to the surface of the first region 12, and the surface of the second sub-region 16 is parallel to the surface of the first region 12, and the second sub-region 16 is close to the first region 12, the scope can be determined based on the relative positional relationship between the surfaces of different regions on the side of the groove structure 14 and the surface of the first region 12, and the relative positional relationship between different regions on the side of the groove structure 14 and the first region 12, and is not specifically limited here.

For the groove structure formed on one side of the first surface, in terms of size, the size of the groove structure formed on semiconductor substrates of different specifications may be different, and, as shown in Figure 1, it can be understood that the distance between the groove bottom surface 19 of the groove structure 14 and the first surface will affect the distance between the portion of the second doped semiconductor layer 18 arranged on the groove bottom surface 19 of the groove structure 14 and the portion of the first doped semiconductor layer 17 arranged in the first region 12 separated along the thickness direction of the semiconductor substrate 11, thereby affecting the leakage risk between the first doped semiconductor layer 17 and the second doped semiconductor layer 18. Therefore, the distance between the groove bottom surface 19 of the groove structure 14 and the first surface can be determined based on the anti-leakage requirements between the first doped semiconductor layer 17 and the second doped semiconductor layer 18 in the actual application scenario, as well as the actual manufacturing process, and is not specifically limited here. (It should be noted that when the groove bottom surface 19 of the groove structure 14 is formed with a texture structure, the distance between the groove bottom surface 19 of the groove structure 14 and the first surface refers to the distance between the side of the texture structure on the groove structure 14 close to the semiconductor substrate 11 and the first surface)

Exemplarily, the distance between the bottom surface of the groove structure and the first surface can be greater than 5 μm. For example, the distance between the bottom surface of the groove structure and the first surface can be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, 10 μm, 10.5 μm, 11 μm, 11.5 μm, 12 μm, 12.5 μm, 13 μm, 13.5 μm, or 1 4 μm. In this case, when the distance between the bottom surface of the groove structure and the first surface is within the above range, it is beneficial to increase the distance between the portion of the second doped semiconductor layer disposed at the bottom surface of the groove structure and the portion of the first doped semiconductor layer disposed in the first region along the thickness direction of the semiconductor substrate, further reducing the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer.

Secondly, the width of the above-mentioned groove structure will affect the size of the formation range of the first doped semiconductor layer and the second doped semiconductor layer, and the depth of the groove structure will affect the distance between the electrodes that are electrically in contact with the first doped semiconductor layer and the second doped semiconductor layer respectively, which are at least partially staggered along the thickness direction of the semiconductor substrate. Therefore, the specific size of the width and depth of the groove structure can be determined based on the size of the semiconductor substrate in the actual application scenario, the size of the formation range of the first doped semiconductor layer and the second doped semiconductor layer, and the requirements for leakage risk. No specific limitation is made here.

As for the groove bottom surface of the groove structure and the width ranges of the first and second sub-regions 16 in the side surfaces of the groove structure, as shown in FIG1 , the groove bottom surface 19, the first and second sub-regions 15, 16 are located in different positions within the groove structure 14, and the first and second sub-regions 15, 16 have different relative positional relationships with respect to the surface of the first region 12. Based on this, in actual application scenarios, the functional requirements of the groove bottom surface 19, the first and second sub-regions 15, 16 may differ, and correspondingly, the quality requirements for the formation of the second doped semiconductor layer 18 on the groove bottom surface 19, the first and second sub-regions 15, 16 may differ. Therefore, the ratios of the widths of the groove bottom surface 19, the first and second sub-regions 15, 16 of the groove structure 14 to the total width of the second region 13 can be determined based on the above requirements, and are not specifically limited here.

For example, as shown in FIG1 , along the arrangement direction of the first region 12 and the second region 13, the ratio of the width of the groove bottom surface 19 of the groove structure 14 to the total width of the second region 13 can be greater than or equal to 50% and less than or equal to 99.9%. For example, the ratio of the width of the groove bottom surface 19 of the groove structure 14 to the total width of the second region 13 can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, or 99.9%, etc. In this case, it can be understood that because the surface of the groove structure 14 has a height difference with the surface of the first region 12, and compared with the height variation of the side surface of the groove structure 14, the surface height variation of the groove bottom surface 19 of the groove structure 14 is smaller and flatter, thereby improving the formation quality of the second doped semiconductor layer 18 and improving the carrier collection efficiency of the second doped semiconductor layer 18. Based on this, the ratio between the width of the groove bottom surface 19 of the groove structure 14 and the total width of the second region 13 is within the above range, which can prevent the second doped semiconductor layer 18 from being formed on the relatively flat groove bottom surface 19 due to the small proportion of the width of the groove bottom surface 19 of the groove structure 14, thereby ensuring that the second doped semiconductor layer 18 has higher carrier diversion and collection energy.

For example, along the arrangement direction of the first region and the second region, the ratio between the width of the first sub-region and the total width of the second region can be greater than or equal to 0.1% and less than or equal to 5%. For example, the ratio between the width of the first sub-region and the total width of the second region can be 0.1%, 1%, 2%, 3%, 4%, or 5%. In this case, it can be understood that, when other factors (including the height difference between the first region and the bottom surface of the groove structure) are the same, the larger the width of the first sub-region, the smaller the inclination of the first sub-region. Conversely, the smaller the width of the first sub-region, the larger the inclination of the first sub-region. Based on this, the ratio between the width of the first sub-region and the total width of the second region within the above range can prevent the second doped semiconductor layer from having a smaller coating effect at the junction of the first region and the second region due to a larger inclination (i.e., a lower height transition smoothness) due to a smaller width of the first sub-region, thereby ensuring that the second doped semiconductor layer has good formation quality at the junction of the first region and the second region. In addition, it is also possible to prevent the groove bottom surface of the groove structure from accounting for a smaller proportion due to the larger proportion of the width of the first sub-region. For the effect of preventing the groove bottom surface of the groove structure from accounting for a smaller proportion, please refer to the previous text and will not be repeated here.

The ratio of the width of the second sub-region to the total width of the second region can be calculated based on the ratios of the widths of the groove bottom surface of the groove structure and the width of the first sub-region to the total width of the second region, and will not be further described here. The specific widths of the groove bottom surface, the first sub-region, and the second sub-region can be determined based on the specifications of the semiconductor substrate and the actual application scenario.

Exemplarily, along the arrangement direction of the first region and the second region, the width of the second sub-region can be greater than or equal to 100 nm and less than or equal to 600 nm. For example, the width of the second sub-region can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, or 600 nm. In this case, in the actual manufacturing process, after forming the entire first doped semiconductor layer on the first surface, it is necessary to remove the portion of the first doped semiconductor layer located on the majority of the second region under the masking action of the mask layer. Then, under the masking action of the mask layer, the portion of the semiconductor substrate exposed outside the mask layer is etched to form the above-mentioned groove structure. When etching the semiconductor substrate, the etchant not only etches the portion of the semiconductor substrate exposed outside the mask along the thickness direction of the semiconductor substrate, but also has a certain etching effect on the first doped semiconductor layer and the portion of the semiconductor substrate located below the edge region of the mask layer along a direction parallel to the second surface. As a result, the above-mentioned groove structure is formed under the partial isotropic etching action of the etchant, so that the surface of the second sub-region in the groove structure is planar and lower than the surface of the first region, and the portion of the first doped semiconductor layer remaining on the second region is removed. Based on this, the width of the second sub-region is within the above-mentioned range. This can prevent the second doped semiconductor layer from occupying a small proportion of the flat surface portion of the side surface of the groove structure due to the smaller width of the second sub-region, ensuring good formation quality and field passivation effect of the second doped semiconductor layer at the junction of the first region and the second region. It also prevents the groove structure from having a smaller depth due to the shorter etching time of the etchant due to the smaller width of the second sub-region. This ensures that the electrodes of opposite conductivity types on one side of the first surface are staggered by a certain distance along the thickness direction of the semiconductor substrate, further reducing the risk of leakage. In addition, it can also prevent the etchant from taking too long to etch due to the larger width of the second sub-region, resulting in the groove structure being too deep and requiring a thicker semiconductor substrate, which is conducive to the thin-film production of back-contact batteries.

As for the specific widths of the groove bottom surface and the first sub-region, they can be calculated based on the ratios of the groove bottom surface, the first sub-region and the second sub-region to the total width of the second region, and the specific width of the second sub-region, which will not be repeated here.

In addition, since the height difference between the surface of the second sub-region and the surface of the first region will affect the formation quality of the second doped semiconductor layer at the junction of the second sub-region and the first region, as well as the etching time of the etchant for etching the groove structure on the part of the semiconductor substrate corresponding to the second region, the height difference between the surface of the second sub-region and the surface of the first region can be determined based on the formation quality of the second doped semiconductor layer and the specification requirements of the groove structure in the actual application scenario, and no specific limitation is made here.

Exemplarily, the height difference between the surface of the second sub-region and the surface of the first region may be greater than or equal to 5 nm and less than or equal to 40 nm. For example, the height difference between the surface of the second sub-region and the surface of the first region may be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm or 40 nm, etc. In this case, the height difference between the surface of the second sub-region and the surface of the first region is within the above range, which can prevent the etching time of the etchant from being too short due to the small height difference, resulting in a small depth of the groove structure. In addition, it can also prevent the etching time of the etchant from being too long due to the large height difference, resulting in a large depth of the groove structure. The effect of preventing the depth of the groove structure from being small or large can be referred to the above. Secondly, it can also prevent the coating effect of the second doped semiconductor layer at the junction of the second sub-region and the first region from being too small due to the large height difference, thereby ensuring the formation quality of the second doped semiconductor layer at the junction of the second sub-region and the first region.

Furthermore, the relative positional relationship between the surface of the second sub-region and the surface of the first region will also affect the formation quality of the second doped semiconductor layer at the junction of the second sub-region and the first region. Therefore, the relative positional relationship between the surface of the second sub-region and the surface of the first region can be determined based on the formation quality of the second doped semiconductor layer in the actual application scenario and the actual manufacturing process.

For example, as shown in FIG1 , the surface of the second subregion 16, which is continuously distributed with the first subregion 15, can be parallel to the surface of the first region 12. In this case, the height variation of the surface of the second subregion 16 is further reduced relative to the height variation of the first subregion 15. Furthermore, the surface of the second subregion 16 is lower than the surface of the first region 12, so that the portion of the semiconductor substrate 11 corresponding to the second subregion 16 not only has a partial surface parallel to the second subregion 16 and the first region 12, but also has a partial surface connecting the second subregion 16 and the first region 12. This helps to increase the surface area of the portion of the semiconductor substrate 11 corresponding to the second subregion 16, thereby increasing the contact area between the second doped semiconductor layer 18 and the portion of the semiconductor substrate 11 corresponding to the second subregion 16, improving the field passivation effect of the second doped semiconductor layer 18 in the portion of the semiconductor substrate 11 corresponding to the second subregion 16, and further improving the photoelectric conversion efficiency of the back-contact cell.

Alternatively, the surface of the second sub-region, which is continuously distributed with the first sub-region, may also be inclined relative to the surface of the first region, and the inclination rate of the second sub-region relative to the surface of the first region is less than the inclination rate of the first sub-region relative to the surface of the first region. In this case, another possible implementation scheme can be provided for the back-contact battery provided in the embodiment of the present application, which is conducive to improving the applicability of the back-contact battery provided in the embodiment of the present application in different application scenarios.

In terms of surface morphology, the surface of the first region of the first surface of the semiconductor substrate can be polished; alternatively, the surface of the first region can also include a textured structure, with the textured structure on the side of the first region facing away from the semiconductor substrate having a square shape. In this case, the textured structure on the first region has a substantially pyramidal morphology and can be convex or concave along the direction from the second surface to the first surface. This helps increase the specific surface area of the first region. Furthermore, the first doped semiconductor layer formed on at least a portion of the first region has substantially the same undulating characteristics on the side facing away from the semiconductor substrate as the surface of the first region. Therefore, if the first region has a larger specific surface area, this also helps increase the specific surface area of the first doped semiconductor layer on the side facing away from the semiconductor substrate, thereby increasing the contact area between the first doped semiconductor layer and the corresponding electrode and reducing contact resistance. Furthermore, compared to pyramidal or other textured structures, a square textured structure on the side of the first region facing away from the semiconductor substrate helps achieve a relatively low surface roughness on the surface of the first region, thereby improving the formation quality of the first doped semiconductor layer and ensuring that the first doped semiconductor layer has a high carrier collection capacity and field passivation effect.

Regarding the aforementioned groove structure, the groove bottom surface of the groove structure can be flat; alternatively, as shown in Figures 1 to 3 , the groove bottom surface 19 of the groove structure 14 can also be textured. In this case, the textured structure has an uneven surface. When the groove bottom surface 19 of the groove structure 14 is textured, the surface area of the groove bottom surface 19 is increased, improving the light trapping effect of the groove structure 14 and allowing more light to be refracted through the groove bottom surface 19 of the groove structure 14 into the semiconductor substrate 11 and utilized by the semiconductor substrate 11. In addition, the portion of the second doped semiconductor layer 18 corresponding to the second region 13 includes a portion located on the groove bottom surface 19 of the groove structure 14, and the side of the portion of the second doped semiconductor layer 18 formed on the groove bottom surface 19 by deposition or other processes that faces away from the semiconductor substrate 11 will also rise and fall along with the rise and fall of the groove bottom surface 19, that is, the side of the portion of the second doped semiconductor layer 18 formed on the groove bottom surface 19 that faces away from the semiconductor substrate 11 also has an undulating morphology that is substantially the same as the groove bottom surface 19 of the groove structure 14. Therefore, when a textured structure is formed on the groove bottom surface 19 of the groove structure 14, the side of the portion of the second doped semiconductor layer 18 formed on the groove bottom surface 19 that faces away from the semiconductor substrate 11 also has corresponding uneven features, which is beneficial to increasing the surface area of the portion of the second doped semiconductor layer 18 formed on the groove bottom surface 19 that faces away from the semiconductor substrate 11, thereby increasing the contact area between the second doped semiconductor layer 18 and the corresponding electrode, reducing the contact resistance between the second doped semiconductor layer 18 and the corresponding electrode, and further improving the working performance of the back contact battery.

Specifically, the type and size of the texture structure formed on the bottom surface of the groove structure can be determined based on the specific surface area and light trapping effect requirements of the groove bottom surface in actual application scenarios, and are not specifically limited here. The texture structure can be a velvet structure such as a pyramid structure, or a non-pyramid structure (such as a hollow structure, a V-groove structure, or a tower base structure), or a polished structure.

For example, as shown in Figures 1 and 2, the texture structure formed on the groove bottom surface 19 of the groove structure 14 can be a pyramid-shaped velvet structure. In this case, the pyramid-shaped velvet structure is a pentahedral structure. Compared with texture structures with a smaller number of surfaces such as V-shaped grooves, when the texture structure on the groove bottom surface 19 of the groove structure 14 is a pyramid-shaped velvet structure, it is beneficial to increase the specific surface area of the groove bottom surface 19 of the groove structure 14.

Regarding the surface morphology of the first subregion of the groove structure, the surface of the first subregion can be flat; alternatively, as shown in Figures 1, 2, 4, and 5, a textured structure can be formed on the surface of the first subregion 15. The beneficial effects achieved in this case are similar to those achieved by forming a textured structure on the groove bottom surface 19 of the groove structure 14 described above, and will not be further elaborated here.

Specifically, the type and size of the texture structure formed on the surface of the first sub-region can be determined according to the actual application scenario and are not specifically limited here. The texture structure formed on the surface of the first sub-region can be a velvet structure such as a pyramid structure, or a non-pyramid structure (such as a hollow structure, a V-groove structure, or a tower base structure), or a polished structure.

In addition, when texture structures are formed on both the groove bottom surface of the groove structure and the surface of the first sub-region, the morphology of the texture structure formed on the first sub-region can be roughly the same as the morphology of the texture structure formed on the groove bottom surface. Alternatively, as shown in Figures 1 and 2, the morphology of the texture structure formed on the surface of the first sub-region 15 is different from the morphology of the texture structure formed on the groove bottom surface 19 of the groove structure 14. Among them, the groove bottom surface 19 of the groove structure 14 is roughly parallel to the second surface, while the surface of the first sub-region 15 is tilted relative to the surface of the first region. It can be seen that the relative positional relationship between the groove bottom surface 19 of the groove structure 14 and the second surface is different from the relative positional relationship between the surface of the first sub-region 15 and the second surface. Therefore, the crystal orientation of the groove bottom surface 19 of the groove structure 14 and the surface of the first sub-region 15 are different. It can be understood that the surface treatment to form the texture structure is achieved based on the different etching rates of the etchant on portions of the semiconductor substrate 11 along different crystal orientations. Therefore, when the crystal orientations of the bottom surface 19 of the groove structure 14 and the surface of the first sub-region 15 are different, the morphology of the texture structure formed by the etchant on the first sub-region 15 is different from the morphology of the texture structure formed on the bottom surface 19 of the groove structure 14. In this case, in the back-contact battery provided in the embodiment of the present application, when the morphology of the texture structure on the surface of the first sub-region 15 is different from the morphology of the texture structure on the bottom surface 19 of the groove structure 14, there is no need to perform additional operations to form texture structures with roughly the same morphology on the bottom surface 19 of the groove structure 14 and the surface of the first sub-region 15. This reduces the manufacturing difficulty of the back-contact battery and helps simplify the manufacturing process of the back-contact battery.

Specifically, when the morphology of the texture structure formed on the surface of the first sub-region of the groove structure is different from the morphology of the texture structure on the bottom surface of the groove, the morphology of the texture structure formed on the surface of the first sub-region and the surface morphology of the first sub-region can be determined according to the actual manufacturing process and the inclination of the first sub-region relative to the surface of the first region, and no specific limitation is made here.

For example, as shown in Figures 1 and 2, when a textured structure is formed on the bottom surface 19 of the groove structure 14 and a textured structure is formed on the surface of the first sub-region 15, the size of the textured structure formed on the surface of the first sub-region 15 can be larger than the textured structure formed on the bottom surface 19 of the groove structure 14. In this case, it can be understood that, within the same range, the number of textured structures formed on the surface of the region with the larger textured structure is relatively small, which helps to reduce the surface roughness of the region. Based on this, when the size of the textured structure formed on the surface of the first sub-region 15 is larger than the textured structure formed on the bottom surface 19 of the groove structure 14, it helps to reduce the surface roughness of the first sub-region 15, improve the formation quality of the second doped semiconductor layer 18 in the first sub-region 15, and enhance the field passivation effect of the second doped semiconductor layer 18 in the first sub-region 15.

For example, as shown in Figures 1 and 2, the longitudinal section of at least part of the surface of the first sub-region 15 may be serrated. In this case, the serrations have multiple sharp corners. Based on this, when other factors are the same, the specific surface area of the serrated morphology is larger than that of the planar morphology. Therefore, when the longitudinal section of at least part of the surface of the first sub-region 15 is serrated, it is beneficial for the surface of the first sub-region 15 to have a good light trapping effect, further improving the utilization rate of light by the back contact battery. In addition, when other factors are the same, the surface of the serrated morphology has lower roughness than the surface of the pyramid-shaped velvet morphology, and its surface is relatively smooth, which is beneficial to improving the coating effect of the second doped semiconductor layer 18 on the first sub-region 15.

As for the three-dimensional features of the texture structure formed on the first sub-region, they can be determined based on the longitudinal cross-sectional morphology of the first sub-region and the actual manufacturing process, and are not specifically limited here.

For example, as shown in Figures 1 and 2, the texture structure formed on at least part of the surface of the first sub-region 15 is a triangular prism-like structure. The beneficial effects in this case are similar to the beneficial effects of the sawtooth-shaped longitudinal section of at least part of the surface of the first sub-region 15 described above, and will not be repeated here. In addition, the triangular prism-like structure is a polyhedron structure, which is conducive to increasing the specific surface area of the surface of the first sub-region 15 and further reducing the surface reflectivity of the first sub-region 15. It should be understood that the triangular prism-like structure is a structure formed by the remaining part of an edge corner of the pyramid structure that is close to the semiconductor substrate 11 after the part is annihilated. Among them, the ratio between the length of the edge corner exposed to the outside and parallel to the surface of the first region 12 in the triangular prism-like structure and the remaining length of the edge corner partially buried in the semiconductor substrate 11 can be determined according to the inclination of the first sub-region 15 relative to the surface of the first region 12. For example, the ratio of the length of the corners of the triangular prism-like structure that are exposed and parallel to the surface of the first region 12 to the remaining length of the corners partially buried in the semiconductor substrate 11 may be greater than or equal to 1 and less than or equal to 10.

Furthermore, in actual applications, when a textured structure is formed on the surface of the first sub-region, as shown in FIG3 , the surface roughness of each portion of the first sub-region can be the same along the inclination direction of the first sub-region. Alternatively, as shown in FIG2 , FIG4 , and FIG5 , along the arrangement direction of the first region 12 and the second region 13, the first sub-region 15 has a first roughness region 20 and a second roughness region 21, with the second roughness region 21 being adjacent to the second sub-region 16, and the surface roughness of the second roughness region 21 can also be less than the surface roughness of the first roughness region 20. In this case, the portion of the second doped semiconductor layer 18 that is refracted from the second region 13 to the first region 12 transitions from a high-roughness surface to a low-roughness surface, further improving the smoothness of the transition of the second doped semiconductor layer 18 at the interface between the second region 13 and the first region 12, and further enhancing the encapsulation effect of the second doped semiconductor layer 18 at the interface between the second region 13 and the first region 12.

Among them, from the perspective of morphology, when the surface roughness of the second roughness zone is less than the surface roughness of the first roughness zone, as shown in Figure 3, the morphology of the texture structure formed on the second roughness zone can be the same as the morphology of the texture structure formed on the first roughness zone, but the size and/or distribution density of the texture structure on the second roughness zone are different from the size and/or distribution density of the texture structure formed on the first roughness zone. Alternatively, as shown in Figures 2, 4 and 5, the morphology of the texture structure formed on the above-mentioned first roughness zone 20 can also be different from the morphology of the texture structure formed on the second roughness zone 21. In this case, it is beneficial to form a texture structure with a corresponding morphology according to the requirements for the surface roughness of the first roughness zone 20 and the second roughness zone 21 in actual application scenarios, ensuring that the second doped semiconductor layer 18 can smoothly transition at the junction of the second region 13 and the first region 12.

Specifically, the morphology of the texture structure formed on the first roughness area and the second roughness area can be determined according to the surface roughness requirements of the first roughness area and the second roughness area in actual manufacturing and actual application scenarios, and is not specifically limited here.

For example, as shown in Figures 2 to 5, the texture structure formed on the second roughness zone 21 can be a ridge structure, and the extension direction of the ridge structure is parallel to the inclination direction of the first sub-region 15. The texture structure formed on the first roughness zone 20 can be a velvet structure. The morphology of the velvet structure formed on the first roughness zone 20 can refer to the description of the triangular prism-like structure mentioned above, and will not be repeated here. In this case, when other factors are the same, the ridge structure has a smaller degree of undulation than the velvet structure, which is beneficial to reducing the specific surface area of the second roughness zone 21, ensuring that the second roughness zone 21 has a smaller surface roughness, and further beneficial to improving the coating effect of the second doped semiconductor layer 18 on the second roughness zone 21. In addition, when the texture structure on the first roughness zone 20 is a velvet structure, a more mature velveting process can be used to form the texture structure on the first roughness zone 20, which is beneficial to reducing the manufacturing difficulty of the back contact battery and improving the manufacturing efficiency of the back contact battery.

In terms of size, the lengths of the first roughness region and the second roughness region included in the first subregion along the tilt direction of the first subregion, and the heights of the first roughness region and the second roughness region along the thickness direction of the semiconductor substrate can be determined according to the actual manufacturing process.

For example, along the inclined direction of the first sub-region, the length of the second roughness zone can be greater than 0 and less than or equal to 3 μm. For example, the length of the second roughness zone can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. In this case, if the length of the second roughness zone is within the above range, it can prevent the width of the groove bottom surface, which has a flat surface, from being smaller due to the larger length of the second roughness zone causing the side width of the groove structure to account for a larger proportion in the second region. This ensures that at least a majority of the second doped semiconductor layer is formed on a flat surface, thereby improving the field passivation effect of the second doped semiconductor layer on the corresponding region of the first surface of the semiconductor substrate.

For example, along the direction from the second surface to the first surface of the semiconductor substrate, the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure can be greater than or equal to 1 μm and less than or equal to 8 μm. For example, the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm, etc. In this case, it can be understood that when the width of the first roughness zone is a constant value along the direction from the first region to the second region, the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure is proportional to the slope of the first sub-region. Based on this, if the minimum distance from the boundary between the first roughness zone and the second roughness zone to the bottom of the groove structure is within the above range, it can prevent the slope of the first sub-region from being larger due to a larger minimum distance. In addition, it can also prevent the slope of the first sub-region from being smaller due to a smaller minimum distance. The effect of preventing the slope of the first sub-region from being larger or smaller can be referred to above and will not be repeated here.

In addition, the specific length of the first roughness zone along the inclination direction of the first sub-region and the height of the second roughness zone along the thickness direction of the semiconductor substrate can be determined according to the specific width of the first sub-region and the inclination rate of the first sub-region relative to the surface of the first region, which will not be repeated here.

For the second sub-region, as shown in FIG1 , FIG2 , FIG5 and FIG6 , the surface of the second sub-region 16 may be a plane, or a texture structure such as a ridge structure may be formed on the surface of the second sub-region.

It is worth noting that, compared to a surface with a textured structure, as shown in Figures 1, 2, 5, and 6, when the surface of the second sub-region 16 is planar, the surface of the second sub-region 16 is smoother and has a smaller specific surface area. Under certain conditions, the deposition thickness of a film layer is inversely proportional to the specific surface area of the surface on which it is deposited. Therefore, when the surface of the second sub-region 16 is planar, it is more conducive to increasing the thickness of the second doped semiconductor layer 18 formed on the second sub-region 16, thereby enhancing the field passivation effect of the second doped semiconductor layer 18 in the second sub-region 16, further reducing the carrier recombination rate in the second sub-region 16, and improving the photoelectric conversion efficiency of the back-contact cell.

As for the first doped semiconductor layer, in terms of material, the material of the first doped semiconductor layer may include at least one semiconductor material such as silicon, silicon germanium or germanium.

Preferably, the first doped semiconductor layer may include a doped crystalline silicon layer. In this case, compared to doped amorphous silicon layers, doped crystalline silicon layers have higher carrier transport properties. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the carrier recombination rate can be further reduced, which is conducive to improving the photoelectric conversion efficiency of the back-contact solar cell.

In terms of conductivity type, the conductivity type of the first doped semiconductor layer can be N-type, in which case the conductivity type of the second doped semiconductor layer is P-type; or the conductivity type of the first doped semiconductor layer can also be P-type, in which case the conductivity type of the second doped semiconductor layer is N-type.

In terms of the formation position, the first doped semiconductor layer can be directly formed on at least a portion of the first region on the first surface. Alternatively, as shown in FIG1 , the back-contact cell can further include a first passivation layer 22, which is located at least between the first doped semiconductor layer 17 and the first region 12. In this case, the first passivation layer 22 and the first doped semiconductor layer 17 can form a selective contact structure to chemically passivate the first region 12 on the first surface of the semiconductor substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on one side of the first surface and improving the photoelectric conversion efficiency of the back-contact cell.

The material of the first passivation layer can be determined based on the material of the first doped semiconductor layer. For example, if the first doped semiconductor layer comprises a doped crystalline silicon layer, the first passivation layer is a tunneling passivation layer. For another example, if the first doped semiconductor layer comprises a doped amorphous silicon layer, the first passivation layer comprises an intrinsic amorphous silicon layer. Furthermore, the present embodiments do not specifically limit the material of the first passivation layer.

In terms of the formation range, as shown in Figure 8, the first doped semiconductor layer 17 can be formed only on a portion of the first region 12. In addition, the above-mentioned back-contact battery also includes an intrinsic semiconductor layer 24. The intrinsic semiconductor layer 24 is formed on the portion of the first region 12 other than the first doped semiconductor layer 17 in a direction parallel to the first surface. The portion of the second doped semiconductor layer 18 corresponding to the first region 12 covers the portion of the intrinsic semiconductor layer 24 facing away from the semiconductor substrate 11. The intrinsic semiconductor layer 24 is used to electrically isolate the second doped semiconductor layer 18 from the first doped semiconductor layer 17. In this case, the first doped semiconductor layer 17 and the second doped semiconductor layer 18 are both formed on one side of the first surface of the semiconductor substrate 11, and the conductivity types of the two are opposite. Based on this, when the back-contact battery is in operation, the electrons and holes generated after the semiconductor substrate 11 absorbs photons move toward the first doped semiconductor layer 17 and the second doped semiconductor layer 18, respectively, and are collected and conducted by the two layers to form a photocurrent. Among them, since the intrinsic semiconductor layer 24 is non-conductive, the presence of the intrinsic semiconductor layer 24 can electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 18 of opposite conductivity types, inhibit leakage, further reduce the carrier recombination rate on the first side, and improve the photoelectric conversion efficiency of the back contact battery.

Among them, along the arrangement direction of the first region and the second region, the ratio of the width of the above-mentioned intrinsic semiconductor layer and the first doped semiconductor layer to the total width of the first region can be determined according to the extension width of the second doped semiconductor layer above the first region and the requirements for leakage prevention in the actual application scenario, as long as the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated by the intrinsic semiconductor layer. In addition, in the actual manufacturing process, the above-mentioned intrinsic semiconductor layer can be an integrated structure with the first doped semiconductor layer. At this time, the intrinsic semiconductor layer and the first doped semiconductor layer can be formed based on the same manufacturing material and through the same manufacturing steps to simplify the manufacturing process of the back contact battery and improve the manufacturing efficiency of the back contact battery. Alternatively, the intrinsic semiconductor layer can also be a non-integrated structure with the first doped semiconductor layer. At this time, the intrinsic semiconductor layer and the first doped semiconductor layer can be manufactured separately according to the requirements of the actual application scenario, thereby improving the applicability of the back contact battery provided by the embodiment of the present application in different application scenarios.

Secondly, when the back contact battery also includes an intrinsic semiconductor layer, the doping concentration of impurities in the first doped semiconductor layer can be determined based on the carrier collection ability of the first doped semiconductor layer in the actual application scenario, and no specific limitation is made here.

For example, when the back-contact cell further includes an intrinsic semiconductor layer, the impurity doping concentration in the first doped semiconductor layer can be greater than or equal to ^4E20cm3 and less than or equal to ^6E20cm3 . For example, the impurity doping concentration in the first doped semiconductor layer can be greater than or equal to 4E20cm3, ^4.2E20cm3 , ^4.5E20cm3 , ^4.8E20cm3 , ^5E20cm3 , ^5.2E20cm3 , ^5.5E20cm3 , ^5.8E20cm3 , or ^6E20cm3 , ^etc. In this case, as described above, the intrinsic semiconductor layer can electrically isolate the first doped semiconductor layer from the second doped semiconductor layer of opposite conductivity types. In this case, there is no need to reduce the impurity doping concentration in the first doped semiconductor layer to suppress leakage from the first doped semiconductor layer and the second doped semiconductor layer. Based on this, the impurity doping concentration in the first doped semiconductor layer is within the above-mentioned range, which can prevent the low impurity doping concentration therein from resulting in low conductivity and carrier collection ability. In addition, because the impurity doping concentration in the semiconductor material is limited by the solid concentration, the impurity doping concentration in the first doped semiconductor layer is within the above-mentioned range, which can also prevent the difficulty of impurity doping in the first doped semiconductor layer due to a high impurity doping concentration therein.

Alternatively, as shown in FIG1 , the first doped semiconductor layer 17 may also cover the first region 12. Furthermore, the back-contact cell further includes a second passivation layer 23, which is located between the second doped semiconductor layer 18 and the second region 13 and extends over a portion of the first region 12. The portion of the second doped semiconductor layer 18 corresponding to the first region 12 is located over the portion of the second passivation layer 23 corresponding to the first region 12. Using the above technical solution, the first doped semiconductor layer 17 can be formed on various portions of the first region 12, thereby increasing the formation range of the first doped semiconductor layer 17 and, in turn, the carrier collection range of the first doped semiconductor layer 17. Furthermore, the back-contact cell further includes a second passivation layer 23 between the second doped semiconductor layer 18 and the second region 13 and extending over a portion of the first region 12. This second passivation layer 23 can separate the first doped semiconductor layer 17 and the second doped semiconductor layer 18 of opposite conductivity types, further suppressing leakage while also providing another possible implementation solution for the back-contact cell structure, thereby improving the applicability of the back-contact cell provided by the embodiments of the present application in various application scenarios.

When the first doped semiconductor layer also covers the first region, the first doped semiconductor layer and the second doped semiconductor layer are separated by the second passivation layer. The material of the second passivation layer can be determined according to the material of the second doped semiconductor layer.

As for the doping concentration of impurities in the first doped semiconductor layer in this case, it can be determined according to the leakage prevention requirements between the first doped semiconductor layer and the second doped semiconductor layer in actual application scenarios.

For example, the doping concentration of impurities in the first doped semiconductor layer can be less than or equal to 6E19 cm ³ . For example, the doping concentration of impurities in the first doped semiconductor layer can be 6E16 cm ³ , 1E17 cm ³ , 5E17 cm ³ , 1E18 cm ³ , 5E18 cm ³ , 1E19 cm ³ , or 6E19 cm ³ . In this case, the doping concentration of impurities in the first doped semiconductor layer is relatively low, resulting in relatively weak conductivity, which helps further reduce the leakage current between the first doped semiconductor layer and the second doped semiconductor layer.

From the perspective of surface morphology, in the longitudinal section of the back-contact cell, as shown in FIG1 , the side edge of the first doped semiconductor layer 17 close to the second region 13 may be arranged perpendicular to the first surface.

Alternatively, as shown in FIG19 , the side edge of the first doped semiconductor layer 17 near the second region 13 may be a bevel. Furthermore, the height of the bevel gradually decreases along the direction from the first region 12 to the second region 13. In this case, the height variation of the side edge of the first doped semiconductor layer 17 near the second region 13 is reduced, and the second doped semiconductor layer 18 (which may also include a passivation film layer such as a second passivation layer 23) is better coated on the side edge of the first doped semiconductor layer 17 near the second region 13. This prevents unfilled gaps in the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13, which have a surface height difference. This further reduces the number of defects on the first side of the back-contact cell and improves the formation quality of the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13. This improves the field passivation effect of the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13, reduces the carrier recombination rate there, and improves the photoelectric conversion line efficiency of the back-contact cell. In the actual manufacturing process, the inclined surface may be formed by the etchant undercutting the sidewalls of the portion of the first doped semiconductor layer 17 that needs to be retained during the selective etching of the entire first doped semiconductor layer 17. Therefore, the height variation trend of the inclined surface can be determined based on the processing parameters of the selective etching and actual needs, and is not specifically limited here.

Alternatively, as shown in FIG20 , the side edge of the first doped semiconductor layer 17 near the second region 13 may also be bent inwardly of the first doped semiconductor layer 17. In this case, the side edge of the first doped semiconductor layer 17 near the second region 13 may also be a curved surface. In this case, compared to when the side edge of the first doped semiconductor layer 17 near the second region 13 is arranged perpendicular to the first surface, when the side edge of the first doped semiconductor layer 17 near the second region 13 is bent inwardly of the first doped semiconductor layer 17, the side edge of the first doped semiconductor layer 17 near the second region 13 has a larger side surface area, which is beneficial for enhancing the passivation contact area between the second passivation layer 23 or other film layers having a passivation effect and the side edge of the first doped semiconductor layer 17 near the second region 13. Secondly, the side edge of the first doped semiconductor layer 17 near the second region 13 is bent into the first doped semiconductor layer 17, which can also reduce the height variation of the side edge of the first doped semiconductor layer 17 near the second region 13, which is beneficial for the second doped semiconductor layer 18 (which may also include a second passivation layer 23 or other film layers with passivation effect) to better cover the side edge of the first doped semiconductor layer 17 near the second region 13, thereby improving the field passivation effect of the second doped semiconductor layer 18 at the boundary between the first region 12 and the second region 13, reducing the carrier recombination rate here, and helping to improve the photoelectric conversion line efficiency of the back contact battery.

As for the surface morphology of the side of the first doped semiconductor layer away from the semiconductor substrate, the side of the first doped semiconductor layer away from the semiconductor substrate can be a flat surface. Alternatively, as shown in FIG7 , a recessed structure 27 is provided in the portion of the first doped semiconductor layer 17 away from the semiconductor substrate 11 near the second region 13. In this case, the presence of the recessed structure 27 prevents the surface of the portion of the first doped semiconductor layer 17 near the second region 13 on the side away from the semiconductor substrate 11 from contacting the mask layer 26, but is instead exposed through the gap. This facilitates the portion of the second passivation layer 23 or other passivating film layer formed later that fills the gap to be in passivation contact with the first doped semiconductor layer 17, thereby enhancing the passivation effect of the portion of the first doped semiconductor layer 17 near the second region 13 on the side away from the semiconductor substrate 11. Specifically, in the actual manufacturing process, the recessed structure 27 can be formed by the etchant undercutting the top of the cross-section of the portion of the first doped semiconductor layer 17 that needs to be retained during the selective etching of the entire first doped semiconductor layer 17. Based on this, the shape and size of the recessed structure 27 can be determined according to the processing parameters of the selective etching and actual needs, and are not specifically limited here.

Regarding the second doped semiconductor layer, the material of the second doped semiconductor layer may include at least one semiconductor material such as silicon, silicon germanium, or germanium. Exemplarily, the second doped semiconductor layer includes a doped amorphous silicon layer and/or a doped microcrystalline silicon layer.

It should be noted that the "microcrystalline" in the material of the doped microcrystalline silicon layer is a limitation on the grain size of the silicon material. Specifically, the microcrystalline silicon material refers to a silicon material with a grain size of nanometer level.

In terms of formation location, the second doped semiconductor layer can be formed directly on the second region and extend above the first region. As shown in FIG1 , when the first doped semiconductor layer 17 overlies the first region 12, the portion of the second doped semiconductor layer 18 corresponding to the first region 12 is located above the portion of the first doped semiconductor layer 17 facing away from the semiconductor substrate 11. As shown in FIG8 , when the back-contact cell further includes the intrinsic semiconductor layer 24, the portion of the second doped semiconductor layer 18 corresponding to the first region 12 is at least located above the portion of the intrinsic semiconductor layer 24 facing away from the semiconductor substrate 11.

Alternatively, as shown in Figure 1, the above-mentioned back-contact battery may also include a second passivation layer 23, which is located between the second doped semiconductor layer 18 and the second region 13 and extends above part of the first region 12. The portion of the second doped semiconductor layer 18 corresponding to the first region 12 is located on the portion of the second passivation layer 23 corresponding to the first region 12. The material of the second passivation layer 23 can refer to the above and will not be repeated here. In this case, the second passivation layer 23 and the second doped semiconductor layer 18 can constitute a selective contact structure to achieve chemical passivation of at least the second region 13 on the first surface of the semiconductor substrate 11, and to achieve selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on one side of the first surface, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

It should be noted that when the first doped semiconductor layer is formed over the entire first region, as shown in FIG1 , the second doped semiconductor layer 18 extending above the first region 12 can be isolated from the first doped semiconductor layer 17 solely by the second passivation layer 23; alternatively, as shown in FIG9 , a mask layer 26 can be provided between the second doped semiconductor layer 18 extending above the first region 12 and the first doped semiconductor layer 17. In this case, the mask layer 26 not only includes the portion of the first doped semiconductor layer 17 located in the first region 12 during the selective etching of the entire first doped semiconductor layer 17, but also separates the second doped semiconductor layer 18 extending above the first region 12 from the first doped semiconductor layer 17 of opposite conductivity type, thereby reducing the risk of electrical leakage between the two. The material of the mask layer 26 can include any insulating material that has a protective effect on the first doped semiconductor layer 17.

In actual applications, as shown in FIG9 , each portion of the mask layer 26 may be in contact with the first doped semiconductor layer 17. Alternatively, as shown in FIG7 , a gap open toward the second region may be provided between the portion of the mask layer near the second region and the first doped semiconductor layer. In this case, the portion of the subsequently formed second passivation layer or other passivating film extending above the first region may also be filled in the gap, thereby increasing the contact area between the second passivation layer or other passivating film and the first doped semiconductor layer, improving the passivation effect, and thereby facilitating improved conversion efficiency of the back-contact cell.

The aforementioned gap may be formed by providing a recessed structure recessed into the mask layer in a portion near the second region on a side of the mask layer close to the semiconductor substrate. In this case, a gap is formed between the first doped semiconductor layer and the recessed structure. In this case, during the actual manufacturing process, the mask layer may experience structural loosening or hydrogen escape at its edges due to high-temperature operations such as laser processing. Consequently, during the selective etching of the first doped semiconductor layer, this portion may be susceptible to corrosion by the etchant, forming a recessed structure.

Alternatively, as shown in FIG7 , a recessed structure 27 recessed into the first doped semiconductor layer may be provided in a portion near the second region on a side of the first doped semiconductor layer facing away from the semiconductor substrate 11, with a gap formed between the mask layer and the recessed structure 27. In this case, the presence of the recessed structure 27 prevents the surface of the portion near the second region on the side of the first doped semiconductor layer facing away from the semiconductor substrate from contacting the mask layer, but is instead exposed through the gap. This facilitates passivation contact between the portion of a subsequently formed second passivation layer or other passivating film layer that fills the gap and the first doped semiconductor layer 17, thereby enhancing the passivation effect of the portion near the second region on the side of the first doped semiconductor layer facing away from the semiconductor substrate.

As for the size of the gap, it can be determined according to the specific etching conditions when selectively etching the first doped semiconductor layer and actual needs, and is not specifically limited here.

In terms of thickness, the thickness of each portion of the second passivation layer can be substantially the same. Alternatively, as shown in Figures 19 and 20, when a textured structure is formed on the bottom surface 19 of the groove structure 14, the thickness of the second passivation layer 23 at the bottom of the groove structure 14 can be less than the thickness at the second sub-region 16. In this case, the thickness of the second passivation layer 23 at the bottom of the groove structure 14 is smaller, which helps to make this portion have a lower tunneling resistance, resulting in a higher carrier collection efficiency for the second doped semiconductor layer 18. The second passivation layer 23 is thicker in the second sub-region 16, which helps to increase the passivation effect of this portion, and the second sub-region 16 is closer to the first region 12 on which the first doped semiconductor layer 17 is disposed. Based on this, when the second passivation layer 23 is thicker in the second sub-region 16, it helps to make the portion of the second passivation layer 23 in the second sub-region 16 have a higher isolation effect, further reducing the risk of leakage between the second doped semiconductor layer 18 and the first doped semiconductor layer 17.

In actual applications, the thickness of the second passivation layer at the bottom of the groove structure can be smaller than that at the second sub-region by differentiating the morphology of the texture structure formed on the bottom surface of the groove structure and the surface of the second sub-region. Alternatively, the second passivation layer can be formed with different thicknesses on the bottom surface of the groove structure and the surface of the second sub-region. The specific thicknesses of the portion of the second passivation layer corresponding to the bottom surface of the groove structure and the portion located on the second sub-region can be set according to actual needs and are not specifically limited here.

An embodiment of the present application provides a photovoltaic module, which includes multiple back-contact cells, which are electrically connected together in series and/or in parallel. For example, Figure 21 provides a schematic diagram of multiple back-contact cells electrically connected together. As shown in Figure 21, multiple back-contact cells are arranged in sequence along direction A to form a cell string, and multiple back-contact cells in the cell string are connected in series. Two or more cell strings are arranged in sequence along direction A to form a group of cell strings, and multiple groups of cell strings are arranged in sequence along direction B.

In the manufacturing process of the back-contact battery, after the bottom of the groove structure of the semiconductor substrate is textured, after the first doped semiconductor layer and the second doped semiconductor layer are formed, and after the transparent conductive layer 8 is formed, the semiconductor substrate needs to be cleaned to remove residues, stains, etc. remaining in the process. The cleaning generally adopts a wet process such as a chain process or a roller liquid process to clean the battery cell. During the cleaning process, a roller is used to transport the battery cell. The roller has teeth, and the surface of the semiconductor substrate that needs to be cleaned faces the roller. In this way, due to the weight of the semiconductor substrate itself, the pressure of the water film and/or the pressure of the drying roller, the teeth of the roller may extend into the interior of the groove structure and contact the pyramid at the bottom of the groove structure, the second doped semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer 8 arranged at the bottom of the groove, resulting in scratches on the pyramid at the bottom of the groove structure, the second doped semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer 8 arranged at the bottom of the groove, thereby affecting the performance of the back-contact battery.

In view of the above situation, in order to reduce the situation where the teeth on the roller scratch the surface of the battery cell and improve the yield of the battery cell, the present application also provides a back-contact battery, which can be used in the above-mentioned photovoltaic module.

The present application further provides a back-contact battery, which includes: a semiconductor substrate, the semiconductor substrate having a first surface and a second surface relative to each other, the first surface having a plurality of groove structures, the groove structures being recessed toward the second surface relative to the rest of the first surface, and the bottoms of the groove structures being pyramid-shaped velvet surfaces; a first doped semiconductor layer being arranged on a portion of the first surface other than the groove structures; a second doped semiconductor layer being arranged at the bottom of the groove structures; the second doped semiconductor layer having a conductivity type opposite to that of the first doped semiconductor layer; wherein, along the thickness direction of the semiconductor substrate, a surface of the second doped semiconductor layer at the pyramid top at the bottom of the groove facing away from the semiconductor substrate is at a distance h0 from a surface of the first doped semiconductor layer facing away from the semiconductor substrate, and 292nm≤h0≤15288nm.

Referring to FIG. 22 , a back-contact cell provided in one embodiment of the present application includes a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer, a transparent conductive layer 8 , a first passivation layer, a second passivation layer, a first electrode, and a second electrode. The semiconductor substrate has a first surface and a second surface facing each other. The first doped semiconductor layer and the second doped semiconductor layer are both disposed on the first surface of the semiconductor substrate.

In which, along a direction parallel to the first surface of the semiconductor substrate, a first doped semiconductor layer is formed on a partial area of the first surface of the semiconductor substrate. A plurality of groove structures are formed on the portion of the first surface of the semiconductor substrate exposed outside the first doped semiconductor layer. The groove structure is recessed toward the second surface relative to the rest of the first surface. That is, the groove structure is arranged lower than the rest of the first surface, and the first doped semiconductor layer is arranged on the portion of the first surface other than the groove structure. The above-mentioned second doped semiconductor layer is arranged at the bottom of the groove structure, that is, the second doped semiconductor layer covers the bottom surface of the groove structure. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, so as to collect and conduct electrons and holes respectively, which is conducive to the formation of photocurrent. The presence of the above-mentioned groove structure can at least partially stagger the electrode structures that are electrically in contact with the first doped semiconductor layer and the second doped semiconductor layer respectively along the thickness direction of the semiconductor substrate, which is conducive to suppressing leakage.

Furthermore, the groove bottom of the groove structure presents a pyramid-shaped velvet surface with an uneven texture. This pyramid-shaped velvet surface increases the surface area of the groove bottom, improving the light trapping effect of the groove structure and allowing more light to be refracted through the groove bottom into the semiconductor substrate and utilized by the semiconductor substrate. In addition, the portion of the second doped semiconductor layer located on the bottom of the groove structure, the side of the second doped semiconductor layer formed on the bottom of the groove through deposition and other processes that is away from the semiconductor substrate will also fluctuate along with the undulations of the groove bottom, that is, the side of the portion of the second doped semiconductor layer formed on the bottom of the groove that is away from the semiconductor substrate also has roughly the same undulating morphology as the groove bottom of the groove structure. Therefore, when a pyramid-shaped velvet surface is formed on the bottom of the groove structure, the side of the second doped semiconductor layer formed on the bottom of the groove that is away from the semiconductor substrate also has corresponding uneven features, which is beneficial to increasing the surface area of the second doped semiconductor layer formed on the bottom of the groove that is away from the semiconductor substrate, and further beneficial to increasing the contact area between the second doped semiconductor layer and the corresponding electrode, and beneficial to reducing the contact resistance between the second doped semiconductor layer and the corresponding electrode, and further improving the working performance of the back contact battery.

In some embodiments, as shown in FIG22 , along the thickness direction of the semiconductor substrate, a distance between a surface of the second doped semiconductor layer at the pyramid tip disposed at the bottom of the trench facing away from the semiconductor substrate and a surface of the first doped semiconductor layer facing away from the semiconductor substrate is h0, where 292 nm ≤ h0 ≤ 15288 nm. In other words, along the direction from the second surface to the first surface of the semiconductor substrate, a minimum distance between a surface of the second doped semiconductor layer disposed at the bottom of the trench facing away from the semiconductor substrate and a surface of the first doped semiconductor layer facing away from the semiconductor substrate is h0, where 292 nm ≤ h0 ≤ 15288 nm. For example, h0 can be 292 nm, 500 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm, 15000 nm, or 15288 nm.

In the preparation process of the back contact battery, referring to FIG23, after the second doped semiconductor layer is made, the semiconductor substrate formed with the second doped semiconductor layer needs to be cleaned. During the cleaning, the semiconductor substrate is conveyed forward by a roller. On the one hand, if h0 is too small, the teeth 7a of the roller will easily contact and scratch the second doped semiconductor layer at the bottom of the groove after extending into the groove structure. The second doped semiconductor layer at the bottom of the groove is used for passivation and carrier collection. If the second doped semiconductor layer is scratched or damaged, it will greatly affect the passivation effect and the effect of collecting carriers, thereby affecting the photoelectric conversion of the back contact battery. On the other hand, if h0 is too large, the depth of the groove structure needs to be set deeper, that is, more parts of the semiconductor substrate need to be removed, which will reduce the overall mechanical strength of the cell. In addition, the back-contact cell uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If too much of the semiconductor substrate is removed, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of the semiconductor substrate will be reduced. In this way, the number of photogenerated carriers, that is, holes and electrons, generated by irradiation on the semiconductor substrate will be reduced, thereby reducing the photoelectric conversion rate of the back-contact cell. Taking the above two aspects into consideration, in the back-contact cell provided by the embodiment of the present invention, h0 is set within a reasonable range to reduce the situation where the teeth 7a of the roller extend into the groove structure and scratch the second doped semiconductor layer at the bottom of the groove, while ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back-contact cell will not be reduced, and the cell has sufficient mechanical strength.

In some embodiments, 2992 nm ≤ h0 ≤ 8288 nm. Exemplarily, h0 is 2992 nm, 3500 nm, 4500 nm, 5500 nm, 6500 nm, 7500 nm, or 8288 nm. This further prevents the teeth 7 a of the roller from extending into the groove structure and scratching the second doped semiconductor layer at the bottom of the groove, further ensuring high light absorption of the semiconductor substrate, preventing a decrease in the photoelectric conversion efficiency of the back-contact solar cell, and providing sufficient mechanical strength for the solar cell.

In actual application, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate. The semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

It is understood that the first surface of the semiconductor substrate corresponds to the backlight-repelling surface of the back-contact cell, and the second surface of the semiconductor substrate corresponds to the light-facing surface of the back-contact cell. Based on this, the light-facing surface of the semiconductor substrate can be flat, or it can also be a velvet surface. Because velvet traps light, a velvet surface on the light-facing surface of the semiconductor substrate can reduce its reflectivity, allowing more light to be refracted from the light-facing surface into the semiconductor substrate for absorption and utilization, thereby improving the photoelectric conversion efficiency of the back-contact cell.

The second doped semiconductor layer may be provided only at the bottom of the groove structure, or may be provided at the bottom of the groove structure and the sidewalls of the groove structure.

In some embodiments, as shown in FIG22 , the second doped semiconductor layer is further disposed on the sidewalls of the recess structure and extends above the portion of the first doped semiconductor layer facing away from the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the distance between the surface of the second doped semiconductor layer at the pyramid tip at the bottom of the recess facing away from the semiconductor substrate and the surface of the second doped semiconductor layer overlying the first doped semiconductor layer facing away from the semiconductor substrate is h1, where 312 nm ≤ h1 ≤ 15348 nm.

In the case where the second doped semiconductor layer extends to the side of the first doped semiconductor layer facing away from the semiconductor substrate, the second doped semiconductor layer disposed on the side of the first doped semiconductor layer facing away from the semiconductor substrate can increase the distance between the teeth of the roller and the second doped semiconductor layer at the top of the pyramid covering the bottom of the groove. To prevent the teeth of the roller from scratching the second doped semiconductor layer at the bottom of the groove, h1 can be set within the range of 312 nm ≤ h1 ≤ 15348 nm. Exemplarily, h1 is 312 nm, 500 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm, or 15348 nm, etc. This can further prevent the teeth 7 a of the roller from extending into the groove structure and scratching the second doped semiconductor layer at the bottom of the groove.

In some examples, 3012 nm ≤ h1 ≤ 8348 nm.

As shown in Figures 22 and 23, along the thickness direction of the semiconductor substrate, the distance between the pyramid tip at the bottom of the recessed structure of the semiconductor substrate and the surface of the first doped semiconductor layer facing away from the semiconductor substrate is h2, 330 nm ≤ h2 ≤ 15300 nm. In other words, along the direction from the second surface to the first surface of the semiconductor substrate, the minimum distance between the pyramid tip at the bottom of the recessed structure and the surface of the first doped semiconductor layer facing away from the semiconductor substrate is h2, 330 nm ≤ h2 ≤ 15300 nm.

In the process of manufacturing back-contact cells, after forming the first doped semiconductor layer and texturing the bottom of the groove structure, and before forming the second doped semiconductor layer, the semiconductor substrate needs to be cleaned to remove the texturing liquid remaining on the surface. Considering that if h2 is too small, during the cleaning process, after the teeth 7a of the roller extend into the groove structure, they will contact the pyramid at the bottom of the groove structure, and then scratch the top of the pyramid at the bottom of the groove structure. If the top of the pyramid is scratched, the number of defects will increase, and when the second doped semiconductor layer is subsequently deposited to form the second doped semiconductor layer, it will affect the film formation quality of the second doped semiconductor layer, and then affect the passivation and carrier collection function of the second doped semiconductor layer. Therefore, damaging the top of the pyramid will have a greater impact on the subsequent process; if h2 is too large, the depth of the groove structure needs to be set deeper, that is, more parts of the semiconductor substrate need to be removed, which will reduce the overall mechanical strength of the battery cell, and the back contact battery uses light to separate electrons and holes on the semiconductor substrate to generate electricity. If too much of the semiconductor substrate is removed, the transmission path of light in the semiconductor substrate will be reduced, and the light absorption rate of light in the semiconductor substrate will be reduced. In this way, the number of photogenerated carriers, i.e., holes and electrons, generated by irradiation on the semiconductor substrate will be reduced, thereby reducing the photoelectric conversion rate of the back contact battery. In view of the above situation, in this technical solution, h2 is set within the range of 330nm to 15300nm, thereby further preventing the teeth 7a of the roller from extending into the groove structure and scratching the pyramid at the bottom of the groove structure during the cleaning process, and further ensuring that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the back contact battery will not decrease, and the battery cell has sufficient mechanical strength.

Illustratively, h2 is 330 nm, 500 nm, 800 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm, 15000 nm or 15300 nm.

In some examples, 3030 nm ≤ h2 ≤ 8300 nm.

In some specific embodiments, as shown in FIG22 , along the thickness direction of the semiconductor substrate, the distance from the pyramid tip at the bottom of the trench to the surface of the first surface excluding the recessed structure is h3, where 300 nm ≤ h3 ≤ 15000 nm. In this case, other film layers formed on the semiconductor substrate are not considered, and only the distance from the pyramid tip to the surface of the first surface excluding the recessed structure is considered.

In this case, the depth of the groove structure is maintained within a reasonable range, which ensures that the light absorption rate of the semiconductor substrate and the photoelectric conversion rate of the back-contact battery will not decrease, and the battery cell has sufficient mechanical strength; at the same time, it also ensures that after other film layers are formed on the semiconductor substrate, when the semiconductor substrate is cleaned, the teeth 7a of the roller extend into the groove structure and will not contact the pyramid at the bottom of the groove structure, or will not contact the film layer deposited on the pyramid at the bottom of the groove structure, such as the second doped semiconductor layer, to ensure that the teeth 7a of the roller will not scratch the pyramid at the bottom of the groove structure, or will not scratch the film layer formed on the pyramid at the bottom of the groove structure.

Illustratively, h3 is 300 nm, 500 nm, 800 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm, 10000 nm, 11000 nm, 12000 nm, 13000 nm, 14000 nm or 15000 nm.

In some examples, 3000 nm ≤ h3 ≤ 8000 nm.

In some specific embodiments, the base size of the pyramid at the bottom of the trench of the semiconductor substrate ranges from 500 nm to 7000 nm, and the height ranges from 300 nm to 6000 nm. The dimensions of the pyramid include the base size and the height size. The base size of the pyramid refers to the maximum dimension of the base of the pyramid along a direction parallel to the first surface, which can be the diagonal dimension of the base or the length of the side of the base. The height of the pyramid refers to the dimension of the top of the pyramid extending from the top of the pyramid along a direction perpendicular to the first surface to the base.

It is understood that, given a constant distance between the base of the pyramid and the surface of the first surface other than the groove structure, or to other film layers formed on the semiconductor substrate, the larger the size of the pyramid, the smaller the distance between the top of the pyramid and the surface of the first surface other than the groove structure, or to other film layers formed on the semiconductor substrate. That is, in the actual manufacture of back-contact cells, the distance between the top of the pyramid and the surface of the first surface other than the groove structure, or to other film layers formed on the semiconductor substrate, is closely related to the size of the pyramid. Considering that if the size of the pyramid is too large, the teeth 7a of the roller will easily contact the pyramid at the bottom of the groove structure or the film layers deposited on the pyramid after extending into the groove structure during the cleaning process, thereby scratching the top of the pyramid at the bottom of the groove structure or the film layers deposited on the pyramid. Therefore, when designing back-contact cells, it is necessary to match the size of the pyramid with the distance between the top of the pyramid and the surface of the first surface other than the groove structure, or to other film layers formed on the semiconductor substrate, to prevent the roller from scratching the top of the pyramid or the film layers deposited on the pyramid during the cleaning process. Furthermore, if the size of the pyramid is too small, it will reduce the surface area of the groove bottom of the groove structure, thereby affecting the light trapping effect of the groove structure and the surface area of the film layer deposited at the groove bottom. Therefore, in this technical solution, on the one hand, the base size and height of the pyramid at the groove bottom of the semiconductor substrate are set within a reasonable range, so that the groove bottom of the groove structure can maintain the light trapping effect while the height of the pyramid at the groove bottom is appropriately reduced, thereby making the pyramid tip at the groove bottom further away from, for example, the surface of the first doped semiconductor layer facing away from the semiconductor substrate. In this way, it can further ensure that other film layers disposed at the pyramid tip at the groove bottom, such as but not limited to the second doped semiconductor layer or the transparent conductive layer 8, are also further away from the surface of the first doped semiconductor layer facing away from the semiconductor substrate, thereby preventing the teeth 7a of the roller 7 from extending into the groove structure and scratching the second doped semiconductor layer or the transparent conductive layer 8 at the groove bottom. Furthermore, during the cleaning process of the semiconductor substrate after the texturing process is completed, the teeth 7a of the roller 7 can be prevented from contacting the pyramid at the groove bottom of the groove structure after extending into the groove structure, thereby ensuring that the teeth 7a of the roller 7 do not scratch the pyramid tip at the groove bottom of the groove structure.

Exemplarily, the base size of the pyramid is 500 nm, 800 nm, 1000 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, 2200 nm, 2500 nm, 2800 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 5500 nm, 6000 nm, 6500 nm or 7000 nm, etc. In addition, the tower height is 300 nm, 500 nm, 800 nm, 1000 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, 2200 nm, 2500 nm, 2800 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 5500 nm or 6000 nm, etc.

In some examples, the base size of the pyramid ranges from 1000 nm to 3500 nm, and the height of the pyramid ranges from 300 nm to 6000 nm.

As shown in FIG22 , the spacing between adjacent first doped semiconductor layers is L, and 200 μm ≤ L ≤ 800 μm. That is, the width of the area not covered by the first doped semiconductor layer is L, or in other words, the maximum width between the sidewalls of the groove structure is L. On the one hand, if the spacing L between adjacent first doped semiconductor layers is too small, the width of the second doped semiconductor layer will be too small, that is, the area of the semiconductor substrate covered by the second doped semiconductor layer will be small, and the size of the area of the semiconductor substrate covered by the second doped semiconductor layer will affect the number of carriers collected by the second doped semiconductor layer. If the spacing L between adjacent first doped semiconductor layers is too large, that is, the area of the semiconductor substrate covered by the second doped semiconductor layer is large, the area of the semiconductor substrate covered by the first doped semiconductor layer will be small, and the size of the area of the semiconductor substrate covered by the first doped semiconductor layer will affect the number of carriers collected by the first doped semiconductor layer. Therefore, when setting the spacing between adjacent first doped semiconductor layers, it is necessary to comprehensively consider the area of the semiconductor substrate covered by the first doped semiconductor layer and the area of the semiconductor substrate covered by the second doped semiconductor layer. On the other hand, the cross-section of the roller teeth 7a is generally conical. The wider the notch of the groove structure, the longer the roller teeth 7a extend into the groove structure. Therefore, if the spacing L between adjacent first doped semiconductor layers is too large, the notch of the groove structure is wider, the longer the roller teeth 7a extend into the groove structure, and the smaller the distance between the roller teeth 7a and the pyramid tip at the bottom of the groove, the more likely it is to scratch the pyramid at the bottom of the groove structure, the second doped semiconductor layer arranged at the bottom of the groove, or the transparent conductive layer 8 arranged at the bottom of the groove. Therefore, in order to prevent the roller from scratching the pyramid tip or the film layer deposited on the pyramid during the cleaning process, when designing a back-contact battery, it is necessary to match the spacing L between adjacent first doped semiconductor layers with the distance from the pyramid tip to the surface of the first surface other than the groove structure, or to other film layers formed on the semiconductor substrate, so as to prevent the roller from scratching the pyramid tip at the bottom of the groove or the film layer deposited on the pyramid tip during the cleaning process.

In view of the above, in this technical solution, the spacing L between adjacent first doped semiconductor layers is set within a reasonable range. This allows the roller teeth 7a to extend into the groove structure, where the side walls of the groove structure can abut against the tapered teeth 7a, limiting the length of the roller teeth 7a extending into the groove structure. This appropriately increases the distance between the roller teeth 7a and the pyramidal apex at the groove bottom. This further ensures that the distance between the second doped semiconductor layer at the pyramidal apex at the groove bottom and the surface of the first doped semiconductor layer facing away from the semiconductor substrate is appropriately increased, further preventing the roller teeth 7a from extending into the groove structure and scratching the second doped semiconductor layer at the groove bottom. Furthermore, setting the spacing L between adjacent first doped semiconductor layers within a reasonable range prevents the roller teeth 7a from extending into the groove structure and scratching the pyramid at the groove bottom, the second doped semiconductor layer at the groove bottom, or the transparent conductive layer 8 at the groove bottom. This also prevents the width of the second doped semiconductor layer from being too small, which could affect carrier collection by the second doped semiconductor layer.

For example, the distance L between adjacent first doped semiconductor layers may be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm or 800 μm.

In some examples, 350 μm ≤ L ≤ 600 μm.

In some embodiments, 0.36≤h0/L≤76.4. It can be understood that if the depth of the groove structure is deeper, the length of the roller teeth 7a allowed to extend into the groove structure is greater, while ensuring that the pyramid tip at the bottom of the groove, the second doped semiconductor layer located on the pyramid tip at the bottom of the groove, and the transparent conductive layer 8 located on the pyramid tip at the bottom of the groove are not scratched. In this way, when the depth of the groove structure is deeper, the groove width of the groove structure can be appropriately increased, and the groove width of the groove structure is roughly equal to the spacing L between adjacent first doped semiconductor layers. Based on this, the embodiment of the present application sets the ratio of h0/L within a reasonable range to ensure that the roller teeth 7a extend into the groove structure without scratching the pyramid tip at the bottom of the groove, the second doped semiconductor layer located on the pyramid tip at the bottom of the groove, and the transparent conductive layer 8 located on the pyramid tip at the bottom of the groove, and to increase the width of the second doped semiconductor layer, thereby improving the carrier collection efficiency of the second doped semiconductor layer.

Illustratively, h0/L can be 0.36, 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, or 76.4.

As shown in Figure 22, the width of the groove bottom of the groove structure is L1, and 170μm≤L1≤790μm. It can be understood that the spacing L between adjacent first doped semiconductor layers is related to the width L1 of the groove bottom of the groove structure. As the width L1 of the groove bottom of the groove structure increases, the spacing L between adjacent first doped semiconductor layers increases. When designing a back-contact cell, on the one hand, if the width L1 of the groove bottom of the groove structure is too small, the width of the second doped semiconductor layer will be too small, that is, the area covered by the second doped semiconductor layer on the semiconductor substrate will be small, affecting the number of carriers collected by the second doped semiconductor layer. On the other hand, if the width L1 of the groove bottom of the groove structure is too wide, that is, the area covered by the second doped semiconductor layer on the semiconductor substrate will be large, then the area covered by the first doped semiconductor layer on the semiconductor substrate will be small. The size of the area covered by the first doped semiconductor layer on the semiconductor substrate affects the number of carriers collected by the first doped semiconductor layer. Therefore, when setting the width of the groove bottom of the groove structure, it is necessary to comprehensively consider the area covered by the first doped semiconductor layer and the area covered by the second doped semiconductor layer on the semiconductor substrate. Furthermore, if the width L1 of the groove bottom is too wide, the groove opening of the groove structure will also be wider, making it easier for the teeth 7a of the roller to extend into the groove structure through the groove opening, thereby more easily scratching the pyramid at the bottom of the groove structure, the second doped semiconductor layer disposed at the bottom of the groove, or the transparent conductive layer 8 disposed at the bottom of the groove. In view of the above, in this technical solution, the width L1 of the groove bottom of the groove structure is set within a reasonable range to prevent the teeth 7a of the roller from extending into the groove structure and scratching the pyramid at the bottom of the groove structure, the second doped semiconductor layer disposed at the bottom of the groove, or the transparent conductive layer 8 disposed at the bottom of the groove. At the same time, the width of the second doped semiconductor layer is prevented from being too small, thereby affecting the collection of carriers by the second doped semiconductor layer.

Exemplarily, the width L1 of the bottom of the groove structure is 170μm, 180μm, 200μm, 230μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, 520μm, 550μm, 580μm, 600μm, 620μm, 650μm, 690μm, 700μm, 720μm, 750μm or 790μm, etc. Optionally, the width L1 of the bottom of the groove structure is 320μm to 590μm.

In some embodiments, as shown in FIG22 , the sidewalls of the groove structure include an inclined surface that is inclined away from the second surface in a direction away from the middle region of the groove bottom. It should be noted that in this embodiment, the inclined surface extends in a substantially straight line from the bottom to the top of the inclined surface, and the inclined surface is not concave toward the second surface. This configuration facilitates a smoother transition in height from the lower surface of the groove bottom to the higher surface region for forming the first doped semiconductor layer on the first surface of the semiconductor substrate. This facilitates better coverage of the second doped semiconductor layer on the sidewalls of the groove structure during formation, preventing unfilled gaps in the second doped semiconductor layer at the sidewalls of the groove structure with a surface height difference. This reduces the number of defects on the first surface side of the back-contact cell and improves the quality of the second doped semiconductor layer formed at the sidewalls of the groove structure, thereby improving the field passivation effect of the second doped semiconductor layer formed at the sidewalls of the groove structure, reducing the carrier recombination rate there, and improving the photoelectric conversion efficiency of the back-contact cell.

Among them, the width of the inclined surface is L2, 5μm≤L2≤15μm. Since the inclined surface is set higher than the bottom of the groove, if the width L2 of the inclined surface is too wide, the teeth 7a of the roller will easily scratch the inclined surface or the film layer deposited on the inclined surface after extending into the groove structure; if the width L2 of the inclined surface is too narrow, then under the condition that the height difference and height change trend of the inclined surface remain unchanged, the inclination angle of the inclined surface will be large, and in the process of forming the second doped semiconductor layer, a gap will easily form between the second doped semiconductor layer and the inclined surface, which will increase the number of defects in the second doped semiconductor layer formed at the inclined surface. In view of the above situation, in this technical solution, the width L2 of the inclined surface is set within a reasonable range to prevent the teeth 7a of the roller from scratching the inclined surface or the film layer deposited on the inclined surface after extending into the groove structure, while ensuring that the formation quality of the second doped semiconductor layer at the side wall of the groove structure is improved, and the carrier collection efficiency of the second doped semiconductor layer is improved.

Illustratively, the width L2 of the inclined surface is 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm.

In some embodiments, the sidewall of the groove structure further includes a platform, which is located on the side of the inclined surface away from the bottom of the groove. The sidewall of the groove structure also includes a vertical surface extending in a direction perpendicular to the first surface, and the vertical surface is located on the side of the platform away from the semiconductor substrate. The surface of the above-mentioned platform is a polished surface, and the platform can be arranged parallel to the second surface or inclined relative to the second surface. Using this technical solution, the arrangement of the platform can increase the spacing L between adjacent first doped semiconductor layers, which is conducive to increasing the width of the second doped semiconductor layer, thereby increasing the carrier collection efficiency of the second doped semiconductor layer.

Along the width direction of the groove structure, the width of the platform can be greater than or equal to 100nm and less than or equal to 600nm. For example, the width of the platform can be 100nm, 200nm, 300nm, 400nm, 500nm or 600nm, etc. In the actual manufacturing process, after the first doped semiconductor layer is formed as a whole layer on the first surface, it is necessary to pattern the first doped semiconductor layer under the masking action of the mask layer. Then, under the masking action of the mask layer, the portion of the semiconductor substrate exposed outside the mask layer is etched to form the above-mentioned groove structure. In which, when etching the semiconductor substrate, the etchant can not only etch the portion of the semiconductor substrate exposed outside the masking action along the thickness direction of the semiconductor substrate, but also has a certain etching effect on the first doped semiconductor layer and the portion of the semiconductor substrate located below the edge area of the mask layer along the direction parallel to the second surface, thereby forming the above-mentioned groove structure under the partial isotropic etching action of the etchant, realizing a platform in the groove structure, and lower than the first surface. The formation of the above-mentioned platform is conducive to a smoother transition trend of the second doped semiconductor layer in the area where the inclined surface and the vertical surface meet, preventing the second doped semiconductor layer from having defects such as gaps in the area where the inclined surface and the vertical surface meet, i.e., the platform area, thereby improving the formation quality of the area where the inclined surface and the vertical surface meet, i.e., the platform area.

In some embodiments, as shown in Figures 22 and 24-26, the inclined surface 6b includes a pyramid-shaped textured surface, and the size of the pyramids on the inclined surface 6b is larger than the size of the pyramids at the groove bottom. In this case, it can be understood that, within the same range, the number of pyramids formed on the surface of the area with larger pyramids is relatively small, which helps reduce the surface roughness of this area. Based on this, when the size of the pyramids formed on the inclined surface 6b is larger than the pyramids formed at the groove bottom of the groove structure, it helps reduce the roughness of the inclined surface 6b, improves the formation quality of the second doped semiconductor layer on the inclined surface 6b, and enhances the field passivation effect of the second doped semiconductor layer on the inclined surface 6b.

It should be noted that the pyramids at the bottom of the groove are uniform in size, while the pyramids at the inclined surface 6b are non-uniform in size. The pyramids located on the inclined surface 6b include those located on the inclined surface and at the intersection of the non-inclined surface and the groove bottom, that is, the pyramids located on the inclined surface away from the groove bottom, and also include the pyramids located at the intersection of the inclined surface and the groove bottom.

It can be understood that, as shown in Figures 24 to 26, a portion of the inclined surface 6b forms a complete pyramid-shaped velvet surface, and a portion of the inclined surface 6b can also form an incomplete pyramid-shaped velvet surface, and the incomplete pyramid-shaped velvet surface can be, for example, a triangular prism-like structure. Based on this, when other factors are the same, the surface area of the triangular prism-like structure is larger than that of the plane morphology. Therefore, when at least part of the surface of the inclined surface 6b forms a triangular prism-like structure, it is beneficial for the inclined surface 6b to have a good light trapping effect, further improving the utilization rate of light by the back contact battery. In addition, when other factors are the same, the surface of the triangular prism-like structure has lower roughness than the surface of the pyramid-shaped velvet morphology, and its surface is relatively smooth, which is beneficial to improving the coating effect of the second doped semiconductor layer on the inclined surface 6b. Of course, in addition to the complete pyramid-shaped velvet surface and the incomplete pyramid-shaped velvet surface, other structures may also be formed on the inclined surface 6b, such as a raised strip structure. A structure without a pyramid tip and in the shape of a strip can be considered as a raised strip structure. This application does not limit the size of the raised strip structure.

In some embodiments, as shown in FIG24 , the pyramid located on the inclined surface 6b and at the intersection of the non-inclined surface and the groove bottom has a tower height ranging from 50 nm to 3000 nm, and a tower base size ranging from 2000 nm to 8000 nm. The pyramid on the inclined surface 6b includes a first side surface and a second side surface, wherein the first side surface is substantially parallel to the inclined surface 6b, and the second side surface intersects the inclined surface 6b. The tower height of the pyramid on the inclined surface 6b refers to the distance a between the top of the pyramid and a plane passing through the bottom of the second side surface and parallel to the second surface, as shown in the vertical dotted line portion in FIG24 ; the tower base size of the pyramid on the inclined surface 6b refers to the distance b from the bottom of the second side surface extending to the first side surface in a direction parallel to the second surface, as shown in the horizontal dotted line portion in FIG24 .

Considering that if the size of the pyramid on the inclined surface 6b is too large, the teeth 7a of the roller will easily contact the pyramid on the inclined surface 6b after extending into the groove structure during the cleaning process, thereby scratching the pyramid on the inclined surface 6b or the film layer deposited on the pyramid on the inclined surface; therefore, when designing a back contact battery, it is necessary to make the size of the pyramid located on the inclined surface 6b and at the intersection of the non-inclined surface and the groove bottom consistent with the width L2 of the inclined surface, the width L1 of the groove bottom of the groove structure, and the surface of the second doped semiconductor layer located at the top of the pyramid at the groove bottom along the thickness direction of the semiconductor substrate away from the semiconductor substrate. The distance h0 between the surface of the first doped semiconductor layer and the surface facing away from the semiconductor substrate, the distance h2 between the pyramid tip at the bottom of the groove structure of the semiconductor substrate and the surface facing away from the semiconductor substrate, and the distance h3 between the pyramid tip at the bottom of the groove of the semiconductor substrate and the surface of the first surface other than the groove structure need to match. That is, the size of the pyramid located on the inclined surface 6b and at the intersection of the non-inclined surface and the groove bottom needs to match the above L1, L2, h0, h2 and h3 to prevent the roller from scratching the pyramid tip on the inclined surface 6b or the film layer deposited on the pyramid during the cleaning process. For example, if h3 is large, the size of the pyramid on the inclined surface 6b can be set larger; if h3 is small, the size of the pyramid on the inclined surface 6b can be set smaller; if L1 is large, the size of the pyramid on the inclined surface 6b can be set smaller.

On the other hand, if the size of the pyramids on the inclined surface is too small, it will not be conducive to reducing the surface roughness of the inclined surface 6b, which may affect the quality of the second doped semiconductor layer formed on the inclined surface 6b. In view of the above situation, the height and base size of the pyramids on the inclined surface 6b are set within a reasonable range. This can prevent the roller teeth 7a from contacting the pyramids on the inclined surface 6b after extending into the groove structure, thereby ensuring that the roller teeth 7a will not scratch the pyramids on the inclined surface 6b or the film deposited on the pyramids. At the same time, it is beneficial to reduce the surface roughness of the inclined surface 6b and improve the quality of the second doped semiconductor layer formed on the inclined surface 6b.

For example, the height of the pyramid located on the inclined surface 6b and at the intersection of the non-inclined surface 6b and the groove bottom is 50 nm, 100 nm, 150 nm, 200 nm, 500 nm, 800 nm, 1000 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, 2200 nm, 2500 nm, 2800 nm, or 3000 nm. The base size of the pyramid located on the inclined surface 6b and at the intersection of the non-inclined surface 6b and the groove bottom is 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 5500 nm, 6000 nm, 6500 nm, 7000 nm, 7500 nm, or 8000 nm.

In some examples, the pyramid located on the inclined surface 6 b and at the junction of the non-inclined surface 6 b and the groove bottom has a height of 100 nm to 2000 nm, and a base of 100 nm to 2000 nm.

In other embodiments, as shown in FIG26 , the intersection of the inclined surface 6 b and the groove bottom is located on the side of the dotted line near the first doped semiconductor layer, and is located on the inclined surface 6 b. The pyramid located at the intersection of the inclined surface 6 b and the groove bottom has a height ranging from 1000 nm to 9000 nm, and a base size ranging from 1000 nm to 9000 nm. In this case, compared to the non-intersection of the inclined surface 6 b and the groove bottom, the intersection of the inclined surface 6 b and the groove bottom is farther away from the tooth 7 a extending into the groove structure. Therefore, the size of the pyramid located at the intersection of the inclined surface 6 b and the groove bottom can be appropriately increased so that the size of the pyramid located at the intersection of the inclined surface 6 b and the groove bottom is larger than the size of the pyramid located on the inclined surface 6 b. This helps reduce the roughness at the intersection of the inclined surface 6 b and the groove bottom, thereby improving the formation quality of the second doped semiconductor layer at this location.

Exemplarily, the height of the pyramid located on the inclined surface 6b and at the junction of the inclined surface 6b and the groove bottom is 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm, 3000nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm, 7000nm, 7500nm, 8000nm, 8500nm or 9000nm. The tower base size is 1000nm, 1200nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 5500nm, 6000nm, 6500nm, 7000nm, 7500nm, 8000nm, 8500nm or 9000nm.

In some examples, the pyramid located on the inclined surface 6 b and at the junction of the inclined surface 6 b and the groove bottom has a height of 1500 nm to 5000 nm, and a base of 1500 nm to 5000 nm.

As shown in FIG27 , in some other embodiments, the pyramid tip at the bottom of the groove of the semiconductor substrate 1 is arc-shaped. In this case, compared to a pyramid with a pointed tip, the height of the pyramid with an arc-shaped tip is appropriately reduced, thereby increasing the distance between the pyramid tip at the bottom of the groove and the surface of the first doped semiconductor layer facing away from the semiconductor substrate. This also increases the distance between the second doped semiconductor layer located at the pyramid tip at the bottom of the groove and the surface of the first doped semiconductor layer facing away from the semiconductor substrate. This further reduces the probability of the roller teeth 7a extending into the groove structure and scratching the pyramid at the bottom of the groove structure, the second doped semiconductor layer disposed at the bottom of the groove, or the transparent conductive layer 8 disposed at the bottom of the groove. Furthermore, the arc-shaped pyramid tip at the bottom of the semiconductor substrate can appropriately increase the contact area between the pyramid tip and the second doped semiconductor layer, thereby improving the deposition quality of the second doped semiconductor layer at the pyramid tip, reducing defects in the formation of the second doped semiconductor layer, and enhancing the passivation effect.

In some embodiments, the curvature radius of the arc-shaped pyramid tip is 70 nm to 150 nm.

In some embodiments, the arc angle of the arc-shaped pyramid spire ranges from 30° to 150°.

It is understandable that, on the one hand, if the curvature radius and curvature range of the arc-shaped pyramid spire are too large, some of the light irradiated by the arc-shaped pyramid spire cannot be refracted into the semiconductor substrate and utilized, affecting the light trapping effect of the groove structure. On the other hand, if the curvature radius and curvature range of the arc-shaped pyramid spire are too small, the purpose of appropriately reducing the pyramid height cannot be achieved. Based on this, setting the curvature radius and curvature range of the arc-shaped pyramid spire within an appropriate range can both appropriately reduce the pyramid height and thus reduce the risk of scratches on the pyramid at the groove bottom, while ensuring the light trapping effect of the groove structure.

For example, the radius of curvature of the top of the pyramid with an arc-shaped tip is 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, and may be 100 nm to 110 nm. The curvature range of the top of the pyramid with an arc-shaped tip is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, or 150°.

In some embodiments, the surface of the portion of the semiconductor substrate other than the groove structure may be a polished surface or may be formed with a textured structure. In the case where the surface of the portion of the semiconductor substrate other than the groove structure is formed with a textured structure, the textured structure is square, specifically may be roughly in the shape of a tower base, which may be convexly arranged along the direction from the second surface to the first surface, or may be concavely arranged along the direction from the second surface to the first surface. In this case, it is beneficial to increase the specific surface area of the portion of the semiconductor substrate other than the groove structure. Secondly, the side of the first doped semiconductor layer formed on the portion of the semiconductor substrate other than the groove structure that is away from the semiconductor substrate has roughly the same undulating features as the surface of the portion of the semiconductor substrate other than the groove structure. Therefore, in the case where the portion of the semiconductor substrate other than the groove structure has a larger specific surface area, it is also beneficial to increase the specific surface area of the first doped semiconductor layer on the side away from the semiconductor substrate, thereby increasing the contact area between the first doped semiconductor layer and the corresponding electrode, and reducing the contact resistance. At the same time, compared with the pyramid-shaped texture structure, when the texture structure on the surface of the semiconductor substrate other than the groove structure is square, it is beneficial to make the surface of the semiconductor substrate other than the groove structure have a relatively low surface roughness, which is beneficial to improving the formation quality of the above-mentioned first doped semiconductor layer and ensuring that the first doped semiconductor layer has a higher carrier collection ability and passivation effect.

In terms of conductivity type, the conductivity type of the first doped semiconductor layer can be N-type, in which case the conductivity type of the second doped semiconductor layer is P-type; or the conductivity type of the first doped semiconductor layer can also be N-type, in which case the conductivity type of the second doped semiconductor layer is N-type.

In addition, the material of the first doped semiconductor layer and the second doped semiconductor layer can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. Taking the example that the material of the first doped semiconductor layer and the second doped semiconductor layer are both silicon (Si), the second doped semiconductor layer can include one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. In this case, especially when the second doped semiconductor layer is doped amorphous silicon, the second doped semiconductor layer is more susceptible to scratches. The second doped semiconductor layer is used for passivation and carrier collection, and scratches significantly affect the passivation and carrier collection effects. However, when the second doped semiconductor layer is doped polycrystalline silicon, such as when the back-contact cell is a TBC (Tunnel Oxide Passivated Contact) cell, the second doped semiconductor layer has a passivation layer on the side facing away from the semiconductor substrate, which can perform a passivation function. In this case, scratches on the second doped semiconductor layer have less impact on the passivation performance of the solar cell. Furthermore, the isolation trench of the TBC cell contains insulating material, which can passivate the isolation trench. Therefore, scratches on the insulating material also have a relatively small impact on the performance of the solar cell. In view of the above, when the second doped semiconductor layer comprises one or more of doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon, it is necessary to prevent the second doped semiconductor layer located at the bottom of the groove structure from being scratched by the teeth 7a of the roller extending into the groove structure to ensure that the performance of the back-contact cell is not affected.

In addition, the first doped semiconductor layer can be doped polycrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the back contact battery. Of course, the first doped semiconductor layer can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The first doped semiconductor layer can be additionally formed on the semiconductor substrate through deposition technology, or it can be formed in the semiconductor substrate through diffusion, ion implantation, etc.

In other embodiments, the back-contact cell further includes a transparent conductive layer 8, which is disposed on the side of the first and second doped semiconductor layers that is distal from the semiconductor substrate. Transparent conductive layer 8 is provided with an opening 8a extending through its thickness, disconnecting transparent conductive layer 8 located on the first doped semiconductor layer from transparent conductive layer 8 located on the second doped semiconductor layer. Transparent conductive layer 8 has high electrical conductivity, enabling timely conduction of collected carriers and reducing the carrier recombination rate. Furthermore, transparent conductive layer 8 can reduce the contact resistance between the first and second doped semiconductor layers and the electrodes.

As shown in FIG8 , the orthographic projection of the opening 8a extending through the transparent conductive layer 8 on the first surface is located within the orthographic projection of the portion of the second doped semiconductor layer extending onto the first doped semiconductor layer on the first surface. This prevents the second doped semiconductor layer from being electrically connected to the first doped semiconductor layer through the transparent conductive layer 8, thereby preventing leakage. Furthermore, this ensures that carriers collected in the portion of the second doped semiconductor layer within the recessed structure can be transferred through the transparent conductive layer 8 to the electrode in contact with the first doped semiconductor layer, thereby improving the conversion efficiency of the battery.

Alternatively, as shown in FIG29 , along the width direction of opening 8a, the orthographic projection of opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the second doped semiconductor layer extending onto the first doped semiconductor layer, and also partially overlaps with the orthographic projection of the portion of the first doped semiconductor layer not covered by the second doped semiconductor layer. This arrangement can also prevent the second doped semiconductor layer from being electrically connected to the first doped semiconductor layer through transparent conductive layer 8, thereby preventing leakage.

Alternatively, as shown in FIG30 , along the width direction of opening 8a, the orthographic projection of opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the second doped semiconductor layer extending onto the first doped semiconductor layer, and also partially overlaps with the orthographic projection of the portion of the second doped semiconductor layer covering inclined surface 6b or the bottom of the groove. This arrangement can also prevent the second doped semiconductor layer from being electrically connected to the first doped semiconductor layer through transparent conductive layer 8, thereby preventing leakage.

Alternatively, as shown in FIG31 , along the width direction of opening 8a, the orthographic projection of opening 8a on the first surface partially overlaps with the orthographic projection of the portion of the first doped semiconductor layer not covered by the second doped semiconductor layer, and also partially overlaps with the orthographic projection of the portion of the second doped semiconductor layer covering the inclined surface 6b or the groove bottom. This arrangement increases the width of opening 8a and the distance between the transparent conductive layers 8 on either side of opening 8a, further preventing the second doped semiconductor layer from contacting and causing recombination with the first doped semiconductor layer.

In the above technical solution, along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer 8 disposed on the pyramid apex at the bottom of the groove and facing away from the semiconductor substrate and the surface of the transparent conductive layer 8 disposed on the first doped semiconductor layer and facing away from the semiconductor substrate is greater than or equal to 316 nm and less than or equal to 15385 nm. Here, "the transparent conductive layer 8 disposed on the first doped semiconductor layer" can refer to being disposed only on the first doped semiconductor layer or being disposed in the overlapping region of the first doped semiconductor layer and the second doped semiconductor layer. In this case, after forming the transparent conductive layer 8, if the distance between the surface of the transparent conductive layer 8 disposed on the pyramid apex at the bottom of the groove and facing away from the semiconductor substrate and the surface of the transparent conductive layer 8 disposed on the first doped semiconductor layer and facing away from the semiconductor substrate is too small, then during the cleaning process, the teeth 7a of the roller, after extending into the groove structure, can easily contact the transparent conductive layer 8 on the pyramid apex at the bottom of the groove structure and scratch the transparent conductive layer 8 on the pyramid apex. Therefore, when designing a back-contact battery, it is necessary to match the distance between the surface of the transparent conductive layer 8 on the pyramid top at the bottom of the groove facing away from the semiconductor substrate and the surface of the transparent conductive layer 8 on the first doped semiconductor layer facing away from the semiconductor substrate, the distance h1 between the surface of the second doped semiconductor layer on the pyramid top at the bottom of the groove facing away from the semiconductor substrate and the surface of the second doped semiconductor layer covering the first doped semiconductor layer facing away from the semiconductor substrate, and the spacing L between adjacent first doped semiconductor layers, so as to ensure that during the cleaning process of the semiconductor substrate, the teeth 7a of the roller will not contact the transparent conductive layer 8 at the bottom of the groove structure after extending into the groove structure, thereby preventing the teeth 7a of the roller from scratching the transparent conductive layer 8 on the pyramid top at the bottom of the groove structure.

Exemplarily, the distance between the surface of the transparent conductive layer 8 at the top of the pyramid at the bottom of the groove and the surface of the transparent conductive layer 8 on the first doped semiconductor layer facing away from the semiconductor substrate is 316nm, 1000nm, 2000nm, 3000nm, 4000nm, 5000nm, 6000nm, 7000nm, 8000nm, 9000nm, 10000nm, 11000nm, 12000nm, 13000nm, 14000nm, 15000nm or 15385nm, optionally, it can be 3016nm to 8385nm.

In addition, the material of the transparent conductive layer 8 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

In some embodiments, the thickness of the second doped semiconductor layer at the bottom of the groove structure is less than the thickness of the second doped semiconductor layer at the sidewalls of the groove structure and/or overlying the first doped semiconductor layer. With this arrangement, the thickness of the second doped semiconductor layer overlying the first doped semiconductor layer is greater. When the second doped semiconductor layer overlying the first doped semiconductor layer supports the roller, the teeth 7a on the roller can be further away from the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer 8 disposed on the second doped semiconductor layer. Furthermore, the thickness of the second doped semiconductor layer at the bottom of the groove structure is less, which can further increase the distance between the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer 8 disposed on the second doped semiconductor layer. In summary, when the thickness of the second doped semiconductor layer at the bottom of the groove structure is less than the thickness of the second doped semiconductor layer overlying the first doped semiconductor layer, the distance between the teeth 7a on the roller and the second doped semiconductor layer at the bottom of the groove structure or the transparent conductive layer disposed on the second doped semiconductor layer is further increased, further reducing the possibility that the teeth 7a of the roller extend into the groove structure and scratch the second doped semiconductor layer at the bottom of the groove or the transparent conductive layer 8 disposed on the second doped semiconductor layer.

In each of the above-mentioned embodiments, the back-contact cell may further include a passivation layer and an anti-reflection layer disposed on the second surface. The second-surface passivation layer is located between the second surface of the semiconductor substrate and the anti-reflection layer. The second-surface passivation layer serves to passivate surface defects in the semiconductor substrate and reduce recombination. For example, it can passivate silicon-oxygen dangling bonds on the front surface of the crystalline silicon substrate layer through field passivation or chemical bonding. The anti-reflection layer serves to block light reflected from the top surface of the crystalline silicon by regulating the material and thickness of the anti-reflection layer. The material type of the second-surface passivation layer is not particularly limited, and includes, for example, but is not limited to, a-Si, polycrystalline silicon, microcrystalline silicon, silicon oxide, etc. The material of the anti-reflection layer includes, but is not limited to, silicon nitride.

The embodiments of the present application also provide the following three specific embodiments to specifically illustrate the working performance of the back contact battery of the embodiments of the present application.

Example 1

In the back contact cell provided in Example 1, the first doped semiconductor layer is a P-type doped polysilicon layer, and a tunneling oxide layer is formed between the first doped semiconductor layer and the semiconductor substrate. A pyramid-shaped structure is formed on the bottom surface of the groove structure. A triangular prism-shaped structure is formed on the first roughness area in the first sub-region of the side surface of the groove structure, and a ridgeline structure is formed on the second roughness area. The surface of the second sub-region of the side surface of the groove structure is flat. The second doped semiconductor layer is an N-type doped amorphous silicon layer, and the back contact cell also includes an intrinsic amorphous silicon layer located on the second area and extending above a portion of the first area, and the N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer.

In terms of size, the ratio between the width of the bottom surface of the groove structure and the total width of the second area is 97%. The height of the pyramid-shaped velvet structure formed on the bottom surface of the groove is 1.5μm, the top angle of the pyramid-shaped velvet structure is 75°, and the average height from the top of the pyramid-shaped velvet structure to the surface of the first area is 8um. The length of the longer edge of the triangular prism-like structure formed on the first roughness area is 7 times the length of the shorter edge, and the width of the first roughness area is 0.1% of the total width of the second area. In addition, the vertical height from the top of the pyramid-shaped velvet structure formed on the bottom surface of the groove to the junction of the first roughness area and the second roughness area is 5μm. The length of the hypotenuse from the junction of the second roughness area and the first roughness area to the edge of the second sub-area is 2.5μm. The average width of the second sub-area is 200nm. And the surface height difference between the second sub-area and the first area is 20nm.

Example 2

The structure of the back-contact battery provided in Example 2 is the same as that of the back-contact battery provided in Example 1, except that the ratio of the width of the first roughness zone included in the first sub-region to the total width of the second region is different from the corresponding ratio in the back-contact battery provided in Example 1. Specifically, in the back-contact battery provided in Example 2, the ratio of the width of the first roughness zone included in the first sub-region to the total width of the second region is 0.3%.

Example 3

The structure of the back-contact cell provided in Example 3 is identical to that of the back-contact cell provided in Example 1, except that the ratio of the vertical height from the top of the pyramid-shaped velvet structure formed on the groove bottom surface to the boundary between the first roughness region and the second roughness region is different from that in the back-contact cell provided in Example 1. In the back-contact cell provided in Example 3, the vertical height from the top of the pyramid-shaped velvet structure formed on the groove bottom surface to the boundary between the first roughness region and the second roughness region is 3 μm.

Table 1 Test parameters of back contact cells provided in Examples 1 to 3

The data in Table 1 demonstrate that, with other factors remaining the same, increasing the ratio of the width of the first roughness region included in the first subregion to the total width of the second region from 0.1% to 0.3% in Example 2 reduces the slope of the first subregion relative to the surface of the first region, improving the quality of the second doped semiconductor layer formed on the first subregion, thereby slightly increasing the conversion efficiency and short-circuit current density of the back-contact cell. Furthermore, reducing the vertical height from the top of the pyramidal velvet structure formed on the bottom surface of the groove in Example 3 to the boundary between the first and second roughness regions from 5 μm to 3 μm reduces the proportion of the first roughness region with greater surface roughness in the first subregion, thereby increasing the proportion of the second doped semiconductor layer formed on the second roughness region with less surface roughness, thereby improving the quality of the second doped semiconductor layer formed on the first subregion, thereby slightly increasing the conversion efficiency, short-circuit current density, and fill factor of the back-contact cell.

In a second aspect, embodiments of the present application provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 10 to 18. Specifically, the method for manufacturing a back-contact battery includes the following steps:

First, a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface facing each other. The first surface has first and second regions alternately arranged. The material of the semiconductor substrate and the extent of the first and second regions on one side of the first surface are described above and are not further described here.

Next, as shown in FIG. 13 and FIG. 14 , a first doped semiconductor layer 17 is formed on at least the first region 12 of the first surface.

Among them, the material of the above-mentioned first doped semiconductor layer and the range of its formation on the first region can refer to the above. In the actual manufacturing process, the above-mentioned formation of at least the first doped semiconductor layer on the first region of the first surface may include the steps of: as shown in Figure 10, forming a whole layer of intrinsic semiconductor material layer 25 on the first surface. Next, as shown in Figure 12, the portion of the intrinsic semiconductor material layer 25 located on at least a portion of the first region 12 is selectively doped to form a first doped semiconductor layer 17 on the portion of the intrinsic semiconductor material layer 25 located on at least a portion of the first region 12. Next, a mask layer 26 is formed covering the first region 12. Then, as shown in Figure 14, under the masking action of the mask layer 26, the portion of the intrinsic semiconductor material layer located on the second region 13 is removed.

In actual applications, chemical vapor deposition or other processes can be used to form a layer of intrinsic semiconductor material disposed entirely on one side of the first surface. Subsequently, the portion of the intrinsic semiconductor layer located on at least a portion of the first region can be doped under the masking action of a corresponding mask layer or mask plate. Specifically, when the first doped semiconductor layer in the manufactured back-contact battery covers the first region, the mask layer or mask plate used for the selective doping described above needs to cover the portion of the intrinsic semiconductor material layer located on the second region. Under the masking action of the mask layer or mask plate, the portion of the intrinsic semiconductor material layer located on the first region is doped to form the first doped semiconductor layer on the first region. Alternatively, as shown in FIG12 , when the first doped semiconductor layer 17 in the manufactured back-contact cell is formed only on a portion of the first region 12, the selectively applied mask layer or reticle needs to cover not only the portion of the intrinsic semiconductor material layer 25 located on the second region 13, but also the portion of the intrinsic semiconductor material layer 25 located on a portion of the first region 12. Under the masking action of the mask layer or reticle, the portion of the intrinsic semiconductor material layer 25 located on the portion of the first region 12 is doped, so that the doped portion of the intrinsic semiconductor material layer 25 located on the first region 12 forms the first doped semiconductor layer 17, and the undoped portion of the intrinsic semiconductor material layer 25 located on the first region 12 forms the intrinsic semiconductor layer 24 (see FIG13 ). After at least the first doped semiconductor layer 17 is formed according to the above method, a mask layer 26 covering the first region 12 can be formed by deposition and photolithography. The material of the mask layer 26 can be silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbide, or intrinsic silicon. It is understood that when the first doped semiconductor layer 17 covers the first region 12, the mask layer 26 covering the first region 12 is located on the side of the first doped semiconductor layer 17 facing away from the semiconductor substrate 11. When the first doped semiconductor layer 17 is located only on a portion of the first region 12 and the back-contact cell includes an intrinsic semiconductor layer 24, the mask layer 26 covering the first region 12 is located on the side of the first doped semiconductor layer 17 and the intrinsic semiconductor layer 24 facing away from the semiconductor substrate 11. Next, as shown in FIG14 , an etching method such as laser etching or a wet chemical process is used to remove the portion of the intrinsic semiconductor material layer located on the second region 13 under the masking action of the mask layer 26.

It should be noted that, as shown in FIG11 , in addition to forming the first doped semiconductor layer 17 by the aforementioned selective doping method, it is also possible to form the first doped semiconductor layer 17 by performing a doping treatment on each portion of the intrinsic semiconductor material layer 25 after forming the entire intrinsic semiconductor material layer 25. Then, as shown in FIG14 , at least the portion of the first doped semiconductor layer 17 located on the second region 13 is removed under the masking action of a corresponding mask layer or reticle.

In addition, when the back contact battery also includes the above-mentioned first passivation layer, after providing a semiconductor substrate and before forming at least a first doped semiconductor layer on the first area having the first surface, the manufacturing method of the back contact battery also includes the steps of: forming a first passivation layer 22 on the first area 12 as shown in Figure 10.

Specifically, before forming the first doped semiconductor layer, a deposition and etching process may be used to form the first passivation layer only on the first region. Alternatively, as shown in FIG10 , before forming the first doped semiconductor layer 17 , a deposition process may be used to form the entire first passivation layer 22 disposed on the first surface. Then, as shown in FIG14 , the portion of the intrinsic semiconductor material layer located above the second region 13 is removed under the masking action of the mask layer 26 . Subsequently, a corresponding etching process may be used under the masking action of the mask layer 26 to remove the portion of the first passivation layer 22 located above the second region 13 .

Next, as shown in Figure 16, the portion of semiconductor substrate 11 corresponding to second region 13 is selectively etched, causing the surface of second region 13 to be lower than the surface of first region 12 along the direction from the second surface to the first surface, thereby forming recess structure 14. Along the arrangement direction of first and second regions 12, 13, the side surface of recess structure 14 has continuously distributed first sub-regions 15 and second sub-regions 16, with second sub-region 16 adjacent to first region 12. The surface of first sub-region 15 is inclined relative to the surface of the first region, and the cross-sectional area of the portion of first sub-region 15 of recess structure 14 gradually increases in a direction away from the first surface. The surface of second sub-region 16 is planar.

The size information and surface morphology information of the groove bottom surface, the first sub-region, and the second sub-region of the groove structure can be referred to above and will not be repeated here. In the actual manufacturing process, as shown in Figure 15, under the masking action of the mask layer 26, after removing the portion of the intrinsic semiconductor material layer located on the second region 13, the portion of the semiconductor substrate 11 corresponding to the second region 13 can be etched using a wet chemical process under the masking action of the mask layer 26 to make the surface of the second region 13 lower than the surface of the first region 12 along the direction from the second surface to the first surface, thereby forming the groove structure 14.

It should be noted that after removing the portion of the intrinsic semiconductor material layer located on the second region and before forming the groove structure, a wet chemical process or the like can be used to polish the portion of the semiconductor substrate corresponding to the second region. After the polishing process, the surface of the second region is lower than the surface of the first region. And after the polishing process, the height difference between the surface of the second region and the surface of the first region will affect the inclination rate of the first sub-region relative to the surface of the first region in the side of the groove structure formed subsequently (the greater the height difference between the surface of the second region and the surface of the first region after the polishing process, the greater the inclination rate of the surface of the first sub-region relative to the surface of the first region). Therefore, the degree of polishing can be determined based on the inclination rate of the surface of the first sub-region relative to the surface of the first region in the actual application scenario.

In addition, a wet chemical process is used to etch the portion of the semiconductor substrate corresponding to the second area, so that the surface of the second area is lower than the surface of the first area along the direction from the second surface to the first surface. The etching conditions such as the etching time for forming the groove structure will affect the height difference between the second sub-area and the first area in the side of the groove structure formed, as well as the depth of the groove structure. Therefore, the etching parameters of the wet chemical process can be determined according to the height difference between the second sub-area and the first area, as well as the depth of the groove structure in the actual application scenario, and no specific limitation is made here.

Furthermore, when a velvet structure is formed on the bottom surface of the groove structure and the surface of at least a portion of the first sub-region in the manufactured back-contact battery, when etching the portion of the semiconductor substrate corresponding to the second region so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface, after the groove structure is formed, and before forming the second doped semiconductor layer covering the second region and extending to above a portion of the first region, the manufacturing method of the above-mentioned back-contact battery further includes the steps of: as shown in FIG15 , performing a velvet treatment on the bottom surface 19 of the groove structure 14 and at least a portion of the first sub-region 15. The morphology of the velvet structure formed on the bottom surface 19 of the groove and at least a portion of the first sub-region 15 after the velvet treatment can be referred to the above. Secondly, the embodiments of the present application do not specifically limit the processing conditions of the velvet treatment.

In addition, as described above, the mask layer used to remove the portion of the intrinsic semiconductor material layer (or the intrinsic semiconductor material layer and the second passivation layer) located on the second region can be removed by a wet chemical process, etc., after forming the groove structure (or texturing treatment) and before forming the second doped semiconductor layer 18, as shown in FIG16 . Alternatively, the mask layer can be retained.

18 , a second doped semiconductor layer 18 is formed covering the second region 13 and extending over a portion of the first region 12. The second doped semiconductor layer 18 and the first doped semiconductor layer 17 have opposite conductivity types.

In the actual manufacturing process, as shown in FIG17 , chemical vapor deposition and doping processes can be used to form a whole layer of the second doped semiconductor layer 18 arranged on one side of the first surface. Then, as shown in FIG18 , laser etching and other processes are used, and under the masking action of the corresponding mask layer or mask plate, the portion of the second doped semiconductor layer 18 located above at least a portion of the first doped semiconductor layer 17 is removed. In addition, if the mask layer 26 covering the first region 12 is retained after the groove structure 14 is formed (or the texturing treatment) and before the second doped semiconductor layer 18 is formed, it is also necessary to remove the portion of the mask layer 26 covering at least a portion of the first doped semiconductor layer 17, so that the first doped semiconductor layer 17 is electrically connected to the corresponding electrode.

In which, when the back contact battery also includes the above-mentioned second passivation layer, after etching the portion of the semiconductor substrate corresponding to the second area so as to make the surface of the second area lower than the surface of the first area along the direction from the second surface to the first surface to form a groove structure, and before forming a second doped semiconductor layer covering the second area and extending to above part of the first area, the manufacturing method of the above-mentioned back contact battery also includes the steps of: as shown in Figure 17, forming a second passivation layer 23 covering the second area 13 and extending to above part of the first area 12.

Specifically, before forming the second doped semiconductor layer, a deposition and etching process may be used to form a second passivation layer that only covers the second region and extends over a portion of the first region. Alternatively, as shown in FIG17 , before forming the first doped semiconductor layer 17 , a deposition process may be used to form a second passivation layer 23 disposed entirely on the first surface. Then, as shown in FIG18 , the portion of the second doped semiconductor layer 18 located above at least a portion of the first doped semiconductor layer 17 is removed under the masking action of a corresponding mask layer or reticle. Subsequently, a corresponding etching process is used under the masking action of the mask layer or reticle to remove the portion of the second passivation layer 23 located above at least a portion of the first doped semiconductor layer 17.

The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims (36)

A back contact battery, comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; the first surface having alternating first and second regions; along a direction from the second surface to the first surface, a surface of the second region is lower than a surface of the first region, thereby forming a groove structure; along an arrangement direction of the first and second regions, a side surface of the groove structure has continuously distributed first and second sub-regions, with the second sub-region being adjacent to the first region; a surface of the first sub-region is inclined relative to a surface of the first region, and a cross-sectional area of a portion of the first sub-region of the groove structure gradually increases in a direction away from the first surface; and a surface of the second sub-region is planar; a first doped semiconductor layer located on at least a portion of the first region; and a second doped semiconductor layer located on the second region and extending to above a portion of the first region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. The back-contact battery according to claim 1, characterized in that, along the arrangement direction of the first region and the second region, the ratio of the width of the groove bottom surface of the groove structure to the total width of the second region is greater than or equal to 50% and less than or equal to 99.9%; and/or Along the arrangement direction of the first region and the second region, a ratio of a width of the first sub-region to a total width of the second region is greater than or equal to 0.1% and less than or equal to 5%; and/or, Along the arrangement direction of the first region and the second region, the width of the second sub-region is greater than or equal to 100 nm and less than or equal to 600 nm; and/or, A height difference between a surface of the second sub-region and a surface of the first region is greater than or equal to 5 nm and less than or equal to 40 nm. The back contact battery according to claim 1, characterized in that a texture structure is formed on the bottom surface of the groove structure; and/or, A texture structure is formed on the surface of the first sub-region; and/or, The surface of the second sub-region is arranged parallel to the surface of the first region; and/or, A texture structure is formed on the surface of the first region; the texture structure on the surface of the first region has a square shape on a side facing away from the semiconductor substrate. The back-contact battery according to claim 1 is characterized in that a texture structure is formed on the surface of the first sub-region; along the arrangement direction of the first region and the second region, the first sub-region has a first roughness zone and a second roughness zone, and the second roughness zone is close to the second sub-region; the surface roughness of the second roughness zone is less than the surface roughness of the first roughness zone. The back contact battery according to claim 4 is characterized in that the morphology of the texture structure formed on the first roughness area is different from the morphology of the texture structure formed on the second roughness area. The back contact battery according to claim 4, characterized in that the texture structure formed on the second roughness area is a ridge structure; the extension direction of the ridge structure is parallel to the inclination direction of the first sub-area; The texture structure formed on the first roughness area is a suede structure. The back contact battery according to claim 4, characterized in that, along the inclined direction of the first sub-region, the length of the second roughness zone is greater than 0 and less than or equal to 3 μm; and/or Along the direction from the second surface to the first surface of the semiconductor substrate, a minimum distance from a boundary between the first roughness area and the second roughness area to the bottom of the groove structure is greater than or equal to 1 μm and less than or equal to 8 μm. The back-contact battery according to claim 1 is characterized in that, when texture structures are formed on the surface of the first sub-region and on the bottom surface of the groove structure, the morphology of the texture structure formed on the surface of the first sub-region is different from the morphology of the texture structure formed on the bottom surface of the groove structure. The back-contact battery according to claim 8, characterized in that a longitudinal section of at least a portion of the surface of the first sub-region is serrated; and/or, The texture structure formed on at least part of the surface of the first sub-region is a triangular prism-like structure; and/or, The texture structure formed on the bottom surface of the groove structure is a pyramid-shaped velvet structure. The back-contact cell according to claim 1, further comprising a first passivation layer, wherein the first passivation layer is located at least between the first doped semiconductor layer and the first region; and/or The back-contact battery also includes a second passivation layer, which is located between the second doped semiconductor layer and the second region and extends above a portion of the first region; the portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second passivation layer corresponding to the first region. The back-contact battery according to claim 1, characterized in that the back-contact battery further comprises an intrinsic semiconductor layer; the intrinsic semiconductor layer is formed on a portion of the first region other than the first doped semiconductor layer in a direction parallel to the first surface; a portion of the second doped semiconductor layer corresponding to the first region covers a portion of the intrinsic semiconductor layer facing away from the semiconductor substrate, and the intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer; or, The first doped semiconductor layer covers the first region, and the doping concentration of impurities in the first doped semiconductor layer is less than or equal to ^6E19cm3 ; the back-contact battery also includes a second passivation layer, which is located between the second doped semiconductor layer and the second region and extends above a portion of the first region; the portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second passivation layer corresponding to the first region. The back-contact cell according to claim 11, wherein, when the back-contact cell further comprises the intrinsic semiconductor layer, the doping concentration of impurities in the first doped semiconductor layer is greater than or equal to 4E20 cm ³ and less than or equal to 6E20 cm ³ . The back contact cell according to any one of claims 1 to 12, characterized in that the first doped semiconductor layer comprises a doped crystalline silicon layer; The conductivity type of the first doped semiconductor layer is N-type, and the conductivity type of the second doped semiconductor layer is P-type; and/or, The second doped semiconductor layer includes a doped amorphous silicon layer and/or a doped microcrystalline silicon layer. The back-contact battery according to claim 1 is characterized in that a mask layer is provided between the second doped semiconductor layer extending above the first region and the first doped semiconductor layer, and a gap open toward the second region is provided between a portion of the mask layer close to the second region and the first doped semiconductor layer. The back-contact battery according to claim 1, characterized in that, in a longitudinal section of the back-contact battery, the side edge of the first doped semiconductor layer close to the second region is bent inwardly toward the first doped semiconductor layer. The back-contact battery according to claim 1 is characterized in that, on a side of the first doped semiconductor layer away from the semiconductor substrate, a portion close to the second region is provided with a recessed structure recessed into the first doped semiconductor layer. The back-contact battery according to claim 1 is characterized in that the side edge of the first doped semiconductor layer close to the second region is inclined; and the height of the inclined surface gradually decreases along the direction from the first region to the second region. The back-contact cell according to claim 10, further comprising a first passivation layer, wherein the first passivation layer is at least located between the first doped semiconductor layer and the first region; The back-contact cell further includes a second passivation layer, the second passivation layer being located between the second doped semiconductor layer and the second region and extending over a portion of the first region; a portion of the second doped semiconductor layer corresponding to the first region being located on a portion of the second passivation layer corresponding to the first region; A texture structure is formed on the bottom surface of the groove structure, and a square structure is formed on the surface of the first region. In the second passivation layer and the second doping layer, the sum of the thicknesses of the second passivation layer and the second doping layer located at the bottom of the groove structure is less than the sum of the thicknesses of the second passivation layer and the second doping layer located in the second sub-region. The back contact battery according to claim 3 is characterized in that, when a texture structure is formed on the bottom surface of the groove structure and a texture structure is formed on the surface of the first sub-region, the size of the texture structure formed on the surface of the first sub-region is larger than the texture structure formed on the bottom surface of the groove structure. The back contact battery according to claim 1 is characterized in that the distance between the bottom surface of the groove structure and the surface of the first area of the first surface is greater than 5 μm. The back-contact battery according to claim 1 is characterized in that the bottom of the groove structure is a pyramid-shaped velvet surface, and along the thickness direction of the semiconductor substrate, the distance between the surface of the second doped semiconductor layer away from the semiconductor substrate at the top of the pyramid at the bottom of the groove and the surface of the first doped semiconductor layer away from the semiconductor substrate is h0, 292nm≤h0≤15288nm. According to the back-contact battery according to claim 1, the bottom of the groove structure has a pyramid-shaped velvet surface, and along the thickness direction of the semiconductor substrate, the distance between the surface of the second doped semiconductor layer at the top of the pyramid at the bottom of the groove structure facing away from the semiconductor substrate and the surface of the second doped semiconductor layer covering the first doped semiconductor layer facing away from the semiconductor substrate is h1, 312nm≤h1≤15348nm. The back-contact battery according to claim 1 is characterized in that the bottom of the groove structure is a pyramid-shaped velvet surface, and along the thickness direction of the semiconductor substrate, the distance between the pyramid top of the groove structure bottom of the semiconductor substrate and the surface of the first doped semiconductor layer away from the semiconductor substrate is h2, 330nm≤h2≤15300nm. The back-contact battery according to claim 1 is characterized in that the bottom of the groove structure is a pyramid-shaped velvet surface, and along the thickness direction of the semiconductor substrate, the distance from the pyramid top of the bottom of the groove structure of the semiconductor substrate to the surface of the first surface other than the groove structure is h3, 300nm≤h3≤15000nm. The back contact battery according to claim 1 is characterized in that the bottom of the groove structure is a pyramid-shaped velvet surface, the base size of the pyramid at the bottom of the groove of the semiconductor substrate ranges from 500nm to 7000nm, and the tower height ranges from 300nm to 6000nm. The back contact battery according to claim 1 is characterized in that the spacing between adjacent first doped semiconductor layers is L, 200 μm ≤ L ≤ 800 μm; and/or the width of the groove bottom of the groove structure is L1, 170 μm ≤ L1 ≤ 790 μm. The back contact battery according to claim 1, wherein the sidewall of the groove structure comprises an inclined surface, and in a direction away from the middle area of the groove bottom, the inclined surface is inclined in a direction away from the second surface; The width of the inclined surface is L2, 5μm≤L2≤15μm. The back contact battery according to claim 1, wherein the groove bottom of the groove structure is a pyramid-shaped velvet surface, and the pyramid tip of the groove bottom of the semiconductor substrate is an arc shape; The curvature radius of the arc-shaped pyramid top is 70nm to 150nm; and/or the curvature range of the arc-shaped pyramid top is 30° to 150°. The back-contact cell according to claim 1, further comprising a transparent conductive layer, wherein the transparent conductive layer is disposed on a side of the first doped semiconductor layer and the second doped semiconductor layer away from the semiconductor substrate, and the transparent conductive layer is provided with an opening extending through the thickness thereof; Along the thickness direction of the semiconductor substrate, the distance between the surface of the transparent conductive layer arranged at the top of the pyramid at the bottom of the groove and the surface of the transparent conductive layer arranged on the first doped semiconductor layer and facing away from the semiconductor substrate is greater than or equal to 316 nm and less than or equal to 1538 nm. The back-contact battery according to claim 1 is characterized in that the thickness of the second doped semiconductor layer located at the bottom of the groove structure is less than the thickness of the second doped semiconductor layer located on the sidewall of the groove structure and/or covering the first doped semiconductor layer. A method for manufacturing a back-contact battery, comprising: A semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface has first regions and second regions alternately distributed; forming at least a first doped semiconductor layer on the first region of the first surface; The portion of the semiconductor substrate corresponding to the second region is selectively etched so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure; along the arrangement direction of the first and second regions, the side surface of the groove structure has a first sub-region and a second sub-region that are continuously distributed, and the second sub-region is close to the first region; the surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of the portion of the first sub-region of the groove structure gradually increases in a direction away from the first surface; and the surface of the second sub-region is a plane. A second doped semiconductor layer is formed covering the second region and extending to a portion of the first region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. The method for manufacturing a back-contact battery according to claim 31, wherein forming at least a first doped semiconductor layer on the first region of the first surface comprises: forming an entire layer of intrinsic semiconductor material on the first surface; selectively doping a portion of the intrinsic semiconductor material layer located on at least a portion of the first region, so that the portion of the intrinsic semiconductor material layer located on at least a portion of the first region forms the first doped semiconductor layer; forming a mask layer covering the first region; Under the masking effect of the mask layer, the portion of the intrinsic semiconductor material layer located on the second region is removed. The method for manufacturing a back-contact battery according to claim 31 or 32, characterized in that forming at least a first doped semiconductor layer on the first region of the first surface comprises: A first doped semiconductor layer and an intrinsic semiconductor layer are formed on the first region of the first surface; the intrinsic semiconductor layer is used to electrically isolate the second doped semiconductor layer from the first doped semiconductor layer. The method for manufacturing a back-contact battery according to claim 32, wherein the selective etching of the portion of the semiconductor substrate corresponding to the second region so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming a groove structure, comprises: Under the masking action of the mask layer, a wet chemical process is used to etch the portion of the semiconductor substrate corresponding to the second region, so that the surface of the second region is lower than the surface of the first region along the direction from the second surface to the first surface, thereby forming the groove structure. The method for manufacturing a back-contact battery according to claim 31, characterized in that after selectively etching the portion of the semiconductor substrate corresponding to the second region so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface, forming the groove structure, and before forming the second doped semiconductor layer covering the second region and extending above a portion of the first region, the method for manufacturing a back-contact battery further comprises: The groove bottom surface of the groove structure and at least a portion of the first sub-region are subjected to texturing treatment. The method for manufacturing a back-contact battery according to claim 31, characterized in that after providing a semiconductor substrate and before forming at least a first doped semiconductor layer on the first region of the first surface, the method for manufacturing a back-contact battery further comprises: forming a first passivation layer on the first region; and/or, The selective etching of the portion of the semiconductor substrate corresponding to the second region so as to make the surface of the second region lower than the surface of the first region along the direction from the second surface to the first surface to form a groove structure, and before forming a second doped semiconductor layer covering the second region and extending to above a portion of the first region, the manufacturing method of the back contact battery also includes: forming a second passivation layer covering the second region and extending to above a portion of the first region.