WO2025192872A1 - Apparatus and method for managing state of apparatus on basis of control signal - Google Patents

Abstract

According to one embodiment, an apparatus for communication with a terminal may comprise a fronthaul transceiver, a first processing circuit, a second processing circuit, a radio frequency transceiver, and a processor. The processor may be configured to receive, from a distributed unit (DU), a control message for indicating unused resources in an uplink or a downlink. The processor may be configured to identify whether the number of at least one resource block (RB) in the unused resources corresponds to a designated number. The processor may be configured to set the state of each of the first processing circuit and the second processing circuit to an idle state on the basis of the number of the at least one RB corresponding to the designated number. The processor may be configured to set the state of the first processing circuit to the idle state while the second processing circuit operates, on the basis of the number of the at least one RB, which is less than the designated number.

Description

Device and method for managing the state of a device based on a control signal

The present disclosure relates to a device and method for managing the state of a device based on a control signal.

As transmission capacity increases in wireless communication systems, functional splitting, which functionally separates base stations, is being implemented. Through functional splitting, base stations can be divided into distributed units (DUs) and radio units (RUs). A fronthaul interface is defined for communication between DUs and RUs.

The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

According to one embodiment, a device for communication with a terminal may include a fronthaul transceiver, a first processing circuit for processing a frequency domain signal according to fast Fourier transform (FFT) processing or inverse fast Fourier transform (IFFT) processing, a second processing circuit for processing a time domain signal according to the FFT processing or IFFT processing, a radio frequency (RF) transceiver for transmitting or receiving the time domain signal, and a processor. The processor may be configured to receive, through the fronthaul transceiver, a control message for indicating unused resources in uplink or downlink from a distributed unit (DU). The processor may be configured to identify, based on the control message, whether the number of at least one resource block (RB) in the unused resource corresponds to a designated number. The processor may be configured to set a state of each of the first processing circuit and the second processing circuit to the idle state based on the number of the at least one RB corresponding to the designated number. The processor may be configured to set the state of the first processing circuit to the idle state while the second processing circuit is operating, based on the number of the at least one RB being less than the specified number.

According to one embodiment, a method performed in a device for communication with a terminal may include receiving, through a fronthaul transceiver of the device, a control message for indicating unused resources in uplink or downlink from a distributed unit (DU). The method may include identifying, based on the control message, whether the number of at least one resource block (RB) in the unused resource corresponds to a designated number. The method may include setting a state of each of a first processing circuit of the device for processing a signal in a frequency domain according to fast Fourier transform (FFT) processing or inverse fast Fourier transform (IFFT) processing and a second processing circuit of the device for processing a signal in a time domain according to the FFT processing or IFFT processing to the idle state, based on the number of the at least one RB corresponding to the designated number. The method may include setting a state of the first processing circuit to the idle state while the second processing circuit operates, based on the number of the at least one RB being less than the designated number.

Figure 1a illustrates a wireless communication system.

Figure 1b illustrates an example for explaining a resource partitioning scheme for uplink transmission and downlink transmission.

Figure 2a illustrates a front-hole interface.

Figure 2b illustrates the fronthaul interface of an O(open)-RAN(radio access network).

Figure 3a illustrates the functional configuration of a distributed unit (DU).

Figure 3b illustrates the functional configuration of a RU (radio unit).

Figure 4 illustrates an example of function split between DU and RU.

Figure 5 illustrates an example of the operation of an RU in an FDD system.

Figure 6a illustrates an example of the operation of an RU for processing a DL signal in a TDD system.

Figure 6b illustrates an example of the operation of an RU for processing a UL signal in a TDD system.

Figure 7 illustrates an example of a simplified structure of an RU for setting the state of at least some of the components of the RU to an idle state.

Figure 8 shows an example of a simplified structure of a power saving control circuit.

Figure 9 shows an example of a C-plane packet.

Fig. 10 illustrates an example of the operation of a C-plane packet processing circuit for obtaining information included in a C-plane packet.

Figures 11a and 11b illustrate examples of sections indicated via C-plane packets.

Fig. 12 shows an example of the structure of a DL power saving control circuit.

Figure 13 illustrates an example of a simplified structure of a power saving control memory.

Figures 14a and 14b illustrate examples of the operation of a power saving control circuit.

Figure 15 shows an example of the structure of a UL power saving control circuit.

Figure 16 illustrates an example of a simplified structure of a power saving control memory.

Figures 17a and 17b illustrate examples of the operation of a power saving control circuit.

FIG. 18a illustrates an example of a first DL signal processing circuit or a first UL signal processing circuit.

FIG. 18b illustrates an example of a second DL signal processing circuit or a second UL signal processing circuit.

Figure 19 illustrates an example of a memory for a DL digital signal processing circuit or a UL digital signal processing circuit.

FIG. 20 illustrates an example of a memory for a second DL signal processing circuit or a second UL signal processing circuit.

Figure 21 is a flowchart regarding the operation of a device for communication with a terminal.

The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include the plural expression unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

In the following description, terms referring to signals (e.g., signal, information, message, signaling), terms referring to resources (e.g., symbol, slot, subframe, radio frame, subcarrier, resource element (RE), resource block (RB), bandwidth part (BWP), occasion), terms for operational states (e.g., step, operation, procedure), terms referring to data (e.g., packet, user stream, information, bit, symbol, codeword), terms referring to channels, terms referring to network entities, terms referring to components of devices, etc. are examples for convenience of description. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled, but this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." A condition described as "more than" may be replaced with "more than," a condition described as "less than" may be replaced with "less than," and a condition described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of elements from A (including A) to B (including B). hereinafter, "C" and/or "D" mean at least one of "C" or "D," that is, including {"C", "D", "C" and "D"}.

Although the present disclosure describes various embodiments using terms used in some communication standards (e.g., ^3rd Generation Partnership Project (3GPP), extensible radio access network (xRAN), open-radio access network (O-RAN), etc.), these are merely examples for explanation. The various embodiments of the present disclosure can be easily modified and applied to other communication systems.

Figure 1a illustrates a wireless communication system.

Referring to FIG. 1A, FIG. 1A illustrates a base station (110) and a terminal (120) as some of the nodes utilizing a wireless channel in a wireless communication system. Although FIG. 1A illustrates only one base station, the wireless communication system may further include other base stations identical or similar to the base station (110).

The base station (110) is a network infrastructure that provides wireless access to the terminal (120). The base station (110) has coverage defined based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission/reception point (TRP)', or other terms having equivalent technical meanings.

The terminal (120) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). In addition, although not shown in FIG. 1A, the terminal (120) and another terminal may communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without the involvement of a user. In one embodiment, the terminal (120) is a device that performs machine type communication (MTC) and may not be carried by the user. Additionally, according to one embodiment, the terminal (120) may be an MTC UE or an NB (narrowband)-IoT (internet of things) device.

The terminal (120) may be referred to as a terminal, or other terms such as 'user equipment (UE),' 'customer premises equipment (CPE),' 'mobile station,' 'subscriber station,' 'remote terminal,' 'wireless terminal,' 'electronic device,' or 'user device,' or other terms having equivalent technical meanings.

The base station (110) and the terminal (120) can perform beamforming. The base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively low frequency band (e.g., FR 1 (frequency range 1) of NR). In addition, the base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively high frequency band (e.g., FR 2 (or, FR 2-1, FR 2-2, FR 2-3), FR 3 of NR), millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). To improve channel gain, the base station (110) and the terminal (120) can perform beamforming. Here, the beamforming can include transmission beamforming and reception beamforming. The base station (110) and the terminal (120) can impart directionality to the transmitted or received signal. To this end, the base station (110) and the terminal (120) can select serving beams through a beam search or beam management procedure. After the serving beams are selected, subsequent communication can be performed through resources that have a QCL relationship with the resource that transmitted the serving beams.

If large-scale characteristics of a channel carrying a symbol on a first antenna port can be inferred from a channel carrying a symbol on a second antenna port, the first antenna port and the second antenna port can be evaluated to have a QCL relationship. For example, the large-scale characteristics may include at least one of delay spread, Doppler spread, Doppler shift, average gain, average delay, and a spatial receiver parameter.

Although both the base station (110) and the terminal (120) are described as performing beamforming in FIG. 1A, the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Furthermore, the base station may or may not perform beamforming. That is, either only one of the base station and the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, and is formed by one or more antennas (or antenna elements), and this forming process may be referred to as beamforming. Beamforming may include at least one of analog beamforming and digital beamforming (e.g., precoding). Reference signals transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal/physical broadcast channel (SS/PBCH), and a sounding reference signal (SRS). In addition, as a configuration for each reference signal, an IE such as a CSI-RS resource or an SRS-resource may be used, and this configuration may include information associated with the beam. Information associated with a beam may mean whether the configuration (e.g., a CSI-RS resource) uses the same spatial domain filter as another configuration (e.g., another CSI-RS resource within the same CSI-RS resource set) or a different spatial domain filter, or whether it is quasi-co-located (QCL) with a reference signal, and if so, what type it is (e.g., QCL type A, B, C, D).

Figure 1b illustrates an example for explaining a resource division scheme for uplink transmission and downlink transmission. The resource division scheme may include frequency division duplexing (FDD) and time division duplexing (TDD).

Referring to FIG. 1B, examples (150, 160) of methods for dividing resources used for transmitting and receiving data in downlink (DL) transmission from a base station (110) to a terminal (120) and uplink (UL) transmission from a terminal (120) to a base station (110) are illustrated. Example (150) may represent an example of a TDD (time division duplex) method, which is a method for dividing resources for DL transmission and resources for UL transmission according to time. Example (160) may represent an example of an FDD (frequency division duplex) method, which is a method for dividing resources for DL transmission and resources for UL transmission according to frequency.

Referring to example (150), the base station (110) can transmit DL signals to the terminal (120) via DL resources (152). The terminal (120) can receive the DL signals transmitted from the base station (110) via DL resources (152). The terminal (120) can transmit UL signals to the base station (110) via UL resources (154). The base station (110) can receive the UL signals transmitted from the terminal (120) via UL resources (154). Referring to example (150), different time resources can be allocated to the DL resources (152) and the UL resources (154). The DL transmission transmitted by the base station (110) to the terminal (120) and the UL transmission transmitted by the terminal (120) to the base station (110) may be performed in different time domains. Example (150) illustrates an example in which time resources of the same length are allocated to each of the DL resources (152) and the UL resources (154), but the embodiments of the present disclosure are not limited thereto. For example, the DL resources (152) and the UL resources (154) may be allocated time resources of different lengths. In other words, the period for downlink transmission may be set differently from the period for uplink transmission. Alternatively, both the DL resources (152) and the UL resources (154) may be allocated time resources of different lengths. In other words, downlink transmission and uplink transmission may be transmitted aperiodically. Although not shown in example (150), a guard period may be included between DL resources (152) and UL resources (154).

Referring to example (160), the base station (110) can transmit DL signals to the terminal (120) via DL resources (162). The terminal (120) can receive the DL signals transmitted from the base station (110) via DL resources (162). The terminal (120) can transmit UL signals to the base station (110) via UL resources (164). The base station (110) can receive the UL signals transmitted from the terminal (120) via UL resources (164). Referring to example (150), different frequency resources can be allocated to the DL resources (152) and the UL resources (154). In other words, the DL transmission transmitted by the base station (110) to the terminal (120) and the UL transmission transmitted by the terminal (120) to the base station (110) may be performed in different frequency domains. Example (150) illustrates an example in which frequency resources for the same size band are allocated to each of the DL resources (152) and the UL resources (154), but the embodiments of the present disclosure are not limited thereto. For example, the DL resources (152) and the UL resources (154) may each be allocated frequency resources for different size bands.

Comparing examples (150) and (160), the DL resources (152) and the UL resources (154) may be allocated a wider frequency band than the DL resources (162) and the UL resources (164). For example, the base station (110) or the terminal (120) of example (150) may transmit a larger amount of data during the same time period than the base station (110) or the terminal (120) of example (160). In contrast, the DL resources (162) and the UL resources (164) may be allocated a narrower frequency band than the DL resources (152) and the UL resources (154), but may be allocated a longer time period. For example, the base station (110) or terminal (120) of example (160) can transmit seamlessly (or continuously) compared to the base station (110) or terminal (120) of example (150).

In order to explain the TDD scheme in the embodiments of the present disclosure, the resource structure of the TDD scheme defined in the communication standard (e.g., LTE or NR) is exemplarily explained. According to one embodiment, the base station (110) and the terminal (120) may use the TDD scheme of LTE. The TDD scheme of LTE defines time resources for downlink communication and time resources for uplink communication in one radio frame. The radio frame may include a UL subframe for uplink (UL) transmission and a DL subframe for downlink (DL) transmission. The frame may include a special subframe (SSF) for switching from downlink transmission to uplink transmission. Here, a combination of a UL subframe, a DL subframe, and a special subframe included in one frame is referred to as a UL/DL configuration. Different UL/DL configurations represent different combinations of UL subframes, DL subframes, and special subframes in one frame. The UL/DL configuration can be operated as shown in Table 1 below. In Table 1 below, D represents a DL subframe, S represents a special subframe, and U represents a UL subframe. For example, UL/DL configuration #2 can include 6 DL subframes, 2 UL subframes, and 2 special subframes, and UL/DL configuration #5 can include 8 DL subframes, 1 UL subframe, and 1 special subframe.

A special subframe may include a downlink pilot time slot (DwPTS), a guard period (GP), and an uplink pilot time slot (UpPTS). The DwPTS is a period for downlink resources within the special subframe and may be used for transmitting a physical downlink shared channel (PDSCH). The UpPTS is a period for uplink resources within the special subframe and may be used for transmitting a sounding reference signal (SRS) or a physical random access channel (PRACH). The guard period (GP) is a period in which neither downlink transmission nor uplink transmission occurs and may be a period required for downlink-uplink switching. The guard period (GP) may be a period located between the DwPTS and the UpPTS within one special subframe (e.g., 1 ms). Here, the combination of the DwPTS, the guard period, and the UpPTS included in one special subframe is referred to as a special subframe configuration (SSF configuration). Different SSF configurations represent different combinations of the length of the DwPTS, the length of the guard interval, and the length of the UpPTS in one frame. When the wireless communication environment supports the LTE-TDD scheme, the SSF configurations can be operated as shown in Table 2 below. For example, SSF configuration #5 can represent a combination in which the DwPTS occupies 3 symbols, the guard interval occupies 9 symbols, and the UpPTS occupies 2 symbols, and SSF configuration #7 can represent a combination in which the DwPTS occupies 10 symbols, the guard interval occupies 2 symbols, and the UpPTS occupies 2 symbols.

According to one embodiment, the base station (110) and the terminal (120) can use the NR TDD scheme. The NR TDD scheme can be configured more flexibly than the LTE TDD scheme. The NR TDD scheme defines a DL-UL pattern indicating a relationship between DL time resources for downlink communication and UL time resources for uplink communication. The DL-UL pattern can include a configuration periodicity, a DL time interval, and an UL time interval. The configuration period can refer to a time for which one DL-UL pattern is applied. For example, the configuration period can be one of 0.5ms, 0.625ms, 1ms, 1.25ms, 2.5ms, 3ms, 4ms, 5ms, and 10ms. The DL time interval can be a time resource for which downlink communication continues. A DL time interval can be expressed as the number of slots, or as the number of slots and the number of symbols, or as the number of symbols only. A DL time interval can be located at the beginning part of a configuration period. A UL time interval can be a time resource during which an uplink continues. A UL time interval can be expressed as the number of slots, or as the number of slots and the number of symbols, or as the number of symbols only. A UL time interval can be located at the end part of a configuration period. Slots other than DL slots (slots in which all symbols are DL symbols) and UL slots (slots in which all symbols are UL symbols) within a configuration period can be flexible slots. Downlink symbols, uplink symbols, and flexible symbols can also be distinguished from the symbols within a slot (e.g., 14 symbols). As an example of the resource structure of NR TDD, when the subcarrier spacing (SCS) is 15 kHz, five slots can be defined during a configuration period of 5 ms. The first two slots of the five slots are downlink slots, the last two slots are uplink slots, and the middle slot can have both uplink and downlink symbols. The first five symbols of the 14 symbols of the remaining slots can be downlink symbols, the last three symbols of the 14 symbols can be uplink symbols, and the remaining six symbols of the 14 symbols can be flexible symbols.

In TDD, since the same carrier frequency is used for uplink and downlink transmission, a distinction between DL time intervals and UL time intervals is necessary. Therefore, as described above, resource structures for TDD may include DL time intervals, UL time intervals, and a remaining interval between the DL time intervals and UL time intervals. For example, in the DL time interval in which the base station (110) transmits a signal, a transmission path is used, but in the UL time interval in which the base station (110) receives a signal, a reception path may not be used instead of the transmission path.

In the past, in communication systems with relatively large cell radius of base stations, each base station was installed to include the functions of a digital processing unit (or distributed unit (DU)) and a radio frequency (RF) processing unit (or radio unit (RU)). However, as higher frequency bands are used in 4G (4th generation) and/or subsequent communication systems (e.g., 5G) and the cell coverage of base stations decreases, the number of base stations to cover a specific area has increased. The installation costs for operators to install base stations have also increased. In order to minimize the installation costs of base stations, a structure has been proposed in which the DU and RU of a base station are separated, one or more RUs are connected to one DU via a wired network, and one or more RUs are geographically distributed to cover a specific area. Hereinafter, the deployment structure and expanded examples of base stations according to various embodiments of the present disclosure are described through FIGS. 2A and 2B.

FIG. 2A illustrates a fronthaul interface. Unlike the backhaul between a base station and a core network, fronthaul refers to the connection between entities between a wireless LAN and a base station. FIG. 2A illustrates an example of a fronthaul structure between a DU (210) and one RU (220), but this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and multiple RUs. For example, embodiments of the present disclosure can be applied to a fronthaul structure between one DU and two RUs. Furthermore, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and three RUs.

Referring to FIG. 2A, a base station (110) may include a DU (210) and an RU (220). A fronthaul (215) between the DU (210) and the RU (220) may be operated via an interface. For operation of the fronthaul (215), an interface such as an enhanced common public radio interface (eCPRI) or radio over ethernet (ROE) may be used, for example.

As communications technology advances, mobile data traffic increases, significantly increasing the bandwidth requirements for the fronthaul between the digital unit and the radio unit. In deployments such as C-RAN (centralized/cloud radio access network), the DU performs functions for the packet data convergence protocol (PDCP), radio link control (RLC), media access control (MAC), and physical layer (PHY), while the RU can be implemented to perform additional functions for the PHY layer in addition to its radio frequency (RF) functions.

DU (210) may be responsible for upper layer functions of a wireless network. For example, DU (210) may perform functions of the MAC layer and a part of the PHY layer. Here, a part of the PHY layer refers to functions performed at a higher level among the functions of the PHY layer, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to an embodiment, if DU (210) complies with the O-RAN standard, it may be referred to as O-DU (O-RAN DU). DU (210) may be replaced with a first network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

The RU (220) may be responsible for lower layer functions of a wireless network. For example, the RU (220) may perform a part of the PHY layer, an RF function. Here, a part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the DU (210), and may include, for example, iFFT transformation (or FFT transformation), CP (cyclic prefix) insertion (CP removal), and digital beamforming. An example of such specific functional separation is described in detail in FIG. 4. The RU (220) may be referred to as an 'access unit (AU)', an 'access point (AP)', a 'transmission/reception point (TRP)', a 'remote radio head (RRH)', a 'radio unit (RU)', or other terms having an equivalent technical meaning thereto. In one embodiment, if RU (220) complies with the O-RAN standard, it may be referred to as O-RU (O-RAN RU). RU (220) may be represented as a second network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

Although FIG. 2A illustrates that the base station (110) includes a DU (210) and a RU (220), the embodiments of the present disclosure are not limited thereto. The base station according to the embodiments may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform functions of upper layers of an access network (e.g., packet data convergence protocol (PDCP), radio resource control (RRC)) and a distributed unit (DU) configured to perform functions of lower layers. In this case, the distributed unit (DU) may include a digital unit (DU) and a radio unit (RU). Between a core (e.g., 5GC (5G core) or NGC (next generation core)) network and a radio network (RAN), the base station may be implemented in a structure in which the CU, DU, and RU are arranged in that order. The interface between the CU and the distributed unit (DU) may be referred to as an F1 interface.

A centralized unit (CU) can be connected to one or more DUs and can be responsible for functions at a higher layer than the DU. For example, the CU can be responsible for functions at the RRC (radio resource control) and PDCP (packet data convergence protocol) layers, while the DU and RU can be responsible for functions at lower layers. The DU can perform some functions (high PHY) of the RLC (radio link control), MAC (media access control), and PHY (physical) layers, while the RU can be responsible for the remaining functions (low PHY) of the PHY layer. In addition, for example, a digital unit (DU) can be included in a distributed unit (DU) depending on the implementation of a distributed deployment of the base station. Hereinafter, unless otherwise defined, the operations of DU (digital unit) and RU are described, but various embodiments of the present disclosure can be applied to both a base station deployment including CU and a deployment in which DU is directly connected to the core network (i.e., a base station in which CU and DU are integrated as a single entity (e.g., NG-RAN node)).

Figure 2b illustrates the fronthaul interface of an open RAN (radio access network). A base station (110) according to a distributed deployment is exemplified as an eNB or gNB.

Referring to FIG. 2b, the base station (110) may include an O-DU (251) and O-RUs (253-1, ..., 253-n). Hereinafter, for convenience of explanation, the operation and function of the O-RU (253-1) may be understood as a description of each of the other O-RUs (e.g., O-RU (253-n)).

The O-DU (251) is a logical node that includes functions, excluding functions exclusively assigned to the O-RU (253-1), among the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. The O-DU (251) can control the operation of the O-RUs (253-1, ..., 253-n). The O-DU (251) may be referred to as an LLS (lower layer split) CU (central unit). The O-RU (253-1) is a logical node that includes a subset of the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. Real-time aspects of control plane (C-plane) communication and user plane (U-plane) communication with the O-RU (253-1) can be controlled by the O-DU (251).

The O-DU (251) can communicate with the O-RU (253-1) through an LLS interface. The LLS interface corresponds to a fronthaul interface. The LLS interface refers to a logical interface between the O-DU (251) and the O-RU (253-1) that utilizes lower layer functional split (i.e., intra-PHY based functional split). The LLS-C between the O-DU (251) and the O-RU (253-1) provides the C-plane through the LLS interface. The LLS-U between the O-DU (251) and the O-RU (253-1) provides the U-plane through the LLS interface.

In FIG. 2B, to explain the O-RAN, entities of the base station (110) are described as O-DU and O-RU. However, these names are not to be construed as limiting the embodiments of the present disclosure. In the embodiments described below, it is obvious that the operations of the DU (210) can be performed by the O-DU (251). The description of the DU (210) can be applied to the O-DU (251). Similarly, in the embodiments described below, it is obvious that the operations of the RU (220) can be performed by the O-RU (253-1). The description of the RU (220) can be applied to the O-DU (253-1).

Fig. 3a illustrates the functional configuration of a DU (distributed unit). The configuration illustrated in Fig. 3a can be understood as the configuration of the DU (210) of Fig. 2a (or the O-DU (250) of Fig. 2b) as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

Referring to FIG. 3a, DU (210) includes a transceiver (310), memory (320), and processor (330).

The transceiver (310) can perform functions for transmitting and receiving signals in a wired communication environment. The transceiver (310) can include a wired interface for controlling direct connections between devices via a transmission medium (e.g., copper wire, optical fiber). For example, the transceiver (310) can transmit electrical signals to other devices via copper wire, or perform conversion between electrical signals and optical signals. The DU (210) can communicate with a radio unit (RU) via the transceiver (310). The DU (210) can be connected to a core network or a CU in a distributed arrangement via the transceiver (310).

The transceiver (310) may perform functions for transmitting and receiving signals in a wireless communication environment. For example, the transceiver (310) may perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (310) generates complex symbols by encoding and modulating the transmitted bit stream. In addition, when receiving data, the transceiver (310) restores the received bit stream by demodulating and decoding the baseband signal. In addition, the transceiver (310) may include multiple transmission and reception paths. Furthermore, according to one embodiment, the transceiver (310) may be connected to the core network or other nodes (e.g., an integrated access backhaul (IAB).

The transceiver (310) can transmit and receive signals. For example, the transceiver (310) can transmit a management plane (M-plane) message. For example, the transceiver (310) can transmit a management plane (S-plane) message. For example, the transceiver (310) can transmit a control plane (C-plane) message. For example, the transceiver (310) can transmit a user plane (U-plane) message. For example, the transceiver (310) can receive a user plane message. Although only the transceiver (310) is illustrated in FIG. 3A, in other implementations, the DU (210) may include two or more transceivers.

The transceiver (310) transmits and receives signals as described above. Accordingly, all or part of the transceiver (310) may be referred to as a "communication unit," a "transmitter," a "receiver," or a "transmitter-receiver unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that the transceiver (310) performs the processing described above.

Although not illustrated in FIG. 3A, the transceiver (310) may further include a backhaul transceiver for connection to the core network or other base stations. The backhaul transceiver provides an interface for communicating with other nodes within the network. That is, the backhaul transceiver converts a bit stream transmitted from the base station to other nodes, such as other access nodes, other base stations, upper nodes, the core network, etc., into a physical signal, and converts a physical signal received from other nodes into a bit stream.

The memory (320) stores data such as basic programs, application programs, and setting information for the operation of the DU (210). The memory (320) may be referred to as a storage unit. The memory (320) may be composed of volatile memory, nonvolatile memory, or a combination of volatile memory and nonvolatile memory. In addition, the memory (320) provides stored data upon request from the processor (330).

The processor (330) controls the overall operations of the DU (210). The processor (380) may be referred to as a control unit. For example, the processor (330) transmits and receives signals through the transceiver (310) (or through the backhaul communication unit). In addition, the processor (330) records and reads data from the memory (320). In addition, the processor (330) may perform the functions of the protocol stack required by the communication standard. Although only the processor (330) is illustrated in FIG. 3A, the DU (210) may include two or more processors according to other implementation examples.

The configuration of DU (210) illustrated in FIG. 3A is merely an example, and examples of DUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3A. In some embodiments, some configurations may be added, deleted, or changed.

Fig. 3b illustrates the functional configuration of a radio unit (RU). The configuration illustrated in Fig. 3b can be understood as a configuration of the RU (220) of Fig. 2b or the O-RU (253-1) of Fig. 2b as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

Referring to FIG. 3b, the RU (220) includes an RF transceiver (360), a fronthaul transceiver (365), a memory (370), and a processor (380).

The RF transceiver (360) performs functions for transmitting and receiving signals via a wireless channel. For example, the RF transceiver (360) upconverts a baseband signal into an RF band signal and transmits it via an antenna, and downconverts an RF band signal received via the antenna into a baseband signal. For example, the RF transceiver (360) may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, and the like.

The RF transceiver (360) may include multiple transmission and reception paths. Furthermore, the RF transceiver (360) may include an antenna unit. The RF transceiver (360) may include at least one antenna array composed of multiple antenna elements. In terms of hardware, the RF transceiver (360) may be composed of digital circuits and analog circuits (e.g., a radio frequency integrated circuit (RFIC)). Here, the digital circuits and analog circuits may be implemented in a single package. In addition, the RF transceiver (360) may include multiple RF chains. The RF transceiver (360) may perform beamforming. The RF transceiver (360) may apply beamforming weights to a signal to be transmitted and received in order to impart directionality according to the settings of the processor (380). According to one embodiment, the RF transceiver (360) may include a radio frequency (RF) block (or RF section).

According to one embodiment, the RF transceiver (360) can transmit and receive signals on a radio access network. For example, the RF transceiver (360) can transmit a downlink signal. The downlink signal can include a synchronization signal (SS), a reference signal (RS) (e.g., a cell-specific reference signal (CRS), a demodulation (DM)-RS), system information (e.g., a MIB, a SIB, remaining system information (RMSI), other system information (OSI)), a configuration message, control information, or downlink data. In addition, for example, the RF transceiver (360) can receive an uplink signal. The uplink signal may include a random access related signal (e.g., a random access preamble (RAP) (or Msg1 (message 1)), Msg3 (message 3)), a reference signal (e.g., a sounding reference signal (SRS), DM-RS), or a power headroom report (PHR). Although only the RF transceiver (360) is illustrated in FIG. 3b, in other implementation examples, the RU (220) may include two or more RF transceivers.

According to embodiments, the RF transceiver (460) may transmit a RIM-RS. The RF transceiver (460) may transmit a first type of RIM-RS (e.g., RIM-RS type 1 of 3GPP) to indicate the detection of far-field interference. The RF transceiver (460) may transmit a second type of RIM-RS (e.g., RIM-RS type 2 of 3GPP) to indicate the presence or absence of far-field interference.

The fronthaul transceiver (365) can transmit and receive signals. According to one embodiment, the fronthaul transceiver (365) can transmit and receive signals on the fronthaul interface. For example, the fronthaul transceiver (365) can receive a management plane (M-plane) message. For example, the fronthaul transceiver (365) can receive a management plane (S-plane) message. For example, the fronthaul transceiver (365) can receive a control plane (C-plane) message. For example, the fronthaul transceiver (365) can transmit a user plane (U-plane) message. For example, the fronthaul transceiver (365) can receive a user plane message. Although only the fronthaul transceiver (365) is shown in FIG. 3b, according to other implementation examples, the RU (220) may include two or more fronthaul transceivers.

The RF transceiver (360) and the fronthaul transceiver (365) transmit and receive signals as described above. Accordingly, all or part of the RF transceiver (360) and the fronthaul transceiver (365) may be referred to as a 'communication unit', a 'transmitter unit', a 'receiver unit', or a 'transmitter-receiver unit'. In addition, in the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360). In the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360).

The memory (370) stores data such as basic programs, application programs, and setting information for the operation of the RU (220). The memory (370) may be referred to as a storage unit. The memory (370) may be configured as volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the memory (370) provides the stored data according to a request from the processor (380). According to one embodiment, the memory (370) may include a memory for conditions, commands, or setting values related to the SRS transmission method.

The processor (380) controls the overall operations of the RU (220). The processor (380) may be referred to as a control unit. For example, the processor (380) transmits and receives signals through the RF transceiver (360) or the fronthaul transceiver (365). In addition, the processor (380) records and reads data in the memory (370). In addition, the processor (380) may perform functions of a protocol stack required by a communication standard. Although only the processor (380) is illustrated in FIG. 3B, the RU (220) may include two or more processors according to other implementation examples. The processor (380) may be a set of instructions or codes stored in the memory (370), or may be a storage space that stores instructions/codes or instructions/codes that are at least temporarily residing in the processor (380), or may be a part of the circuitry that constitutes the processor (380). Additionally, the processor (380) may include various modules for performing communication. The processor (380) may control the RU (220) to perform operations according to the embodiments described below.

The configuration of RU (220) illustrated in FIG. 3b is merely an example, and examples of RUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3b. In some embodiments, some configurations may be added, deleted, or changed.

Figure 4 illustrates an example of function split between DUs and RUs. As wireless communication technologies advance (e.g., the introduction of 5G ( ^5th generation) communication systems (or NR (new radio) communication systems), the frequency bands used have increased further. As the cell radius of base stations has become significantly smaller, the number of RUs required for installation has also increased further. Furthermore, in 5G communication systems, the amount of data transmitted has increased by a factor of up to ten, significantly increasing the transmission capacity of wired networks transmitted to the fronthaul. Due to the factors described above, the installation cost of wired networks in 5G communication systems may increase significantly. Therefore, in order to lower the transmission capacity of wired networks and reduce the installation cost of wired networks, 'function split' can be utilized, which transfers some of the functions of the modem of the DU to the RUs to lower the transmission capacity of the fronthaul.

To reduce the burden on the DU, the role of the RU, which is traditionally solely responsible for RF functions, can be expanded to include some physical layer functions. As the RU performs higher-layer functions, its throughput increases, which can increase transmission bandwidth in the fronthaul while reducing latency requirements due to response processing. However, as the RU performs higher-layer functions, virtualization gains decrease, and the RU's size, weight, and cost increase. Considering the trade-offs between the advantages and disadvantages described above, implementing an optimal functional separation is required.

Referring to Figure 4, the functional separation in the physical layer below the MAC layer is illustrated. For the downlink (DL) that transmits a signal to a terminal through a wireless network, the base station can sequentially perform channel encoding/scrambling, modulation, layer mapping, antenna mapping, RE mapping, digital beamforming (e.g., precoding), iFFT transform/CP insertion, and RF transform. For the uplink (UL) that receives a signal from a terminal through a wireless network, the base station can sequentially perform RF transform, FFT transform/CP removal, digital beamforming (pre-combining), RE demapping, channel estimation, layer demapping, demodulation, and decoding/descrambling. The separation of uplink and downlink functions can be defined in various types depending on the needs of vendors, discussions in standards, etc., according to the above-mentioned trade-offs.

In the first functional separation (405), the RU performs the RF function, and the DU performs the PHY function. The first functional separation is one in which the PHY function is not substantially implemented in the RU, and may be referred to as Option 8, for example. In the second functional separation (410), the RU performs iFFT conversion/CP insertion in the DL and FFT conversion/CP removal in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the second functional separation (410) may be referred to as Option 7-1. In the third functional separation (420a), the RU performs iFFT conversion/CP insertion in the DL and FFT conversion/CP removal and digital beamforming in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the third functional separation (420a) may be referred to as Option 7-2x Category A. In the fourth functional separation (420b), the RU performs up to digital beamforming in both the DL and UL, and the DU performs upper PHY functions after the digital beamforming. For example, the fourth functional separation (420b) may be referred to as Option 7-2x Category B. In the fifth functional separation (425), the RU performs up to RE mapping (or RE demapping) in both the DL and UL, and the DU performs upper PHY functions after RE mapping (or RE demapping). For example, the fifth functional separation (425) may be referred to as Option 7-2. In the sixth functional separation (430), the RU performs up to modulation (or demodulation) in both the DL and UL, and the DU performs upper PHY functions after modulation (or demodulation). For example, the sixth functional separation (430) may be referred to as Option 7-3. In the seventh functional separation (440), the RU performs encoding/scrambling (or decoding/descrambling) in both the DL and UL, and the DU performs subsequent upper PHY functions up to modulation (or demodulation). For example, the seventh functional separation (440) may be referred to as Option 6.

In one embodiment, when a large amount of signal processing is expected, such as in the FR 1 MMU, functional separation at a relatively high layer (e.g., the fourth functional separation (420b)) may be required to reduce fronthaul capacity. In addition, functional separation at too high a layer (e.g., the sixth functional separation (430)) may complicate the control interface and cause a burden on the implementation of the RU due to the inclusion of a large number of PHY processing blocks within the RU. Therefore, appropriate functional separation may be required depending on the arrangement and implementation method of the DU and the RU.

In one embodiment, if the precoding of data received from the DU cannot be processed (i.e., if the precoding capability of the RU is limited), the third functional separation (420a) or a lower functional separation (e.g., the second functional separation (410)) may be applied. Conversely, if the DU has the capability to process the precoding of data received from the DU, the fourth functional separation (420b) or a higher functional separation (e.g., the sixth functional separation (430)) may be applied.

Hereinafter, embodiments in the present disclosure are described based on the third functional separation (420a) (which may be referred to as category A (CAT-A)) or the fourth functional separation (420b) (which may be referred to as category B (CAT-B)) for performing beamforming processing in an RU unless otherwise specified. The O-RAN standard distinguishes the types of O-RUs depending on whether the precoding function is located at the interface of the O-DU or the O-RU interface. An O-RU that does not perform precoding (i.e., has low complexity) may be referred to as a CAT-A O-RU. An O-RU that performs precoding may be referred to as a CAT-B O-RU.

Hereinafter, the term "upper-PHY" refers to physical layer processing handled in the DU of the fronthaul interface. For example, the upper-PHY may include FEC encoding/decoding, scrambling, and modulation/demodulation. Hereinafter, the term "lower-PHY" refers to physical layer processing handled in the RU of the fronthaul interface. For example, the lower-PHY may include FFT/iFFT, digital beamforming, PRACH (physical random access channel) extraction, and filtering. However, the above-described criteria do not exclude embodiments through other functional separations. The functional configuration, signaling, or operation of the embodiments described below may be applied not only to the third functional separation (420a) or the fourth functional separation (420b), but also to other functional separations.

Embodiments of the present disclosure exemplarily describe the standards of eCPRI and O-RAN as fronthaul interfaces when transmitting messages between a DU (e.g., DU (210) of FIG. 2a) and an RU (e.g., RU (220) of FIG. 2a). The Ethernet payload of the message may include an eCPRI header, an O-RAN header, and additional fields. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but other expressions having equivalent meanings to each term may be used instead in various embodiments of the present disclosure. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but are not limited thereto. For example, in various embodiments of the present disclosure, the CPRI standard may be used as the fronthaul interface.

The fronthaul transport protocol can use Ethernet and eCPRI, which are easy to share with networks. The Ethernet payload can include an eCPRI header and an O-RAN header. The eCPRI header can be located at the beginning of the Ethernet payload. The contents of the eCPRI header are as follows.

1) ecpriVersion (4 bits): This parameter indicates the eCPRI protocol version.

2) ecpriReserved (3 bits): This parameter is reserved for further use by eCPRI.

3) ecpriConcatenation (1 bit): This parameter indicates when eCPRI concatenation is in use.

4) ecpriMessage (1 byte): This parameter indicates the type of service carried by the message type. For example, the parameter indicates an IQ data message, a real-time control data message, or a transmission network delay measurement message.

5) ecpriPayload (2 bytes): This parameter indicates the byte size of the payload portion of the eCPRI message.

6) ecpriRtcid/ecpriPcid (2 bytes): This parameter is the eAxC (extended antenna-carrier) identifier (eAxC ID) and identifies a specific data flow associated with each C-plane (ecpriRtcid) or U-plane (ecpriPcid) message.

7) ecpriSeqid (2 bytes): This parameter provides unique message identification and ordering at both levels. The first octet of this parameter is a sequence ID used to identify the order of messages within the eAxC message stream. The sequence ID is used to ensure that all messages are received and to reorder out-of-order messages. The second octet of this parameter is a subsequence ID. The subsequence ID is used to ensure ordering and implement reordering when radio-transport-level (eCPRI or IEEE-1914.3) fragmentation occurs.

The eAxC identifier (ID) includes a band and sector identifier ('BandSector_ID'), a component carrier identifier ('CC_ID'), a spatial stream identifier ('RU_Port_ID'), and a distributed unit identifier ('DU_Port_ID'). The bit allocation of the eAxC ID can be distinguished as follows.

1) DU_port ID: The DU_port ID is used to distinguish processing units (e.g., different baseband cards) in the O-DU. The O-DU is expected to allocate bits for the DU_port ID, and the O-RU is expected to append the same value to the UL U-plane message carrying the same sectionId data.

2) BandSector_ID: Aggregated cell identifier (band and sector distinction supported by O-RU).

3) CC_ID: CC_ID identifies the carrier component supported by the O-RU.

4) RU_port ID: The RU_port ID specifies logical flows such as data layer or spatial streams, and signaling channels that require separate numerologies (e.g. PRACH) or special antenna allocation such as SRS.

The application protocol of the fronthaul may include a control plane (C-plane), a user plane (U-plane), a synchronization plane (S-plane), and a management plane (M-plane).

The control plane may be configured to provide scheduling information and beamforming information via control messages. The control plane refers to real-time control between DUs and RUs. The user plane may include IQ sample data transmitted between DUs and RUs. The user plane may include user downlink data (IQ data or SSB/RS), uplink data (IQ data or SRS/RS), or PRACH data. A weight vector of the beamforming information described above may be multiplied by the user's data. The synchronization plane generally refers to traffic between DUs and RUs for a synchronization controller (e.g., IEEE grand master). The synchronization plane may be related to timing and synchronization. The management plane refers to non-real-time control between DUs and RUs. The management plane may be related to initial setup, non-realtime reset or reset, and non-realtime report.

Control plane messages, or C-plane messages, can be encapsulated based on a two-layer header approach. The first layer can consist of the eCPRI common header or the IEEE 1914.3 common header, which contains fields used to indicate the message type. The second layer is the application layer, which contains fields necessary for control and synchronization. Within the application layer, sections define the characteristics of U-plane data transmitted or received on a beam with a single pattern ID. The following section types are supported within the C-plane:

Section Type can indicate the purpose of control messages transmitted on the control plane. For example, the purposes of each Section Type are as follows.

1) sectionType=0: Used to indicate resource blocks or symbols not used in DL or UL.

2) sectionType=1: Used for most DL/UL wireless channels. Here, "most" refers to channels that do not require time or frequency offsets, such as those required for mixed numerology channels.

3) sectionType=2: reserved for further use

4) sectionType=3: PRACH and mixed-numerology channels. Channels that require a time or frequency offset or differ from the nominal SCS value(s).

5) sectionType=4: reserved for further use

6) sectionType=5: UE scheduling information. Transmits UE scheduling information so that the RU can perform real-time BF weight calculations (O-RAN optional BF method).

7) sectionType=6: Transmits UE-specific channel information. Periodically transmits UE channel information to enable the RU to perform real-time BF weight calculations (O-RAN optional BF method).

8) sectionType=7: Used for LAA support

Figure 5 illustrates an example of the operation of an RU in an FDD system.

Referring to FIG. 5, the RU (220) can receive a control signal (or control message) regarding downlink (DL) and uplink (UL) from the DU (210). The RU (220) can perform an operation regarding downlink or uplink based on the control signal received from the DU (210). In the following specification, for the convenience of explanation, it is described that a device for communicating with a terminal is configured as the RU (220), but is not limited thereto. For example, the device for communicating with a terminal may be an MMU (massive multiple-input and multiple-output unit). The MMU may be configured to perform at least some of the functions of the RU (220). The MMU may be configured to perform at least some of the functions of the DU (210).

For example, RU (220) can receive a control signal (e.g., C-plane message, C-plane MSG) from DU (210). After receiving the control signal, RU (220) can receive a data signal including DL traffic (e.g., U-plane message, U-plane MSG). Based on the control signal, RU (220) can transmit the DL traffic to a terminal connected to RU (220). For example, RU (220) can be configured to process a signal between a modem (MODEM) and a terminal connected to RU (220).

For example, RU (220) can receive a control signal (e.g., C-plane message, C-plane MSG) from DU (210). Based on the control signal, RU (220) can receive a signal including UL traffic from a terminal connected to RU (220). RU (220) can transmit a data signal including UL traffic (e.g., U-plane message, U-plane MSG) to DU (210).

According to one embodiment, the RU (220) may include a front-hole signal processing circuit (510), a DL signal control circuit (521), a DL digital signal processing circuit (522), an analog signal processing circuit (530), a UL signal control circuit (541), and a UL digital signal processing circuit (542).

For example, the fronthaul signal processing circuit (510) may be configured to process a control signal (e.g., a C-plane message) received from the DU (210), a data signal (e.g., a U-plane message) received from the DU (210), and a data signal (e.g., UL traffic) received from the terminal.

For example, the DL signal control circuit (521) may be configured to control the DL digital signal processing circuit (522) based on a control signal received from the front-haul signal processing circuit (510).

For example, the DL digital signal processing circuit (522) may be configured to convert a digital signal in the frequency domain into an analog signal in the time domain based on a signal received from the DL signal control circuit (521). As an example, the DL digital signal processing circuit (522) may include a circuit for performing inverse fast Fourier transform (IFFT) processing (or IFFT operation). The DL digital signal processing circuit (522) may obtain DL traffic included in a data signal and convert a digital signal related to the DL traffic into an analog signal related to the DL traffic.

For example, the analog signal processing circuit (530) may be configured to transmit a time-domain analog signal to a terminal or receive a time-domain analog signal from a terminal. The analog signal processing circuit (530) may transmit UL traffic to the UL signal processing circuit (542).

For example, the UL signal control circuit (541) may be configured to control the UL digital signal processing circuit (542) based on a control signal received from the fronthaul signal processing circuit (510).

For example, the UL digital signal processing circuit (542) may be configured to convert an analog signal in the time domain into a digital signal in the frequency domain based on a signal received from the UL signal control circuit (541). As an example, the UL digital signal processing circuit (542) may include a circuit for performing fast Fourier transform (FFT) processing (or FFT operation). The UL digital signal processing circuit (542) may receive UL traffic from the analog signal processing circuit (530). The UL digital signal processing circuit (542) may convert an analog signal regarding the UL traffic into a digital signal regarding the UL traffic based on a signal received from the UL signal control circuit (541).

According to one embodiment, the RU (220) may be configured to operate based on the FDD scheme. When the RU (220) operates based on the FDD scheme, the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) may operate in the DL section (or DL frequency section). For example, when (220) operates based on the FDD scheme, the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) may operate in the DL section (or DL frequency section). For example, when (220) operates based on the FDD method, the states of the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) can each be set to an active state in the DL section (or DL frequency section).

When the RU (220) operates based on the FDD method, the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be operated in the UL section (or UL frequency section). For example, when (220) operates based on the FDD method, the states of the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be set to an active state in the UL section (or UL frequency section). For example, when (220) operates based on the FDD method, the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be operated in the UL section (or UL frequency section).

As described above, when the RU (220) operates based on the FDD method, the time domain for transmitting or receiving a signal may not be distinguished. Therefore, when the RU (220) operates based on the FDD method, all circuits for processing a digital signal (e.g., a fronthaul signal processing circuit (510), a DL signal control circuit (521), a DL digital signal processing circuit (522), a UL signal control circuit (541), a UL digital signal processing circuit (542), and an analog signal processing circuit (530)) may be operated. However, in an area where there are few terminals to provide service and/or within a time period where there are few terminals to provide service, the DU (210) may set the state of at least some of the components of the RU (220) to an idle state.

Figure 6a illustrates an example of the operation of an RU for processing a DL signal in a TDD system.

Figure 6b illustrates an example of the operation of an RU for processing a UL signal in a TDD system.

Referring to FIGS. 6A and 6B, the RU (220) can receive a control signal (or control message) regarding downlink (DL) and uplink (UL) from the DU (210). The RU (220) can perform an operation regarding downlink or uplink based on the control signal received from the DU (210). In the following specification, for convenience of explanation, it is described that a device for communicating with a terminal is configured as the RU (220), but is not limited thereto. For example, the device for communicating with a terminal may be an MMU (massive multiple-input and multiple-output unit). The MMU may be configured to perform at least some of the functions of the RU (220). The MMU may be configured to perform at least some of the functions of the DU (210). For example, the DU (210) of FIG. 6a or FIG. 6b may correspond to the DU (210) of FIG. 5. The RU (220) of FIG. 6a or FIG. 6b may correspond to the RU (220) of FIG. 5.

According to one embodiment, the RU (220) may be configured to operate based on the TDD scheme. FIG. 6a illustrates an example of the operation of components of the RU (220) (or circuits included in the RU (220)) in the DL section when the RU (220) operates based on the TDD scheme. FIG. 6b illustrates an example of the operation of components of the RU (220) (or circuits included in the RU (220)) in the UL section when the RU (220) operates based on the TDD scheme.

Referring to FIG. 6A, when the RU (220) operates based on the TDD scheme, the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) may be operated in the DL section (or DL time section). For example, when (220) operates based on the TDD scheme, the states of the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) may be set to an active state in the DL section (or DL time section). For example, when (220) operates based on the TDD scheme, the fronthaul signal processing circuit (510), the DL signal control circuit (521), the DL digital signal processing circuit (522), and the analog signal processing circuit (530) may be operated in the DL section (or DL time section).

When the RU (220) operates based on the TDD scheme, the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be operated in the UL section (or UL time section). For example, when (220) operates based on the TDD scheme, the states of the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be set to an active state in the UL section (or UL time section). For example, when (220) operates based on the TDD scheme, the fronthaul signal processing circuit (510), the UL signal control circuit (541), the UL digital signal processing circuit (542), and the analog signal processing circuit (530) may be operated in the UL section (or UL time section).

Referring to FIGS. 6A and 6B, when the RU (220) operates based on the TDD method, the time domain for transmitting or receiving a signal can be distinguished. Accordingly, when the RU (220) transmits a DL signal, the states of the UL signal control circuit (541) and the UL digital signal processing circuit (542) can be set to an idle state. When the RU (220) receives a UL signal, the states of the DL signal control circuit (521) and the DL digital signal processing circuit (522) can be set to an idle state.

For example, DU (210) can set the state of at least some of the components of RU (220) to an idle state. DU (210) can set the state of at least some of the components of RU (220) to an idle state by indicating an idle section or a guard symbol section. For example, DU (210) can indicate an idle section or a guard symbol section to RU (220) by transmitting a control signal of section type 0 to RU (220).

Referring to Fig. 6a, when a DL signal is transmitted, the DL traffic included in the data signal received from the DU (210) can be set to '0' within the idle period. Within the idle period, both the input and output of the DL digital signal processing circuit (522) can be set to '0'. Accordingly, the DL signal control circuit (521) can perform control of the clock circuit regardless of the idle period.

When a UL signal is received, within the idle period, the UL digital signal processing circuit (542) can receive a noise signal from the analog signal processing circuit (530). The UL digital signal processing circuit (542) can process the noise signal regardless of the idle period.

As described above, even within the idle period, the RU (220) may control the clock circuit or process noise signals. Therefore, unnecessary power consumption of the RU (220) may occur within the idle period. In the following specification, the RU (220) may set the state of at least some of the components of the RU (220) to the idle state based on the control plane message received from the DU (210). The RU (220) may generate a control signal for indicating the idle state based on the control plane message. The RU (220) may set the state of at least some of the components of the RU (220) to the idle state based on the control signal.

The idle state described below may be distinguished from the idle state described in FIGS. 5, 6A, and 6B. For example, in the idle state described in FIGS. 5, 6A, and 6B, the RU (220) may control a clock circuit or perform processing of a noise signal, but in the idle state described below, the RU (220) may not control a clock circuit or perform processing of a noise signal.

Figure 7 illustrates an example of a simplified structure of an RU for setting the state of at least some of the components of the RU to an idle state.

Referring to FIG. 7, RU (702) can receive C-plane messages regarding downlink (DL) and uplink (UL) from DU (701). RU (702) can perform operations regarding downlink or uplink based on the C-plane messages received from DU (701). In the following specification, for convenience of explanation, it is described that a device for communicating with a terminal is configured as RU (702), but is not limited thereto. For example, the device for communicating with a terminal may be a massive multiple-input and multiple-output unit (MMU). The MMU may be configured to perform at least some of the functions of the RU (702). The MMU may be configured to perform at least some of the functions of the DU (701). For example, DU (701) may correspond to DU (210) of FIGS. 2A to 6B. RU (702) may correspond to RU (220) of FIGS. 2a to 6b.

According to one embodiment, the RU (702) may include a front-haul signal processing circuit (710), a DL signal control circuit (721), a DL digital signal processing circuit (722), an analog signal processing circuit (730), a UL signal control circuit (741), a UL digital signal processing circuit (742), and a power saving control circuit (750).

For example, the DL digital signal processing circuit (722) can perform IFFT processing. The DL digital signal processing circuit (722) can include a first DL signal processing circuit (761), a second DL signal processing circuit (762), and an IFFT processing circuit (763). The first DL signal processing circuit (761) can be configured to process a DL signal in a frequency domain. The first DL signal processing circuit (761) can be configured to perform processing on a signal (or traffic) before IFFT processing (or IFFT operation) is performed. The IFFT processing circuit (763) can be configured to convert a DL signal in a frequency domain into a DL signal in a time domain. The second DL signal processing circuit (762) can be configured to process a DL signal in a time domain. The second DL signal processing circuit (762) may be configured to perform processing on a signal (or traffic) after IFFT processing (or IFFT operation) is performed.

For example, the UL digital signal processing circuit (742) can perform FFT processing. The UL digital signal processing circuit (742) can include a first UL signal processing circuit (771), a second UL signal processing circuit (772), and an FFT processing circuit (773). The first UL signal processing circuit (771) can be configured to process a UL signal in a time domain. The first UL signal processing circuit (771) can be configured to perform processing on a signal (or traffic) before FFT processing (or FFT operation) is performed. The FFT processing circuit (773) can be configured to convert a UL signal in a time domain into a UL signal in a frequency domain. The second UL signal processing circuit (772) can be configured to process a UL signal in a frequency domain. The second UL signal processing circuit (772) can be configured to perform processing on a signal (or traffic) after FFT processing (or FFT operation) is performed.

For example, the RU (702) can receive a C-plane packet from the DU (701). The C-plane packet can include at least one C-plane message. For example, one C-plane message can include information about one section. The fronthaul signal processing circuit (710) can obtain a C-plane message (or at least one C-plane message) based on the C-plane packet. The fronthaul signal processing circuit (710) can transmit (or provide, transfer) the C-plane message to the DL signal control circuit (721) and/or the UL signal control circuit (741).

When a DL signal is transmitted from RU (702), RU (702) can receive a DL U-plane packet from DU (701). The fronthaul signal processing circuit (710) can obtain a U-plane message (or at least one U-plane message) based on the U-plane packet. The fronthaul signal processing circuit (710) can transmit (or provide, transfer) the DL U-plane message to the DL digital signal processing circuit (722).

When a UL signal is received from the RU (702), the fronthaul signal processing circuit (710) can receive UL traffic (or UL data) from the terminal. The fronthaul signal processing circuit (710) can obtain a UL U-plane packet including a U-plane message (or at least one U-plane message) based on the UL traffic received from the terminal. The fronthaul signal processing circuit (710) can transmit the UL U-plane packet to the DU (701).

For example, the DL signal control circuit (721) may be configured to control the DL digital signal processing circuit (722). The DL signal control circuit (721) may obtain (or generate) a control signal for controlling the DL digital signal processing circuit (722) based on a C-plane message. The DL signal control circuit (721) may transmit (or provide, transfer) the obtained control signal to the DL digital signal processing circuit (722). The DL digital signal processing circuit (722) may process a DL U-plane message based on the control signal. The DL digital signal processing circuit (722) may obtain DL traffic and transmit (or provide, transfer) the DL traffic to the analog signal processing circuit (730). The DL traffic may be transmitted to the terminal via the analog signal processing circuit (730).

For example, the UL signal control circuit (741) may be configured to control the UL digital signal processing circuit (742). The UL signal control circuit (741) may obtain (or generate) a control signal for controlling the UL digital signal processing circuit (742) based on a C-plane message. The UL signal control circuit (741) may transmit (or provide, transfer) the obtained control signal to the UL digital signal processing circuit (742). The UL digital signal processing circuit (742) may obtain UL traffic through the analog signal processing circuit (730). The fronthaul signal processing circuit (710) may obtain a UL U-plane packet based on the control signal. The UL U-plane packet may be transmitted to the DU (701) through the fronthaul signal processing circuit (710).

According to one embodiment, when the RU (702) operates based on the TDD method, within the DL section, the power saving control circuit (750) may generate a signal (UL_PWRSV_CTRL) for setting the state of the UL signal control circuit (741) and/or the UL digital signal processing circuit (742) to an idle state. The power saving control circuit (750) may transmit the signal (UL_PWRSV_CTRL) for setting the state of the UL signal control circuit (741) and/or the UL digital signal processing circuit (742) to the UL signal control circuit (741) and/or the UL digital signal processing circuit (742). The UL signal control circuit (741) and/or the UL digital signal processing circuit (742) may operate in an idle state based on the signal received from the power saving control circuit (750).

According to one embodiment, when the RU (702) operates based on the TDD method, within the UL section, the power saving control circuit (750) may generate a signal (DL_PWRSV_CTRL) for setting the state of the DL signal control circuit (721) and/or the DL digital signal processing circuit (722) to an idle state. The power saving control circuit (750) may transmit the signal (DL_PWRSV_CTRL) for setting the state of the DL signal control circuit (721) and/or the DL digital signal processing circuit (722) to an idle state to the DL signal control circuit (721) and/or the DL digital signal processing circuit (722). The DL signal control circuit (721) and/or the DL digital signal processing circuit (722) may operate in an idle state based on the signal received from the power saving control circuit (750).

According to one embodiment, the power saving control circuit (750) can obtain at least one control signal for setting the state of at least one of the components of the RU (702) (e.g., the DL signal control circuit (721), the DL digital signal processing circuit (722), the UL signal control circuit (741), and/or the UL digital signal processing circuit (742)) to an idle state based on a C-plane packet. The power saving control circuit (750) can set the state of at least one of the components of the RU (702) to an idle state by transmitting the obtained at least one control signal to at least one of the components (e.g., the DL signal control circuit (721), the DL digital signal processing circuit (722), the UL signal control circuit (741), and/or the UL digital signal processing circuit (742)). Hereinafter, an example of the structure and operation of a power saving circuit (750) for obtaining a control signal for setting the state of at least one of the components of the RU (702) to an idle state based on a C-plane packet will be described.

Figure 8 shows an example of a simplified structure of a power saving control circuit.

Figure 9 shows an example of a C-plane packet.

Referring to FIG. 8, the power saving control circuit (750) may include a C-plane packet processing circuit (751), a DL power saving control circuit (752), and a UL power saving control circuit (753).

The C-plane packet processing circuit (751) may be configured to process a C-plane packet received from the DU (701). For example, the C-plane packet processing circuit (751) may be configured to obtain information required for generating at least one control signal to set the state of at least one of the components of the RU (702) (e.g., the DL signal control circuit (721), the DL digital signal processing circuit (722), the UL signal control circuit (741), and/or the UL digital signal processing circuit (742)) to an idle state based on the C-plane packet. An example of a C-plane packet will be described later in FIG. 9.

Referring to FIG. 9, the C-plane packet (900) can be used to indicate resources that are not used for transmitting and/or receiving signals. For example, the section type of the C-plane packet (900) can be set to 0. When the section type of the C-plane packet (900) is set to 0, the C-plane packet (900) can indicate resources that are not used for transmitting and/or receiving signals.

A C-plane packet (900) may include transport header (e.g., eCPRI header or IEEE 1914.3) information (910), common header information (920), first section information (930-1), first section extension information (930-2), second session information (940-1), and second session extension information (940-2). An example in which the C-plane packet (900) illustrated in FIG. 9 includes a first U-plane message including the first section information (930-1) and the first section extension information (930-2) and a second U-plane message including the second session information (940-1) and the second session extension information (940-2) is shown, but this is exemplary and not limited thereto.

The transmission header information (910) may include 'ecpriVersion', 'ecpriReserved', 'ecpriConcatenation', 'ecpriMessage', 'ecpriPayload', 'ecpriRtcid/ecpriPcid', and 'ecpriSeqid' as described above.

Common header information (920) may include 'dataDirection' indicating the data transmission direction of the base station (e.g., gNB), 'payloadVersion' indicating the valid payload protocol version of IEs in the application layer, and 'filterindex' indicating the index for the channel filter between IQ data and the air interface to be used in both DL and UL.

The common header information (920) may include information indicating the location of a time resource to which a message is applicable. The location of the time resource may be indicated by a frame, a subframe, a slot, or a symbol. The common header information (920) may include 'frameId' indicating a frame number, 'subframeId' indicating a subframe number, 'slotId' indicating a slot number, and 'startSymbolId' indicating a symbol number. A frame is determined based on a 256 modulo operation. A subframe has a unit of 1 ms included in a 10 ms frame. Slot numbers are numbered within a subframe, and the maximum size may be 1, 2, 4, 8, or 16 depending on the numerology.

The common header information (920) may include 'numberOfsections' indicating the number of data sections (hereinafter, 'sections') included in the C-plane packet. The common header information (920) may include 'sectionType' determining the characteristics of the C-plane data. According to an embodiment, the 'sectionType' of the common header information (920) may indicate 0. According to an embodiment, the common header information (920) may include a wireless application header (921).

Common header information (920) may include 'timeOffset' indicating a time offset. Common header information (920) may include 'frameStructure' indicating a frame structure. Common header information (920) may include 'cpLength' indicating a CP (cyclic prefix) length. Common header information (920) may include a reserved field.

Each of the first section information (930-1) and the second section information (940-1) is layer-specific information and may include information regarding resources allocated in one slot (e.g., 14 symbols). In the C-plane and the U-plane, a section may refer to an area to which resources are allocated. For example, one section may represent a resource area for N RBs in the frequency domain (e.g., N is 1 to 273 according to the current NR standard) and M symbols in the time domain (e.g., N is 1 to 14 according to the current NR standard) in a resource grid expressed as time-frequency resources.

Each of the first section information (930-1) and the second section information (940-1) may include 'sectionId' meaning a section identifier. Each of the first section information (930-1) and the second section information (940-1) may include 'rb' indicating whether every RB is used or every other RB is used, 'symInc' meaning a symbol number increment command, 'startPrbc' indicating a starting PRB number of a data section description, 'numPrbc' indicating the number of consecutive PRBs per data section description, 'reMask' defining an RE mask within a PRB, 'numSymbol' defining the number of PRACH (physical random access channel) repetitions or the number of symbols to which section control is applied, 'ef' indicating an extension flag, and 'beamId' defining a beam pattern to be applied to U-plane data. For example, as the value of 'ef' is set to 1, the C-plane packet (900) may include the first section extension information (930-2) or the second section extension information (940-2). The first section extension information (930-2) or the second section extension information (940-2) may be selectively included in the C-plane packet (900) depending on the value of 'ef'.

For example, each of the first section extension information (930-2) or the second section extension information (940-2) may include information regarding group configuration for multiple ports. The first section extension information (930-2) or the second section extension information (940-2) may be configured based on at least one section extension type among a plurality of section extension types.

Referring back to FIG. 8, the C-plane packet processing circuit (751) may acquire sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE based on the C-plane packet. For example, sectionType may be composed of 8 bits. dataDirection may be composed of 1 bit. slotId may be composed of 6 bits. startSymbol may be composed of 6 bits. numSymbol may be composed of 4 bits. startPrbc may be composed of 10 bits. numPrbc may be composed of 8 bits. CP_UPDATE may be composed of 1 bit. sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, and numPrbc may be included in a C-plane packet (e.g., the C-plane packet (900) of FIG. 9). For example, CP_UPDATE may be used to indicate that all data for a section has been acquired. The C-plane packet processing circuit (751) may set the value of CP_UPDATE to a specified value (e.g., '1') when all data for a section has been acquired based on the C-plane packet.

According to one embodiment, the C-plane packet processing circuit (751) may transmit (or provide, transfer) sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE to the DL power saving control circuit (752) and the UL power saving control circuit (753).

According to one embodiment, the DL power saving control circuit (752) may receive information about an idle section in which a DL signal is not transmitted (e.g., sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE) from the C-plane packet processing circuit (751). The DL power saving control circuit (752) may set the state of at least one component of the DL digital signal processing circuit (722) to an idle state based on information about DL timing (e.g., DL_SLOT_IDX, DL_SYMBOL_SYNC, DL_SYMBOL_IDX, and/or DL_RB_IDX).

For example, the DL power saving control circuit (752) may receive sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE from the C-plane packet processing circuit (751). The DL power saving control circuit (752) may receive DL_SLOT_IDX, DL_SYMBOL_SYNC, DL_SYMBOL_IDX, and/or DL_RB_IDX. The DL power saving control circuit (752) can obtain DL_PWRSV_CTRL_SYM and/or DL_PWRSV_CTRL_RB based on sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, CP_UPDATE, DL_SLOT_IDX, DL_SYMBOL_SYNC, DL_SYMBOL_IDX, and/or DL_RB_IDX.

For example, DL_SLOT_IDX can indicate the index of a slot for a DL signal. DL_SLOT_IDX can be set to 6 bits. DL_SYMBOL_SYNC can be used for symbol synchronization for a DL signal. DL_SYMBOL_SYNC can be set to 1 bit. DL_SYMBOL_IDX can indicate the index of a symbol for a DL signal. DL_SYMBOL_IDX can be set to 4 bits. DL_RB_IDX can indicate the index of an RB for a DL signal. DL_RB_IDX can be set to 10 bits.

For example, DL_PWRSV_CTRL_RB can be used to set the state of a component (e.g., the first DL signal processing circuit (761)) for processing a signal in a frequency domain of the DL digital signal processing circuit (722) to an idle state. DL_PWRSV_CTRL_RB can be set to 1 bit. Based on DL_PWRSV_CTRL_RB being set to a specified value (e.g., 1), the state of a component (e.g., the first DL signal processing circuit (761)) for processing a signal in a frequency domain of the DL digital signal processing circuit (722) can be set to an idle state.

For example, DL_PWRSV_CTRL_SYM can be used to set the state of a component (e.g., the second DL signal processing circuit (762)) for processing a time domain signal of the DL digital signal processing circuit (722) to an idle state. DL_PWRSV_CTRL_SYM can be set to 1 bit. Based on DL_PWRSV_CTRL_SYM being set to a specified value (e.g., 1), the state of a component (e.g., the second DL signal processing circuit (762)) for processing a time domain signal of the DL digital signal processing circuit (722) can be set to an idle state.

According to one embodiment, the UL power saving control circuit (753) may receive information about an idle section in which a UL signal is not transmitted (e.g., sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE). The UL power saving control circuit (753) may set the state of at least one component of the UL digital signal processing circuit (742) to an idle state based on information about UL timing (e.g., UL_SLOT_IDX, UL_SYMBOL_SYNC, UL_SYMBOL_IDX, and/or UL_RB_IDX).

For example, the UL power saving control circuit (753) may receive sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE from the C-plane packet processing circuit (751). The UL power saving control circuit (753) may receive UL_SLOT_IDX, UL_SYMBOL_SYNC, UL_SYMBOL_IDX, and/or UL_RB_IDX. The UL power saving control circuit (753) can obtain UL_PWRSV_CTRL_SYM and/or UL_PWRSV_CTRL_RB based on sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, CP_UPDATE, UL_SLOT_IDX, UL_SYMBOL_SYNC, UL_SYMBOL_IDX, and/or UL_RB_IDX.

For example, UL_SLOT_IDX can indicate the index of a slot for a UL signal. UL_SLOT_IDX can be set to 6 bits. UL_SYMBOL_SYNC can be used for symbol synchronization for a UL signal. UL_SYMBOL_SYNC can be set to 1 bit. UL_SYMBOL_IDX can indicate the index of a symbol for a UL signal. UL_SYMBOL_IDX can be set to 4 bits. UL_RB_IDX can indicate the index of an RB for a UL signal. UL_RB_IDX can be set to 10 bits.

For example, UL_PWRSV_CTRL_RB may be used to set the state of a component (e.g., the second UL signal processing circuit (772)) for processing a signal in a frequency domain of the UL digital signal processing circuit (742) to an idle state. UL_PWRSV_CTRL_RB may be set to 1 bit. Based on UL_PWRSV_CTRL_RB being set to a specified value (e.g., 1), the state of a component (e.g., the second UL signal processing circuit (772)) for processing a signal in a frequency domain of the UL digital signal processing circuit (742) may be set to an idle state.

For example, UL_PWRSV_CTRL_SYM can be used to set the state of a component (e.g., the second UL signal processing circuit (772)) for processing a time domain signal of the UL digital signal processing circuit (742) to an idle state. UL_PWRSV_CTRL_SYM can be set to 1 bit. Based on UL_PWRSV_CTRL_SYM being set to a specified value (e.g., 1), the state of a component (e.g., the second UL signal processing circuit (772)) for processing a time domain signal of the UL digital signal processing circuit (742) can be set to an idle state.

Fig. 10 illustrates an example of the operation of a C-plane packet processing circuit for obtaining information included in a C-plane packet.

Referring to FIG. 10, in operation 1010, the C-plane packet processing circuit (751) can obtain a C-plane packet (e.g., the C-plane packet (900) of FIG. 9). For example, the C-plane packet processing circuit (751) can obtain a C-plane packet from the DU (701).

In operation 1020, the C-plane packet processing circuit (751) can identify the transmission header of the C-plane packet (e.g., the transmission header information (910) of FIG. 9). For example, the C-plane packet processing circuit (751) can identify the transmission header of the C-plane packet based on parsing the transmission header of the C-plane packet. The C-plane packet processing circuit (751) can obtain ecpriRtcid/ecpriPcid based on identifying the transmission header of the C-plane packet.

In operation 1030, the C-plane packet processing circuit (751) can identify a common header (e.g., common header information (920) of FIG. 9). For example, the C-plane packet processing circuit (751) can identify the common header of the C-plane packet based on parsing the common header. The C-plane packet processing circuit (751) can obtain sectionType, dataDirection, slotId, startSymbol, numberOfsections, and sectionType based on identifying the common header of the C-plane packet.

In operation 1040, the C-plane packet processing circuit (751) can identify whether the section type of the C-plane packet is 0. The C-plane packet processing circuit (751) can identify whether the section type of the C-plane packet is 0 to identify whether the C-plane packet indicates a resource that is not used for transmitting and/or receiving a signal. For example, the C-plane packet processing circuit (751) can perform operation 1080 when the section type of the C-plane packet is not 0. The C-plane packet processing circuit (751) can perform operation 1080 based on the section type of the C-plane packet being not 0.

In operation 1050, if the section type of the C-plane packet is 0, the C-plane packet processing circuit (751) can identify section information (e.g., the first section information (930-1) or the second section information (940-1) of FIG. 9). The C-plane packet processing circuit (751) can identify section information (e.g., the first section information (930-1) or the second section information (940-1) of FIG. 9) based on the section type of the C-plane packet being 0.

For example, the C-plane packet processing circuit (751) can identify section information of a C-plane packet based on parsing the section information. The C-plane packet processing circuit (751) can obtain startPrbc, numPrbc, reMask, and numsymbol based on identifying the section information of the C-plane packet.

In operation 1060, the C-plane packet processing circuit (751) can identify whether section extension information exists. The C-plane packet processing circuit (751) can identify whether section extension information exists based on whether the value of ef is 1. For example, if section extension information does not exist, the C-plane packet processing circuit (751) can perform operation 1080.

In operation 1070, if section extension information exists, the C-plane packet processing circuit (751) can identify the section extension information. The C-plane packet processing circuit (751) can identify the section extension information based on the existence of the section extension information.

In operation 1080, the C-plane packet processing circuit (751) can identify whether information about all sections included in the C-plane packet has been obtained. The C-plane packet can include information about at least one section. Therefore, the C-plane packet processing circuit (751) can identify whether information about all sections has been obtained in order to obtain information about all sections included in the C-plane packet. For example, if information about all sections has not been obtained, the C-plane packet processing circuit (751) can obtain information about other sections by performing operation 1040.

In operation 1090, the C-plane packet processing circuit (751) can output the acquired information. If information about all sections is acquired, the C-plane packet processing circuit (751) can set the value of CP_UPDATE to a designated value (e.g., 1). For example, the C-plane packet processing circuit (751) can transmit (or provide, transfer) the acquired information (e.g., sectionType, dataDirection, slotId, startSymbol, numSymbol, startPrbc, numPrbc, and/or CP_UPDATE) to the DL power saving control circuit (752) and the UL power saving control circuit (753).

Figures 11a and 11b illustrate examples of sections indicated via C-plane packets.

Referring to FIGS. 11A and 11B , a C-plane packet can indicate at least one section. For example, a C-plane packet can be used to indicate resource blocks or symbols that are not used in the DL or UL within a single slot. The section type of a C-plane packet can be set to 0.

According to one embodiment, a C-plane packet may include at least one C-plane message. One C-plane message may indicate information about one section. For example, a C-plane packet may indicate information about three sections. The C-plane packet may indicate information about a first section, information about a second section, and information about a third section.

For example, the section ID of the first section may be set to k. The ID of the start symbol of the first section (or startSymbolID) may be set to 0. The number of symbols of the first section (or numSymbol) may be set to 5. The index of the start RB of the first section (or startPrbc) may be set to e. The number of RBs of the first section (or numPrbc) may be set to f.

For example, the section ID of the second section may be set to m. The ID of the start symbol of the second section (or startSymbolID) may be set to 1. The number of symbols of the second section (or numSymbol) may be set to 3. The index of the start RB of the second section (or startPrbc) may be set to a. The number of RBs of the second section (or numPrbc) may be set to b.

For example, the section ID of the third section may be set to n. The ID of the starting symbol of the third section (or startSymbolID) may be set to 4. The number of symbols of the third section (or numSymbol) may be set to 2. The index of the starting RB of the third section (or startPrbc) may be set to c. The number of RBs of the third section (or numPrbc) may be set to d.

Referring to FIG. 11A, on a resource grid (1100) composed of symbols (or time) and RBs (or frequencies), a first region (1110) may represent resources (e.g., symbols or RBs) allocated for a first section. A second region (1120) may represent resources (e.g., symbols or RBs) allocated for a second section. A third region (1130) may represent resources (e.g., symbols or RBs) allocated for a third section.

For example, since the section type of the C-plane packet is set to 0, resources corresponding to the first region (1110), the second region (1120), and the third region (1130) may be set not to be used in the data transmission direction (e.g., DL or UL) indicated through dataDirection.

Referring to FIG. 11b, a symbol-by-symbol spectrum according to the resources allocated for the first section, the second section, and the third section can be illustrated.

Within the 0th symbol (symbol #0), resources for the first section can be allocated from RB index e to RB index (e+f-1).

Within the first symbol (symbol #1), resources for the first section from RB index e to RB index (e+f-1) and resources for the second section from RB index a to RB index (a+b-1) can be allocated.

Within the second symbol (symbol #2), resources for the first section from RB index e to RB index (e+f-1) and resources for the second section from RB index a to RB index (a+b-1) can be allocated.

Within the third symbol (symbol #3), resources for the first section from RB index e to RB index (e+f-1) and resources for the second section from RB index a to RB index (a+b-1) can be allocated.

Within the 4th symbol (symbol #4), resources for the first section from RB index e to RB index (e+f-1) and resources for the third section from RB index c to RB index (c+d-1) can be allocated.

Within the 5th symbol (symbol #5), resources for the third section from RB index c to RB index (c+d-1) can be allocated.

According to one embodiment, the DL power saving control circuit (752) and the UL power saving control circuit (753) illustrated in FIG. 8 may generate a control signal to set resources corresponding to the first to third sections not to be used according to slot timing and symbol timing based on information obtained from the C-plane packet processing circuit (751). For example, regions allocated to C-plane packets of section type 0 (e.g., the first region (1110), the second region (1120), and the third region) may be allocated with the resolution of a resource block. For example, in a TDD system, a region in which dataDirection is not set to '1' (or DL) may be set as an idle region within a region allocated for DL. Hereinafter, examples of the structure and operation of each of the DL power saving control circuit (752) and the UL power saving control circuit (753) will be described.

Fig. 12 shows an example of the structure of a DL power saving control circuit.

Referring to FIG. 12, the DL power saving control circuit (752) may include a power saving control signal generation circuit (1210), a bit concatenation circuit (1220), a write control circuit (1230), a power saving control memory (1240), a read control circuit (1250), and a power saving align circuit (1260).

According to one embodiment, the power saving control signal generation circuit (1210) can obtain (or generate) DL_PWRSV_CTRL_RB and DL_PWRSV_CTRL_SYM based on sectionType and dataDirection.

DL_PWRSV_CTRL_RB can be used to set the state of a component (e.g., the first DL signal processing circuit (761)) for processing a signal in a frequency domain of the DL digital signal processing circuit (722) to an idle state. DL_PWRSV_CTRL_RB can be set to 1 bit. Based on DL_PWRSV_CTRL_RB being set to a specified value (e.g., 1), the state of a component (e.g., the first DL signal processing circuit (761)) for processing a signal in a frequency domain of the DL digital signal processing circuit (722) can be set to an idle state.

For example, DL_PWRSV_CTRL_SYM can be used to set the state of a component (e.g., the second DL signal processing circuit (762)) for processing a time domain signal of the DL digital signal processing circuit (722) to an idle state. DL_PWRSV_CTRL_SYM can be set to 1 bit. Based on DL_PWRSV_CTRL_SYM being set to a specified value (e.g., 1), the state of a component (e.g., the second DL signal processing circuit (762)) for processing a time domain signal of the DL digital signal processing circuit (722) can be set to an idle state.

An algorithm for representing the operation of the power saving control signal generation circuit (1210) can be configured as shown in the table below.

Referring to Table 3, MaxRB may indicate the maximum number of RBs that can be processed by the DL digital signal processing circuit (722). When dataDirection is 1, section type is 0, and the number of at least one RB allocated to the section (numPrbc) corresponds to the maximum number of RBs, the state of the first DL signal processing circuit (761) included in the DL digital signal processing circuit (722) may be set to an idle state. When the number of at least one RB allocated to the section (numPrbc) corresponds to the maximum number of RBs, all RBs that can be processed by the DL digital signal processing circuit (722) may not be used. Therefore, the state of the second DL signal processing circuit (762) included in the DL digital signal processing circuit (722) may be set to an idle state.

For example, if dataDirection is 1, section type is 0, and the number of at least one RB allocated to the section (numPrbc) is less than the maximum number of RBs, the state of the first DL signal processing circuit (761) for the section may be set to an idle state. If the number of at least one RB (numPrbc) is less than the maximum number of RBs, a signal is transmitted in the entire section of the corresponding symbol even if only one RB is allocated. Therefore, the state of the second DL signal processing circuit (762) may be set to an active state.

For example, if dataDirection is 1 and section type is not 0, the C-plane packet may not indicate unused resources. Accordingly, the states of the first DL signal processing circuit (761) and the second DL signal processing circuit (762) may be set to an active state.

For example, if dataDirection is not 1, the C-plane packet may contain information about the UL signal. Accordingly, the states of the first DL signal processing circuit (761) and the second DL signal processing circuit (762) may be set to an idle state.

According to one embodiment, the bit concatenation circuit (1220) may obtain (or generate) WriteData based on DL_PWRSV_CTRL_RB, DL_PWRSV_CTRL_SYM, and endPrbc. For example, endPrbc may be obtained based on startPrbc and numPrbc. endPrbc may be set to the sum of startPrbc and numPrbc. WriteData may be data to be stored in the power saving control memory (1240). For example, WriteData may be set to 22 bits.

According to one embodiment, the write control circuit (1230) may obtain (or generate) WriteEnable_A and WriteAddress_A based on CP_UPDATE, slotID, startSymbol, and endSymbol. For example, endSymbol may be obtained based on startSymbol and numSymbol. endSymbol may be set to the sum of startSymbol and numSymbol.

An algorithm for representing the operation of the write control circuit (1230) can be configured as shown in the table below.

Referring to Table 4, write_en is an example of writeEnable_A. write_addr is an example of WriteAddress_A. The write control circuit (1230) may be configured to identify an address for storing (or writing) WriteData to the power saving control memory (1240).

According to one embodiment, the power saving control memory (1240) may be configured to store information for a control signal for the DL digital signal processing circuit (722) (or, the first DL signal processing circuit (761) or the second DL signal processing circuit (762)). An example of the structure of the power saving control memory (1240) will be described later in FIG. 13.

According to one embodiment, the read control circuit (1250) can obtain (or generate) WriteEnable_B, ReadEnable_B, Address_B, and WriteData_B based on DL_SLOT_IDX and DL_SYMBOL_IDX.

An algorithm for representing the operation of the read control circuit (1250) can be configured as shown in the table below.

Referring to Table 5, write_en is an example of writeEnable_B. read_en is an example of readEnable_B. addr is an example of Address_B. write_data is an example of Writedata_B. The read control circuit (1250) may be configured to identify an address for reading ReadData from the power saving control memory (1240).

According to one embodiment, the power saving adjustment circuit (1260) can obtain (or generate) DL_PWRSV_CTRL_RB and DL_PWRSV_CTRL_SYM based on ReadData.

An algorithm for representing the operation of the power saving adjustment circuit (1260) can be configured as shown in the table below.

Referring to Table 6, PWRSV_CTRL_RB is an example of DL_PWRSV_CTRL_RB. PWRSV_CTRL_SYM is an example of DL_PWRSV_CTRL_SYM. The power saving adjustment circuit (1260) may be configured to obtain DL_PWRSV_CTRL_RB and DL_PWRSV_CTRL_SYM stored in the power saving control memory (1240) from the corresponding symbol or the corresponding slot.

Figure 13 illustrates an example of a simplified structure of a power saving control memory.

Referring to FIG. 13, the power saving control memory (1240) may be configured to store information for a control signal for the DL digital signal processing circuit (722) (or the first DL signal processing circuit (761) or the second DL signal processing circuit (762)).

For example, in the power saving control memory (1240), addresses (1310) for even slots and addresses (1320) for odd slots may be set according to the value of the least significant bit (LSB) of slotId. Depending on the address, DL_PWRSV_CTRL_SYM, DL_PWRSV_CTRL_RB, endPrbc, and/or startPrbc may be stored.

According to the DL signal processing timing of the DL digital signal processing circuit (722), data (e.g., PWRSV CTRL Data) stored in the power saving control memory (1240) may be read. In this case, DL_PWRSV_CTRL_SYM may be activated during a symbol period, and DL_PWRSV_CTRL_RB may be activated during a frequency period from an RB index according to startPrbc to an RB index according to endPrbc (e.g., endPrbc-1). For example, DL_PWRSV_CTRL_SYM may be set to 1 during a symbol period, and DL_PWRSV_CTRL_RB may be set to 1 during a frequency period from an RB index according to startPrbc to an RB index according to endPrbc (e.g., endPrbc-1).

Referring to the algorithm in Table 5, there may be unallocated areas for sections on the resource grid. To allow idle operation within these areas, DL_PWRSV_CTRL_SYM and/or DL_PWRSV_CTRL_RB may be set to 1'b1 when the read operation for each symbol is completed.

Figures 14a and 14b illustrate examples of the operation of a power saving control circuit.

Referring to FIGS. 14A and 14B, as illustrated in FIG. 8, the power saving control circuit (750) may include a C-plane packet processing circuit (751), a DL power saving control circuit (752), and a UL power saving control circuit (753). Within a section for the RU (702) to transmit a DL signal, the C-plane packet processing circuit (751) and the DL power saving control circuit (752) may operate.

Fig. 14a shows an example of the operation of the power saving control circuit (750) in slot #(a-1) and slot #a. Fig. 14b shows an example of the operation of the power saving control circuit (750) to perform power saving for symbol #0 of slot #a in sections (1410, 1420, 1430). Time section (1410) may be associated with a section in which DL_SYMBO_IDX indicates symbol #12 of slot #(a-1). Time section (1420) may be associated with a section in which DL_SYMBO_IDX indicates symbol #13 of slot #(a-1). Time section (1440) may be associated with a section in which DL_SYMBO_IDX indicates symbol #0 of slot #a.

Within a time interval (1410), a C-plane packet processing circuit (751) may receive a C-plane packet (1411) from a DU (701). The C-plane packet (1411) may be configured to indicate unused resources for a DL signal. The section type of the C-plane packet (1411) may be set to 0.

The C-plane packet processing circuit (751) can obtain sectionType, dataDirection, slotID, startSymbol, startPrbc, and numPrbc based on the C-plane packet (1411). The C-plane packet processing circuit (751) can set the value of CP_UPDATE to 1 based on obtaining information on all sections set within slot #a.

Although not shown, the power saving control memory (1240) can store the acquired information.

Within a time interval (1431) including a portion of the time interval (1420) and the time interval (1430), the read control circuit (1250) can transmit (or provide, transfer) WriteEnalbe_B, ReadEnable_B, Address_B, and WriteData_B to the power saving control memory (1240) to obtain (or read) stored information from the power saving control memory (1240).

The power saving control memory (1240) can output ReadData based on WriteEnable_B, ReadEnable_B, Address_B, and WriteData_B. The time interval (1433) refers to the delay time of the power saving control memory (1240).

For example, if startPrbc points to c and endPrbc points to e, DL_PWRSV_CTRL_RB may be output as 1 while DL_RB_IDX points from c to e (or during the time interval (1434)). Since the number of unused RBs is less than MaxRB, DL_PWRSV_CTRL_SYM may be output as 0 while DL_RB_IDX points from c to e (or during the time interval (1434)).

According to one embodiment, the power saving control circuit (750) can transmit (or provide, transmit) DL_PWRSV_CTRL_RB and DL_PWRSV_CTRL_SYM to the DL signal control circuit (721) and the DL digital signal processing circuit (722).

A DL signal for slot #a may be transmitted through the DL digital signal processing circuit (722). While the DL signal for slot #a is transmitted, the DL signal control circuit (721) and the DL digital signal processing circuit (722) may operate in an idle state within the corresponding section based on DL_PWRSV_CTRL_RB and DL_PWRSV_CTRL_SYM. For example, while DL_PWRSV_CTRL_RB is set to 1, the state of the first DL signal processing circuit (761) of the DL digital signal processing circuit (722) may be set to an idle state. For example, while DL_PWRSV_CTRL_SYM is set to 1, the state of the second DL signal processing circuit (762) of the DL digital signal processing circuit (722) may be set to an idle state.

Fig. 15 shows an example of the structure of a UL power saving control circuit.

Referring to FIG. 15, the UL power saving control circuit (753) may include a power saving control signal generation circuit (1510), a bit concatenation circuit (1520), a write control circuit (1530), a power saving control memory (1540), a read control circuit (1550), and a power saving align circuit (1560).

According to one embodiment, the power saving control signal generation circuit (1510) can obtain (or generate) UL_PWRSV_CTRL_RB and UL_PWRSV_CTRL_SYM based on sectionType and dataDirection.

UL_PWRSV_CTRL_RB may be used to set the state of a component (e.g., the first UL signal processing circuit (771)) for processing a signal in a frequency domain of the UL digital signal processing circuit (742) to an idle state. UL_PWRSV_CTRL_RB may be set to 1 bit. Based on UL_PWRSV_CTRL_RB being set to a specified value (e.g., 1), the state of a component (e.g., the first UL signal processing circuit (771)) for processing a signal in a frequency domain of the UL digital signal processing circuit (742) may be set to an idle state.

For example, UL_PWRSV_CTRL_SYM can be used to set the state of a component (e.g., the second UL signal processing circuit (772)) for processing a time domain signal of the UL digital signal processing circuit (742) to an idle state. UL_PWRSV_CTRL_SYM can be set to 1 bit. Based on UL_PWRSV_CTRL_SYM being set to a specified value (e.g., 1), the state of a component (e.g., the second UL signal processing circuit (772)) for processing a time domain signal of the UL digital signal processing circuit (742) can be set to an idle state.

An algorithm for representing the operation of the power saving control signal generation circuit (1510) can be configured as shown in the table below.

Referring to Table 7, MaxRB may indicate the maximum number of RBs that can be processed by the UL digital signal processing circuit (742). When dataDirection is 0, section type is 0, and the number of at least one RB allocated to the section (numPrbc) corresponds to the maximum number of RBs, the state of the first UL signal processing circuit (771) included in the UL digital signal processing circuit (742) may be set to an idle state. When the number of at least one RB allocated to the section (numPrbc) corresponds to the maximum number of RBs, all RBs that can be processed by the UL digital signal processing circuit (742) may not be used. Therefore, the state of the second UL signal processing circuit (772) included in the UL digital signal processing circuit (742) may be set to an idle state.

For example, if dataDirection is 0, section type is 0, and the number of at least one RB allocated to the section (numPrbc) is less than the maximum number of RBs, the state of the first UL signal processing circuit (771) for the section may be set to an idle state. If the number of at least one RB (numPrbc) is less than the maximum number of RBs, a signal is transmitted in the entire section of the corresponding symbol even if only one RB is allocated. Therefore, the state of the second UL signal processing circuit (772) may be set to an active state.

For example, if dataDirection is 0 and section type is not 0, the C-plane packet may not indicate unused resources. Accordingly, the states of the first UL signal processing circuit (771) and the second UL signal processing circuit (772) may be set to an active state.

For example, if dataDirection is not 0, the C-plane packet may contain information about a DL signal. Accordingly, the states of the first UL signal processing circuit (771) and the second UL signal processing circuit (772) may be set to an idle state.

According to one embodiment, the bit concatenation circuit (1520) may obtain (or generate) WriteData based on UL_PWRSV_CTRL_RB, UL_PWRSV_CTRL_SYM, and endPrbc. For example, endPrbc may be obtained based on startPrbc and numPrbc. endPrbc may be set to the sum of startPrbc and numPrbc. WriteData may be data to be stored in the power saving control memory (1540). For example, WriteData may be set to 22 bits.

According to one embodiment, the write control circuit (1530) may obtain (or generate) WriteEnable_A and WriteAddress_A based on CP_UPDATE, slotID, startSymbol, and endSymbol. For example, endSymbol may be obtained based on startSymbol and numSymbol. endSymbol may be set to the sum of startSymbol and numSymbol.

An algorithm for representing the operation of the write control circuit (1530) can be configured as shown in the table below.

Referring to Table 8, write_en is an example of writeEnable_A. write_addr is an example of WriteAddress_A. The write control circuit (1530) may be configured to identify an address for storing (or writing) WriteData in the power-saving control memory (1540). The algorithm according to Table 8 may correspond to the algorithm according to Table 4.

According to one embodiment, the power saving control memory (1540) may be configured to store information for a control signal for the UL digital signal processing circuit (742) (or the first UL signal processing circuit (771) or the second UL signal processing circuit (772)). An example of the structure of the power saving control memory (1540) will be described later in FIG. 16.

According to one embodiment, the read control circuit (1550) can obtain (or generate) WriteEnable_B, ReadEnable_B, Address_B, and WriteData_B based on UL_SLOT_IDX and UL_SYMBOL_IDX.

An algorithm for representing the operation of the read control circuit (1550) can be configured as shown in the table below.

Referring to Table 9, write_en is an example of writeEnable_B. read_en is an example of readEnable_B. addr is an example of Address_B. write_data is an example of Writedata_B. The read control circuit (1550) may be configured to identify an address for reading ReadData from the power saving control memory (1540).

According to one embodiment, the power saving adjustment circuit (1560) can obtain (or generate) UL_PWRSV_CTRL_RB and UL_PWRSV_CTRL_SYM based on ReadData.

An algorithm for representing the operation of the power saving adjustment circuit (1560) can be configured as shown in the table below.

Referring to Table 10, PWRSV_CTRL_RB is an example of UL_PWRSV_CTRL_RB. PWRSV_CTRL_SYM is an example of UL_PWRSV_CTRL_SYM. The power saving adjustment circuit (1560) may be configured to obtain UL_PWRSV_CTRL_RB and UL_PWRSV_CTRL_SYM stored in the power saving control memory (1540) from the corresponding symbol or the corresponding slot.

Figure 16 illustrates an example of a simplified structure of a power saving control memory.

Referring to FIG. 16, the power saving control memory (1540) may be configured to store information for a control signal for the UL digital signal processing circuit (742) (or the first UL signal processing circuit (771) or the second UL signal processing circuit (772)).

For example, in the power saving control memory (1540), addresses (1610) for even slots and addresses (1620) for odd slots may be set according to the value of the least significant bit (LSB) of slotId. Depending on the address, UL_PWRSV_CTRL_SYM, UL_PWRSV_CTRL_RB, endPrbc, and/or startPrbc may be stored.

According to the UL signal processing timing of the UL digital signal processing circuit (742), data (e.g., PWRSV CTRL Data) stored in the power saving control memory (1540) may be read. In this case, UL_PWRSV_CTRL_SYM may be activated during a symbol period, and UL_PWRSV_CTRL_RB may be activated during a frequency period from an RB index according to startPrbc to an RB index according to endPrbc (e.g., endPrbc-1). For example, UL_PWRSV_CTRL_SYM may be set to 1 during a symbol period, and UL_PWRSV_CTRL_RB may be set to 1 during a frequency period from an RB index according to startPrbc to an RB index according to endPrbc (e.g., endPrbc-1).

Referring to the algorithm in Table 9, there may be unallocated areas for sections on the resource grid. To allow idle operation within these areas, UL_PWRSV_CTRL_SYM and/or UL_PWRSV_CTRL_RB may be set to 1'b1 when the read operation for each symbol is completed.

Figures 17a and 17b illustrate examples of the operation of a power saving control circuit.

Referring to FIGS. 17A and 17B, as illustrated in FIG. 8, the power saving control circuit (750) may include a C-plane packet processing circuit (751), a UL power saving control circuit (753), and a UL power saving control circuit (753). Within a period in which the RU (702) transmits a UL signal, the C-plane packet processing circuit (751) and the UL power saving control circuit (753) may operate.

Fig. 17a shows an example of the operation of the power saving control circuit (750) in slot #(a-1) and slot #a. Fig. 17b shows an example of the operation of the power saving control circuit (750) to perform power saving for symbol #0 of slot #a in sections (1710, 1720, 1730). Time section (1710) may be associated with a section in which UL_SYMBO_IDX indicates symbol #15 of slot #(a-1). Time section (1720) may be associated with a section in which UL_SYMBO_IDX indicates symbol #16 of slot #(a-1). Time section (1740) may be associated with a section in which UL_SYMBO_IDX indicates symbol #0 of slot #a.

Within a time interval (1710), a C-plane packet processing circuit (751) may receive a C-plane packet (1711) from a DU (701). The C-plane packet (1711) may be configured to indicate unused resources for UL signals. The section type of the C-plane packet (1711) may be set to 0.

The C-plane packet processing circuit (751) can obtain sectionType, dataDirection, slotID, startSymbol, startPrbc, and numPrbc based on the C-plane packet (1711). The C-plane packet processing circuit (751) can set the value of CP_UPDATE to 1 based on obtaining information on all sections set within slot #a.

Although not shown, the power saving control memory (1540) can store the acquired information.

Within a time interval (1731) including a portion of the time interval (1720) and the time interval (1730), the read control circuit (1550) can transmit (or provide, transfer) WriteEnalbe_B, ReadEnable_B, Address_B, and WriteData_B to the power saving control memory (1540) to obtain (or read) stored information from the power saving control memory (1540).

The power saving control memory (1540) can output ReadData based on WriteEnable_B, ReadEnable_B, Address_B, and WriteData_B. The time interval (1733) refers to the delay time of the power saving control memory (1540).

For example, if startPrbc points to c and endPrbc points to e, UL_PWRSV_CTRL_RB may be output as 1 while UL_RB_IDX points from c to e (or during the time interval (1734)). Since the number of unused RBs is less than MaxRB, UL_PWRSV_CTRL_SYM may be output as 0 while UL_RB_IDX points from c to e (or during the time interval (1734)).

According to one embodiment, the power saving control circuit (750) can transmit (or provide, transmit) UL_PWRSV_CTRL_RB and UL_PWRSV_CTRL_SYM to the UL signal control circuit (721) and the UL digital signal processing circuit (742).

A UL signal for slot #a may be transmitted through the UL digital signal processing circuit (742). While the UL signal for slot #a is transmitted, the UL signal control circuit (721) and the UL digital signal processing circuit (742) may operate in an idle state within the corresponding section based on UL_PWRSV_CTRL_RB and UL_PWRSV_CTRL_SYM. For example, while UL_PWRSV_CTRL_RB is set to 1, the state of the first UL signal processing circuit (771) of the UL digital signal processing circuit (742) may be set to an idle state. For example, while UL_PWRSV_CTRL_SYM is set to 1, the state of the second UL signal processing circuit (772) of the UL digital signal processing circuit (742) may be set to an idle state.

FIG. 18a illustrates an example of a first DL signal processing circuit or a first UL signal processing circuit.

FIG. 18b illustrates an example of a second DL signal processing circuit or a second UL signal processing circuit.

Referring to FIG. 18A, the circuit for the operation block (1810) may be included in the DL digital signal processing circuit (722) or the UL digital signal processing circuit (742). For example, the circuit for the operation block (1810) may be included in the first DL signal processing circuit (761) for processing a DL signal in the frequency domain. For example, the circuit for the operation block (1810) may be included in the first UL signal processing circuit (771) for processing a UL signal in the frequency domain.

According to one embodiment, the operation block (1810) may include an OR gate (1811), a multiplier (1812), and a multiplexer (MUX) (1813). The RESET signal and PWR_CTRL_RB (e.g., DL_ PWR_CTRL_RB or UL_ PWR_CTRL_RB) may be set as inputs of the OR gate (1811). The output of the OR gate (1811) and data (or signal) in the frequency domain may be set as inputs of the multiplier (1812). The multiplier (1812) may be used to multiply the data in the frequency domain by a digital gain. The output of the multiplier (1812) and 0 may be set as inputs of the MUX (1813), and the PWR_CTRL_RB may be set as a selector input of the MUX (1813).

According to the operation block (1810), when PWR_CTRL_RB is set to 1, 0 may be output instead of frequency domain data. When PWR_CTRL_RB is set to 0, frequency domain data may be output.

For example, the first DL signal processing circuit (761) including a circuit for the operation block (1810) can output 0 when DL_PWR_CTRL_RB is 1. The first DL signal processing circuit (761) including a circuit for the operation block (1810) can output DL data (or DL signal) in a frequency domain to which a digital gain is applied (or multiplied) when DL_PWR_CTRL_RB is 0.

For example, the first UL signal processing circuit (771) including the circuit for the operation block (1810) can output 0 when UL_PWR_CTRL_RB is 1. The first UL signal processing circuit (771) including the circuit for the operation block (1810) can output UL data (or UL signal) in the frequency domain to which a digital gain is applied (or multiplied) when UL_PWR_CTRL_RB is 0.

Referring to FIG. 18B, the circuit for the operation block (1820) may be included in the DL digital signal processing circuit (722) or the UL digital signal processing circuit (742). For example, the circuit for the operation block (1820) may be included in the second DL signal processing circuit (762) for processing the DL signal in the time domain. For example, the circuit for the operation block (1820) may be included in the second UL signal processing circuit (772) for processing the UL signal in the time domain.

According to one embodiment, the operation block (1820) may include an OR gate (1821), a multiplier (1822), and a multiplexer (MUX) (1823). A RESET signal and PWR_CTRL_SYM (e.g., DL_ PWR_CTRL_SYM or UL_ PWR_CTRL_SYM) may be set as inputs of the OR gate (1821). An output of the OR gate (1821) and data (or signal) in the time domain may be set as inputs of the multiplier (1822). The multiplier (1822) may be used to multiply data in the time domain by a digital gain. The output of the multiplier (1822) and 0 may be set as inputs of the MUX (1823), and the PWR_CTRL_SYM may be set as a selector input of the MUX (1823).

According to the operation block (1820), if PWR_CTRL_SYM is set to 1, 0 may be output instead of time domain data. If PWR_CTRL_SYM is set to 0, time domain data may be output.

For example, the second DL signal processing circuit (762) including the circuit for the operation block (1820) can output 0 when DL_PWR_CTRL_SYM is 1. The second DL signal processing circuit (762) including the circuit for the operation block (1820) can output DL data (or DL signal) in the time domain to which a digital gain is applied (or multiplied) when DL_PWR_CTRL_SYM is 0.

For example, the second UL signal processing circuit (772) including the circuit for the operation block (1820) can output 0 when UL_PWR_CTRL_SYM is 1. The second UL signal processing circuit (772) including the circuit for the operation block (1820) can output UL data (or UL signal) in the time domain to which a digital gain is applied (or multiplied) when UL_PWR_CTRL_SYM is 0.

Referring to Fig. 18a, PWR_CTRL_RB may be generated depending on the point in time when data (or signal) in the frequency domain is processed. PWR_CTRL_RB may be connected to a RESET signal and used to stop the operation of the operation block (1812). As the operation of the operation block (1812) is stopped, power consumption may be reduced and the output of the operation block (1812) may be set to 0 (or masked).

Referring to Fig. 18b, PWR_CTRL_SYM can be generated depending on the point in time when time-domain data (or signal) is processed. PWR_CTRL_SYM can be connected to a RESET signal and used to stop the operation of the operation block (1822). As the operation of the operation block (1822) is stopped, power consumption is reduced and the output of the operation block (1822) can be set to 0 (or masked).

Figure 19 illustrates an example of a memory for a DL digital signal processing circuit or a UL digital signal processing circuit.

FIG. 20 illustrates an example of a memory for a second DL signal processing circuit or a second UL signal processing circuit.

Referring to FIG. 19, the memory (1900) may be configured for a DL digital signal processing circuit (722) and/or a UL digital signal processing circuit (742). For example, the memory (1900) may be configured to store frequency domain data and output frequency domain data. The memory (1900) may be configured for a first DL signal processing circuit (761) and/or a first UL signal processing circuit (771).

For example, the memory (1900) may be configured to store time domain data and output time domain data. The memory (1900) may be configured for the second DL signal processing circuit (762) and/or the second UL signal processing circuit (772).

According to one embodiment, BUF_EN_A', BUF_WR_EN_A', BUF_WR_ADDR_A, and BUF_WR_DATA_A may be set as input data for a write operation of the memory (1900). BUF_EN_B', BUF_RD_EN_B', and BUF_RD_ADDR_A may be set as input data for a read operation of the memory (1900). BUF_RD_DATA_A may be set as output data for a read operation of the memory (1900).

For example, BUF_EN_A' and BUF_WR_EN_A' can be used to activate a write operation of the memory (1900). BUF_EN_A' can be changed from BUF_EN_A. When frequency domain data is stored in the memory (1900), BUF_EN_A' can be changed from BUF_EN_A based on PWR_CTRL_RB. When time domain data is stored in the memory (1900), BUF_EN_A' can be changed from BUF_EN_A based on PWR_CTRL_SYM. For example, BUF_WR_EN_A' can be changed from BUF_WR_EN_A. When frequency domain data is stored in the memory (1900), BUF_WR_EN_A' can be changed from BUF_ WR_EN_A based on PWR_CTRL_RB. When time domain data is stored in memory (1900), BUF_WR_EN_A' can be changed from BUF_WR_EN_A based on PWR_CTRL_SYM.

For example, BUF_WR_DATA_A may be data to be stored in memory (1900). For example, BUF_WR_ADDR_A may indicate an address of memory (1900) where BUF_WR_DATA_A will be stored (written).

For example, BUF_EN_B' and BUF_RD_EN_B' can be used to activate a read operation of the memory (1900). BUF_EN_B' can be changed from BUF_EN_B. When frequency domain data is stored in the memory (1900), BUF_EN_B' can be changed from BUF_EN_B based on PWR_CTRL_RB (e.g., DL_PWR_CTRL_RB or UL_PWR_CTRL_RB). When time domain data is stored in the memory (1900), BUF_EN_B' can be changed from BUF_EN_B based on PWR_CTRL_SYM (e.g., DL_PWR_CTRL_SYM or UL_PWR_CTRL_SYM). For example, BUF_WR_EN_B' can be changed from BUF_RD_EN_B. When frequency domain data is stored in the memory (1900), BUF_WR_RD_B' can be changed from BUF_RD_EN_B based on PWR_CTRL_RB. When time domain data is stored in the memory (1900), BUF_RD_EN_B' can be changed from BUF_RD_EN_B based on PWR_CTRL_SYM. For example, BUF_RD_ADDR_B can indicate an address of the memory (1900). For example, BUF_RD_DATA_A can be data output from the memory (1900) according to BUF_RD_ADDR_B.

Referring to FIG. 20, an example in which a memory (1900) is configured to store frequency domain data and output frequency domain data may be illustrated. For example, the memory (1900) may be configured for the first DL signal processing circuit (761) and/or the first UL signal processing circuit (771). In FIG. 20, an example in which the memory (1900) is configured to store frequency domain data and output frequency domain data is illustrated, but this is for convenience of explanation and is not limited thereto.

For example, at time point (2010), frequency domain data may begin to be stored in memory (1900). For example, based on C-plane packets, unused resources may be indicated from RB index c to RB index e.

In the writing section (2020) from RB index 0 to RB index (c-1), BUF_EN_A' and BUF_WR_EN_A' may be set to 1. In the writing section (2020), data from RB index 0 to RB index (c-1) may be stored in the memory (1900).

In the write interval (2030) from RB index c to RB index e, BUF_EN_A' and BUF_WR_EN_A' may be set to 0. In the write interval (2030), data from RB index c to RB index e may be ignored. In some embodiments, the memory (1900) may not operate in the write interval (2030). In some embodiments, data from RB index c to RB index e may be stored as 0 in the write interval (2030).

In the write section (2030) from the RB index (c+1) to the RB index (MaxRB-1), BUF_EN_A' and BUF_WR_EN_A' can be set to 1. In the write section (2030), data from the RB index (c+1) to the RB index (MaxRB-1) can be stored in the memory (1900).

From the time point (2010), data in the frequency domain may begin to be written to the memory (1900), and after the delay period (2011), data in the frequency domain may begin to be output to the memory (1900).

In the reading section (2050) from RB index 0 to RB index (c-1), BUF_EN_B' and BUF_RD_EN_B' can be set to 1. In the reading section (2050), data from RB index 0 to RB index (c-1) can be output from the memory (1900).

In the read section (2060) from RB index c to RB index e, BUF_EN_B' and BUF_RD_EN_B' may be set to 0. In the read section (2060), data from RB index c to RB index e may be ignored. In some embodiments, the memory (1900) may not operate in the read section (2060). In some embodiments, data from RB index c to RB index e may be output as 0 in the read section (2060).

In the read section (2070) from the RB index (c+1) to the RB index (MaxRB-1), BUF_EN_A' and BUF_RD_EN_A' can be set to 1. In the read section (2070), data from the RB index (c+1) to the RB index (MaxRB-1) can be output from the memory (1900).

According to FIGS. 19 and 20, when an unused resource is indicated according to a C-plane packet, a processing operation for the unused resource may not be performed during a processing section for the unused resource (e.g., a write section (2030) or a read section (2060)). Accordingly, power consumption resulting from the operation of the memory (1900) may be reduced.

Figure 21 is a flowchart regarding the operation of a device for communication with a terminal.

Referring to FIG. 21, operations 2110 to 2140 may be related to operations for setting the respective states of the first processing circuit and the second processing circuit included in a device (e.g., RU (702) or MMU) for communication with a terminal.

According to one embodiment, a device for communicating with a terminal may include a fronthaul transceiver, a first processing circuit (e.g., a first DL signal processing circuit (761) or a first UL signal processing circuit (771)), a second processing circuit (e.g., a second DL signal processing circuit (771) or a second UL signal processing circuit (772)), a radio frequency transceiver, a memory (e.g., a power saving control memory (1240)), and a processor. For example, the first processing circuit may be configured to process a signal in a frequency domain according to FFT processing or IFFT processing. The second processing circuit may be configured to process a signal in a time domain according to FFT processing or IFFT processing. The memory may be configured to set states of each of the first processing circuit and the second processing circuit.

In operation 2110, the device (or the processor of the device) may receive a control message from a DU (e.g., DU (701)) via a fronthaul transceiver to indicate unused resources in the uplink or downlink. For example, an example of the control message may be a C-plane packet (or C-plane message). The control message may be configured based on a specified section type (e.g., section type 0).

For example, the device may identify the number of at least one RB (e.g., numPrbc) in the unused resource based on a control message. The device may identify, based on the control message, a first index (e.g., startPrbc) indicating a start RB for the unused resource. The device may identify, based on the number of at least one RB and the first index, a second index (e.g., endPrbc) indicating an end RB for the unused resource. The device may identify the unused resource based on the first index and the second index. The unused resource may be identified based on the first index and the second index.

For example, the device may obtain information about a section based on a control message. The information about the section may indicate unused resources. The information about the section may include a first index indicating the number of at least one RB and/or a starting RB.

In operation 2120, the device may determine whether the number of at least one RB in the unused resource corresponds to a specified number. For example, the device may determine whether the number of at least one RB corresponds to a specified number to set the states of each of the first processing circuit and the second processing circuit. For example, the specified number may include the maximum number of RBs that can be processed by the device.

According to one embodiment, the device may obtain first information (e.g., DL_PWRSV_CTRL_RB) for setting a state of a first processing circuit to an idle state and/or second information (e.g., DL_PWRSV_CTRL_SYM) for setting a state of a second processing circuit to an idle state based on whether the number of at least one RB in the unused resource corresponds to a designated number. The device may store the first information and/or the second information in a memory of the device.

In operation 2130, if the number of at least one RB in the unused resource corresponds to a designated number, the device may set the states of each of the first processing circuit and the second processing circuit to an idle state. For example, the device may set the states of each of the first processing circuit and the second processing circuit to an idle state based on whether the number of at least one RB in the unused resource corresponds to a designated number. For example, the device may set the states of each of the first processing circuit and the second processing circuit to an idle state based on whether the number of at least one RB corresponds to a designated number. The device may set the states of both the first processing circuit and the second processing circuit to an idle state.

For example, the device may set the first information to a first value (e.g., 1) based on the number of at least one RB corresponding to a specified number. The first information may be set to the first value based on the number of at least one RB corresponding to a specified number.

For example, the device may set the second information to a first value (e.g., 1) based on the number of at least one RB corresponding to a specified number. The second information may be set to the first value based on the number of at least one RB corresponding to a specified number.

According to one embodiment, based on the number of at least one RB corresponding to the specified number, the state of the first processing circuit can be set to an idle state within a frequency interval for at least one RB. According to one embodiment, based on the number of at least one RB corresponding to the specified number, the state of the second processing circuit can be set to an idle state within a time interval for at least one RB.

In operation 2140, the device may set the state of the first processing circuit to an idle state while the second processing circuit operates, based on the number of at least one RB in the unused resource being distinct from a designated number. For example, the device may set the state of the first processing circuit to an idle state while the second processing circuit operates, based on the number of at least one RB in the unused resource being distinct from a designated number. For example, the device may set the state of the first processing circuit to an idle state while the second processing circuit operates, based on the number of at least one RB in the unused resource being less than a designated number. For example, the state of the first processing circuit may be set to an idle state while the second processing circuit operates, based on the number of at least one RB being less than a designated number. For example, the state of the second processing circuit may be set to an active state and the state of the first processing circuit may be set to an idle state, based on the number of at least one RB being less than a designated number.

For example, the device may set the first information to a first value (e.g., 1) based on the number of at least one RB being less than a specified number. The first information may be set to the first value based on the number of at least one RB being less than a specified number.

For example, the device may set the second information to a second value (e.g., 0) distinct from the first value based on the number of at least one RB being less than a specified number. The second information may be set to the second value based on the number of at least one RB being less than a specified number.

In one embodiment, based on the number of at least one RB being less than a specified number, the state of the first processing circuit can be set to an idle state within a frequency interval for the at least one RB. In one embodiment, based on the number of at least one RB being less than a specified number, the state of the second processing circuit can be set to an active state within a time interval for the at least one RB.

According to one embodiment, a device for communication with a terminal may include a fronthaul transceiver, a first processing circuit for processing a frequency domain signal according to fast Fourier transform (FFT) processing or inverse fast Fourier transform (IFFT) processing, a second processing circuit for processing a time domain signal according to the FFT processing or IFFT processing, a radio frequency (RF) transceiver for transmitting or receiving the time domain signal, and a processor. The processor may be configured to receive, through the fronthaul transceiver, a control message for indicating unused resources in uplink or downlink from a distributed unit (DU). The processor may be configured to identify, based on the control message, whether the number of at least one resource block (RB) in the unused resource corresponds to a designated number. The processor may be configured to set a state of each of the first processing circuit and the second processing circuit to the idle state based on the number of the at least one RB corresponding to the designated number. The processor may be configured to set the state of the first processing circuit to the idle state while the second processing circuit is operating, based on the number of the at least one RB being less than the specified number.

According to one embodiment, the device may include a memory for setting the states of each of the first processing circuit and the second processing circuit. The memory may be configured to store first information for setting the state of the first processing circuit to the idle state and second information for setting the state of the second processing circuit to the idle state.

According to one embodiment, the first information may be set to a first value based on the number of the at least one RB corresponding to the specified number. The second information may be set to the first value based on the number of the at least one RB corresponding to the specified number.

According to one embodiment, the first information may be set to the first value based on the number of the at least one RB being less than the specified number. The second information may be set to a second value distinct from the first value based on the number of the at least one RB being less than the specified number.

In one embodiment, the processor may be configured to identify, based on the control message, the number of the at least one RB and a first index indicating a start RB for the unused resource. The processor may be configured to identify, based on the number of the at least one RB and the first index, a second index indicating an end RB for the unused resource.

According to one embodiment, the unused resource may be identified based on the first index and the second index.

According to one embodiment, the state of the first processing circuit may be set to the idle state within the frequency range for the at least one RB.

According to one embodiment, the state of the second processing circuit may be set to the idle state within a time interval for the at least one RB based on the number of the at least one RB corresponding to the specified number.

According to one embodiment, the control message may be configured based on a specified section type.

In one embodiment, the specified number may be the maximum number of RBs that can be processed by the device.

According to one embodiment, a method performed in a device for communication with a terminal may include receiving, through a fronthaul transceiver of the device, a control message for indicating unused resources in uplink or downlink from a distributed unit (DU). The method may include identifying, based on the control message, whether the number of at least one resource block (RB) in the unused resource corresponds to a designated number. The method may include setting a state of each of a first processing circuit of the device for processing a signal in a frequency domain according to fast Fourier transform (FFT) processing or inverse fast Fourier transform (IFFT) processing and a second processing circuit of the device for processing a signal in a time domain according to the FFT processing or IFFT processing to the idle state, based on the number of the at least one RB corresponding to the designated number. The method may include setting a state of the first processing circuit to the idle state while the second processing circuit operates, based on the number of the at least one RB being less than the designated number.

According to one embodiment, the device may include a memory for setting the states of each of the first processing circuit and the second processing circuit. The memory may be configured to store first information for setting the state of the first processing circuit to the idle state and second information for setting the state of the second processing circuit to the idle state.

According to one embodiment, the first information may be set to a first value based on the number of the at least one RB corresponding to the specified number. The second information may be set to the first value based on the number of the at least one RB corresponding to the specified number.

According to one embodiment, the first information may be set to the first value based on the number of the at least one RB being less than the specified number. The second information may be set to a second value distinct from the first value based on the number of the at least one RB being less than the specified number.

In one embodiment, the method may include an operation of identifying, based on the control message, the number of the at least one RB and a first index indicating a start RB for the unused resource. The method may include an operation of identifying, based on the number of the at least one RB and the first index, a second index indicating an end RB for the unused resource.

According to one embodiment, the unused resource may be identified based on the first index and the second index.

According to one embodiment, the state of the first processing circuit may be set to the idle state within the frequency range for the at least one RB.

According to one embodiment, the state of the second processing circuit may be set to the idle state within a time interval for the at least one RB based on the number of the at least one RB corresponding to the specified number.

According to one embodiment, the control message may be configured based on a specified section type.

In one embodiment, the specified number may be the maximum number of RBs that can be processed by the device.

According to the above-described embodiment, based on the C-plane message transmitted by the DU to the RU (or MMU), the RU (or MMU) can identify a section in which it can operate in an idle state. Within the identified section, low-power operation of the digital logic (e.g., the first DL signal processing circuit, the second DL signal processing circuit, the first UL signal processing circuit, or the second UL signal processing circuit) can be performed. The section in which it can operate in an idle state can be indicated based on a C-plane message configured based on section type 0. The control message can indicate a section in which at least some of the components of the RU operate in an idle state regardless of the state of the FDD system and/or the TDD system. As at least some of the components of the RU operate in an idle state, power consumption can be reduced, and the cost required for heat dissipation can be reduced. As at least some of the components of the RU operate in an idle state, restrictions on system characteristics due to power consumption limits can be alleviated.

The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured to be executed by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure. The one or more programs may be provided as a computer program product. The computer program product may be traded between a seller and a buyer as a commodity. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store (e.g., Play Store) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created in a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device performing an embodiment of the present disclosure.

In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed in the singular or plural form, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in the plural form may be composed of singular elements, or components expressed in the singular form may be composed of plural elements.

According to embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Meanwhile, although the detailed description of the present disclosure has described specific embodiments, it is obvious that various modifications are possible within the scope of the present disclosure.

Claims (15)

In a device for communication with a terminal, Fronthaul transceiver; A first processing circuit for processing a signal in the frequency domain according to FFT (fast Fourier transform) processing or IFFT (inverse fast Fourier transform) processing; A second processing circuit for processing a time domain signal according to the above FFT processing or IFFT processing; A radio frequency (RF) transceiver for transmitting or receiving a signal in the above time domain; and comprising a processor, said processor comprising: Through the fronthaul transceiver, a control message for indicating unused resources in the uplink or downlink is received from a DU (distributed unit), Based on the above control message, identify whether the number of at least one RB (resource block) in the unused resource corresponds to a specified number, Based on the number of said at least one RB corresponding to the specified number, setting the state of each of said first processing circuit and said second processing circuit to said idle state, Based on the number of said at least one RB being less than the specified number, while the second processing circuit is operating, the state of the first processing circuit is configured to be set to the idle state. Device. In the first paragraph, the device, Further comprising a memory for setting the state of each of the first processing circuit and the second processing circuit, The above memory is, Configured to store first information for setting the state of the first processing circuit to the idle state and second information for setting the state of the second processing circuit to the idle state, Device . In the second paragraph, the first information is: Based on the number of said at least one RB corresponding to the above specified number, set to a first value, The above second information is, Based on the number of said at least one RB corresponding to the specified number, set to said first value, Device. In the third paragraph, the first information is: Based on the number of said at least one RB being less than the specified number, set to said first value, The above second information is, Based on the number of said at least one RB being less than the specified number, set to a second value distinct from the first value, Device. In the first paragraph, the processor, Based on the above control message, identify the number of at least one RB and a first index indicating a start RB for the unused resource, Further configured to identify a second index indicating an end RB for the unused resource based on the number of at least one RB and the first index, Device. In the fifth paragraph, the unused resources are: Identified based on the first index and the second index, Device. In the first paragraph, the state of the first processing circuit is: Within the frequency range for at least one RB, which is set to the idle state, Device. In the seventh paragraph, the state of the second processing circuit is: Based on the number of said at least one RB corresponding to the number specified above, within the time interval for said at least one RB, set to the idle state, Device. In the first paragraph, the control message, Constructed based on the specified section type, Device. In the first paragraph, the specified number is The maximum number of RBs that can be processed by the above device, Device. In a method performed in a device for communication with a terminal, An operation of receiving a control message for indicating unused resources in uplink or downlink from a DU (distributed unit) through a fronthaul transceiver of the above device; An operation of identifying whether the number of at least one resource block (RB) in the unused resource corresponds to a specified number based on the above control message; An operation of setting the state of each of a first processing circuit of the device for processing a signal in a frequency domain according to FFT (fast Fourier transform) processing or IFFT (inverse fast Fourier transform) processing and a second processing circuit of the device for processing a signal in a time domain according to FFT processing or IFFT processing to the idle state based on the number of the at least one RB corresponding to the specified number; and An operation comprising setting the state of the first processing circuit to the idle state while the second processing circuit is operating, based on the number of the at least one RB being less than the specified number. method. In the 11th paragraph, the device, Further comprising a memory for setting the state of each of the first processing circuit and the second processing circuit, The above memory is, Configured to store first information for setting the state of the first processing circuit to the idle state and second information for setting the state of the second processing circuit to the idle state, method. In the 12th paragraph, the first information is: Based on the number of said at least one RB corresponding to the above specified number, set to a first value, The above second information is, Based on the number of said at least one RB corresponding to the specified number, set to said first value, method. In the 13th paragraph, the first information is: Based on the number of said at least one RB being less than the specified number, set to said first value, The above second information is, Based on the number of said at least one RB being less than the specified number, set to a second value distinct from the first value, method. In the 11th paragraph, the method, An operation of identifying the number of at least one RB and a first index indicating a start RB for the unused resource based on the control message; and Further comprising an operation of identifying a second index indicating an end RB for the unused resource based on the number of at least one RB and the first index. method.