WO2025192132A1 - SiC COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING SAME - Google Patents

Abstract

This SiC composite substrate comprises: a single crystal SiC substrate; and a polycrystalline SiC layer superposed on the top surface of the single crystal SiC substrate, the polycrystalline SiC layer being formed by alternately stacking a granular structure layer that contains granular SiC crystal grains and a columnar structure layer that contains columnar SiC crystal grains. SiC crystal grains having a grain size of 2 μm or less may occupy 80% or more of the granular SiC crystal grains included in the granular structure layer, and SiC crystal grains having a grains size of 5 μm or more may occupy 50% or more of the columnar SiC crystal grains included in the columnar structure layer.

Description

SiC composite substrate and method of manufacturing same

This disclosure relates to a SiC composite substrate and a method for manufacturing the same.

Traditionally, SiC-based devices such as Schottky barrier diodes (SBDs), MOSFETs, and IGBTs have been used for power control applications. The single-crystal SiC substrates on which such SiC-based devices are formed are generally manufactured using a sublimation recrystallization method known as the modified Lely method. However, this method has the drawback of low efficiency in crystal growth and wafer processing, resulting in high manufacturing costs. Therefore, to reduce manufacturing costs, SiC composite substrates have sometimes been manufactured by growing a polycrystalline growth layer on a single-crystal SiC substrate using chemical vapor deposition (CVD).

Such SiC composite substrates can sometimes warp during crystal growth or after the substrate is ground. For freestanding SiC films formed by CVD, technology has been developed to suppress warping by providing specific layers on both sides (see Patent Documents 1 and 2).

Japanese Patent Application Laid-Open No. 2001-158666 Japanese Patent Application Laid-Open No. 2003-113472

[overview]
However, even in a SiC composite substrate in which a polycrystalline SiC layer is laminated on a single crystal substrate such as 4H—SiC, it is required to suppress warpage.

The present disclosure has been proposed in light of the above-mentioned circumstances, and aims to provide a SiC composite substrate in which a polycrystalline SiC layer is crystal-grown on a single-crystal SiC substrate, which does not warp, and a method for manufacturing the same.

In order to solve the above-mentioned problems, the SiC composite substrate disclosed herein includes a single-crystal SiC substrate and a polycrystalline SiC layer laminated on the top surface of the single-crystal SiC substrate, the polycrystalline SiC layer being formed by alternating layers of granular structure layers containing granular SiC crystal grains and columnar structure layers containing columnar SiC crystal grains.

The method for manufacturing a SiC composite substrate disclosed herein includes the steps of providing a single-crystal SiC substrate and alternately stacking, on the top surface of the single-crystal SiC substrate, a granular structure layer containing granular SiC crystal grains and a columnar structure layer containing columnar SiC crystal grains to form a polycrystalline SiC layer.

FIG. 1 is a cross-sectional view of a SiC composite substrate according to the present embodiment. FIG. 2A is a diagram illustrating a polycrystalline SiC layer in the SiC composite substrate of the present embodiment. FIG. 2B is a diagram illustrating a polycrystalline SiC layer in the SiC composite substrate of the present embodiment. FIG. 3A is a diagram illustrating the case where the top surface of the SiC composite substrate of this embodiment is ground. FIG. 3B is a diagram illustrating the case where the top surface of the SiC composite substrate of this embodiment is ground. FIG. 4 is a cross-sectional view showing a modified SiC composite substrate. FIG. 5A is a diagram illustrating a polycrystalline SiC layer in a modified SiC composite substrate. FIG. 5B is a diagram illustrating a polycrystalline SiC layer in a modified SiC composite substrate. FIG. 6A is a process diagram of the method for manufacturing a SiC composite substrate according to this embodiment. FIG. 6B is a process diagram of the method for manufacturing the SiC composite substrate of this embodiment. FIG. 6C is a process diagram of the method for manufacturing a SiC composite substrate according to this embodiment. FIG. 7 is a cross-sectional view of a Schottky barrier diode. FIG. 8 is a cross-sectional view of a trench FET. FIG. 9 is a cross-sectional view of a planar FET. FIG. 10 is a cross-sectional view of an IGBT.

Detailed Description
Hereinafter, embodiments of a SiC composite substrate and a manufacturing method thereof will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples, and the numerical values, shapes, materials, components, and the installation positions and connection forms of the components are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the embodiments, components that are not recited in the independent claims that represent the highest concepts are described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the embodiments and their modified examples may include similar components, and the same components are assigned common reference numerals, and redundant explanations will be omitted.

(SiC composite substrate)
FIG. 1 is a cross-sectional view of a SiC composite substrate 1 according to the present embodiment. The SiC composite substrate 1 according to the present embodiment is configured by laminating a polycrystalline SiC layer 15 on a top surface 11a of a single-crystal SiC substrate 11. The single-crystal SiC substrate 11 is assumed to be configured with the 4H crystalline polytype of SiC, but may be configured with other crystalline polytypes such as 6H or 3C. Furthermore, the top surface 11a of the single-crystal SiC substrate 11 is assumed to be the (0001) plane, but is not limited to this plane and may be other planes. The single-crystal SiC substrate 11 may be formed by a sublimation method or an epitaxial method.

The polycrystalline SiC layer 15 is composed of alternating layers of granular structure layers 12 and columnar structure layers 13, each having a predetermined thickness. The granular structure layer 12 is composed of granular SiC crystal grains, with 80% or more of the SiC crystal grains having a grain size of 2 μm or less. The columnar structure layer 13 is composed of columnar SiC crystal grains, with 50% or more of the SiC crystal grains having a grain size of 5 μm or more.

The polycrystalline SiC layer 15 is composed of 2 to 25 granular structure layers 12 and columnar structure layers 13 in total. Within the polycrystalline SiC layer 15, the granular structure layer 12 is in contact with the single-crystal SiC substrate 11. The granular structure layer 12 and the columnar structure layer 13 have thicknesses ranging from 20 μm to 250 μm. The granular structure layer 12 and the columnar structure layer 13 may each have a uniform thickness or different thicknesses. The columnar crystal grains that make up the columnar structure layer 13 may include crystal grains whose longitudinal direction is the thickness direction of the columnar structure layer 13 and whose both ends reach the bottom and top surfaces of the columnar structure layer 13.

In the SiC composite substrate 1, the single-crystal SiC substrate 11 is configured as an n-type semiconductor doped with n-type impurities such as nitrogen (N), phosphorus (P), and arsenic (As). The polycrystalline SiC layer 15 may be configured as an n-type semiconductor doped with n-type impurities in the same manner, or as a p-type semiconductor doped with p-type impurities such as boron (B) and aluminum (Al). The polycrystalline SiC layer 15 may also be formed by chemical vapor deposition (CVD).

2A and 2B are diagrams illustrating the polycrystalline SiC layer 15 in the SiC composite substrate 1 of this embodiment. As shown in FIG. 2A, in the granular structure layer 12, the lowest layer of the polycrystalline SiC layer 15 stacked on the top surface 11a of the single-crystal SiC substrate 11, the small-grained granular SiC crystal grains have many grain boundaries, and the SiC crystal grains aggregate in a direction that reduces their surface area, causing the layer to shrink and generating tensile stress 12a. As a result, the granular structure layer 12, the lowest layer of the polycrystalline SiC layer 15, applies tensile stress to the top surface 11a of the single-crystal SiC substrate 11, causing the SiC composite substrate 1 to warp so that the polycrystalline SiC layer 15 side is recessed.

As shown in Figure 2B, in the SiC composite substrate 1 of this embodiment, the polycrystalline SiC layer 15 is constructed by alternately stacking granular structure layers 12 and columnar structure layers 13. In the granular structure layer 12, tensile stress is generated within the layer, as described above. In the columnar structure layer 13, the columnar structure layer collides with the growth of neighboring SiC crystal grains during the growth process of the SiC crystal grains, causing the layer to expand, generating compressive stress 13a.

The polycrystalline SiC layer 15 is constructed by alternately stacking granular structure layers 12, in which tensile stress 12a occurs, and columnar structure layers 13, in which compressive stress 13a occurs, so that the tensile stress 12a and compressive stress 13a cancel each other out in the polycrystalline SiC layer 15. This reduces the stress exerted by the polycrystalline SiC layer 15 on the single-crystal SiC substrate 11, and suppresses warping in the SiC composite substrate 1.

Here, the number of granular structure layers 12 and columnar structure layers 13 included in the polycrystalline SiC layer 15 may be controlled depending on the magnitude relationship between the tensile stress generated in the granular structure layers 12 and the compressive stress generated in the columnar structure layers 13. Similarly, the thicknesses of the granular structure layers 12 and columnar structure layers 13 included in the polycrystalline SiC layer may be controlled depending on the magnitude relationship between the tensile stress generated in the granular structure layers 12 and the compressive stress generated in the columnar structure layers 13. Both the number and thickness of the granular structure layers 12 and columnar structure layers 13 may be controlled.

Figures 3A and 3B are diagrams illustrating the case where the SiC composite substrate 1 of this embodiment is ground. Figure 3A is a diagram illustrating the case where the top surface of the SiC composite substrate 1 is ground. As shown in Figure 3A, even when the upper part of the polycrystalline SiC layer 15 is ground from the top surface of the SiC composite substrate 1, the remaining polycrystalline SiC layer 15 is composed of alternatingly stacked granular structure layers 12 and columnar structure layers 13. In the remaining polycrystalline SiC layer 15, the tensile stress 12a generated in the granular structure layer 12 and the compressive stress 13a generated in the columnar structure layer 13 cancel each other out. As a result, the stress exerted by the polycrystalline SiC layer 15 on the single-crystal SiC substrate 11 is reduced, and warping of the SiC composite substrate 1 is suppressed.

Figure 3B is a diagram illustrating the case where the bottom surface of SiC composite substrate 1 of this embodiment is ground. As shown in Figure 3B, when the bottom surface 11b of single crystal SiC substrate 11, which corresponds to the bottom surface of SiC composite substrate 1, is ground to a predetermined height, the polycrystalline SiC layer 15 stacked on the top surface 11a of single crystal SiC substrate 11 remains unchanged. Even after grinding, the stress exerted by polycrystalline SiC layer 15 on single crystal SiC substrate 11 is reduced in the same way as before grinding, and warping of SiC composite substrate 1 is suppressed.

As explained above, in the SiC composite substrate 1 of this embodiment, the polycrystalline SiC layer 15 is constructed by alternately stacking granular structure layers 12, in which tensile stress 12a occurs within the layer, and columnar structure layers 13, in which compressive stress 13a occurs within the layer, so that these tensile stresses 12a and compressive stresses 13a cancel each other out. This prevents warping in the SiC composite substrate 1.

Figure 4 is a cross-sectional view showing a modified SiC composite substrate 2. The modified SiC composite substrate 2 differs from the SiC composite substrate shown in Figure 1 in that, while the granular structure layer 12 contacts the top surface 11a of the single-crystal SiC substrate 11, the columnar structure layer 13 contacts the top surface 11a of the single-crystal SiC substrate 11. As the other configurations are the same as those of the SiC composite substrate 1 shown in Figure 1, corresponding components are designated by common reference numerals to clarify the correspondence.

Figures 5A and 5B are diagrams illustrating the polycrystalline SiC layer 15 in a modified SiC composite substrate 2. As shown in Figure 5A, in the lowest columnar structure layer 13 of the polycrystalline SiC layer 15 stacked on the top surface 11a of the single crystal SiC substrate 11, large-grained, columnar SiC crystal grains push against each other, causing repulsive forces between the SiC crystal grains and generating compressive stress 13a within the layer. As a result, the lowest columnar structure layer 13 in the polycrystalline SiC layer 15 applies compressive stress to the top surface 11a of the single crystal SiC substrate 11, causing the SiC composite substrate 2 to warp so that the bottom surface 11b of the single crystal SiC substrate 11 is recessed.

As shown in FIG. 5B , in the modified SiC composite substrate 2, the polycrystalline SiC layer 15 is formed by alternately stacking granular structure layers 12 and columnar structure layers 13. As described above, compressive stress occurs within the columnar structure layer 13. In the granular structure layer 12, small granular crystal grains attempt to aggregate, creating attractive forces between the SiC crystal grains, generating tensile stress 12a within the layer. The polycrystalline SiC layer 15 is formed by alternately stacking granular structure layers 12, in which tensile stress 12a occurs, and columnar structure layers 13, in which compressive stress 13a occurs. This allows the tensile stress 12a and compressive stress 13a to cancel each other out in the polycrystalline SiC layer 15. This reduces the stress applied by the polycrystalline SiC layer 15 to the single-crystal SiC substrate 11, suppressing warpage in the SiC composite substrate 1.

In this way, both the modified SiC composite substrate 2 and the polycrystalline SiC layer 15 are constructed by alternately stacking granular structure layers 12, in which tensile stress 12a occurs within the layers, and columnar structure layers 13, in which compressive stress 13a occurs within the layers, so that these tensile stresses 12a and compressive stresses 13a cancel each other out. This prevents warping in the SiC composite substrate 1.

(Method for manufacturing SiC composite substrate)
Next, a method for manufacturing the SiC composite substrate 1 shown in Fig. 1 will be described. First, as shown in Fig. 6A, a single-crystal SiC substrate 11 is provided. The single-crystal SiC substrate 11 may be fabricated by sublimation or may be formed by epitaxial growth on a seed crystal. The single-crystal SiC substrate 11 is doped with n-type impurities and configured as an n-type semiconductor.

As shown in Figure 6B, a granular structure layer 12, the lowest layer of the polycrystalline SiC layer 15, is formed on the top surface 11a of the single-crystal SiC substrate 11. The granular structure layer 12 can be formed, for example, by growing SiC crystal grains with a 3C polytype using hot-wall CVD under conditions of 1400°C or less and 240 hPa or more. Note that when configuring the polycrystalline SiC layer 15 as an n-type semiconductor, an n-type additive is added to the CVD source gas, and when configuring it as a p-type semiconductor, a p-type additive is added.

As shown in Figure 6C, a columnar structure layer 13 is formed on the granular structure layer 12 formed in the process shown in Figure 6B. The columnar structure layer 13 can be formed, for example, by growing SiC crystal grains with a 3C polytype using hot wall CVD under conditions of 1500°C or higher and 133 hPa or lower. As with the granular structure layer 12, an n-type additive is added to the CVD source gas when forming the polycrystalline SiC layer 15 into an n-type semiconductor, and a p-type additive is added when forming it into a p-type semiconductor.

Following the step of FIG. 6C, the step of forming the granular structure layer 12 shown in FIG. 6B and the step of forming the columnar structure layer 13 shown in FIG. 6C are repeated so that the granular structure layers 12 and the columnar structure layers 13 are alternately stacked. The step of forming the granular structure layers 12 and the columnar structure layers 13 is then continued until a predetermined total number of polycrystalline SiC layers 15 composed of the granular structure layers 12 and the columnar structure layers 13 is reached. Through this series of steps, the SiC composite substrate 1 shown in FIG. 1 is formed.

In the manufacturing method of the SiC composite substrate 1 of this embodiment, the polycrystalline SiC layer 15 is formed by alternately stacking granular structure layers 12, in which tensile stress 12a occurs within the layers, and columnar structure layers 13, in which compressive stress 13a occurs within the layers. Because these tensile stresses 12a and compressive stresses 13a cancel each other out, the stress exerted by the polycrystalline SiC layer 15 on the single-crystal SiC substrate 11 is reduced, and warping in the SiC composite substrate 1 is suppressed.

(Semiconductor Devices)
Next, an embodiment of a semiconductor device will be described. The semiconductor device of this embodiment uses a SiC composite substrate 1 as shown in Figure 1, with the single-crystal SiC substrate 11 of the SiC composite substrate 1 serving as a drift layer and the polycrystalline SiC layer 15 serving as a substrate layer. Note that, since the SiC composite substrate 1 is used upside down in the semiconductor device, the top and bottom surfaces of the single-crystal SiC substrate 11 and the polycrystalline SiC layer 15 of the SiC composite substrate 1 are located below and above the semiconductor device, respectively.

The following describes examples of electronic devices using the SiC composite substrate 1, including a Schottky barrier diode (SBD), a trench metal oxide field effect transistor (MOSFET), a planar MOSFET, and an insulated-gate bipolar transistor (IGBT).

7 is a cross-sectional view of an SBD 20. The SBD 20 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the SBD 20, the SiC composite substrate 1 is formed by stacking a single-crystal SiC substrate 11 and a polycrystalline SiC layer 15. The single-crystal SiC substrate 11 is lightly doped n ^- type to form a drift layer, and the polycrystalline SiC layer 15 is heavily doped n ⁺ type to form a substrate layer. The top surface of the polycrystalline SiC layer 15 is covered with a cathode electrode 21, which is connected to a cathode terminal K.

The bottom surface 11b of the single-crystal SiC substrate 11 is provided with a contact hole 23 that exposes a portion of the single-crystal SiC substrate 11 as a body region 22, and a field insulating film 25 is formed in a field region 24 surrounding the body region 22. The field insulating film 25 is made of _SiO2 (silicon oxide) but may be made of other insulators such as silicon nitride (SiN). An anode electrode 26 is formed on the field insulating film 25 and is connected to an anode terminal A.

A p-type JTE (junction termination extension) structure 27 is formed near the bottom surface 11b (surface layer) of the single-crystal SiC substrate 11 so as to contact the anode electrode 26. The JTE structure 27 is formed along the contour of the contact hole 23 in the field insulating film 25, spanning the inside and outside of the contact hole 23.

8 is a cross-sectional view of a trench MOSFET 30. The trench MOSFET 30 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the trench MOSFET 30, in the SiC composite substrate 1 in which a single-crystal SiC substrate 11 and a polycrystalline SiC layer 15 are stacked, the single-crystal SiC substrate 11 is doped lightly to n ^- type ions to form a drift layer, and the polycrystalline SiC layer 15 is doped heavily to n ⁺ type ions to form a substrate layer. The top surface of the polycrystalline SiC layer 15 is covered with a drain electrode 31, which is connected to a drain terminal D.

A p-type body region 32 is formed on the bottom surface 11b of the single crystal SiC substrate 11. The portion of the single crystal SiC substrate 11 on the polycrystalline SiC layer 15 side of the body region 32 is a lightly doped n ^- type drain region 33(11) that remains in the state of the single crystal SiC substrate 11. A gate trench 34 is formed in the single crystal SiC substrate 11. The gate trench 34 penetrates the body region 32 from the bottom surface 11b of the single crystal SiC substrate 11, and its deepest portion reaches the drain region 33(11).

A gate insulating film 35 is formed on the inner surface of the gate trench 34 and on the bottom surface 11b of the single-crystal SiC substrate 11, covering the entire inner surface of the gate trench 34. The inside of the gate insulating film 35 is filled with, for example, polysilicon, thereby embedding a gate electrode 36 in the gate trench 34. A gate terminal G is connected to the gate electrode 36.

A highly doped n ⁺ type source region 37 is formed in a surface layer portion of the body region 32, forming part of the side surface of the gate trench 34. In addition, a highly doped p+ type body contact region 38 is formed in the single ^- crystal SiC substrate 11, extending from the bottom surface 11b thereof through the source region 37 and connected to the body region 32.

An interlayer insulating film 41 made of _SiO2 is formed on the single-crystal SiC substrate 11. A source electrode 43 is connected to the source region 37 and the body contact region 38 via a contact hole 42 formed in the interlayer insulating film 41. A source terminal S is connected to the source electrode 43.

By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 36 while generating a predetermined potential difference between the source electrode 43 and the drain electrode 31 (between the source and drain), the electric field from the gate electrode 36 can form a channel near the interface with the gate insulating film 35 in the body region 32. This allows current to flow between the source electrode 43 and the drain electrode 31, turning on the trench MOSFET 30.

9 is a cross-sectional view of a planar MOSFET 50. The planar MOSFET 50 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the planar MOSFET 50, in the SiC composite substrate 1 in which a single-crystal SiC substrate 11 and a polycrystalline SiC layer 15 are stacked, the single-crystal SiC substrate 11 is doped lightly to n ^- type to form a drift layer, and the polycrystalline SiC layer 15 is doped heavily to n ⁺ type to form a substrate layer. The top surface of the polycrystalline SiC layer 15 is covered with a drain electrode 51, which is connected to a drain terminal D.

A p-type body region 52 is formed in a well shape on the bottom surface 11b of the single-crystal SiC substrate 11. In the single-crystal SiC substrate 11, the portion on the polycrystalline SiC layer 15 side of the body region 52 is a lightly doped n ^- type drain region 53 (11), which remains in the state of the single-crystal SiC substrate 11. A highly doped n ⁺ type source region 54 is formed in a surface layer portion of the body region 52, spaced apart from the periphery of the body region 52. A highly doped p ⁺ type body contact region 55 is formed inside the source region 54. The body contact region 55 penetrates the source region 54 in the depth direction and is connected to the body region 52.

A gate insulating film 56 is formed on the bottom surface 11b of the single-crystal SiC substrate 11. The gate insulating film 56 covers the portion of the body region 52 that surrounds the source region 54 (the peripheral portion of the body region 52) and the outer periphery of the source region 54. A gate electrode 57 made of, for example, polysilicon is formed on the gate insulating film 56. The gate electrode 57 faces the peripheral portion of the body region 52, with the gate insulating film 56 in between. A gate terminal G is connected to the gate electrode 57.

An interlayer insulating film 58 made of _SiO2 is formed on the single-crystal SiC substrate 11. A source electrode 62 is connected to the source region 54 and the body contact region 55 via a contact hole 61 formed in the interlayer insulating film 58. A source terminal S is connected to the source electrode 62.

By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 57 while generating a predetermined potential difference between the source electrode 62 and the drain electrode 51 (between the source and drain), the electric field from the gate electrode 57 can form a channel near the interface with the gate insulating film 56 in the body region 52. This allows current to flow between the source electrode 62 and the drain electrode 51, turning the planar MOSFET 50 on.

10 is a cross-sectional view of an IGBT 70. The IGBT 70 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the IGBT 70, in the SiC composite substrate 1 in which a single-crystal SiC substrate 11 and a polycrystalline SiC layer 15 are stacked, the single-crystal SiC substrate 11 is doped lightly n ^- type to form a drift layer, and the polycrystalline SiC layer 15 is doped heavily p ⁺ type to form a substrate layer. The top surface of the polycrystalline SiC layer 15 is covered with a collector electrode 71, which is connected to a collector terminal C.

A p-type body region 72 is formed in a well shape on the bottom surface 11b of the single-crystal SiC substrate 11. In the single-crystal SiC substrate 11, the portion on the polycrystalline SiC layer 15 side of the body region 72 is a lightly doped n ^- type drain region 73 (11), which remains in the state of the single-crystal SiC substrate 11. A highly doped n ⁺ type emitter region 74 is formed in the surface layer of the body region 72, spaced apart from the periphery of the body region 72. A highly doped p ⁺ type body contact region 75 is formed inside the emitter region 74. The body contact region 75 penetrates the emitter region 74 in the depth direction and is connected to the body region 72.

A gate insulating film 76 is formed on the bottom surface 11b of the single-crystal SiC substrate 11. The gate insulating film 76 covers the portion of the body region 72 that surrounds the emitter region 74 (the peripheral portion of the body region 72) and the outer periphery of the emitter region 74. A gate electrode 77 made of, for example, polysilicon is formed on the gate insulating film 76. The gate electrode 77 faces the peripheral portion of the body region 72, with the gate insulating film 76 in between. A gate terminal G is connected to the gate electrode 77.

An interlayer insulating film 78 made of _SiO2 is formed on the single-crystal SiC substrate 11. An emitter electrode 82 is connected to the emitter region 74 and the body contact region 75 via a contact hole 81 formed in the interlayer insulating film 78. An emitter terminal E is connected to the emitter electrode 82.

By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 77 while generating a predetermined potential difference between the emitter electrode 82 and the collector electrode 71 (between the emitter and collector), the electric field from the gate electrode 77 can form a channel near the interface with the gate insulating film 76 in the body region 72. This allows current to flow between the emitter electrode 82 and the collector electrode 71, turning the IGBT 70 on.

The semiconductor device of this embodiment uses the SiC composite substrate 1 of this embodiment, which is configured to prevent warping. This prevents warping in the semiconductor device, ensuring the quality of the semiconductor device.

Although the present disclosure has been described in detail above, it will be clear to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment may be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, which are defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and does not have any limiting meaning on the present disclosure.

(Appendix 1)
The SiC composite substrate 1 includes a single-crystal SiC substrate 11 and a polycrystalline SiC layer 15 laminated on a top surface 11a of the single-crystal SiC substrate 11, the polycrystalline SiC layer 15 being formed by alternately laminating granular-structure layers 12 containing granular SiC crystal grains and columnar-structure layers 13 containing columnar SiC crystal grains. In the polycrystalline SiC layer 15, a tensile stress 12a generated in the granular-structure layer 12 and a compressive stress 13a generated in the columnar-structure layer 13 can be offset.

(Appendix 2)
In the SiC composite substrate 1 described in Supplementary Note 1, the grain-structure layer 12 of the polycrystalline SiC layer 15 may be in contact with the top surface 11 a of the single-crystal SiC substrate 11 .

(Appendix 3)
In the SiC composite substrate 1 described in Supplementary Note 1, the columnar structure layer 13 of the polycrystalline SiC layer 15 may be in contact with the top surface 11 a of the single-crystal SiC substrate 11 .

(Appendix 4)
In the SiC composite substrate 1 according to any one of Supplementary Notes 1 to 3, 80% or more of the granular SiC crystal grains contained in the granular-structure layer 12 may be SiC crystal grains having a grain size of 2 μm or less.

(Appendix 5)
In the SiC composite substrate 1 according to any one of Supplementary Notes 1 to 4, 50% or more of the columnar SiC crystal grains contained in the columnar structure layer 13 may be SiC crystal grains having a grain size of 5 μm or more.

(Appendix 6)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 5, the columnar SiC crystal grains contained in the columnar structure layer 13 may include crystal grains whose longitudinal direction is the thickness direction of the columnar structure layer 13 and whose both ends reach the bottom surface and top surface of the columnar structure layer 13.

(Appendix 7)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 6, the granular structure layer and the columnar structure layer may have a thickness in the range of 20 μm to 250 μm.

(Appendix 8)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 7, the granular structure layer 12 and the columnar structure layer 13 may each have a constant thickness.

(Appendix 9)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 8, the polycrystalline SiC layer 15 may include a total of 2 to 25 granular structure layers 12 and columnar structure layers 13 .

(Appendix 10)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 9, the single-crystal SiC substrate 11 and the polycrystalline SiC layer 15 may both constitute n-type semiconductors.

(Appendix 11)
In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 9, the single crystal SiC substrate 11 may constitute an n-type semiconductor, and the polycrystalline SiC layer 15 may constitute a p-type semiconductor.

(Appendix 12)
The method for manufacturing the SiC composite substrate includes the steps of providing a single-crystal SiC substrate 11 and alternately stacking, on a top surface 11a of the single-crystal SiC substrate 11, granular-structure layers 12 containing granular SiC crystal grains and columnar-structure layers 13 containing columnar SiC crystal grains to form a polycrystalline SiC layer 15. In the polycrystalline SiC layer 15, the tensile stress 12a generated in the granular-structure layer 12 and the compressive stress 13a generated in the columnar-structure layer 13 can be offset.

(Appendix 13)
In the method for manufacturing SiC composite substrate 1 described in Appendix 12, the step of forming polycrystalline SiC layer 15 may be performed such that granular structure layer 12 of polycrystalline SiC layer 15 contacts top surface 11 a of single-crystal SiC substrate 11.

(Appendix 14)
In the method for manufacturing SiC composite substrate 1 described in Appendix 12, the step of forming polycrystalline SiC layer 15 may be performed such that columnar structure layer 13 of polycrystalline SiC layer 15 contacts top surface 11 a of single-crystal SiC substrate 11.

(Appendix 15)
In a semiconductor device using the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 11, the single-crystal SiC substrate 11 and the polycrystalline SiC layer 15 of the SiC composite substrate 1 may serve as a drift layer and a substrate layer, respectively. This suppresses the occurrence of warpage in the SiC composite substrate 1 constituting the semiconductor device, thereby ensuring the quality of the semiconductor device.

(Appendix 16)
The semiconductor device described in Supplementary Note 15 may constitute at least one of a Schottky barrier diode, a planar MOSFET, a trench MOSFET, and an IGBT.

REFERENCE SIGNS LIST 1 SiC composite substrate 11 Single crystal SiC substrate 12 Granular structure layer 13 Columnar structure layer 15 Polycrystalline SiC layer

Claims (16)

a single crystal SiC substrate;
a polycrystalline SiC layer laminated on the top surface of the single crystal SiC substrate, the polycrystalline SiC layer being formed by alternatingly laminating granular structure layers containing granular SiC crystal grains and columnar structure layers containing columnar SiC crystal grains. The SiC composite substrate described in claim 1, wherein the granular structure layer of the polycrystalline SiC layer contacts the top surface of the single-crystal SiC substrate. The SiC composite substrate of claim 1, wherein the columnar structure layer of the polycrystalline SiC layer contacts the top surface of the single-crystal SiC substrate. A SiC composite substrate as described in any one of claims 1 to 3, wherein 80% or more of the granular SiC crystal grains contained in the granular structure layer are SiC crystal grains with a grain size of 2 μm or less. A SiC composite substrate as described in any one of claims 1 to 4, wherein 50% or more of the columnar SiC crystal grains contained in the columnar structure layer are SiC crystal grains with a grain size of 5 μm or more. A SiC composite substrate according to any one of claims 1 to 5, wherein the columnar SiC crystal grains contained in the columnar structure layer include crystal grains whose longitudinal direction is the thickness direction of the columnar structure layer and whose ends reach the bottom and top surfaces of the columnar structure layer. The SiC composite substrate described in any one of claims 1 to 6, wherein the granular structure layer and the columnar structure layer have thicknesses in the range of 20 μm to 250 μm. The SiC composite substrate described in any one of claims 1 to 7, wherein the granular structure layer and the columnar structure layer each have a constant thickness. The SiC composite substrate described in any one of claims 1 to 8, wherein the polycrystalline SiC layer includes a total of 2 to 25 granular structure layers and columnar structure layers. The SiC composite substrate described in any one of claims 1 to 9, wherein the single-crystal SiC substrate and the polycrystalline SiC layer both constitute n-type semiconductors. The SiC composite substrate described in any one of claims 1 to 9, wherein the single-crystal SiC substrate constitutes an n-type semiconductor and the polycrystalline SiC layer constitutes a p-type semiconductor. providing a single crystal SiC substrate;
and forming a polycrystalline SiC layer by alternately stacking a granular structure layer containing granular SiC crystal grains and a columnar structure layer containing columnar SiC crystal grains on the top surface of the single crystal SiC substrate. The method for manufacturing a SiC composite substrate described in claim 12, wherein the step of forming the polycrystalline SiC layer is performed so that the granular structure layer of the polycrystalline SiC layer contacts the top surface of the single-crystal SiC substrate. The method for manufacturing a SiC composite substrate described in claim 12, wherein the step of forming the polycrystalline SiC layer forms the polycrystalline SiC layer so that the columnar structure layer contacts the top surface of the single-crystal SiC substrate. A semiconductor device using the SiC composite substrate according to any one of claims 1 to 11, in which the single-crystal SiC substrate and polycrystalline SiC layer of the SiC composite substrate serve as a drift layer and a substrate layer, respectively. The semiconductor device according to claim 15, which constitutes at least one of a Schottky barrier diode, a planar MOSFET, a trench MOSFET, and an IGBT.