WO2025192032A1 - Imaging device and imaging method - Google Patents

Abstract

The present invention enables a pixel signal output from each of a plurality of pixels in the same row to be binned and read.　This imaging device comprises: a pixel array unit that has pixels arranged in a matrix shape in a row direction and a column direction; vertical signal lines that transmit, in the column direction, pixel signals output from the pixels; a selection circuit that selects a plurality of vertical signal lines which are in columns differing from each other; and an AD conversion unit that performs AD conversion on pixel signals which have been binned on the basis of a vertical signal line selection result obtained by the selection circuit. The selection circuit may perform binning on the basis of source follower addition.

Description

Imaging device and imaging method

This technology relates to an imaging device and an imaging method. More specifically, this technology relates to an imaging device and an imaging method that can add and read pixel signals output from multiple pixels.

In order to improve dynamic range and sensitivity, imaging devices sometimes add and read out pixel signals output from multiple pixels. For example, one imaging device has been disclosed in which two systems of pixel drive lines are wired for each pixel row, and pixels are connected to these pixel drive lines in units of two adjacent columns, allowing two pixel rows to be scanned simultaneously with different pixel columns (see, for example, Patent Document 1).

JP 2010-263526 A

However, with the above-mentioned conventional technology, the vertical signal lines of different columns are connected to separate AD conversion circuits. This makes it impossible to bin and read out the pixel signals output from multiple pixels in the same row.

This technology was developed in light of these circumstances, and aims to enable binning and reading out the pixel signals output from multiple pixels in the same row.

This technology has been made to solve the above-mentioned problems, and its first aspect is an imaging device that includes a pixel array section in which pixels are arranged in a matrix in the row and column directions, vertical signal lines that transmit pixel signals output from the pixels in the column direction, a selection circuit that selects multiple vertical signal lines in different columns, and an AD conversion section that AD converts binned pixel signals based on the selection result of the vertical signal lines by the selection circuit. This has the effect of binning the pixel signals output from multiple pixels in the same row.

Furthermore, in the first aspect, the selection circuit may perform the binning based on source follower addition. This results in the effect of binning pixel signals output from multiple pixels in the same row based on the selection results of multiple vertical signal lines in different columns.

Furthermore, in the first aspect, the AD conversion unit may perform AD conversion on the binning results of pixel signals output from a plurality of pixels having the same rows but different columns. This brings about the effect that pixel signals output from a plurality of pixels having the same rows but different columns are binned and digitized.

In the first aspect, the selection circuit may include a first selection circuit that selects multiple vertical signal lines in different columns, and a second selection circuit that selects multiple vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the column. Alternatively, signals may be output from multiple pixels in different columns via the same vertical signal line, and the number of vertical signal lines between the different columns may match the number of vertical signal lines shifted in the row direction between the first and second selection circuits. Furthermore, the combination of vertical signal lines shared by multiple pixels in the column direction may differ for each pixel row. For example, when viewed from the perspective of a single pixel column, pixels in odd-numbered rows may share vertical signal lines with pixels located to the right, and pixels in even-numbered rows may share vertical signal lines with pixels located to the left. This provides the effect of selecting multiple sets of vertical signal lines in different columns by providing ports in the selection circuit according to the number of columns.

Furthermore, in the first aspect, the pixel array unit may be configured such that pixel signals output from pixels located in different columns share the vertical signal lines, and the number of vertical signal lines provided between the different columns matches the shift in the row direction of the number of vertical signal lines in the columns. This provides the effect of preventing shifts in the center of gravity for each color while selecting sets of multiple vertical signal lines in different columns by providing ports in the selection circuit according to the number of columns.

Furthermore, in the first aspect, the AD conversion unit may include a first AD conversion unit that performs AD conversion on a first pixel signal that has been binned based on the selection result of the vertical signal line by the first selection circuit, and a second AD conversion unit that performs AD conversion on a second pixel signal that has been binned based on the selection result of the vertical signal line by the second selection circuit. This provides the effect of AD converting pixel signals based on the selection result of multiple vertical signal lines that are shifted in the row direction and in different columns.

Furthermore, in the first aspect, the first selection circuit and the first AD conversion unit may be arranged on one side of the pixel array unit in the column direction, and the second selection circuit and the second AD conversion unit may be arranged on the other side of the pixel array unit in the column direction. This brings about the effect that pixel signal readout for the same column is symmetrical in the column direction.

Furthermore, in the first aspect, pixels adjacent to each other in the row direction may be connected to the same vertical signal line. This results in the effect of reading out pixel signals from multiple pixels in the same row via the same vertical signal line.

Furthermore, in the first aspect, the device may include a dummy pixel array section arranged adjacent to the pixel array section in the row direction, with dummy pixels arranged in a matrix in the row and column directions, and a dummy selection circuit that selects a vertical signal line arranged at an end of the pixel array section adjacent to the dummy pixel array section, wherein the vertical signal line selected by the dummy selection circuit may be shared by pixels at the end of the pixel array section and dummy pixels at the end of the dummy pixel array section. This brings about the effect of equalizing the load on the vertical signal line at the end of the pixel array section and the load on the vertical signal line in the center of the pixel array section.

Furthermore, in the first aspect, the pixel array section may include first to fourth rows adjacent to each other and first to fifth columns adjacent to each other, and the connections between the vertical signal lines and the pixels may be set in units of 16 pixels arranged in the first to fourth rows and the first to fourth columns. This enables binning based on the selection results of multiple vertical signal lines in different columns that are shifted in the row direction, while unifying the connections between the vertical signal lines and the pixels in units of 16 pixels.

Furthermore, in the first aspect, the first column may include a first vertical signal line and a second vertical signal line, the second column may include a third vertical signal line and a fourth vertical signal line, the third column may include a fifth vertical signal line and a sixth vertical signal line, the fourth column may include a seventh vertical signal line and an eighth vertical signal line, and the fifth column may include a ninth vertical signal line and a tenth vertical signal line. This provides the effect of unifying the connections between the vertical signal lines and the pixels in units of 16 pixels, while simultaneously reading out pixel signals from two columns in the same row.

Furthermore, in the first aspect, the selection circuit may include a first selection circuit connected to the first to eighth vertical signal lines, and a second selection circuit connected to the third to tenth vertical signal lines. This enables selection of multiple vertical signal lines in different columns that are shifted in the row direction, while simultaneously reading out pixel signals from two columns in the same row.

Furthermore, in the first aspect, the AD conversion unit may include a first AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the first vertical signal line and the fifth vertical signal line, a second AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the fourth vertical signal line and the eighth vertical signal line, a third AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the third vertical signal line and the seventh vertical signal line, and a fourth AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the sixth vertical signal line and the tenth vertical signal line. This brings about the effect of digitizing binned pixel signals based on a selection result of multiple vertical signal lines that are shifted in the row direction and located in different columns.

Furthermore, in the first aspect, the first pixel in the first row and the first column is connected to the first vertical signal line, the second pixel in the second row and the first column and the sixth pixel in the second row and the second column are connected to the third vertical signal line, the third pixel in the third row and the first column is connected to the second vertical signal line, the fourth pixel in the fourth row and the first column and the eighth pixel in the fourth row and the second column are connected to the fourth vertical signal line, and the fifth pixel in the first row and the second column and the ninth pixel in the first row and the third column are connected to the fifth vertical signal line. The seventh pixel in the third row and the second column and the eleventh pixel in the third row and the third column may be connected to the sixth vertical signal line, the tenth pixel in the second row and the third column and the fourteenth pixel in the second row and the fourth column may be connected to the seventh vertical signal line, the twelfth pixel in the fourth row and the third column and the sixteenth pixel in the fourth row and the fourth column may be connected to the eighth vertical signal line, the thirteenth pixel in the first row and the fourth column may be connected to the ninth vertical signal line, and the fifteenth pixel in the third row and the fourth column may be connected to the tenth vertical signal line. This enables binning based on the selection results of multiple vertical signal lines in different columns that are shifted in the row direction, while unifying the connections between the vertical signal lines and pixels in units of 16 pixels.

Furthermore, in the first aspect, the first pixel, the third pixel, the sixth pixel, the eighth pixel, the tenth pixel, the twelfth pixel, the thirteenth pixel, and the fifteenth pixel may be read out at a first timing, and the second pixel, the fourth pixel, the fifth pixel, the seventh pixel, the ninth pixel, the eleventh pixel, the fourteenth pixel, and the sixteenth pixel may be read out at a second timing. This brings about the effect that the readout timings from pixels adjacent to each other in the row direction connected to the same vertical signal line are set to be different from each other.

Furthermore, in the first aspect, the pixels may be arranged in a Bayer array. This prevents misalignment of the center of gravity for each color, while also providing the effect of binning pixel signals output from multiple pixels in the same row.

Furthermore, in the first aspect, the pixels may be arranged in a quad Bayer array. This prevents an increase in pixel size, bins pixel signals output from multiple pixels in the same row, and prevents misalignment of the center of gravity for each color.

The second aspect is an imaging method that selects multiple vertical signal lines that transmit pixel signals output from pixels arranged in a matrix in the row and column directions in the column direction, and bins the pixel signals based on the selection results of the multiple vertical signal lines. This results in the effect of binning the pixel signals output from multiple pixels in the same row.

Furthermore, in the second aspect, the binning results of pixel signals output from a plurality of pixels having the same rows but different columns may be AD converted. This brings about the effect that pixel signals output from a plurality of pixels having the same rows but different columns are binned and digitized.

Furthermore, in the second aspect, at the same time as selecting the plurality of vertical signal lines in different columns, a plurality of vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the columns may be selected. This brings about the effect that by providing ports in the selection circuit according to the number of columns, a set of a plurality of vertical signal lines in different columns can be selected.

1 is a block diagram illustrating an example of the configuration of an imaging apparatus according to a first embodiment. 1 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a first embodiment. FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration example of an AD conversion unit according to the first embodiment. FIG. 2 is a block diagram showing a first readout timing of the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing a second readout timing of the solid-state imaging device according to the first embodiment. FIG. 10 is a block diagram illustrating a configuration example of a solid-state imaging device according to a second embodiment. FIG. 10 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a third embodiment. FIG. 10 is a block diagram illustrating a configuration example of a dummy selection circuit according to a third embodiment. FIG. 10 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a fourth embodiment. FIG. 10 is a diagram illustrating an example of a circuit configuration of a cell provided in a solid-state imaging device according to a fourth embodiment. FIG. 13 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a fifth embodiment. FIG. 13 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to a sixth embodiment. 1 is a block diagram illustrating a schematic configuration example of a vehicle control system. FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described in the following order.
1. First embodiment (example of AD conversion of pixel signals that have been added by source followers based on the selection results of multiple vertical signal lines in different columns in a Bayer array)
2. Second embodiment (an example in which a dummy pixel array section is provided adjacent to a pixel array section in the row direction, and pixel signals that have been added together by source followers based on the selection results of multiple vertical signal lines in different columns in a Bayer arrangement are AD converted)
3. Third embodiment (an example in which a dummy pixel array section is provided adjacent to a pixel array section in the row direction, and some signal paths of a dummy selection circuit are eliminated)
4. Fourth embodiment (example of AD conversion of pixel signals added by source followers based on the selection results of multiple vertical signal lines in different columns in a quad Bayer arrangement)
5. Fifth embodiment (an example in which an AD conversion unit that performs AD conversion on pixel signals output from green pixels in a Bayer arrangement and an AD conversion unit that performs AD conversion on pixel signals output from red pixels R and blue pixels B are arranged on one side of a pixel array unit, and pixel signals that have been added by source followers based on the selection results of multiple vertical signal lines in different columns are AD converted)
6. Sixth embodiment (example in which pixel array sections are stacked)
7. Mobile application examples

1. First embodiment
FIG. 1 is a block diagram showing an example of the configuration of an imaging apparatus according to the first embodiment.

In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a memory unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the memory unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device or a monitoring device, or a mobile object such as a vehicle or a drone.

The optical system 101 allows light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Here, the solid-state imaging device 102 may output a pixel signal read from a single pixel, or may bin and output pixel signals read from multiple pixels. In this case, the solid-state imaging device 102 can bin the pixel signals based on the selection results of multiple vertical signal lines in different columns. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102. The imaging control unit 103 can also instruct the solid-state imaging device 102 on whether or not to perform binning.

The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may also include a processor that executes processing based on software.

The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

The display unit 106 displays captured images and various information that supports the capture operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may also be configured as a touch panel together with the display unit 106.

Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, it may have additional functions that are not disclosed.

FIG. 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, column signal processing sections 114A and 114B, selection circuits S1 to S4, a horizontal scanning circuit 115, and a control circuit 116. Note that the selection circuits S3 and S4 in the figure show the connection state of some of the vertical signal lines VLA and VLB.

The pixel array section 111 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and column direction (also called the vertical direction). Each pixel PX can form a source follower with the column signal processing sections 114A and 114B when reading out a signal.

Each pixel PX is connected to horizontal drive lines HLA, HLB in the row direction, and to vertical signal lines VLA, VLB in the column direction. At this time, each pixel PX is connected to the horizontal drive lines HLA, HLB alternately in the row direction. Also, two adjacent pixels PX in the row direction share one of the vertical signal lines VLA, VLB. At this time, two adjacent pixels PX in the row direction are connected to the same vertical signal line VLA, VLB every third pixel in the column direction. Also, two adjacent pixels PX in the row direction alternately share the vertical signal lines VLA, VLB of the same column every other pixel in the column direction.

In other words, in the pixel array section 111, a unit block UB can be configured with 16 pixels PX belonging to four adjacent first to fourth rows and four adjacent first to fourth columns. Then, the connection between the vertical signal lines VLA, VLB and the pixels PX is set for each unit block UB. At this time, the same connection configuration between the vertical signal lines VLA, VLB and the pixels PX can be repeated for each unit block UB.

In the unit block UB, the first pixel in the first row and first column is connected to the vertical signal line VLA of the first column, the second pixel in the second row and first column and the sixth pixel in the second row and second column are connected to the vertical signal line VLA of the second column. The third pixel in the third row and first column is connected to the vertical signal line VLB of the first column, the fourth pixel in the fourth row and first column and the eighth pixel in the fourth row and second column are connected to the vertical signal line VLB of the second column. The fifth pixel in the first row and second column and the ninth pixel in the first row and third column are connected to the vertical signal line VLA of the third column, and the seventh pixel in the third row and second column and the eleventh pixel in the third row and third column are connected to the vertical signal line VLB of the third column. The tenth pixel in the second row and third column and the fourteenth pixel in the second row and fourth column are connected to the vertical signal line VLA of the fourth column, the twelfth pixel in the fourth row and third column and the sixteenth pixel in the fourth row and fourth column are connected to the vertical signal line VLB of the fourth column, the thirteenth pixel in the first row and fourth column is connected to the vertical signal line VLA of the fifth column, and the fifteenth pixel in the third row and fourth column is connected to the vertical signal line VLB of the fifth column.

Each horizontal drive line HLA, HLB drives each pixel PX in the row direction when reading out a signal from the pixel PX. The vertical signal lines VLA, VLB transmit a potential based on the current that flows when reading out a signal from the pixel PX in the column direction to the column signal processing units 114A, 114B.

Each pixel PX may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared light (NIR: Near Infrared), short-wave infrared light (SWIR: Short Wavelength Infrared), ultraviolet light, or X-rays.

The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may include an address decoder, or may include a driver that drives the horizontal drive lines HLA, HLB selected via the address decoder for each row. In this case, the vertical scanning circuit 112 can drive the pixels PX via each horizontal drive line HLA, HLB so that pixel signals are output at different times from two pixels PX that share the same vertical signal lines VLA, VLB.

The selection circuits S1 to S4 select multiple vertical signal lines VLA, VLB in different columns. At this time, for example, the vertical signal lines VLA, VLB selectable by each selection circuit S1, S2 can be shifted in the row direction by the number of vertical signal lines VLA, VLB in each column. For example, the selection circuit S1 can select multiple vertical signal lines VLA, VLB in different columns from the eight vertical signal lines VLA, VLB in the first to fourth columns. Furthermore, the selection circuit S2 can select multiple vertical signal lines VLA, VLB in different columns from the eight vertical signal lines VLA, VLB in the second to fifth columns. At this time, while the selection circuit S1 selects multiple vertical signal lines VLA, VLB in different columns, the selection circuit S2 can select multiple vertical signal lines VLA, VLB in different columns that are shifted in the row direction by the number of vertical signal lines VLA, VLB in one column.

In this case, pixels PX located in different columns may share vertical signal lines VLA, VLB, and the number of vertical signal lines VLA, VLB between different columns may match the row-direction offset of the number of vertical signal lines VLA, VLB in one column. Furthermore, for vertical signal lines VLA, VLB shared by multiple pixels PX, the column-direction combination may differ for each row of pixels PX. For example, when viewed from the perspective of one pixel column, pixels PX in odd-numbered rows may share vertical signal lines VLA, VLB with pixels PX located to the right, and pixels PX in even-numbered rows may share vertical signal lines VLA, VLB with pixels PX located to the left.

Furthermore, each of the selection circuits S1 to S4... can bin the pixel signals output from the pixels PX based on the selection results of multiple vertical signal lines VLA, VLB that are in different columns. In this case, each of the selection circuits S1 to S4... may perform binning based on source follower addition. Each of the selection circuits S1, S3... can be arranged on one side of the pixel array section 111, and each of the selection circuits S2, S4... can be arranged on the other side of the pixel array section 111. Each of the selection circuits S1 to S4... may be a multiplexer.

Each column signal processing unit 114A, 114B can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, each column signal processing unit 114A, 114B can change the potential of each vertical signal line VLA, VLB based on the charge held in the pixel PX.

Furthermore, each column signal processing unit 114A, 114B processes signals transmitted in the column direction from each pixel PX. For example, each column signal processing unit 114A, 114B can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PX. Furthermore, each column signal processing unit 114A, 114B can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output image signals Go1, Go2, respectively.

Column signal processing unit 114A includes AD conversion units A1, A3, A5, etc. Column signal processing unit 114B includes AD conversion units A2, A4, A6, etc. Each AD conversion unit A1 to A6 can perform AD conversion processing in parallel. At this time, each AD conversion unit A1 to A6 can perform AD conversion based on the comparison result between the pixel signal read out from the pixel PX and a reference signal, and output digital values D1 to D6 of the pixel signal. Furthermore, each AD conversion unit A1 to A6 can AD convert the binning results of pixel signals output from multiple pixels PX that are in the same row but different columns.

The column signal processing unit 114A can be arranged on one side of the pixel array unit 111, and the column signal processing unit 114B can be arranged on the other side of the pixel array unit 111. In this case, each selection circuit S1, S3, etc. can output binned pixel signals based on the selection results of multiple vertical signal lines VLA, VLB in different columns to the column signal processing unit 114A. Each selection circuit S2, S4, etc. can output binned pixel signals based on the selection results of multiple vertical signal lines VLA, VLB in different columns to the column signal processing unit 114B.

The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

The control circuit 116 controls the vertical scanning circuit 112, column signal processing units 114A and 114B, selection circuits S1 to S4, etc., and horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the selection timing of selection circuits S1 to S4, etc., and the processing timing of column signal processing units 114A and 114B. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, selection circuits S1 to S4, etc., column signal processing units 114A and 114B, and horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

FIG. 3 is a block diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment.

In the figure, pixel PX includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. N-channel MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

The amplification transistor 124 and selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply VDD via the reset transistor 123. The power supply VDD is connected to the vertical signal line VLA via the series circuit of the amplification transistor 124 and selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive lines HLA and HLB in Figure 2.

When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is then applied to the vertical signal lines VLA and VLB via the selection transistor 125 and transmitted via the vertical signal lines VLA and VLB. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

FIG. 4 is a block diagram showing an example configuration of an AD conversion unit according to the first embodiment. Note that while the diagram shows only the connection between the selection circuit S1 and the AD conversion unit A1, the connection between the selection circuit S1 and the AD conversion unit A3 can also be configured in a similar manner.

In the same diagram, the selection circuit S1 includes switches W1 to W8. In this case, the selection circuit S1 can be connected to eight vertical signal lines VLA1 to VLB4 via the switches W1 to W8. The eight vertical signal lines VLA1 to VLB4 are arranged in the first to fourth columns of the pixel array section 111. For example, pixels PX1 to PX8 are connected to each of the vertical signal lines VLA1 to VLB4.

The AD conversion unit A1 includes a current source 131, a comparator 132, and a counter 133. The current source 131 can form a source follower with pixels PX1 to PX8 connected to vertical signal lines VLA1 to VLB4, which are connected via switches W1 to W8. By turning on multiple switches W1 to W8, the selection circuit S1 can perform source follower addition of pixel signals transmitted over vertical signal lines VLA1 to VLB4, which are connected to the current source 131 via the turned-on switches W1 to W8.

Comparator 132 compares the output of selection circuit S1 with reference signal VRF and outputs the comparison result to counter 133. The reference signal VRF may include a ramp wave.

The counter 133 performs a counting operation based on the comparison result of the comparator 132, and outputs the count value at that time as the digital value D1 of the pixel signal.

Here, the selection circuit S1 can select vertical signal lines VLA1 to VLB4 based on the switching of switches W1 to W8. At this time, the selection circuit S1 selects multiple vertical signal lines VLA1 to VLB4 that are in different columns, and can perform source-follower addition on the pixel signals transmitted via the selected vertical signal lines VLA1 to VLB4, and output the results to the AD conversion unit A1.

FIG. 5 is a block diagram showing the first readout timing of the solid-state imaging device according to the first embodiment. Note that this figure shows an example in which the pixels PX are arranged in a Bayer array.

In the same figure, of the first to sixteenth pixels of the unit block UB, the second, fourth, tenth, and twelfth pixels are assigned as green pixels Gr. The fifth, seventh, thirteenth, and fourteenth pixels are assigned as green pixels Gb. The first, third, ninth, and eleventh pixels are assigned as red pixels R. The sixth, eighth, fourteenth, and sixteenth pixels are assigned as blue pixels B. The pixel signals output from the red pixels R and blue pixels B can be AD converted by the column signal processing unit 114A. The pixel signals output from the green pixels Gr and Gb can be AD converted by the column signal processing unit 114B. At this time, the first, third, sixth, eighth, tenth, twelfth, thirteenth, and fifteenth pixels can be read out at the first timing.

Here, selection circuit S1 can perform source-follower addition on pixel signals output from the first and third pixels, which are red pixels R, and output the result to AD conversion unit A1. Selection circuit S1 can also perform source-follower addition on pixel signals output from the sixth and eighth pixels, which are blue pixels B, and output the result to AD conversion unit A3. Selection circuit S2 can perform source-follower addition on pixel signals output from the thirteenth and fifteenth pixels, which are green pixels Gb, and output the result to AD conversion unit A2. Selection circuit S2 can also perform source-follower addition on pixel signals output from the tenth and twelfth pixels, which are green pixels Gr, and output the result to AD conversion unit A4. Each of AD conversion units A1 to A4 can perform AD conversion in parallel on pixel signals that have been read out at the first timing and source-follower added.

FIG. 6 is a block diagram showing the second readout timing of the solid-state imaging device according to the first embodiment. Note that this figure shows an example in which the pixels PX are arranged in a Bayer array.

In the same figure, in unit block UB, the second, fourth, fifth, seventh, ninth, eleventh, fourteenth, and sixteenth pixels are read out at the second timing. The second timing can be set so as not to overlap with the first timing.

Here, selection circuit S1 can perform source-follower addition on pixel signals output from the 9th and 11th pixels, which are red pixels R, and output the result to AD conversion unit A1. Selection circuit S1 can also perform source-follower addition on pixel signals output from the 14th and 16th pixels, which are blue pixels B, and output the result to AD conversion unit A3. Selection circuit S2 can perform source-follower addition on pixel signals output from the 5th and 7th pixels, which are green pixels Gb, and output the result to AD conversion unit A2. Selection circuit S2 can also perform source-follower addition on pixel signals output from the 2nd and 4th pixels, which are green pixels Gr, and output the result to AD conversion unit A4. Each of AD conversion units A1 to A4 can perform AD conversion in parallel on pixel signals that have been read out at the second timing and source-follower added.

In this case, it is possible to eliminate the mismatch in the order of data output for each column, which not only prevents data processing in later stages from becoming too complicated, but also enables signal addition processing in which pixel columns are aligned for each color (center of gravity balance is aligned). For example, each AD conversion unit A1, A3 can perform source-follower addition of pixel signals from the same multiple columns (first and third columns), and each AD conversion unit A2, A4 can perform source-follower addition of pixel signals from the same multiple columns (second and fourth columns). This prevents misalignment of the center of gravity for each color during source-follower addition.

In this way, in the first embodiment described above, pixel signals that have been added using source followers are AD converted based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in the Bayer arrangement. This makes it possible to bin and AD convert pixel signals output from multiple pixels PX in the same row while suppressing an increase in relative variation in pixel signals.

Furthermore, the vertical signal lines VLA, VLB selected by each selection circuit S1, S2 are shifted in the row direction by the number of vertical signal lines VLA, VLB for each column. By providing ports in the selection circuits S1, S2 according to the number of columns, it is possible to prevent shifts in the center of gravity for each color while selecting multiple vertical signal lines VLA, VLB in different columns and performing source follower addition.

Furthermore, two vertical signal lines VLA, VLB are provided for each column. This makes it possible to read pixel signals from each column while preventing color mixing, even when two adjacent pixels PX in the row direction share the same vertical signal line VLA, VLB, and prevents a decrease in frame rate.

2. Second embodiment
In the first embodiment described above, pixel signals that have been added together using source-follower logic based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in the Bayer arrangement are AD-converted. In this second embodiment, a dummy pixel array unit is provided adjacent to the pixel array unit 111 in the row direction, and pixel signals that have been added together using source-follower logic based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in the Bayer arrangement are AD-converted.

FIG. 7 is a block diagram showing an example configuration of a solid-state imaging device according to the second embodiment.

In the figure, this solid-state imaging device is the same as the solid-state imaging device of the first embodiment described above, except that a dummy pixel array section 211, a bias circuit 212, and a dummy selection circuit DS have been added. This solid-state imaging device also includes a control circuit 216 instead of the control circuit 116 of the first embodiment described above. The rest of the configuration of this solid-state imaging device is the same as the configuration of the solid-state imaging device of the first embodiment described above.

The dummy pixel array section 211 can be arranged adjacent to the pixel array section 111 in the row direction. The dummy pixel array section 211 may also be provided on both sides of the pixel array section 111 in the row direction. The dummy pixel array section 211 includes a plurality of dummy pixels DPX. The dummy pixels DPX are arranged in a matrix along the row and column directions. In this case, four columns' worth of dummy pixels DPX can be provided. The dummy pixels DPX can equalize the load on the vertical signal lines VLA, VLB at the ends of the pixel array section 111 in the row direction and the load on the vertical signal lines VLA, VLB in the center of the pixel array section 111 in the row direction.

Each dummy pixel DPX is connected to horizontal drive lines HLA, HLB in the row direction and to dummy vertical signal lines VDA, VDB in the column direction. In this case, each dummy pixel DPX is connected to the horizontal drive lines HLA, HLB alternately in the row direction. Furthermore, two adjacent dummy pixels DPX in the row direction share one of the dummy vertical signal lines VDA, VDB. In this case, two adjacent dummy pixels DPX in the row direction are connected to the dummy vertical signal lines VDA, VDB every third pixel in the column direction. However, the dummy pixels DPX at the end of the dummy pixel array unit 211 adjacent to the pixel array unit 111 alternately share one of the vertical signal lines VLA, VLB with the pixels PX at the end of the pixel array unit 111 every other pixel in the column direction. In this case, the wiring configuration of the pixels PX in the first column of the pixel array unit 111 can be made the same as the wiring configuration of the pixels PX in the fifth column of the pixel array unit 111.

The dummy selection circuit DS selects the vertical signal lines VLA, VLB at the row end of the pixel array section 111. The dummy selection circuit DS can be configured in the same way as the selection circuit S1. In this case, of the eight input ports of the dummy selection circuit DS, a bias voltage VT can be applied to six input ports other than the two input ports used to select the vertical signal lines VLA, VLB at the row end of the pixel array section 111.

The bias circuit 212 supplies a bias to the vertical signal lines VLA and VLB at the row end of the pixel array section 111. The bias circuit 212 includes current sources G1 and G2. Current source G1 can be connected to the first of the two output ports of the dummy selection circuit DS, and current source G2 can be connected to the second of the two output ports of the dummy selection circuit DS. In this case, the selection timing of the dummy vertical signal lines VDA and VDB of the dummy selection circuit DS can be made equal to the selection timing of the vertical signal lines VLA and VLB of the selection circuit S2.

The control circuit 216 controls the vertical scanning circuit 112, column signal processing units 114A and 114B, selection circuits S1 to S4, etc., dummy selection circuit DS, and horizontal scanning circuit 115. For example, the control circuit 216 can control the scanning timing in the column direction, the scanning timing in the row direction, the selection timing of selection circuits S1 to S4, etc. and dummy selection circuit DS, and the processing timing of column signal processing units 114A and 114B. In this case, the control circuit 216 can coordinate the vertical scanning circuit 112, selection circuits S1 to S4, etc., dummy selection circuit DS, column signal processing units 114A and 114B, and horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

In this way, in the second embodiment described above, a dummy pixel array section 211 is provided adjacent to the pixel array section 111 in the row direction. This makes it possible to share the pixel PX at the end of the pixel array section 111 in the row direction with the dummy pixel DPX adjacent to it in the row direction when two adjacent pixels PX in the row direction share the same vertical signal lines VLA, VLB. This makes it possible to equalize the load on the vertical signal lines VLA, VLB at the end of the pixel array section 111 in the row direction and the load on the vertical signal lines VLA, VLB in the center of the pixel array section 111 in the row direction, thereby improving the image quality of the solid-state imaging device.

3. Third embodiment
In the second embodiment described above, the dummy pixel array unit 211 is provided adjacent in the row direction to the pixel array unit 111. In this third embodiment, the dummy pixel array unit 211 is provided adjacent in the row direction to the pixel array unit 111, and some signal paths of the dummy selection circuit are eliminated.

FIG. 8 is a block diagram showing an example configuration of a solid-state imaging device according to the third embodiment.

In the same figure, this solid-state imaging device has a dummy selection circuit DS' instead of the dummy selection circuit DS of the second embodiment described above. The rest of the configuration of this solid-state imaging device is the same as the configuration of the solid-state imaging device of the second embodiment described above.

The dummy selection circuit DS' selects the vertical signal lines VLA, VLB at the end of the pixel array section 111 in the row direction. At this time, a bias voltage VT can be applied to six of the eight input ports of the dummy selection circuit DS', excluding the two input ports used to select the vertical signal lines VLA, VLB at the end of the pixel array section 111 in the row direction. The dummy selection circuit DS' has some of the signal paths deleted. At this time, the dummy selection circuit DS' has signal paths deleted that are connected to the same output ports as the ports connected to the end vertical signal lines VLA, VLB during source follower addition. This allows the selection circuits S1 to S4... and the dummy selection circuit DS to operate based on the same control, eliminating the need to increase the number of signal lines in the control circuit 216.

Figure 9 is a block diagram showing an example configuration of a dummy selection circuit according to the third embodiment.

In the same figure, the dummy selection circuit DS' has eight input ports P1 to P8 and two output ports Q1 and Q2. A bias voltage VT is applied to input ports P1 to P6. Output port Q1 is connected to current source G1, and output port Q2 is connected to current source G2.

Here, input port P8 is connected to vertical signal line VLB. At this time, the signal path between input port P8 and output port Q2 of dummy selection circuit DS' is deleted. This prevents the bias voltage VT from being applied to vertical signal line VLB via dummy selection circuit DS' during source follower addition, and allows each selection circuit S1 to S4... and dummy selection circuit DS to operate under the same control.

In this way, in the third embodiment described above, the signal path of the dummy selection circuit DS', which is connected to the same output port as the port connected to the end vertical signal lines VLA and VLB during source follower addition, is eliminated. This allows the selection circuits S1 to S4... and the dummy selection circuit DS to operate based on the same control, making it unnecessary to increase the number of signal lines in the control circuit 216.

4. Fourth embodiment
In the first embodiment described above, pixel signals that have been added together using source-follower techniques are AD-converted based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in a Bayer arrangement. In this fourth embodiment, pixel signals that have been added together using source-follower techniques are AD-converted based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in a quad-Bayer arrangement.

FIG. 10 is a block diagram showing an example configuration of a solid-state imaging device according to the fourth embodiment.

In the figure, this solid-state imaging device has a pixel array section 411, a vertical scanning circuit 412, and a control circuit 416 instead of the pixel array section 111, vertical scanning circuit 112, and control circuit 116 of the first embodiment described above. The rest of the configuration of this solid-state imaging device is the same as the configuration of the solid-state imaging device of the first embodiment described above.

The pixel array unit 411 includes a plurality of cells CE. The cells CE are arranged in a matrix along the row and column directions. Four cells CE share one floating diffusion. In this case, four adjacent cells CE in the row and column directions can form a quad-Bayer array. In a quad-Bayer array, for example, a red pixel R can be assigned to four pixels included in the first cell of the first row and first column. A green pixel Gr can be assigned to four pixels included in the second cell of the first row and second column. A green pixel Gb can be assigned to four pixels included in the third cell of the second row and first column. A blue pixel B can be assigned to four pixels included in the fourth cell of the second row and second column. Each cell CE can form a source follower with the column signal processing units 114A, 114B when reading out a signal.

Each cell CE is connected to horizontal drive lines HLA, HLB in the row direction, and to vertical signal lines VLA, VLB in the column direction. At this time, each cell CE is connected to the horizontal drive lines HLA, HLB alternately in the row direction. Also, two adjacent cells CE in the row direction share one of the vertical signal lines VLA, VLB. At this time, two adjacent cells CE in the row direction are connected to the same vertical signal line VLA, VLB every third cell in the column direction. Also, two adjacent cells CE in the row direction alternately share the vertical signal lines VLA, VLB of the same column every other cell in the column direction.

In other words, in the pixel array section 411, a unit block UC is made up of 16 cells CE belonging to four adjacent first to fourth rows and four adjacent first to fourth columns. The connection between the vertical signal lines VLA, VLB and the cells CE is set for each unit block UC. In this case, the connection relationship between the vertical signal lines VLA, VLB and the cells CE for each unit block UC is the same as the connection relationship between the vertical signal lines VLA, VLB and the pixels PX for each unit block UB in the first embodiment described above.

Each horizontal drive line HLA, HLB drives each cell CE in the row direction when reading out a signal from each pixel included in the cell CE. The vertical signal lines VLA, VLB transmit a potential based on the current that flows when reading out a signal from each pixel included in the cell CE in the column direction to the column signal processing units 114A, 114B.

The vertical scanning circuit 412 scans the pixels contained in the cell CE to be read in the column direction. At this time, the vertical scanning circuit 412 can drive the cells CE via the horizontal drive lines HLA and HLB so that pixel signals are output at different times from two cells CE that share the vertical signal lines VLA and VLB.

The control circuit 416 controls the vertical scanning circuit 412, column signal processing units 114A and 114B, selection circuits S1 to S4, etc., and horizontal scanning circuit 115. For example, the control circuit 416 can control the scanning timing in the column direction, the scanning timing in the row direction, the selection timing of selection circuits S1 to S4, etc., and the processing timing of column signal processing units 114A and 114B. In this case, the control circuit 416 can coordinate the vertical scanning circuit 412, selection circuits S1 to S4, etc., column signal processing units 114A and 114B, and horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

Here, this solid-state imaging device can be provided with, for example, three readout modes. In the first mode, individual readout can be performed from each pixel included in the cell CE. In this first mode, higher image resolution can be achieved. In the second mode, pixel signals from four pixels included in the cell CE can be binned and read out for each column. In this second mode, higher image sensitivity can be achieved. In the third mode, pixel signals from four pixels included in the cell CE can be binned and read out for multiple, mutually different columns. For example, pixel signals from four red pixels R in the cell CE in the first column and pixel signals from four red pixels R in the cell CE in the third column can be binned and read out. In this third mode, even higher image sensitivity can be achieved.

FIG. 11 is a diagram showing an example of the circuit configuration of a cell provided in a solid-state imaging device according to the fourth embodiment.

In the same figure, cell CE has photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 instead of photodiode 121 and transfer transistor 122 of the first embodiment described above. The rest of the configuration of cell CE in the fourth embodiment is the same as the configuration of pixel PX in the first embodiment described above.

The photodiodes 121-1 to 121-4 can be arranged in two rows and two columns. In this case, each of the photodiodes 121-1 to 121-4 can form a pixel. Each of the photodiodes 121-1 to 121-4 is connected to a floating diffusion 126 via a transfer transistor 122-1 to 122-4, respectively. In this case, one floating diffusion 126 can be shared by the four pixels included in the cell CE. Transfer signals TRG1 to TRG4 are applied to the gates of the transfer transistors 122-1 to 122-4. By controlling the application timing of these transfer signals TRG1 to TRG4, signals can be read out individually from each of the photodiodes 121-1 to 121-4, or signals can be binned and read out from each of the photodiodes 121-1 to 121-4.

In this way, in the fourth embodiment described above, pixel signals that have been added using source followers are AD converted based on the selection results of multiple vertical signal lines VLA, VLB that are in different columns in a quad Bayer arrangement. This makes it possible to bin and AD convert pixel signals output from multiple cells CE in the same row while suppressing an increase in pixel size.

It should be noted that the dummy pixel array unit 211 and dummy selection circuit DS of the second embodiment described above may be applied to the solid-state imaging device of the fourth embodiment described above, or the dummy pixel array unit 211 and dummy selection circuit DS' of the third embodiment described above may be applied.

5. Fifth embodiment
In the first embodiment described above, the AD conversion units A1 to A6, etc. are arranged on both sides of the pixel array unit in the Bayer arrangement. In this fifth embodiment, the AD conversion units A1 to A6, etc. are arranged on one side of the pixel array unit in the Bayer arrangement.

FIG. 12 is a block diagram showing an example configuration of a solid-state imaging device according to the fifth embodiment.

In the figure, this solid-state imaging device has a column signal processing unit 114A' and selection circuits S1', S3', etc. instead of the column signal processing unit 114A and selection circuits S1, S3, etc. of the first embodiment described above. The rest of the configuration of this solid-state imaging device is the same as the configuration of the solid-state imaging device of the first embodiment described above.

The column signal processing unit 114A' and selection circuits S1', S3'... are arranged on the same side as the column signal processing unit 114B and selection circuits S2, S4... in the column direction of the pixel array unit 111. The rest of the configuration of the column signal processing unit 114A' and selection circuits S1', S3'... is the same as the configuration of the column signal processing unit 114A and selection circuits S1, S3... in the first embodiment described above.

In this way, in the fifth embodiment described above, the column signal processing units 114A', 114B and selection circuits S1', S2, S3', S4... are arranged on one side of the Bayer-arranged pixel array unit 111. This allows the column signal processing units 114A', 114B and selection circuits S1', S2, S3', S4... to be arranged closely together, suppressing non-uniformity in the characteristics of the column signal processing units 114A', 114B and selection circuits S1', S2, S3', S4... that is caused by in-plane variations in the manufacturing process.

It should be noted that the dummy pixel array unit 211 and dummy selection circuit DS of the second embodiment described above may be applied to the solid-state imaging device of the fifth embodiment described above, or the dummy pixel array unit 211 and dummy selection circuit DS' of the third embodiment described above may be applied, or the quad Bayer arrangement of the fourth embodiment described above may be applied.

6. Sixth embodiment
In the first embodiment described above, pixel signals that are source follower added based on the selection results of multiple vertical signal lines VLA and VLB that are in different columns in a Bayer arrangement are AD converted. In this sixth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

Figure 13 is a perspective view showing an example of the stacking of a pixel array unit according to the sixth embodiment.

In the same figure, the solid-state imaging device includes semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be the pixels PX of FIG. 3, or the four-pixel shared cells CE of FIG. 10. Pad electrodes 932 and via electrodes 933 are formed around the periphery of the pixel array section 923. The via electrodes 933 pass through the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

A peripheral circuit 924 is formed on the semiconductor chip 921. A selection circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed in the peripheral circuit 924. The selection circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array unit 923 in the column direction. The selection circuit 925 may be provided with the selection circuits S1 to S4, etc., of the first to fifth embodiments described above. The column ADC 926 may be provided with the AD conversion units A1 to A6, etc., of the first to fifth embodiments described above.

The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used to directly bond the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on a Cu-Cu connection. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

In this way, in the sixth embodiment described above, the semiconductor chip 922 on which the pixel array section 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of the semiconductor chip on which the solid-state imaging device is formed.

<7. Mobile application examples>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

Figure 14 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.

The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. In the example shown in FIG. 14, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.

The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a driveforce generating device such as an internal combustion engine or drive motor that generates vehicle driveforce, a driveforce transmission mechanism that transmits driveforce to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates vehicle braking force.

The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 accepts these radio waves or signal inputs and controls the vehicle's door lock device, power window device, lamps, etc.

The outside vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to an imaging unit 12031. The outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. Furthermore, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. Connected to the in-vehicle information detection unit 12040 is, for example, a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby enabling cooperative control aimed at autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

In addition, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

The audio/video output unit 12052 transmits at least one audio and/or video output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 14, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

Figure 15 shows an example of the installation position of the imaging unit 12031.

In FIG. 15, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, on the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly capture images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly capture images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly captures images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

Note that Figure 15 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 12101 to 12104, an overhead image of vehicle 12100 viewed from above can be obtained.

At least one of the image capturing units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera consisting of multiple image capturing elements, or an image capturing element having pixels for phase difference detection.

For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify and extract three-dimensional object data regarding three-dimensional objects into categories such as motorcycles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, it can provide driving assistance to avoid a collision by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drivetrain control unit 12010.

At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio/video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio/video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian in a desired position.

The foregoing describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging devices of the first to sixth embodiments described above can be applied to the imaging unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to increase the sensitivity of the imaging device while suppressing an increase in the size of the imaging device.

Note that the above-described embodiment is merely an example of how the present technology can be realized, and there is a corresponding relationship between the particulars in the embodiment and the particulars specifying the invention in the claims. Similarly, there is a corresponding relationship between the particulars specifying the invention in the claims and the particulars in the embodiment of the present technology that have the same title. However, the present technology is not limited to the embodiment, and can be realized by making various modifications to the embodiment without departing from the gist of the technology. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

The present technology can also be configured as follows.
(1) a pixel array section in which pixels are arranged in a matrix in the row and column directions;
a vertical signal line that transmits pixel signals output from the pixels in the column direction;
a selection circuit for selecting a plurality of vertical signal lines that are in different columns from one another;
an AD conversion unit that performs AD conversion on pixel signals that have been binned based on a result of selection of the vertical signal lines by the selection circuit.
(2) The imaging device according to (1), wherein the selection circuit performs the binning based on source follower addition.
(3) The imaging device according to (1) or (2), wherein the AD conversion unit AD converts the binning result of pixel signals output from a plurality of pixels that are in the same row but different columns.
(4) The selection circuit
a first selection circuit for selecting a plurality of vertical signal lines that are in different columns from one another;
The imaging device described in any one of (1) to (3) is provided with a second selection circuit that selects multiple vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the column.
(5) In the pixel array unit, pixel signals output from pixels located in different columns share the vertical signal line;
The imaging device according to (4), wherein the number of vertical signal lines provided between the different columns matches the shift in the row direction of the number of vertical signal lines of the columns.
(6) The AD conversion unit
a first AD conversion unit that performs AD conversion on a first pixel signal that has been binned based on a selection result of the vertical signal line by the first selection circuit;
The imaging device according to (4) or (5), further comprising a second AD conversion unit that AD converts second pixel signals binned based on a selection result of the vertical signal line by the second selection circuit.
(7) the first selection circuit and the first AD conversion unit are arranged on one side of the pixel array unit in the column direction;
The imaging device according to (6), wherein the second selection circuit and the second AD conversion unit are arranged on the other side of the pixel array unit in the column direction.
(8) The imaging device according to any one of (1) to (7), wherein the pixels adjacent to each other in the row direction are connected to the same vertical signal line.
(9) a dummy pixel array section arranged adjacent to the pixel array section in the row direction, in which dummy pixels are arranged in a matrix in the row direction and the column direction;
a dummy selection circuit for selecting a vertical signal line arranged at an end of the pixel array unit adjacent to the dummy pixel array unit,
The imaging device according to any one of (1) to (8), wherein the vertical signal line selected by the dummy selection circuit is shared by pixels at an end of the pixel array section and dummy pixels at an end of the dummy pixel array section.
(10) The pixel array unit
the first to fourth rows adjacent to each other;
The first to fifth columns are adjacent to each other,
An imaging device described in any one of (1) to (9), wherein the connection between the vertical signal lines and the pixels is set in units of 16 pixels arranged from the first row to the fourth row and the first column to the fourth column.
(11) The first column includes a first vertical signal line and a second vertical signal line;
the second column includes a third vertical signal line and a fourth vertical signal line;
the third column includes a fifth vertical signal line and a sixth vertical signal line;
the fourth column includes a seventh vertical signal line and an eighth vertical signal line;
The imaging device according to (10), wherein the fifth column includes a ninth vertical signal line and a tenth vertical signal line.
(12) The selection circuit
a first selection circuit connected to the first to eighth vertical signal lines;
and a second selection circuit connected to the third to tenth vertical signal lines.
(13) The AD conversion unit
a first AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the first vertical signal line and the fifth vertical signal line;
a second AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the fourth vertical signal line and the eighth vertical signal line;
a third AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the third vertical signal line and the seventh vertical signal line;
and a fourth AD converter that performs AD conversion on the pixel signal based on a selection result of the sixth vertical signal line and the tenth vertical signal line.
(14) A first pixel in the first row and the first column is connected to the first vertical signal line;
a second pixel in the second row and the first column and a sixth pixel in the second row and the second column are connected to the third vertical signal line;
a third pixel in the third row and the first column is connected to the second vertical signal line;
a fourth pixel in the fourth row and the first column and an eighth pixel in the fourth row and the second column are connected to the fourth vertical signal line;
a fifth pixel in the first row and the second column and a ninth pixel in the first row and the third column are connected to the fifth vertical signal line;
the seventh pixel in the third row and the second column and the eleventh pixel in the third row and the third column are connected to the sixth vertical signal line;
the tenth pixel in the second row and the third column and the fourteenth pixel in the second row and the fourth column are connected to the seventh vertical signal line;
the twelfth pixel in the fourth row and the third column and the sixteenth pixel in the fourth row and the fourth column are connected to the eighth vertical signal line;
a thirteenth pixel in the first row and the fourth column is connected to the ninth vertical signal line;
The imaging device according to (13), wherein the 15th pixel in the third row and the fourth column is connected to the 10th vertical signal line.
(15) The first pixel, the third pixel, the sixth pixel, the eighth pixel, the tenth pixel, the twelfth pixel, the thirteenth pixel, and the fifteenth pixel are read out at a first timing;
The imaging device described in (15), wherein the second pixel, the fourth pixel, the fifth pixel, the seventh pixel, the ninth pixel, the eleventh pixel, the fourteenth pixel, and the sixteenth pixel are read out at a second timing.
(16) The imaging device according to any one of (10) to (15), wherein the pixels are arranged in a Bayer array.
(17) The imaging device according to any one of (10) to (15), wherein the pixels are arranged in a quad-Bayer array.
(18) selecting a plurality of vertical signal lines that transmit pixel signals output from pixels arranged in a matrix in the row and column directions in the column direction;
an imaging method for binning the pixel signals based on a selection result of the plurality of vertical signal lines;
(19) The imaging method according to (18), in which a binning result of pixel signals output from a plurality of pixels in the same row but different columns is AD converted.
(20) The imaging method described in (18) or (19), wherein, while selecting multiple vertical signal lines in different columns, multiple vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the column are selected.

REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control section 104 Image processing section 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel array section 112 Vertical scanning circuit 114A, 114B Column signal processing section 115 Horizontal scanning circuit 116 Control circuit S1 to S4 Selection circuits A1 to A6 AD conversion section PX Pixel HLA, HLB Horizontal drive lines VLA, VLB Vertical signal lines

Claims (20)

a pixel array section in which pixels are arranged in a matrix in row and column directions;
a vertical signal line that transmits pixel signals output from the pixels in the column direction;
a selection circuit for selecting a plurality of vertical signal lines that are in different columns from one another;
an AD conversion unit that performs AD conversion on pixel signals that have been binned based on a result of selection of the vertical signal lines by the selection circuit. The imaging device according to claim 1 , wherein the selection circuit performs the binning based on source follower addition. The imaging device according to claim 1 , wherein the AD conversion unit performs AD conversion on a binning result of pixel signals output from a plurality of pixels that are in the same row but different columns. The selection circuit
a first selection circuit for selecting a plurality of vertical signal lines that are in different columns from one another;
The imaging device according to claim 1 , further comprising a second selection circuit for selecting a plurality of vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the column. In the pixel array unit, pixel signals output from pixels located in different columns share the vertical signal line,
5. The imaging device according to claim 4, wherein the number of vertical signal lines provided between the different columns is equal to the shift in the row direction by the number of vertical signal lines between the columns. The AD conversion unit
a first AD conversion unit that performs AD conversion on a first pixel signal that has been binned based on a selection result of the vertical signal line by the first selection circuit;
The imaging device according to claim 4 , further comprising a second AD converter that performs AD conversion on second pixel signals binned based on a selection result of the vertical signal line by the second selection circuit. the first selection circuit and the first AD conversion unit are arranged on one side of the pixel array unit in the column direction;
The imaging device according to claim 6 , wherein the second selection circuit and the second AD conversion unit are arranged on the other side of the pixel array unit in the column direction. The imaging device according to claim 1 , wherein the pixels adjacent to each other in the row direction are connected to the same vertical signal line. a dummy pixel array section arranged adjacent to the pixel array section in the row direction, in which dummy pixels are arranged in a matrix in the row direction and the column direction;
a dummy selection circuit for selecting a vertical signal line arranged at an end of the pixel array unit adjacent to the dummy pixel array unit,
The imaging device according to claim 1 , wherein the vertical signal line selected by the dummy selection circuit is shared by pixels at an end of the pixel array section and dummy pixels at an end of the dummy pixel array section. The pixel array unit
the first to fourth rows adjacent to each other;
The first to fifth columns are adjacent to each other,
2. The imaging device according to claim 1, wherein the connections between the vertical signal lines and the pixels are set in units of 16 pixels arranged in the first to fourth rows and the first to fourth columns. the first column includes a first vertical signal line and a second vertical signal line;
the second column includes a third vertical signal line and a fourth vertical signal line;
the third column includes a fifth vertical signal line and a sixth vertical signal line;
the fourth column includes a seventh vertical signal line and an eighth vertical signal line;
The imaging device according to claim 10 , wherein the fifth column includes a ninth vertical signal line and a tenth vertical signal line. The selection circuit
a first selection circuit connected to the first to eighth vertical signal lines;
The imaging device according to claim 11 , further comprising: a second selection circuit connected to the third to tenth vertical signal lines. The AD conversion unit
a first AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the first vertical signal line and the fifth vertical signal line;
a second AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the fourth vertical signal line and the eighth vertical signal line;
a third AD conversion unit that performs AD conversion on the pixel signal based on a selection result of the third vertical signal line and the seventh vertical signal line;
The imaging device according to claim 12 , further comprising: a fourth AD converter that performs AD conversion on the pixel signal based on a selection result of the sixth vertical signal line and the tenth vertical signal line. a first pixel in the first row and the first column is connected to the first vertical signal line;
a second pixel in the second row and the first column and a sixth pixel in the second row and the second column are connected to the third vertical signal line;
a third pixel in the third row and the first column is connected to the second vertical signal line;
a fourth pixel in the fourth row and the first column and an eighth pixel in the fourth row and the second column are connected to the fourth vertical signal line;
a fifth pixel in the first row and the second column and a ninth pixel in the first row and the third column are connected to the fifth vertical signal line;
the seventh pixel in the third row and the second column and the eleventh pixel in the third row and the third column are connected to the sixth vertical signal line;
the tenth pixel in the second row and the third column and the fourteenth pixel in the second row and the fourth column are connected to the seventh vertical signal line;
the twelfth pixel in the fourth row and the third column and the sixteenth pixel in the fourth row and the fourth column are connected to the eighth vertical signal line;
a thirteenth pixel in the first row and the fourth column is connected to the ninth vertical signal line;
The imaging device according to claim 13 , wherein a fifteenth pixel in the third row and the fourth column is connected to the tenth vertical signal line. the first pixel, the third pixel, the sixth pixel, the eighth pixel, the tenth pixel, the twelfth pixel, the thirteenth pixel, and the fifteenth pixel are read out at a first timing;
The imaging device according to claim 14 , wherein the second pixel, the fourth pixel, the fifth pixel, the seventh pixel, the ninth pixel, the eleventh pixel, the fourteenth pixel, and the sixteenth pixel are read out at a second timing. The imaging device according to claim 10 , wherein the pixels are arranged in a Bayer array. The imaging device according to claim 10 , wherein the pixels are arranged in a quad-Bayer array. selecting a plurality of vertical signal lines for transmitting pixel signals in the column direction, the pixel signals being output from pixels arranged in a matrix in the row direction and the column direction;
an imaging method for binning the pixel signals based on a selection result of the plurality of vertical signal lines; 20. The imaging method according to claim 18, wherein a binning result of pixel signals output from a plurality of pixels having the same row but different columns is AD converted. 19. The imaging method according to claim 18, wherein, simultaneously with selecting the plurality of vertical signal lines in different columns, a plurality of vertical signal lines in different columns that are shifted in the row direction by the number of vertical signal lines in the column are selected.