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WO2025192016A1 - Dispositif d'imagerie et procédé d'imagerie - Google Patents

Dispositif d'imagerie et procédé d'imagerie

Info

Publication number
WO2025192016A1
WO2025192016A1 PCT/JP2025/001023 JP2025001023W WO2025192016A1 WO 2025192016 A1 WO2025192016 A1 WO 2025192016A1 JP 2025001023 W JP2025001023 W JP 2025001023W WO 2025192016 A1 WO2025192016 A1 WO 2025192016A1
Authority
WO
WIPO (PCT)
Prior art keywords
floating diffusion
potential
assist
transistor
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2025/001023
Other languages
English (en)
Japanese (ja)
Inventor
謙吾 梅田
祐人 佐藤
公康 椎名
頼人 坂野
聡子 飯田
ヨハネス ソルハスビック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2025192016A1 publication Critical patent/WO2025192016A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

  • This technology relates to an imaging device and an imaging method. More specifically, this technology relates to an imaging device and an imaging method that are provided with multiple floating diffusions.
  • multiple floating diffusions may be provided in a pixel.
  • an imaging device has been disclosed that generates an autofocus signal in response to a row driver activation signal for half or less of the light-receiving elements included in one pixel that includes first to fourth subpixels (see, for example, Patent Document 1).
  • This technology was developed in light of these circumstances, and aims to improve the efficiency of charge transfer between floating diffusions.
  • This technology has been developed to solve the above-mentioned problems, and its first aspect is an imaging device that includes a first floating diffusion to which charge is transferred from a photoelectric conversion unit, a second floating diffusion connectable to the first floating diffusion, and an assist electrode that assists the transfer of charge between the first floating diffusion and the second floating diffusion. This has the effect of improving the efficiency of charge transfer between the first floating diffusion and the second floating diffusion.
  • the assist electrode may be disposed on the first floating diffusion. This has the effect of improving the efficiency of charge transfer via the first floating diffusion.
  • the assist electrode may be disposed on the second floating diffusion. This has the effect of improving the efficiency of charge transfer via the second floating diffusion.
  • the device may further comprise a plurality of pixels sharing the first floating diffusion, a reset transistor that resets the first floating diffusion and the second floating diffusion, an amplification transistor that outputs a signal according to the potential of the first floating diffusion, and a selection transistor that selects the output of the amplification transistor.
  • a switching transistor may be further provided that switches the conversion efficiency of the amplifying transistor. This brings about the effect of realizing DCG (Dual Conversion Gain)-HDR.
  • an assist control unit may be provided that increases the potential of the second floating diffusion via the assist electrode when phase difference information is acquired, and decreases the potential of the second floating diffusion via the assist electrode when luminance information is acquired. This reduces conversion efficiency, enabling the acquisition of phase difference information, while enabling charge to be transferred from the second floating diffusion to the first floating diffusion.
  • a capacitor may be provided for storing the charge photoelectrically converted by the pixel. This has the effect of holding the charge transferred from the photoelectric conversion unit.
  • an assist control unit may be provided that reduces the potential of the first floating diffusion via the assist electrode for each subframe obtained by dividing a frame, and transfers the charge accumulated in the first floating diffusion to the capacitor. This has the effect of making it possible to read out the charge accumulated for each subframe from the capacitor for each frame.
  • the device may further include an assist control unit that reduces the potential of the first floating diffusion via the assist electrode and transfers the charge that has overflowed into the first floating diffusion to the capacitor. This has the effect of causing the charge that has overflowed into the first floating diffusion to be held in the capacitor.
  • an assist control unit may be provided that increases the potential of the first floating diffusion via the assist electrode when charge is accumulated in the photoelectric conversion unit, and decreases the potential of the first floating diffusion via the assist electrode when phase difference information is acquired, and transfers the charge accumulated in the first floating diffusion to the second floating diffusion. This provides the effect of retaining charge that has overflowed from the photoelectric conversion unit, emptying the first floating diffusion of charge, and then transferring charge from the photoelectric conversion unit to the first floating diffusion.
  • the assist control unit may lower the potential of the first floating diffusion via the assist electrode when acquiring a luminance signal, and transfer the charge accumulated in the first floating diffusion to the capacitor. This has the effect of causing the charge that has overflowed to the second floating diffusion to be held in the capacitor.
  • the pixels may be arranged in a quad-Bayer array. This has the effect of achieving HDR while increasing the resolution of color images.
  • an overflow control transistor may be further provided that controls overflow from the pixel to the capacitor. This has the effect of retaining charge that overflows from the pixel without passing through the first floating diffusion and the second floating diffusion.
  • the second aspect is an imaging method that controls the potential of the first floating diffusion or the second floating diffusion via an assist electrode provided on the first floating diffusion to which charge is transferred from a photoelectric conversion unit or on a second floating diffusion connectable to the first floating diffusion, thereby assisting the transfer of charge between the first floating diffusion and the second floating diffusion. This has the effect of improving the efficiency of charge transfer between the first floating diffusion and the second floating diffusion.
  • the potential of the second floating diffusion may be increased via the assist electrode, and a pixel signal used for phase difference information may be read from the pixel when the conversion efficiency of converting charge to voltage is reduced; the potential of the second floating diffusion may be decreased via the assist electrode, and charge may be transferred from the second floating diffusion to the first floating diffusion; and a pixel signal used for luminance information may be read from the first floating diffusion when the conversion efficiency is increased.
  • the potential of the first floating diffusion may be lowered via the assist electrode for each subframe obtained by dividing a frame, the charge accumulated in the first floating diffusion may be transferred to a capacitor, and the charge transferred to the capacitor may be read out for each frame. This brings about the effect that the charge accumulated for each subframe can be read out from the capacitor for each frame.
  • the potential of the first floating diffusion may be increased via the assist electrode when charge is accumulated in the photoelectric conversion unit, and the potential of the first floating diffusion may be decreased via the assist electrode when phase difference information is acquired, and the charge accumulated in the first floating diffusion may be transferred to the second floating diffusion. This results in the effect that the charge accumulated in the first floating diffusion is held in the second floating diffusion.
  • FIG. 1 is a block diagram illustrating an example of the configuration of an imaging apparatus according to a first embodiment.
  • 1 is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a first embodiment.
  • FIG. 2 is a diagram illustrating an example of a circuit configuration of a cell provided in the solid-state imaging device according to the first embodiment.
  • 4 is a timing chart showing an example of a readout operation of the solid-state imaging device according to the first embodiment.
  • FIG. 4 is a diagram illustrating an example of potential during a readout period of the solid-state imaging device according to the first embodiment.
  • FIG. 2 is a plan view showing a first example of a cell layout according to the first embodiment; FIG.
  • FIG. 2 is a cross-sectional view showing a first example of a cell configuration according to the first embodiment.
  • FIG. 10 is a plan view showing a second example of a cell layout according to the first embodiment.
  • FIG. 4 is a cross-sectional view showing a second example of the configuration of the cell according to the first embodiment.
  • FIG. 10 is a diagram illustrating an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a second embodiment. 10 is a timing chart showing an example of a readout operation of the solid-state imaging device according to the second embodiment.
  • FIG. 10 is a diagram illustrating an example of potential during a readout period of the solid-state imaging device according to the second embodiment.
  • FIG. 10 is a diagram illustrating an example of potential during a readout period of the solid-state imaging device according to the second embodiment.
  • FIG. 10 is a plan view showing an example of a pixel layout according to a second embodiment.
  • FIG. 10 is a cross-sectional view illustrating a configuration example of a pixel according to a second embodiment.
  • FIG. 10 is a diagram illustrating an example of a circuit configuration of a cell provided in a solid-state imaging device according to a third embodiment. 10 is a timing chart showing an example of a readout operation of the solid-state imaging device according to the third embodiment.
  • FIG. 11 is a diagram illustrating an example of potential during a readout period of a solid-state imaging device according to a third embodiment.
  • FIG. 10 is a plan view showing an example of a pixel layout according to a second embodiment.
  • FIG. 10 is a cross-sectional view illustrating a configuration example of a pixel according to a second embodiment.
  • FIG. 10 is
  • FIG. 11 is a diagram illustrating an example of potential during a readout period of a solid-state imaging device according to a third embodiment.
  • FIG. 11 is a plan view showing an example of a layout of cells according to a third embodiment.
  • FIG. 10 is a cross-sectional view showing a configuration example of a cell according to a third embodiment.
  • FIG. 10 is a diagram illustrating an example of a circuit configuration of a cell provided in a solid-state imaging device according to a fourth embodiment.
  • 13 is a timing chart showing an example of a readout operation of the solid-state imaging device according to the fourth embodiment.
  • FIG. 13 is a diagram illustrating an example of potential during a readout period of a solid-state imaging device according to a fourth embodiment.
  • FIG. 13 is a diagram illustrating an example of potential during a readout period of a solid-state imaging device according to a fourth embodiment.
  • FIG. 13 is a plan view showing an example of a layout of cells according to a fourth embodiment;
  • FIG. 10 is a cross-sectional view showing a configuration example of a cell according to a fourth embodiment.
  • FIG. 13 is a diagram illustrating an example of a circuit configuration of a cell provided in a solid-state imaging device according to a fifth embodiment.
  • FIG. 13 is a plan view showing a first layout example of a cell according to a fifth embodiment;
  • FIG. 13 is a cross-sectional view showing a first configuration example of a cell according to a fifth embodiment.
  • FIG. 13 is a plan view showing a second layout example of the cell according to the fifth embodiment.
  • FIG. 13 is a cross-sectional view showing a second configuration example of the cell according to the fifth embodiment.
  • FIG. 13 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to a sixth embodiment.
  • 1 is a block diagram illustrating a schematic configuration example of a vehicle control system.
  • FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment an example in which an assist electrode is provided to control the potential of the floating diffusion, and the potential of the floating diffusion is increased via the assist electrode when phase difference information is acquired, and the potential of the floating diffusion is decreased via the assist electrode when luminance information is acquired
  • Second embodiment an example in which the potential of the floating diffusion is lowered via an assist electrode for each subframe obtained by dividing a frame, and the charge accumulated in the floating diffusion is transferred to a capacitor
  • Third embodiment (example in which the potential of the floating diffusion is lowered via the assist electrode when phase difference information is acquired, and the charge overflowing into the floating diffusion is transferred to the capacitor) 4.
  • FIG. 1 is a block diagram showing an example of the configuration of an imaging apparatus according to the first embodiment.
  • the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a memory unit 105, a display unit 106, and an operation unit 107.
  • the imaging device 100 also includes a drive control unit 109.
  • the imaging control unit 103, the image processing unit 104, the memory unit 105, the display unit 106, the operation unit 107, and the drive control unit 109 are connected to one another via a bus 108.
  • the imaging device 100 may be used standalone, or may be incorporated into a mobile terminal such as a smartphone, an authentication device or a monitoring device, or a vehicle or drone.
  • the optical system 101 allows light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102.
  • the optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture.
  • the optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.
  • the solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. At this time, the solid-state imaging device 102 can perform HDR by switching the conversion efficiency of the pixels.
  • the solid-state imaging device 102 can also include multiple floating diffusions to which charges are transferred from the pixels.
  • the solid-state imaging device 102 may also include multiple pixels per column that can acquire phase difference information.
  • the solid-state imaging device 102 may also acquire luminance information from the multiple pixels used to acquire the phase difference information.
  • the solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • the CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.
  • the imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.
  • the image processing unit 104 performs image processing based on the output from the solid-state imaging device 102.
  • Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing.
  • the image processing unit 104 may include a processor that executes processing based on software.
  • the image processing unit 104 includes an HDR processing unit 104A.
  • HDR processing unit 104A performs HDR processing based on pixel signals read out from solid-state imaging device 102.
  • HDR processing unit 104A can generate an HDR image based on a combination of pixel signals read out from solid-state imaging device 102 with low conversion efficiency and pixel signals read out from solid-state imaging device 102 with high conversion efficiency.
  • the storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102.
  • the storage unit 105 can also store programs that operate the imaging device 100 based on software.
  • the storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.
  • the display unit 106 displays captured images and various information that supports the capture operation.
  • the display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.
  • the operation unit 107 provides a user interface for operating the imaging device 100.
  • the operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100.
  • the operation unit 107 may also be configured as a touch panel together with the display unit 106.
  • the drive control unit 109 controls the drive of the optical system 101 based on pixel signals read out from the solid-state imaging device 102 and operation information operated by the operation unit 107.
  • the drive control unit 109 can obtain phase difference information based on pixel signals read out from the solid-state imaging device 102, and control autofocus based on the phase difference information.
  • the drive control unit 109 can also perform manual focus and control zoom magnification based on operation information operated by the operation unit 107.
  • FIG. 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.
  • the pixel array section 111 includes a plurality of cells 120.
  • the cells 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction).
  • a cell 120 may share two pixels with one floating diffusion, four pixels with one floating diffusion, eight pixels with one floating diffusion, or may be composed of a single pixel. Multiple pixels included in a cell 120 may be used as phase difference pixels.
  • a cell 120 may also include a capacitor that stores charge transferred from the pixel.
  • the capacitor may be an MIM (Metal Insulation Metal) capacitor.
  • a cell 120 can form a source follower with the column readout circuit 113 when reading out a signal.
  • Each cell 120 is connected to a horizontal drive line 131 in the row direction and to a vertical signal line 132 in the column direction.
  • the horizontal drive line 131 drives each cell 120 horizontally when reading out a signal from the cell 120.
  • the vertical signal line 132 vertically transmits a potential based on the current that flows when a signal is read from the cell 120 to the column signal processing unit 114.
  • the pixels included in the cell 120 may be arranged in a Bayer array or a quad-Bayer array.
  • the light received by each pixel included in each cell 120 may be visible light, near-infrared light (NIR: Near Infrared), short-wave infrared light (SWIR: Short Wavelength Infrared), ultraviolet light, or X-rays.
  • NIR Near Infrared
  • SWIR Short Wavelength Infrared
  • ultraviolet light or X-rays.
  • the vertical scanning circuit 112 vertically scans each pixel included in the cell 120 to be read.
  • the vertical scanning circuit 112 may be configured using a vertical register.
  • the vertical scanning circuit 112 may include an address decoder, or may include a driver that drives the horizontal drive lines 131 selected via the address decoder for each row.
  • the vertical scanning circuit 112 includes an assist control unit 112A.
  • the assist control unit 112A assists in the transfer of charge between the multiple floating diffusions included in the cell 120.
  • the assist control unit 112A can control the potential of the floating diffusion of each cell 120 to assist in the transfer of charge between the multiple floating diffusions.
  • the assist control unit 112A can form a potential gradient between the floating diffusions of each cell 120.
  • the column readout circuit 113 When reading out a signal from a cell 120, the column readout circuit 113 can form a source follower with each cell 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the cell 120.
  • the column signal processing unit 114 processes signals transmitted vertically from the cells 120.
  • the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted vertically from the cells 120.
  • CDS correlated double sampling
  • the column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted vertically from each cell 120, and output the imaging signal Gout.
  • AD Analog to Digital
  • the column signal processing unit 114 includes a column ADC unit 114A.
  • the column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the results of comparing the pixel signal read from the cell 120 with a reference signal.
  • the horizontal scanning circuit 115 scans each pixel included in the cell 120 to be read in the row direction.
  • the horizontal scanning circuit 115 may be configured using a horizontal register.
  • the control circuit 116 controls the vertical scanning circuit 112, column readout circuit 113, column signal processing unit 114, and horizontal scanning circuit 115.
  • the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.
  • the control circuit 116 can coordinate the vertical scanning circuit 112, column readout circuit 113, column signal processing unit 114, and horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.
  • FIG. 3 is a diagram showing an example of the circuit configuration of a cell provided in a solid-state imaging device according to the first embodiment.
  • cell 120 includes photodiodes PD1 and PD2, transfer transistors TG1 and TG2, reset transistor 121, amplification transistor 122, selection transistor 123, switching transistor 124, assist electrode 125, and floating diffusions FD1 and FD2.
  • the transfer transistors TG1 and TG2, reset transistor 121, amplification transistor 122, selection transistor 123, and switching transistor 124 may be MOS (Metal Oxide Semiconductor) transistors.
  • Each photodiode PD1, PD2 performs photoelectric conversion and accumulates the photoelectrically converted charge. At this time, the photodiodes PD1, PD2 can be used to acquire phase difference information or brightness information. Each photodiode PD1, PD2 can constitute a pixel. Each transfer transistor TG1, TG2 transfers the charge accumulated in each photodiode PD1, PD2 to the floating diffusion FD1. The reset transistor 121 resets the floating diffusions FD1, FD2. At this time, the floating diffusion FD2 can be provided between the reset transistor 121 and the switching transistor 124. The amplification transistor 122 outputs a signal according to the potential of the floating diffusion FD1. The selection transistor 123 selects the output of the amplification transistor 122.
  • the switching transistor 124 switches the conversion efficiency of the amplification transistor 122. At this time, the switching transistor 124 can switch the capacitance added to the gate of the amplification transistor 122.
  • the assist electrode 125 assists in the transfer of charges between the floating diffusions FD1 and FD2.
  • the assist electrode 125 can be placed on the floating diffusion FD2. In this case, the assist electrode 125 can control the potential of the floating diffusion FD2.
  • Each transfer transistor TG1, TG2 is connected between the cathode of each photodiode PD1, PD2 and the floating diffusion FD1.
  • the floating diffusion FD1 is shared by the photodiodes PD1 and PD2.
  • the amplification transistor 122 and selection transistor 123 are connected in series.
  • the drain of the amplification transistor 122 is connected to the power supply voltage VDD.
  • the gate of the amplification transistor 122 is connected to the floating diffusion FD1.
  • the source of the selection transistor 123 is connected to the vertical signal line 132.
  • the switching transistor 124 is connected between the floating diffusions FD1 and FD2.
  • the reset transistor 121 is connected between the floating diffusion FD2 and the power supply voltage VDD.
  • Transfer signals TGL1 and TGL2 are applied to the gates of the transfer transistors TG1 and TG2.
  • a reset signal RST is applied to the gate of the reset transistor 121.
  • a selection signal SEL is applied to the gate of the selection transistor 123.
  • a switching signal FDG is applied to the gate of the switching transistor 124.
  • An assist signal AST1 is applied to the assist electrode 125.
  • the transfer signals TGL1 and TGL2, the reset signal RST, the selection signal SEL, the switching signal FDG, and the assist signal AST1 can be transmitted to the cell 120 via the horizontal drive line 131.
  • FIG. 4 is a timing chart showing an example of a readout operation of the solid-state imaging device according to the first embodiment.
  • this signal readout process includes a high conversion efficiency P-phase readout period T1, a low conversion efficiency P-phase readout period T2, a low conversion efficiency first D-phase readout period T3, a low conversion efficiency second D-phase readout period T4, and a high conversion efficiency D-phase readout period T5.
  • the assist control unit 112A can assist the transfer of charge between the floating diffusions FD1 and FD2 based on the timing set by these periods T1 to T5.
  • the high conversion efficiency P-phase readout period T1 and the low conversion efficiency P-phase readout period T2 can acquire reset signals used in CDS processing for high and low conversion efficiencies, respectively.
  • the low conversion efficiency first D-phase readout period T3 and the low conversion efficiency second D-phase readout period T4 can acquire phase difference information used for autofocus.
  • the high conversion efficiency D-phase readout period T5 can acquire brightness information used for captured images. Note that the P phase is the period during which the reset level is AD converted, and the D phase is the period during which the reset level + pixel signal is AD converted.
  • the reset signal RST rises, turning on the reset transistor 121 and resetting the floating diffusion FD1. Thereafter, the reset signal RST falls and the reset transistor 121 turns off. Also, before the high conversion efficiency P-phase read period T1, the switch signal FDG rises, turning on the switch transistor 124 and setting the conversion efficiency of the cell 120 to low conversion efficiency. Furthermore, before the high conversion efficiency P-phase read period T1, the assist signal AST1 rises and the potential of the floating diffusion FD2 is lowered via the assist electrode 125.
  • the switching signal FDG is set to a low level.
  • the switching transistor 124 is turned off, and the conversion efficiency of the cell 120 is set to high conversion efficiency.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level, and the high conversion efficiency P-phase level read from the cell 120 is AD converted for each column.
  • the switching signal FDG is set to a high level.
  • the switching transistor 124 is turned on, and the conversion efficiency of the cell 120 is set to a low conversion efficiency.
  • the floating diffusions FD1 and FD2 are connected.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level, and the low conversion efficiency P-phase level read from the cell 120 is AD converted for each column.
  • the transfer signal TGL1 rises, the transfer transistor TG1 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusions FD1 and FD2.
  • the transfer signal TGL1 falls, and the transfer transistor TG1 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency first D-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency first D-phase level, and the low conversion efficiency first D-phase level read out from the cell 120 is AD converted for each column.
  • the transfer signals TGL1 and TGL2 rise, turning on the transfer transistors TG1 and TG2 and transferring the charge accumulated in each photodiode PD1 and PD2 to the floating diffusions FD1 and FD2. Then, the transfer signals TGL1 and TGL2 fall, turning off the transfer transistors TG1 and TG2.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency second D-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency second D-phase level, and the low conversion efficiency second D-phase level read out from the cell 120 is AD converted for each column.
  • the assist signal AST1 falls, and the potential of the floating diffusion FD2 rises via the assist electrode 125.
  • the switching signal FDG is set to a low level. At this time, the switching transistor 124 turns off, and the conversion efficiency of the cell 120 is set to high conversion efficiency. If the potential of the floating diffusion FD2 rises before the switching signal FDG falls, a potential gradient is formed from the floating diffusion FD2 to the floating diffusion FD1. The charge stored in the floating diffusion FD2 is then transferred to the floating diffusion FD1.
  • the switching signal FDG may be gradually lowered to improve the efficiency of the transfer from the floating diffusion FD2 to the floating diffusion FD1.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122. Then, in the column ADC unit 114A, a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level, and the high conversion efficiency D-phase level read from the cell 120 is AD converted for each column.
  • FIG. 5 is a diagram showing an example of potentials during a readout period of the solid-state imaging device according to the first embodiment. Note that a to e in FIG. 5 show an example of potentials at timings P1 to P5 in FIG. 4. Also, a to e in FIG. 5 show an example of potentials of the photodiode PD1, transfer transistor TG1, and floating diffusions FD1 and FD2.
  • the transfer transistor TG1 and switching transistor 124 are turned off. At this time, the charge EL1 photoelectrically converted by the photodiode PD1 is stored in the photodiode PD1. In addition, the potential of the floating diffusion FD2 is lowered via the assist electrode 125.
  • the transfer transistor TG1 and switching transistor 124 are turned on.
  • the charge EL1 accumulated in the photodiode PD1 is transferred to the floating diffusions FD1 and FD2.
  • the conversion efficiency of the amplification transistor 122 is set to low. In this state, by reading out the pixel signal via the amplification transistor 122, left-side phase difference information can be obtained from the cell 120.
  • the transfer transistor TG2 is turned on.
  • the charge EL2 accumulated in the photodiode PD2 is transferred to the floating diffusions FD1 and FD2.
  • the charges EL1 and EL2 accumulated in the photodiodes PD1 and PD2 are held in the floating diffusions FD1 and FD2.
  • the sum of the left-side phase difference information and the right-side phase difference information can be obtained from the cell 120.
  • the right-side phase difference information can be obtained.
  • left-side phase difference information and right-side phase difference information can be obtained based on pixel signals read out with low conversion efficiency. Therefore, even when the signal strength is so large that the charge photoelectrically converted by photodiode PD1 cannot be contained within the capacity of floating diffusion FD1, saturation of the left-side phase difference information can be prevented, preventing autofocus failures.
  • the switching transistor 124 is turned off.
  • the conversion efficiency of the amplifier transistor 122 is set to high conversion efficiency.
  • a luminance signal can be obtained from the cell 120 by reading out the pixel signal via the amplifier transistor 122.
  • the charges accumulated in the two photodiodes PD1 and PD2 can be detected with high conversion efficiency, improving sensitivity.
  • FIG. 6 is a plan view showing a first example of a cell layout according to the first embodiment
  • FIG. 7 is a cross-sectional view showing a first example of a pixel configuration according to the first embodiment. Note that FIG. 7 shows an example configuration cut along line A1-A2 in FIG. 6.
  • the solid-state imaging device 102 includes a semiconductor substrate SUB.
  • a P-type semiconductor substrate can be used for the semiconductor substrate SUB.
  • the semiconductor substrate SUB is separated into cells 120 by pixel isolation regions ISG1.
  • the pixel isolation regions ISG1 may be, for example, rear deep trench isolation (RDTI).
  • RDTI rear deep trench isolation
  • the pixel isolation regions ISG1 can be formed in the depth direction from the back surface side of the semiconductor substrate SUB.
  • the pixel isolation regions ISG1 can be arranged at the boundaries of the cells 120.
  • An active region AK1 is provided on the semiconductor substrate SUB, and the active region AK1 is isolated by an isolation region ISA1.
  • the isolation region ISA1 may be STI (Shallow Trench Isolation).
  • Photodiodes PD1 and PD2, a channel region, and impurity diffusion layers DF1 to DF4 are formed in the active region AK1.
  • the photodiodes PD1 and PD2 are arranged symmetrically.
  • Floating diffusions FD1 and FD2 and source and drain layers of the pixel transistors are formed in the impurity diffusion layers DF1 to DF4.
  • the pixel transistors may include transfer transistors TG1 and TG2, a reset transistor 121, an amplification transistor 122, a selection transistor 123, and a switching transistor 124.
  • the impurity diffusion layer DF1 can be an N - type impurity diffusion layer.
  • the impurity diffusion layer DF1 can be disposed at the position of the photodiodes PD1 and PD2.
  • the impurity diffusion layer DF2 can be an N-type impurity diffusion layer.
  • the impurity diffusion layer DF2 can be disposed within the impurity diffusion layer DF1.
  • the impurity diffusion layer DF2 can be disposed at the position of the channel regions of the photodiodes PD1 and PD2 and the transfer transistors TG1 and TG2.
  • the impurity diffusion layer DF3 can be an N-type impurity diffusion layer.
  • the impurity diffusion layer DF3 can be disposed at the position of the channel regions of the reset transistor 121, the amplification transistor 122, the selection transistor 123, and the switching transistor 124. Furthermore, floating diffusions FD1 and FD2 can be formed in the impurity diffusion layer DF3.
  • the impurity diffusion layer DF4 can be an N + type impurity diffusion layer.
  • the impurity diffusion layer DF4 can be disposed at the position of the source layer or drain layer of the pixel transistor.
  • Gate electrodes E1, E2, G1 to G4 and an assist electrode 125 are formed on the active region AK1, with a gate insulating film GZ interposed between them. Gate electrodes E1 and E2 can be arranged symmetrically. Each gate electrode E1 and E2 can be arranged at the corner of photodiode PD1 and PD2, respectively. An impurity diffusion layer DF2 is formed below gate electrodes E1 and E2, and an impurity diffusion layer DF3 is formed below gate electrodes G1 to G4 and the assist electrode 125. The assist electrode 125 is arranged between gate electrodes G1 and G4. Gate electrodes G2 and G3 are arranged adjacent to each other. Gate electrode E1 is used for transfer transistor TG1. Gate electrode E2 is used for transfer transistor TG2. Gate electrode G1 is used for reset transistor 121. Gate electrode G2 is used for amplification transistor 122. Gate electrode G3 is used for selection transistor 123. Gate electrode G4 is used for switching transistor 124.
  • Contact CN1 is arranged at the corner between photodiodes PD1 and PD2.
  • Contact CN2 is arranged next to gate electrode G3.
  • Contact CN3 is arranged next to gate electrode G1.
  • Ground potential is applied to contact CN1.
  • the potential VSL of vertical signal line 132 is applied to contact CN2.
  • Power supply potential VDD is applied to contact CN3.
  • the semiconductor substrate SUB may be made of Si, InGaAs, InP, InSb, HgCdTe, or the like.
  • the gate electrodes E1, E2, G1 to G4 and the assist electrode 125 may be made of, for example, polycrystalline silicon.
  • the pixel isolation region ISG1 and the element isolation region ISA1 may be made of, for example, an insulator such as SiO2 .
  • a light-shielding material such as carbon black may be embedded in the pixel isolation region ISG1 to prevent color mixing, etc.
  • FIG. 8 is a plan view showing a second example of a cell layout according to the first embodiment
  • FIG. 9 is a cross-sectional view showing a second example of a cell configuration according to the first embodiment.
  • this solid-state imaging device 102 has an element isolation region ISA2, an active region AK2, and contacts CN4 and CN5 instead of the element isolation region ISA1, active region AK1, and contact CN3 of Figures 6 and 7.
  • the rest of the configuration of this solid-state imaging device 102 is the same as the configuration of the solid-state imaging device 102 of Figures 6 and 7.
  • the semiconductor substrate SUB is separated into cells 120 by pixel isolation regions ISG2.
  • the pixel isolation regions ISG2 may be, for example, FFTI (Full-thickness Front Deep Trench Isolation). In this case, the pixel isolation regions ISG2 can penetrate the semiconductor substrate SUB in the depth direction.
  • the pixel isolation regions ISG2 can be arranged on the boundaries of the cells 120.
  • An active region AK2 is provided on the semiconductor substrate SUB, and the active region AK2 is isolated by an element isolation region ISA2.
  • the element isolation region ISA2 may be STI.
  • the active region AK2 can be bent at right angles at both ends of the cell 120.
  • Photodiodes PD1 and PD2, channel regions, and impurity diffusion layers DF1 to DF4 are formed in the active region AK2.
  • Floating diffusions FD1 and FD2, and source and drain layers of the pixel transistors are formed in the impurity diffusion layers DF1 to DF4.
  • Contact CN4 is arranged adjacent to gate electrode G2 in the column direction.
  • Contact CN5 is arranged adjacent to gate electrode G1 in the column direction.
  • the power supply potential VDD is applied to contacts CN4 and CN5.
  • an assist electrode 125 that controls the potential of floating diffusion FD2, and floating diffusions FD1 and FD2 are connected to acquire phase difference information with low conversion efficiency.
  • the potential of floating diffusion FD2 is then controlled via assist electrode 125 to transfer the charge of floating diffusion FD2 to floating diffusion FD1, and floating diffusions FD1 and FD2 are separated to acquire luminance information with high conversion efficiency.
  • DCG Direct Conversion Gain
  • Second embodiment In the first embodiment described above, it is possible to acquire phase difference information at low conversion efficiency by controlling the potential of the floating diffusion FD2 via the assist electrode 125. In this second embodiment, it is possible to control the potential of the floating diffusion FD1 via the assist electrode, and transfer the charge accumulated in the floating diffusion FD1 to a capacitor for each subframe obtained by dividing a frame.
  • FIG. 10 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the second embodiment.
  • pixel 220 has a photodiode PD, a transfer transistor TG, and an assist electrode 225 instead of the photodiodes PD1 and PD2, transfer transistors TG1 and TG2, and assist electrode 125 of the first embodiment described above. Furthermore, pixel 220 has a capacitor 221 added to cell 120 of the first embodiment described above. The other configuration of pixel 220 of the second embodiment is the same as the configuration of cell 120 of the first embodiment described above.
  • the photodiode PD performs photoelectric conversion and accumulates the photoelectrically converted charge.
  • the transfer transistor TG transfers the charge accumulated in the photodiode PD to the floating diffusion FD1.
  • the assist electrode 225 assists in the transfer of charge between the floating diffusions FD1 and FD2.
  • the assist electrode 225 can be placed on the floating diffusion FD1. In this case, the assist electrode 225 can control the potential of the floating diffusion FD1.
  • Capacitor 221 holds the charge accumulated in photodiode PD. At this time, the charge accumulated in photodiode PD can be transferred to capacitor 221 via floating diffusions FD1 and FD2.
  • Capacitor 221 can be a MOM (Metal Oxide Metal) capacitor or an MIM capacitor. Capacitor 221 can be connected in series to switching transistor 124. At this time, floating diffusion FD2 can be connected between capacitor 221 and switching transistor 124. The other end of capacitor 221 can be connected to control potential MVDD. Control potential MVDD can control the voltage applied to capacitor 221 during the shutter period, accumulation period, etc. At this time, capacitor 221 can be pulse-driven based on control potential MVDD to reduce dark current. Note that control potential MVDD may be power supply potential VDD.
  • a transfer signal TGL is applied to the gate of the transfer transistor TG.
  • An assist signal AST2 is applied to the assist electrode 225.
  • the transfer signal TGL and the assist signal AST2 can be transmitted to the pixel 220 via the horizontal drive line 131.
  • FIG. 11 is a timing chart showing an example of a readout operation of a solid-state imaging device according to the second embodiment. While the diagram shows an example in which one frame is divided into eight subframes, one frame may also be divided into a number of subframes other than eight.
  • the assist control unit 112A can assist in the transfer of charge between the floating diffusions FD1 and FD2 based on the timing set for each subframe.
  • the reset signal RST falls. After that, the transfer signal TGL1 rises, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1.
  • the transfer signal TGL1 falls.
  • the assist signal AST2 falls, and then the switching signal FDG rises.
  • a potential gradient is formed from the floating diffusion FD1 to the floating diffusion FD2, and the charge accumulated in the floating diffusion FD1 is transferred to the capacitor 221 via the floating diffusion FD2.
  • the charge accumulated in the photodiode PD in one subframe is held in the capacitor 221.
  • the switching signal FDG falls, the assist signal AST2 rises, and the reset signal RST rises.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the potential based on the charge held in the capacitor 221 is applied to the gate of the amplification transistor 122. Then, in the column ADC unit 114A, a counting operation is performed based on the potential VSL of the vertical signal line 132 at this time, and the pixel signal read from the pixel 220 is AD converted for each frame.
  • the subject includes an LED (Light Emitting Diode) light source.
  • the brightness of LED light sources is adjusted using PWM (Pulse Width Modulation) control. As a result, they repeatedly turn on and off.
  • PWM Pulse Width Modulation
  • the LED light source is on during the eight subframes, charge accumulates in the photodiode PD.
  • no charge accumulates in the photodiode PD.
  • at least one of the eight subframes can include a period during which the LED light source is on.
  • FIGS. 12 and 13 are diagrams showing an example of potential during the readout period of a solid-state imaging device according to the second embodiment. Note that a to e in FIG. 12 and a to e in FIG. 13 show an example of potential at timings P21 to P25 in FIG. 11 in each of two consecutive subframes. Also, a to e in FIG. 12 and 13 show an example of potential of the photodiode PD, transfer transistor TG, and floating diffusions FD1 and FD2. Also, FIGS. 12 and 13 show a state in which the LED light source is lit.
  • the transfer transistor TG is turned off.
  • the photodiode PD and the floating diffusion FD1 are separated from each other.
  • the potential of the floating diffusion FD1 is increased via the assist electrode 225.
  • the switching transistor 124 is turned on. At this time, a potential gradient is formed from the floating diffusion FD1 to the floating diffusion FD2, and the charge EL1 stored in the floating diffusion FD1 is transferred to the capacitor 221 via the floating diffusion FD2. As a result, the charge EL1 stored in the photodiode PD in one subframe is held in the capacitor 221.
  • switching transistor 124 is turned on. At this time, a potential gradient is formed from floating diffusion FD1 to floating diffusion FD2, and charge EL2 accumulated in floating diffusion FD1 is transferred to capacitor 221 via floating diffusion FD2. As a result, charge EL2 accumulated in photodiode PD in one subframe is held in capacitor 221.
  • FIG. 14 is a plan view showing an example of a pixel layout according to the second embodiment
  • FIG. 15 is a cross-sectional view showing an example of a pixel configuration according to the second embodiment. Note that FIG. 15 shows an example of a configuration cut along line B1-B2 in FIG. 14.
  • the semiconductor substrate SUB is separated into pixels 220 by pixel isolation regions ISG1.
  • the pixel isolation regions ISG1 can be arranged at the boundaries of the pixels 220.
  • An active region AK2 is provided on the semiconductor substrate SUB, and the active region AK2 is isolated by an element isolation region ISA2.
  • a photodiode PD, a channel region, and impurity diffusion layers DF23 and DF24 are formed in the active region AK2.
  • Floating diffusions FD1 and FD2, and the source and drain layers of the pixel transistors are formed in the impurity diffusion layers DF23 and DF24.
  • the impurity diffusion layer DF23 can be an N-type impurity diffusion layer.
  • the impurity diffusion layer DF23 can be disposed at the position of the channel regions of the reset transistor 121, the amplification transistor 122, the selection transistor 123, and the switching transistor 124.
  • the impurity diffusion layer DF24 can be an N + type impurity diffusion layer.
  • the impurity diffusion layer DF24 can be disposed at the position of the source layer or drain layer of the pixel transistor. Furthermore, floating diffusions FD1 and FD2 can be formed in the impurity diffusion layer DF24.
  • Gate electrodes E21, G21 to G24, and assist electrode 225 are formed on active region AK2, each with a gate insulating film GZ interposed therebetween.
  • Gate electrode E21 can be arranged at the center of a side of photodiode PD.
  • An impurity diffusion layer DF23 is formed below gate electrodes G21 to G24 and assist electrode 225.
  • Assist electrode 225 is arranged between gate electrodes G21 and G24.
  • Gate electrode E21 is used for transfer transistor TG1.
  • Gate electrode G21 is used for reset transistor 121.
  • Gate electrode G22 is used for amplification transistor 122.
  • Gate electrode G23 is used for selection transistor 123.
  • Gate electrode G24 is used for switching transistor 124.
  • a contact CN21 is arranged in the center of one side of the photodiode PD.
  • a contact CN23 is arranged between the gate electrodes G21 and G22.
  • a contact CN22 is arranged next to the gate electrode G23.
  • a floating diffusion FD2 is arranged next to the gate electrode G24.
  • a ground potential is applied to the contact CN21.
  • a potential VSL of the vertical signal line 132 is applied to the contact CN22.
  • a power supply potential VDD is applied to the contact CN23.
  • a capacitor 221 is connected to the floating diffusion FD2.
  • pixel isolation region ISG1 was formed based on RDTI, but pixel isolation region ISG2 may also be formed based on FFTI.
  • the potential of the floating diffusion FD1 is controlled via the assist electrode 225, making it possible to transfer the charge accumulated in the floating diffusion FD1 to the capacitor 221 for each subframe into which a frame is divided.
  • This allows the charge accumulated in the photodiode PD and floating diffusion FD1 to be transferred to the capacitor 221 for each subframe without leaving any signal charge in the photodiode PD and floating diffusion FD1. Therefore, the charge generated based on intermittent exposure can be transferred to the capacitor 221 for each subframe, while the charge accumulated in the capacitor 221 can be read out for each frame, making it possible to suppress flicker that occurs when photographing an LED light source.
  • FIG. 16 is a diagram showing an example of the circuit configuration of a cell provided in a solid-state imaging device according to the third embodiment.
  • cell 320 has an assist electrode 325 instead of the assist electrode 125 of the first embodiment described above. Furthermore, cell 320 has a capacitor 321 added to cell 120 of the first embodiment described above. The rest of the configuration of cell 320 of the third embodiment is the same as the configuration of cell 120 of the first embodiment described above.
  • the assist electrode 325 assists in the transfer of charge between the floating diffusions FD1 and FD2.
  • the assist electrode 325 can be placed on the floating diffusion FD1. In this case, the assist electrode 325 can control the potential of the floating diffusion FD1.
  • Capacitor 321 holds the charge accumulated in photodiodes PD1 and PD2. At this time, the charge accumulated in photodiodes PD1 and PD2 can be transferred to capacitor 321 via floating diffusions FD1 and FD2.
  • a lateral overflow integration capacitor (LOFIC) can be used as capacitor 321.
  • Capacitor 321 can be connected in series with switching transistor 124. At this time, floating diffusion FD2 can be connected between capacitor 321 and switching transistor 124.
  • the switching transistor 124 and the reset transistor 121 can be connected in parallel to the floating diffusion FD1.
  • FIG. 17 is a timing chart showing an example of a readout operation of a solid-state imaging device according to the third embodiment.
  • this signal readout process includes a high conversion efficiency P-phase readout period T31, a high conversion efficiency first D-phase readout period T32, a high conversion efficiency second D-phase readout period T33, a D-phase batch readout period T34, and a P-phase batch readout period T35.
  • the assist control unit 112A can assist the transfer of charge between the floating diffusions FD1 and FD2 based on the timing set in these periods T31 to T35.
  • the high conversion efficiency P-phase readout period T31 can acquire a reset signal used for CDS processing for high conversion efficiency.
  • the high conversion efficiency first D-phase readout period T32 and the high conversion efficiency second D-phase readout period T33 can acquire phase difference information used for autofocus.
  • the D-phase batch readout period T34 can acquire brightness information used for captured images.
  • the P-phase batch readout period T35 can acquire a reset signal used for DDS (Double Data Sampling) processing.
  • the reset signal RST and transfer signals TGL1 and TGL2 are set to low level, and the reset transistor 121 and transfer transistors TG1 and TG2 are turned off. Furthermore, the switching signal FDG and assist signal AST3 are set to high level, turning on the switching transistor 124 and lowering the potential of the floating diffusion FD1 via the assist electrode 325. At this time, charge is accumulated in each of the photodiodes PD1 and PD2 based on the incident light, and charge overflowing from each of the photodiodes PD1 and PD2 is accumulated in the floating diffusions FD1 and FD2 and the capacitor 321.
  • the switching signal FDG falls, the switching transistor 124 turns off, and the floating diffusions FD1 and FD2 are separated from each other.
  • the assist signal AST3 falls, and the potential of the floating diffusion FD1 rises via the assist electrode 325.
  • the charge accumulated in the floating diffusion FD1 is transferred to the floating diffusion FD2.
  • the switching signal FDG rises, the switching signal FDG falls, and the charge remaining in the floating diffusion FD1 is transferred to the floating diffusion FD2.
  • the switching transistor 124 turns off, and the conversion efficiency of the cell 320 is set to high conversion efficiency.
  • the assist signal AST3 rises, and the potential of the floating diffusion FD1 is lowered via the assist electrode 325.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level, and the high conversion efficiency P-phase level read from the cell 320 is AD converted for each column.
  • the transfer signal TGL1 rises, the transfer transistor TG1 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.
  • the transfer signal TGL1 falls, and the transfer transistor TG1 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency first D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency first D-phase level, and the high conversion efficiency first D-phase level read out from the cell 320 is AD converted for each column.
  • the transfer signals TGL1 and TGL2 rise, turning on the transfer transistors TG1 and TG2 and transferring the charge accumulated in each photodiode PD1 and PD2 to the floating diffusion FD1.
  • the transfer signals TGL1 and TGL2 fall, turning off the transfer transistors TG1 and TG2.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency second D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency second D-phase level, and the high conversion efficiency second D-phase level read out from the cell 120 is AD converted for each column.
  • the switching signal FDG rises, the switching transistor 124 turns on, and the conversion efficiency of cell 320 is set to low.
  • the floating diffusions FD1 and FD2 are connected to each other.
  • the transfer signals TGL1 and TGL2 rise, the transfer transistors TG1 and TG2 turn on, and the charge accumulated in each photodiode PD1 and PD2 is transferred to the floating diffusions FD1 and FD2.
  • the transfer signals TGL1 and TGL2 fall, and the transfer transistors TG1 and TG2 turn off.
  • the D-phase batch level applied to the gate of the amplifier transistor 122 is set based on the charge accumulated in the floating diffusions FD1 and FD2 and the capacitor 321.
  • the potential VSL of the vertical signal line 132 is then set based on the source follower operation when this D-phase batch level is applied to the gate of the amplifier transistor 122.
  • a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the D-phase collective level, and the D-phase collective level read from the cell 320 is AD converted for each column.
  • the reset signal RST rises, turning on the reset transistor 121 and resetting the floating diffusions FD1, FD2 and capacitor 321. After that, the reset signal RST falls, turning off the reset transistor 121.
  • the P-phase batch level applied to the gate of the amplifier transistor 122 is set based on the reset state of the floating diffusions FD1, FD2 and capacitor 321.
  • the potential VSL of the vertical signal line 132 is then set based on the source follower operation when this P-phase batch level is applied to the gate of the amplifier transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the P-phase batch level, and the P-phase batch level read out from the cell 320 is AD converted for each column.
  • FIGS. 18 and 19 are diagrams showing an example of potentials during the readout period of a solid-state imaging device according to the third embodiment. Note that a to d in FIG. 18 and a to c in FIG. 19 show an example of potentials at timings P31 to P37 in FIG. 17. Also, a to d in FIG. 18 and a to c in FIG. 19 show an example of potentials of photodiode PD1, transfer transistor TG1, and floating diffusions FD1 and FD2.
  • the transfer transistor TG1 is turned on and the switching transistor 124 is turned off.
  • the charge EL1 accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.
  • the conversion efficiency of the amplifier transistor 122 is set to high conversion efficiency. In this state, by reading out the pixel signal via the amplifier transistor 122, it is possible to obtain left-side phase difference information from the cell 320.
  • the charges EL1 and EL2 in the floating diffusion FD1 empty, the charge EL1 accumulated in the photodiode PD1 can be transferred to the floating diffusion FD1. Therefore, even when the intensity of the incident light is strong, it is possible to prevent the charge transferred to the floating diffusion FD1 from overflowing, and to prevent failure to obtain phase difference information.
  • the transfer transistor TG2 is turned on.
  • the charge EL2 accumulated in the photodiode PD2 is transferred to the floating diffusion FD1.
  • the charges EL1 and EL2 accumulated in the photodiodes PD1 and PD2 are held in the floating diffusion FD1.
  • the sum of the left-side phase difference information and the right-side phase difference information can be obtained from the cell 320.
  • the right-side phase difference information can be obtained.
  • the switching transistor 124 is turned on.
  • the conversion efficiency of the amplifier transistor 122 is set to low.
  • a luminance signal can be obtained from the cell 320 by reading out the pixel signal via the amplifier transistor 122.
  • the charges accumulated in the two photodiodes PD1 and PD2 and the charges overflowing from the photodiodes PD1 and PD2 can be detected with low conversion efficiency, improving the dynamic range.
  • the charges overflowing from the photodiodes PD1 and PD2 can be stored in the capacitor 321. This makes it possible to use long exposure times while achieving HDR, and suppress flicker that occurs when photographing an LED light source.
  • FIG. 20 is a plan view showing an example of a pixel layout according to the third embodiment
  • FIG. 21 is a cross-sectional view showing an example of a pixel configuration according to the third embodiment. Note that FIG. 21 shows an example of a configuration cut along line B1-B2 in FIG. 20.
  • the semiconductor substrate SUB is separated into cells 320 by pixel isolation regions ISG1.
  • the pixel isolation regions ISG1 can be arranged on the boundaries of the cells 320.
  • An active region AK3 is provided on the semiconductor substrate SUB, and the active region AK3 is isolated by an element isolation region ISA3.
  • Photodiodes PD1 and PD2, a channel region, and impurity diffusion layers DF23 and DF24 are formed in the active region AK3.
  • Floating diffusions FD1 and FD2, and the source and drain layers of the pixel transistors are formed in the impurity diffusion layers DF23 and DF24.
  • Gate electrodes E1, E2, G21 to G24 and an assist electrode 325 are formed on the active region AK3, each with a gate insulating film GZ interposed therebetween.
  • the assist electrode 325 is disposed between the gate electrodes G21 and G24.
  • pixel isolation region ISG1 was formed based on RDTI, but pixel isolation region ISG2 may also be formed based on FFTI.
  • the potential of the floating diffusion FD1 is lowered via the assist electrode 325, and the charge that has overflowed into the floating diffusion FD1 is transferred to the capacitor 321.
  • This allows overflow from the photodiodes PD1 and PD2 to the capacitor 321 via the floating diffusions FD1 and FD2, while also emptying the charge in the floating diffusion FD1 when phase difference information is acquired.
  • This makes it possible to acquire phase difference information while suppressing an increase in cell size, and also enables DCG-HDR to be achieved.
  • FIG. 22 is a diagram showing an example of the circuit configuration of a cell provided in a solid-state imaging device according to the fourth embodiment.
  • cell 420 has an assist electrode 425 instead of the assist electrode 125 of the first embodiment described above. Furthermore, cell 420 has photodiodes PD3 to PD8, transfer transistors TG3 to TG8, pass transistor 127, and capacitor 321 added to cell 120 of the first embodiment described above. The rest of the configuration of cell 420 of the fourth embodiment is the same as the configuration of cell 120 of the first embodiment described above.
  • Each photodiode PD1 to PD8 performs photoelectric conversion and accumulates the photoelectrically converted charge.
  • photodiodes PD1 to PD8 can be used to acquire phase difference information or brightness information.
  • photodiodes PD1 and PD2 can be paired to acquire phase difference information
  • photodiodes PD3 and PD4 can be paired to acquire phase difference information
  • photodiodes PD5 and PD6 can be paired to acquire phase difference information
  • photodiodes PD7 and PD8 can be paired to acquire phase difference information.
  • Each photodiode PD1 to PD8 can form a pixel. These eight pixels can be pixels of the same color.
  • a quad Bayer array can be formed with four cells 420 arranged in two rows and two columns. Each transfer transistor TG1 to TG8 transfers the charge accumulated in each photodiode PD1 to PD8 to the floating diffusion FD1.
  • the assist electrode 425 assists in the transfer of charge between the floating diffusions FD1 and FD2.
  • the assist electrode 425 can be placed on the floating diffusion FD1. In this case, the assist electrode 425 can control the potential of the floating diffusion FD1.
  • Pass transistor 127 establishes a charge transfer path between each of photodiodes PD1 to PD8 and capacitor 321 in cell 420. Pass transistor 127 is connected in series with capacitor 321. In this case, pass transistor 127 can be connected between capacitor 321 and floating diffusion FD2.
  • Each transfer transistor TG1 to TG8 is connected between the cathode of each photodiode PD1 to PD8 and the floating diffusion FD1.
  • the floating diffusion FD1 is shared by the photodiodes PD1 to PD8.
  • Transfer signals TGL1 to TGL8 are applied to the gates of the transfer transistors TG1 to TG8.
  • An assist signal AST4 is applied to the assist electrode 425.
  • the transfer signals TGL1 to TGL8 and the assist signal AST4 can be transmitted to the cell 420 via the horizontal drive line 131.
  • FIG. 23 is a timing chart showing an example of a readout operation of a solid-state imaging device according to the fourth embodiment.
  • this signal readout process includes high conversion efficiency first to fourth P-phase readout periods T41, T44, T47, and T50, high conversion efficiency first to eighth D-phase readout periods T42, T43, T45, T46, T48, T49, T51, and T52, a D-phase batch readout period T53, and a P-phase batch readout period T54.
  • the assist control unit 112A can assist the transfer of charge between the floating diffusions FD1 and FD2 based on the timing set in these periods T41 to T54.
  • reset signals used in CDS processing for high conversion efficiency can be obtained.
  • phase difference information used for autofocus can be obtained.
  • D-phase batch readout period T53 brightness information used for captured images can be obtained.
  • P-phase batch readout period T54 a reset signal used for DDS processing can be obtained.
  • the reset signal RST and transfer signals TGL1 to TGL8 are set to low level, and the reset transistor 121 and transfer transistors TG1 to TG8 are turned off. Furthermore, the switching signal FDG and assist signal AST4 are set to high level, turning on the switching transistor 124 and lowering the potential of the floating diffusion FD1 via the assist electrode 425. At this time, charge is accumulated in each of the photodiodes PD1 to PD8 based on the incident light, and charge that overflows from each of the photodiodes PD1 to PD8 is accumulated in the floating diffusions FD1, FD2 and capacitor 321.
  • the switching signal FDG falls, the switching transistor 124 turns off, and the floating diffusions FD1 and FD2 are separated from each other.
  • the assist signal AST4 falls, and the potential of the floating diffusion FD1 rises via the assist electrode 425. At this time, the charge accumulated in the floating diffusion FD1 is transferred to the floating diffusion FD2.
  • the switching signal FDG rises, the switching signal FDG falls, and the charge remaining in the floating diffusion FD1 is transferred to the floating diffusion FD2.
  • the switching transistor 124 turns off, and the conversion efficiency of the cell 420 is set to high conversion efficiency.
  • the assist signal AST4 rises, and the potential of the floating diffusion FD1 is lowered via the assist electrode 425.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level, and the high conversion efficiency P-phase level read from the cell 420 is AD converted for each column.
  • the transfer signal TGL1 rises, the transfer transistor TG1 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.
  • the transfer signal TGL1 falls, and the transfer transistor TG1 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency first D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency first D-phase level, and the high conversion efficiency first D-phase level read out from the cell 420 is AD converted for each column.
  • the transfer signals TGL1 and TGL2 rise, turning on the transfer transistors TG1 and TG2 and transferring the charge accumulated in each photodiode PD1 and PD2 to the floating diffusion FD1.
  • the transfer signals TGL1 and TGL2 fall, turning off the transfer transistors TG1 and TG2.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency second D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency second D-phase level, and the high conversion efficiency second D-phase level read out from the cell 420 is AD converted for each column.
  • the assist signal AST4 falls, increasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG rises, turning on the switching transistor 124. At this time, the floating diffusions FD1 and FD2 are connected to each other, forming a potential gradient from the floating diffusion FD1 to the floating diffusion FD2. As a result, the charge stored in the floating diffusion FD1 is transferred to the floating diffusion FD2, and the floating diffusion FD1 becomes empty. Thereafter, the assist signal AST4 rises, decreasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG falls, turning off the switching transistor 124.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency first P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency first P-phase level, and the high conversion efficiency first P-phase level read from the cell 420 is AD converted for each column.
  • the transfer signal TGL3 rises, the transfer transistor TG3 turns on, and the charge accumulated in the photodiode PD3 is transferred to the floating diffusion FD1.
  • the transfer signal TGL3 falls, and the transfer transistor TG3 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency third-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency third-phase level, and the high conversion efficiency third-phase level read out from the cell 420 is AD converted for each column.
  • the transfer signals TGL3 and TGL4 rise, turning on the transfer transistors TG3 and TG4 and transferring the charge accumulated in each photodiode PD3 and PD4 to the floating diffusion FD1. Then, the transfer signals TGL3 and TGL4 fall, turning off the transfer transistors TG3 and TG4. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency fourth-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency fourth-phase level, and the high conversion efficiency fourth-phase level read out from the cell 420 is AD converted for each column.
  • the assist signal AST4 falls, increasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG rises, turning on the switching transistor 124. At this time, the floating diffusions FD1 and FD2 are connected to each other, forming a potential gradient from the floating diffusion FD1 to the floating diffusion FD2. As a result, the charge stored in the floating diffusion FD1 is transferred to the floating diffusion FD2, and the floating diffusion FD1 becomes empty. Thereafter, the assist signal AST4 rises, decreasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG falls, turning off the switching transistor 124.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency third P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency third P-phase level, and the high conversion efficiency third P-phase level read from the cell 420 is AD converted for each column.
  • the transfer signal TGL5 rises, the transfer transistor TG5 turns on, and the charge accumulated in the photodiode PD5 is transferred to the floating diffusion FD1.
  • the transfer signal TGL5 falls, and the transfer transistor TG5 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency 5D phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency 5D phase level, and the high conversion efficiency 5D phase level read out from the cell 420 is AD converted for each column.
  • the transfer signals TGL5 and TGL6 rise, turning on the transfer transistors TG5 and TG6 and transferring the charge accumulated in each photodiode PD5 and PD6 to the floating diffusion FD1. Then, the transfer signals TGL5 and TGL6 fall, turning off the transfer transistors TG5 and TG6.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency 6D phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency 6D phase level, and the high conversion efficiency 6D phase level read out from the cell 420 is AD converted for each column.
  • the assist signal AST4 falls, increasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG rises, turning on the switching transistor 124. At this time, the floating diffusions FD1 and FD2 are connected to each other, forming a potential gradient from the floating diffusion FD1 to the floating diffusion FD2. As a result, the charge stored in the floating diffusion FD1 is transferred to the floating diffusion FD2, and the floating diffusion FD1 becomes empty. Thereafter, the assist signal AST4 rises, decreasing the potential of the floating diffusion FD1 via the assist electrode 425. Furthermore, the switching signal FDG falls, turning off the switching transistor 124.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency fourth P phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency fourth P phase level, and the high conversion efficiency fourth P phase level read from the cell 420 is AD converted for each column.
  • the transfer signal TGL7 rises, the transfer transistor TG7 turns on, and the charge accumulated in the photodiode PD7 is transferred to the floating diffusion FD1.
  • the transfer signal TGL7 falls, and the transfer transistor TG7 turns off.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency 7D phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency 7D phase level, and the high conversion efficiency 7D phase level read out from the cell 420 is AD converted for each column.
  • the transfer signals TGL7 and TGL8 rise, turning on the transfer transistors TG7 and TG8 and transferring the charge accumulated in each photodiode PD7 and PD8 to the floating diffusion FD1. Then, the transfer signals TGL7 and TGL8 fall, turning off the transfer transistors TG7 and TG8.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency 8D phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A a counting operation is performed based on the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency 8D phase level, and the high conversion efficiency 8D phase level read out from the cell 420 is AD converted for each column.
  • the assist signal AST4 falls, increasing the potential of the floating diffusion FD1 via the assist electrode 425.
  • the switching signal FDG rises, turning on the switching transistor 124 and setting the conversion efficiency of the cell 420 to low conversion efficiency.
  • the floating diffusions FD1 and FD2 are connected to each other.
  • the transfer signals TGL1 to TGL8 rise, turning on the transfer transistors TG1 to TG8, and transferring the charge accumulated in each photodiode PD1 to PD8 to the floating diffusions FD1 and FD2. Thereafter, the transfer signals TGL1 to TGL8 fall, turning off the transfer transistors TG1 to TG8.
  • the D-phase batch level applied to the gate of the amplification transistor 122 is set based on the charge accumulated in the floating diffusions FD1 and FD2 and the capacitor 321.
  • the potential VSL of the vertical signal line 132 is set based on the source follower operation when this D-phase collective level is applied to the gate of the amplification transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the D-phase collective level, and the D-phase collective level read from the cell 420 is AD converted for each column.
  • the reset signal RST rises, turning on the reset transistor 121 and resetting the floating diffusions FD1, FD2 and capacitor 321. After that, the reset signal RST falls, turning off the reset transistor 121.
  • the P-phase batch level applied to the gate of the amplifier transistor 122 is set based on the reset state of the floating diffusions FD1, FD2 and capacitor 321.
  • the potential VSL of the vertical signal line 132 is then set based on the source follower operation when this P-phase batch level is applied to the gate of the amplifier transistor 122.
  • the column ADC unit 114A then performs a counting operation based on the potential VSL of the vertical signal line 132 corresponding to the P-phase batch level, and the P-phase batch level read from the cell 420 is AD converted for each column.
  • FIGS. 24 and 25 are diagrams showing an example of potential during the readout period of a solid-state imaging device according to the fourth embodiment. Note that a to d in FIG. 24 and a to d in FIG. 25 show an example of potential at the timings of P41 to P48 in FIG. 23. Also, a to d in FIG. 24 and a to d in FIG. 25 show an example of potential at the photodiode PD1, transfer transistor TG1, and floating diffusions FD1 and FD2.
  • the transfer transistor TG1 is turned on and the switching transistor 124 is turned off.
  • the charge EL1 accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.
  • the conversion efficiency of the amplification transistor 122 is set to high conversion efficiency. In this state, by reading out the pixel signal via the amplification transistor 122, left-side phase difference information can be obtained from the cell 420.
  • the transfer transistor TG2 is turned on.
  • the charge EL2 accumulated in the photodiode PD2 is transferred to the floating diffusion FD1.
  • the charges EL1 and EL2 accumulated in the photodiodes PD1 and PD2 are held in the floating diffusion FD1.
  • the sum of the left-side phase difference information and the right-side phase difference information can be obtained from the cell 320.
  • the right-side phase difference information can be obtained.
  • FIG. 26 is a plan view showing an example of a pixel layout according to the fourth embodiment
  • FIG. 27 is a cross-sectional view showing an example of a pixel configuration according to the fourth embodiment. Note that FIG. 27 shows an example of a configuration cut along line C1-C2 in FIG. 26.
  • the semiconductor substrate SUB is separated into cells 420 by pixel isolation regions ISG1.
  • the pixel isolation regions ISG1 can be arranged at the boundaries of the cells 420.
  • An active region AK4 is provided on the semiconductor substrate SUB, and the active region AK4 is isolated by an element isolation region ISA4. Photodiodes PD1 to PD8, channel regions, and impurity diffusion layers DF41 to DF44 are formed in the active region AK4. Floating diffusions FD1 and FD2, and the source and drain layers of the pixel transistors are formed in the impurity diffusion layers DF43 and DF44.
  • Photodiodes PD1 and PD2 can be arranged line-symmetrically, photodiodes PD3 and PD4 can be arranged line-symmetrically, photodiodes PD5 and PD6 can be arranged line-symmetrically, and photodiodes PD7 and PD8 can be arranged line-symmetrically.
  • the planar shape of each photodiode PD1 to PD8 can be a right-angled triangle.
  • photodiodes PD1 and PD2 can be paired to form a square region
  • photodiodes PD3 and PD4 can be paired to form a square region
  • photodiodes PD5 and PD6 can be paired to form a square region
  • photodiodes PD7 and PD8 can be paired to form a square region. It is also possible to form one larger square region to include these four square regions.
  • each photodiode PD1 and PD8 can face each other in the diagonal direction
  • the ends of each photodiode PD2 and PD7 can face each other in the diagonal direction
  • the ends of each photodiode PD3 and PD6 can face each other in the diagonal direction
  • the ends of each photodiode PD4 and PD5 can face each other in the diagonal direction.
  • the impurity diffusion layer DF41 can be an N - type impurity diffusion layer.
  • the impurity diffusion layer DF41 can be disposed at the position of the photodiodes PD1 to PD8.
  • the impurity diffusion layer DF42 can be an N-type impurity diffusion layer.
  • the impurity diffusion layer DF42 can be disposed within the impurity diffusion layer DF41.
  • the impurity diffusion layer DF42 can be disposed at the position of the channel regions of the photodiodes PD1 to PD8 and the transfer transistors TG1 to TG8.
  • the impurity diffusion layer DF43 can be an N-type impurity diffusion layer.
  • the impurity diffusion layer DF43 can be disposed at the position of the channel regions of the reset transistor 121, the amplification transistor 122, the selection transistor 123, the switching transistor 124, and the pass transistor 127. Furthermore, floating diffusions FD1 and FD2 can be formed in the impurity diffusion layer DF43.
  • the impurity diffusion layer DF44 can be an N + type impurity diffusion layer.
  • the impurity diffusion layer DF44 can be disposed at the position of the source layer or drain layer of the pixel transistor.
  • Gate electrodes E41 to E48, G41 to G45, and assist electrode 425 are formed on active region AK4, each with a gate insulating film GZ interposed therebetween. Assist electrode 425 is arranged in a position surrounded by photodiodes PD1 to PD8. Each gate electrode E41 to E48 can be arranged at the end of each photodiode PD1 to PD8. Here, gate electrodes E41 to E48 can be arranged adjacent to assist electrode 425. In this case, each gate electrode E41 to E48 can be arranged between each photodiode PD1 to PD8 and assist electrode 425.
  • An impurity diffusion layer DF42 is formed below gate electrodes E41 to E48, and an impurity diffusion layer DF43 is formed below gate electrodes G41 to G45 and assist electrode 425.
  • Gate electrodes G42 and G43 are arranged adjacent to each other.
  • Gate electrodes G41 and G44 are arranged adjacent to each other.
  • Gate electrodes E41 to E48 are used for transfer transistors TG1 to TG8, respectively.
  • Gate electrode G41 is used for the reset transistor 121.
  • Gate electrode G42 is used for the amplification transistor 122.
  • Gate electrode G43 is used for the selection transistor 123.
  • Gate electrode G44 is used for the switching transistor 124.
  • Gate electrode G45 is used for the pass transistor 127.
  • a contact CN41 is arranged between photodiodes PD2 and PD3.
  • a contact CN42 is arranged next to gate electrode G43.
  • a contact CN43 is arranged next to gate electrode G41.
  • a contact CN44 is arranged next to gate electrode G45.
  • a ground potential is applied to contact CN41.
  • a potential VSL of vertical signal line 132 is applied to contact CN42.
  • a power supply potential VDD is applied to contact CN43.
  • a capacitor 321 is connected to contact CN44.
  • pixel isolation region ISG1 was formed based on RDTI, but pixel isolation region ISG2 may also be formed based on FFTI.
  • the potential of the floating diffusion FD1 is boosted via the assist electrode 425 when charge is accumulated in the photodiodes PD1 to PD8, and the potential of the floating diffusion FD1 is lowered via the assist electrode 425 when phase difference information is acquired, transferring charge between the floating diffusions FD1 and FD2.
  • This allows overflow from the photodiodes PD1 to PD8 to the capacitor 321 via the floating diffusions FD1 and FD2, while also emptying the charge in the floating diffusion FD1 when phase difference information is acquired. This makes it possible to acquire phase difference information while suppressing an increase in cell size, and achieves DCG-HDR.
  • FIG. 28 is a diagram showing an example of the circuit configuration of a cell provided in a solid-state imaging device according to the fifth embodiment.
  • cell 520 is the same as cell 420 of the fourth embodiment described above, with overflow control transistors TF1 and TF2 added.
  • the rest of the configuration of cell 520 of the fifth embodiment is the same as the configuration of cell 420 of the fourth embodiment described above.
  • the overflow control transistor TF1 controls the overflow of charge from the photodiodes PD1 to PD4 to the capacitor 321.
  • the overflow control transistor TF2 controls the overflow of charge from the photodiodes PD5 to PD8 to the capacitor 321.
  • the overflow control transistor TF1 is connected between the drain of each transfer transistor TG1 to TG4 and the capacitor 321.
  • the overflow control transistor TF2 is connected between the drain of each transfer transistor TG5 to TG8 and the capacitor 321.
  • the overflow control transistors TF1 and TF2 may be MOS transistors. Overflow control voltages OFG1 and OFG2 are applied to the gates of each overflow control transistor TF1 and TF2.
  • the overflow control voltages OFG1 and OFG2 may be fixed potentials. By providing the overflow control transistors TF1 and TF2, charge can be overflowed from the photodiodes PD1 to PD8 to the capacitor 321 without passing through the floating diffusions FD1 and FD2.
  • cell 520 can be performed in the same way as the read operation of cell 420. At this time, cell 520 can perform the read operation according to the timing shown in Figure 23.
  • FIG. 29 is a plan view showing a first example layout of a pixel according to the fifth embodiment
  • FIG. 30 is a cross-sectional view showing a first example configuration of a pixel according to the fifth embodiment
  • FIG. 31 is a plan view showing a second example layout of a pixel according to the fifth embodiment
  • FIG. 32 is a cross-sectional view showing the second example configuration of a pixel according to the fifth embodiment.
  • the difference between FIG. 29 and FIG. 31 is that a cutout is provided in the assist electrode 525.
  • providing a cutout in the assist electrode 525 reduces the parasitic capacitance of FD1, thereby improving conversion efficiency.
  • FIGS. 30 and 32 show example configurations cut along lines C1-C2 in FIGS. 29 and 31, respectively.
  • the semiconductor substrate SUB is separated into cells 520 by pixel isolation regions ISG1.
  • the pixel isolation regions ISG1 can be arranged on the boundaries of the cells 520.
  • An active region AK5 is provided on the semiconductor substrate SUB, and the active region AK5 is isolated by an element isolation region ISA5. Photodiodes PD1 to PD8, channel regions, and impurity diffusion layers DF41 to DF44 are formed in the active region AK5.
  • Gate electrodes E41 to E48, G41 to G45, F1, F2, and an assist electrode 525 are formed on the active region AK5, each with a gate insulating film GZ interposed therebetween.
  • the assist electrode 525 is disposed in a position surrounded by the photodiodes PD1 to PD8.
  • an opening K5 is formed in the assist electrode 525.
  • the opening K5 can be disposed in the center of the assist electrode 525.
  • a floating diffusion FD1 can be disposed in the opening K5.
  • Gate electrode F1 can be arranged between photodiodes PD2 and PD3.
  • contact CN41 can be arranged between gate electrode F1 and assist electrode 525.
  • Gate electrode F2 can be arranged between photodiodes PD6 and PD7.
  • contact CN44 can be arranged between gate electrodes F2 and G45.
  • pixel isolation region ISG1 was formed based on RDTI, but pixel isolation region ISG2 may also be formed based on FFTI.
  • overflow control transistors TF1 and TF2 are added to the fifth embodiment described above. This makes it possible to control overflow from photodiodes PD1 to PD8 to capacitor 321, while also emptying the charge in floating diffusion FD1 when acquiring phase difference information. This makes it possible to acquire phase difference information while suppressing an increase in cell size, and also enables DCG-HDR to be achieved.
  • Figure 33 is a perspective view showing an example of the stacking of a pixel array unit according to the sixth embodiment.
  • the solid-state imaging device includes semiconductor chips 921 and 922.
  • Semiconductor chip 922 is stacked on semiconductor chip 921.
  • a pixel array section 923 is formed in the semiconductor chip 922.
  • pixels 931 are arranged in a matrix in the row and column directions.
  • the pixel 931 may be cell 120 of FIG. 3, pixel 220 of FIG. 10, cell 320 of FIG. 16, cell 420 of FIG. 22, or cell 520 of FIG. 28.
  • Pad electrodes 932 and via electrodes 933 are formed around the periphery of the pixel array section 923.
  • the via electrodes 933 pass through the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.
  • a peripheral circuit 924 is formed on the semiconductor chip 921.
  • a column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed in the peripheral circuit 924.
  • the column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.
  • the column ADC 926 can be provided with an AD conversion unit according to any of the first to eleventh embodiments described above.
  • the semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used to directly bond the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on a Cu-Cu connection.
  • the material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.
  • the semiconductor chip 922 on which the pixel array section 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of the semiconductor chip on which the solid-state imaging device is formed.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.
  • Figure 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • the functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain in accordance with various programs.
  • the drivetrain control unit 12010 functions as a control device for a driveforce generating device such as an internal combustion engine or drive motor that generates vehicle driveforce, a driveforce transmission mechanism that transmits driveforce to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates vehicle braking force.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps.
  • radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts these radio waves or signal inputs and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the outside vehicle information detection unit 12030 is connected to an imaging unit 12031.
  • the outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle. Connected to the in-vehicle information detection unit 12040 is, for example, a driver state detection unit 12041 that detects the driver's state.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby enabling cooperative control aimed at autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.
  • the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030.
  • the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/video output unit 12052 transmits at least one audio and/or video output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • Figure 35 shows an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, on the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly capture images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided on the side mirrors mainly capture images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided on the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • Imaging range 12111 indicates the imaging range of imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of imaging unit 12104 provided on the rear bumper or back door.
  • At least one of the image capturing units 12101 to 12104 may have a function for acquiring distance information.
  • at least one of the image capturing units 12101 to 12104 may be a stereo camera consisting of multiple image capturing elements, or an image capturing element having pixels for phase difference detection.
  • the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 can classify and extract three-dimensional object data regarding three-dimensional objects into categories such as motorcycles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, it can provide driving assistance to avoid a collision by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drivetrain control unit 12010.
  • At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian.
  • the audio/video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis.
  • the audio/video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian in a desired position.
  • the foregoing describes an example of a vehicle control system to which the technology disclosed herein can be applied.
  • the technology disclosed herein can be applied to the imaging unit 12031 of the configuration described above.
  • the imaging devices of the first to tenth embodiments described above can be applied to the imaging unit 12031.
  • the present technology can also be configured as follows. (1) a first floating diffusion to which charges are transferred from the photoelectric conversion unit; a second floating diffusion connectable to the first floating diffusion; an assist electrode that assists the transfer of charges between the first floating diffusion and the second floating diffusion. (2) The imaging device according to (1), wherein the assist electrode is disposed on the first floating diffusion. (3) The imaging device according to (1) or (2), wherein the assist electrode is disposed on the second floating diffusion. (4) a plurality of pixels sharing the first floating diffusion; a reset transistor that resets the first floating diffusion and the second floating diffusion; an amplifying transistor that outputs a signal according to the potential of the first floating diffusion; The imaging device according to any one of claims 1 to 3, further comprising a selection transistor that selects an output of the amplification transistor.
  • the imaging device according to (4) further comprising a switching transistor that switches the conversion efficiency of the amplifying transistor.
  • the imaging device described in (5) further includes an assist control unit that increases the potential of the second floating diffusion via the assist electrode when phase difference information is acquired, and decreases the potential of the second floating diffusion via the assist electrode when brightness information is acquired.
  • the imaging device according to (5) further comprising a capacitor that stores electric charges photoelectrically converted by the pixel.
  • the imaging device described in (7) further includes an assist control unit that reduces the potential of the first floating diffusion via the assist electrode for each subframe obtained by dividing a frame, and transfers the charge accumulated in the first floating diffusion to the capacitor.
  • the imaging device described in (7) further comprising an assist control unit that lowers the potential of the first floating diffusion via the assist electrode and transfers charge that has overflowed into the first floating diffusion to the capacitor.
  • the imaging device described in (7) further includes an assist control unit that increases the potential of the first floating diffusion via the assist electrode when accumulating charge in the photoelectric conversion unit, decreases the potential of the first floating diffusion via the assist electrode when acquiring phase difference information, and transfers the charge accumulated in the first floating diffusion to the second floating diffusion.
  • the assist control unit lowers the potential of the first floating diffusion via the assist electrode when acquiring a luminance signal, and transfers the charge accumulated in the first floating diffusion to the capacitor.
  • An imaging method that controls the potential of the first floating diffusion or the second floating diffusion via an assist electrode provided on the first floating diffusion to which charges are transferred from a photoelectric conversion unit or on a second floating diffusion connectable to the first floating diffusion, thereby assisting the transfer of charges between the first floating diffusion and the second floating diffusion.
  • Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 112A Assist control unit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 120 Cell PD1, PD2 Photodiode FD1, FD2 Floating diffusion TG1, TG2 Transfer transistor 121 Reset transistor 122 Amplification transistor 123 Selection transistor 124 Switching transistor 125 Assist electrode 131 Horizontal drive line 132 Vertical signal line

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention permet d'améliorer l'efficacité de transfert de charge entre des diffusions flottantes.　Un dispositif d'imagerie selon la présente invention comprend : une première diffusion flottante à laquelle une charge est transférée à partir d'une unité de conversion photoélectrique ; une seconde diffusion flottante qui peut être reliée à la première diffusion flottante ; et une électrode d'assistance qui facilite le transfert de charge entre la première diffusion flottante et la seconde diffusion flottante. L'électrode d'assistance peut être disposée sur la première diffusion flottante.
PCT/JP2025/001023 2024-03-11 2025-01-15 Dispositif d'imagerie et procédé d'imagerie Pending WO2025192016A1 (fr)

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JP2024-036620 2024-03-11

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WO2025192016A1 true WO2025192016A1 (fr) 2025-09-18

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JP2012119349A (ja) * 2010-11-29 2012-06-21 Sony Corp 固体撮像装置とその駆動方法、及び電子機器
WO2018155297A1 (fr) * 2017-02-27 2018-08-30 パナソニックＩｐマネジメント株式会社 Dispositif d'imagerie à semi-conducteur
JP2020047734A (ja) * 2018-09-18 2020-03-26 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器
WO2023002643A1 (fr) * 2021-07-19 2023-01-26 テックポイント インク Élément d'imagerie et dispositif d'imagerie
JP2023114999A (ja) * 2022-02-07 2023-08-18 三星電子株式会社 イメージセンサー及びその駆動方法
JP2023162762A (ja) * 2022-04-27 2023-11-09 ソニーセミコンダクタソリューションズ株式会社 光検出装置および増幅回路
WO2023234069A1 (fr) * 2022-05-30 2023-12-07 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et appareil électronique
JP2024029309A (ja) * 2022-08-22 2024-03-06 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子および電子機器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012119349A (ja) * 2010-11-29 2012-06-21 Sony Corp 固体撮像装置とその駆動方法、及び電子機器
WO2018155297A1 (fr) * 2017-02-27 2018-08-30 パナソニックＩｐマネジメント株式会社 Dispositif d'imagerie à semi-conducteur
JP2020047734A (ja) * 2018-09-18 2020-03-26 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及び電子機器
WO2023002643A1 (fr) * 2021-07-19 2023-01-26 テックポイント インク Élément d'imagerie et dispositif d'imagerie
JP2023114999A (ja) * 2022-02-07 2023-08-18 三星電子株式会社 イメージセンサー及びその駆動方法
JP2023162762A (ja) * 2022-04-27 2023-11-09 ソニーセミコンダクタソリューションズ株式会社 光検出装置および増幅回路
WO2023234069A1 (fr) * 2022-05-30 2023-12-07 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et appareil électronique
JP2024029309A (ja) * 2022-08-22 2024-03-06 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子および電子機器

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