WO2025192083A1 - Logic semiconductor device - Google Patents

Abstract

Provided is a semiconductor device with which it is possible to shorten the distance between a semiconductor chip and a trench capacitor. In a logic semiconductor device (1), a silicon substrate unit (12), a transistor layer (14), a wiring layer (16), and a capacitor unit (50) having a through-via (53) and a capacitor (60) formed therein are formed in the stated order.

Description

Logic Semiconductor Device

The present invention relates to a logic semiconductor device.

Deep trench capacitors are known as capacitors that achieve high capacitance while minimizing the area they occupy on the substrate surface. Patent Document 1 discloses a method for fabricating deep trench capacitors used in DRAM (Dynamic Random Access Memory) cells.

Japanese Patent Application Laid-Open No. 2004-103777

In the past, when deep trench capacitors were fabricated within semiconductor devices, they were fabricated on a silicon interposer. Furthermore, the semiconductor chip and silicon interposer were bonded via bumps. Therefore, conventional semiconductor packages had the problem of a large distance between the transistors formed on the semiconductor chip and the deep trench capacitor.

The present invention therefore aims to provide a semiconductor device that can shorten the distance between the semiconductor chip and the trench capacitor.

The logic semiconductor device of the present invention comprises, in this order, a silicon substrate section, a transistor layer, a wiring layer, and a capacitor section in which a through via and a capacitor are formed.

The present invention provides a semiconductor device that can shorten the distance between the semiconductor chip and the trench capacitor.

FIG. 1 is a cross-sectional view of a logic semiconductor device according to this embodiment. FIG. 2 is a diagram showing an outline of a semiconductor package in which the logic semiconductor device of this embodiment is used. FIG. 3 is a diagram showing how the chip wafer and the capacitor wafer are bonded together. FIG. 4A is a diagram showing a capacitor wafer bonding surface of a capacitor wafer. FIG. 4B is a diagram showing the chip wafer bonding surface of the chip wafer. FIG. 5 shows the state before the silicon chip portion and the capacitor portion are bonded together. FIG. 6 is a diagram showing the bonding surface of the capacitor portion. FIG. 7 is a diagram showing the bonding surface of the tip portion. FIG. 8 is a cross-sectional view of a trench capacitor. FIG. 9 is a diagram showing an outline of a conventional semiconductor package.

(Logic semiconductor device)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given of an embodiment of the present invention with reference to the drawings. First, a logic semiconductor device 1 according to an embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a diagram showing a cross section of the logic semiconductor device 1. Hereinafter, the X direction, Y direction, and Z direction may be indicated in the drawings. The X direction, Y direction, and Z direction are directions that are perpendicular to one another. The Z direction is the direction in which a silicon chip section 10 and a capacitor section 50, which will be described later, are stacked. FIG. 1 shows a cross section of the logic semiconductor device 1 taken along a plane parallel to the X direction and the Z direction.

In the logic semiconductor device 1 of this embodiment, a silicon substrate portion 12, a transistor layer 14, a wiring layer 16, and a capacitor portion 50 are formed in this order. Each will be described in order below.

(silicon chip part and capacitor part)
The logic semiconductor device 1 includes a silicon chip section 10 and a capacitor section 50. The silicon chip section 10 and the capacitor section 50 are integrated by being directly bonded together. Direct bonding refers to bonding without using any material other than the silicon chip section 10 and the capacitor section 50, such as an adhesive, a solder bump, or a liquid curable resin such as underfill. An example of direct bonding is hybrid bonding.

(Chip bonding surface and capacitor bonding surface)
The surface of the silicon chip portion 10 that is bonded to the capacitor portion 50 is called the chip portion bonding surface 11. The surface of the capacitor portion 50 that is bonded to the silicon chip portion 10 is called the capacitor portion bonding surface 51. In the logic semiconductor device 1 of this embodiment, the chip portion bonding surface 11 and the capacitor portion bonding surface 51 are directly bonded by hybrid bonding to form the logic semiconductor device 1. Note that the direct bonding between the chip portion bonding surface 11 and the capacitor portion bonding surface 51 is not limited to hybrid bonding.

(Silicon chip part)
The silicon chip portion 10 includes a silicon substrate portion 12, a transistor layer 14, and a wiring layer 16. The silicon substrate portion 12, the transistor layer 14, and the wiring layer 16 are stacked in this order in the Z direction. The silicon chip portion 10 can function as a logic semiconductor.

(Silicon substrate and transistor layer)
The silicon substrate portion 12 is a substrate for forming transistors on at least one surface thereof. The transistor layer 14 is a layer including transistors formed on the surface of the silicon substrate portion 12. The number of transistors included in the transistor layer 14 is not limited.

(wiring layer)
The wiring layer 16 is a layer for connecting transistors and the like included in the transistor layer 14 to electrodes and the like formed in the capacitor section 50. The wiring layer 16 includes a chip section insulating section 18 and a wiring section. The wiring section is not shown. The wiring section includes wiring for electrically connecting transistors and the like included in the transistor layer 14 to electrodes and the like formed in the capacitor section 50. The chip section insulating section 18 is an insulating portion formed between wires in the wiring section. Furthermore, if the surface of the wiring layer 16 that contacts the capacitor section 50 is defined as the wiring layer bonding surface, the wiring layer bonding surface is the same as the chip section bonding surface 11.

(Capacitor section)
Next, a description will be given of the capacitor section 50. The capacitor section 50 includes a through via 53, a trench capacitor 60, and a capacitor section insulating section 52. In the capacitor section 50, a surface opposite to the capacitor section bonding surface 51 is called a capacitor section back surface 58.

(Through via)
The through via 53 is a conductive through hole that penetrates from the capacitor unit bonding surface 51 to the capacitor unit rear surface 58. The through via 53 is also called a TSV (Through Silicon Via).

(trench capacitor)
The trench capacitor 60 may be a so-called deep trench capacitor. In FIG. 1 , the length of the capacitor section 50 in the Z direction is shown as length 160. Length 160 indicates the thickness of the capacitor section 50 in the Z direction. Furthermore, the length of the trench capacitor 60 in the Z direction is shown as length 162. Length 162 indicates the depth of the trench capacitor 60. Length 160 is, for example, 100 μm. Meanwhile, length 162 is, for example, 20 μm or more and 40 μm or less. Note that the above-mentioned lengths 160 and 162 are examples. The lengths of length 160 and length 162 are not particularly limited.

The capacitor section insulating portion 52 is an insulating portion that fills the spaces between the through vias 53, and between the through vias 53 and the trench capacitor 60. The material of the capacitor section insulating portion 52 can be silicon.

(Semiconductor package)
Before describing the logic semiconductor device 1 in detail, an example of how the logic semiconductor device 1 is used will be described. Fig. 2 is a diagram showing an overview of a semiconductor package 100. The logic semiconductor device 1 can constitute a part of the semiconductor package 100.

As shown in FIG. 2, the semiconductor package 100 includes a logic semiconductor device 1 and a package substrate 110. Package wiring 112 is formed on the package substrate 110. Package insulation portions 114 are formed between the package wiring 112, etc. In addition, ball-shaped package solder portions 116 (solder bumps) are formed on the surface of the semiconductor package 100 opposite the surface on which the logic semiconductor device 1 is placed.

The logic semiconductor device 1 is connected to one surface of the package substrate 110 via device solder parts 59 (solder bumps).

(Semiconductor package)
A conventional semiconductor package 200 will now be described with reference to FIG. 9 . FIG. 9 is a diagram showing an overview of the conventional semiconductor package 200. Note that in the following description, the matters described with reference to FIG. 2 will not be described again. In the conventional semiconductor package 200, a portion having the same function as the logic semiconductor device 1 shown in FIG. 2 is composed of two components: a silicon chip 210 and an interposer 220. The interposer 220 has through vias 222 and trench capacitors 224 formed therein. The silicon chip 210 and the interposer 220 are connected via ball-shaped silicon chip solder portions 212 (solder bumps). The interposer 220 is also connected to the package substrate 110 via ball-shaped interposer solder portions 226 (solder bumps).

As shown in Figures 2 and 9, the logic semiconductor device 1 of this embodiment makes it possible to combine the conventional silicon chip 210 and interposer 220 into a single component. As a result, the logic semiconductor device 1 of this embodiment can shorten the distance between the semiconductor chip and the trench capacitor. Furthermore, the logic semiconductor device 1 of this embodiment can reduce the thickness of the semiconductor package 100 and simplify the configuration of the semiconductor package 100.

The logic semiconductor device 1 will now be described in detail. Figure 3 is a diagram showing how the chip wafer 310 and capacitor wafer 350 are bonded together. The diagram indicated by arrow 301 in Figure 3 shows an overview of the chip wafer bonding surface 311 of the chip wafer 310. The chip wafer 310 is a silicon wafer on which a plurality of silicon chip portions 10 are formed. The chip wafer 310 is bonded to the capacitor wafer 350, which will be described later. The surface of the chip wafer 310 that is bonded to the capacitor wafer 350 is called the chip wafer bonding surface 311. The surface of the chip wafer 310 opposite the chip wafer bonding surface 311 is called the chip wafer back surface 312.

The diagram indicated by arrow 302 in Figure 3 shows the state before the chip wafer 310 and capacitor wafer 350 are bonded. The capacitor wafer 350 is a silicon wafer on which multiple capacitor sections 50 are formed. The surface of the capacitor wafer 350 that is bonded to the chip wafer 310 is called the capacitor wafer bonding surface 351.

When bonding the chip wafer 310 and the capacitor wafer 350, the chip wafer bonding surface 311 of the chip wafer 310 is opposed to the capacitor wafer bonding surface 351 of the capacitor wafer 350. In the example shown in Figure 3, the chip wafer 310 is inverted as indicated by arrow 361, so that the chip wafer bonding surface 311 of the chip wafer 310 is opposed to the capacitor wafer bonding surface 351 of the capacitor wafer 350.

The silicon chip units 10 and capacitor units 50 are formed at corresponding positions on each wafer so that when the chip wafer 310 and capacitor wafer 350 are superimposed on each other, the individual silicon chip units 10 and capacitor units 50 are bonded without misalignment. This will be explained with reference to Figures 4A and 4B. Figure 4A is a diagram showing the capacitor wafer bonding surface 351 of the capacitor wafer 350. Figure 4B is a diagram showing the chip wafer bonding surface 311 of the chip wafer 310 as viewed in the direction of arrow 363 in Figure 3. As shown in Figures 4A and 4B, the capacitor units 50 and silicon chip units 10 are arranged on each wafer so that when the capacitor wafer 350 and chip wafer 310 are superimposed on each other, they come into contact with each other without misalignment. Note that the symbols shown in Figures 4A and 4B but not explained will be explained later with reference to Figures 6 and 7.

Returning to Figure 3, after the chip wafer 310 is inverted as indicated by arrow 361, at least one of the chip wafer 310 and the capacitor wafer 350 is moved relatively as indicated by arrow 363, bringing the chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 into contact.

In this way, the silicon chip portion 10 formed on the chip wafer 310 and the capacitor portion 50 formed on the capacitor wafer 350 are brought into contact and bonded.

The bonding between the silicon chip portion 10 and the capacitor portion 50 will be described in detail. In the following explanation, the bonding between the silicon chip portion 10 and the capacitor portion 50 will be described, focusing on one of the multiple silicon chip portions 10 formed on the chip wafer 310 and one of the multiple capacitor portions 50 formed on the capacitor wafer 350.

(Before joining)
5 is a diagram showing the state before the silicon chip unit 10 and the capacitor unit 50 are bonded together. The directions indicated by arrows 151 and 152 in Fig. 5 are both along the Z direction. The directions indicated by arrows 151 and 152 are opposite to each other.

The silicon chip portion 10 and the capacitor portion 50 are bonded by moving the silicon chip portion 10 relative to the capacitor portion 50 in the direction of arrow 151, and then moving the capacitor portion 50 relative to the silicon chip portion 10 in the direction of arrow 151. In this way, the logic semiconductor device 1 is formed.

The capacitor portion 50 and the silicon chip portion 10 are bonded by bonding the capacitor portion bonding surface 51 and the chip portion bonding surface 11. The capacitor portion bonding surface 51 and the chip portion bonding surface 11 will now be described with reference to Figures 6 and 7. Figure 6 is a diagram showing the capacitor portion bonding surface 51. Figure 7 is a diagram showing the chip portion bonding surface 11. Both Figures 6 and 7 show the object when viewed in the direction of arrow 153 shown in Figure 5. The direction of arrow 153 is the direction looking from the (+) side to the (-) side in the Z direction. Note that the chip portion bonding surface 11 shown in Figure 7 shows the chip portion bonding surface 11 when viewed in the direction of arrow 153, beyond the silicon substrate portion 12, transistor layer 14, and wiring layer 16. In other words, as shown by arrow 154 in Figure 5, this shows the chip portion bonding surface 11 when viewed from inside the wiring layer 16, in other words, from the back surface 11R of the chip portion bonding surface 11.

(Capacitor joint surface)
First, the capacitor portion bonding surface 51 will be described with reference to Fig. 6. The capacitor portion insulating portion 52 is exposed on the capacitor portion bonding surface 51. Furthermore, the through electrodes 54, the capacitor electrodes 62, and the connection wiring 77 are arranged on the capacitor portion bonding surface 51. In other words, on the capacitor portion bonding surface 51, the through electrodes 54, the capacitor electrodes 62, and the connection wiring 77 are arranged within the capacitor portion insulating portion 52. The capacitor portion bonding surface 51 is covered with the capacitor portion insulating portion 52, the through electrodes 54, the capacitor electrodes 62, and the connection wiring 77.

(Through electrode)
The through electrode 54 is an electrode electrically connected to the through via 53 formed in the capacitor section 50. The through electrode 54 is a portion where the end of the through via 53 is exposed on the capacitor section bonding surface 51.

Multiple through electrodes 54 are arranged on the capacitor section bonding surface 51. The number of through electrodes 54 corresponds to the number of through vias 53 formed in the capacitor section 50. Typically, one through electrode 54 is formed for each through via 53.

The arrangement of the through electrodes 54 corresponds to the arrangement of the through vias 53 formed in the capacitor section 50. In the example shown in Figure 6, the through electrodes 54 are arranged in a matrix, but there are no particular restrictions on the arrangement of the through electrodes.

The planar shape of the through electrode 54 is circular. This is because the through via 53 has a cylindrical shape. The cross-sectional shape of the through via is not limited to circular, and may be donut-shaped, rectangular, etc.

The material of the through electrode 54 can be the same as the material that forms the through via 53. An example of a material for the through electrode 54 is copper. However, the material for the through electrode 54 is not limited to copper. Furthermore, the material for the through electrode 54 may be different from the material that forms the through via 53.

(capacitor electrode)
The capacitor electrode 62 is the electrode portion of the trench capacitor 60 formed in the capacitor section 50 .

(trench capacitor)
Here, an outline of the configuration of the trench capacitor 60 will be described. FIG. 8 is a diagram showing a cross section of the trench capacitor 60. The position of line segment 155-156 in FIG. 8 corresponds to the position of line segment 155-156 in FIG. 6. The trench capacitor 60 includes a capacitor electrode 62, a dielectric layer 66, a first electrode layer 68, and a second electrode layer 69. The capacitor electrode 62 includes a first capacitor electrode 64 and a second capacitor electrode 65.

The dielectric layer 66 is sandwiched between a first electrode layer 68 and a second electrode layer 69. There are no particular restrictions on the material of the dielectric layer 66. Capacitance can be increased by using a material with a high dielectric constant, and examples of materials that can be used include silicon oxide, silicon nitride, tantalum oxide, titanium oxide, hafnium oxide, hafnium silicate, HfSiON, and HfAlON. A capacitance is formed in the dielectric layer 66. The first capacitor electrode 64 is the capacitor electrode 62 connected to the first electrode layer 68. The second capacitor electrode 65 is the capacitor electrode 62 connected to the second electrode layer 69.

The first electrode layer 68, the dielectric layer 66, and the second electrode layer 69 extend in the Z direction to form a trench-type capacitor.

The first capacitor electrode 64 and the second capacitor electrode 65 are exposed on the capacitor portion bonding surface 51. A capacitor portion insulating portion 52 is disposed between the first capacitor electrode 64 and the second capacitor electrode 65 on the capacitor portion bonding surface 51. For example, by making the first capacitor electrode 64 a (+) electrode and the second capacitor electrode 65 a (-) electrode, capacitance can be formed in the dielectric layer 66.

Note that the schematic configuration of the trench capacitor 60 shown in Figure 8 is an example. The configuration of the trench capacitor 60 can be modified as appropriate.

(capacitor electrode)
Returning to Fig. 6 , the capacitor electrode 62 will be described. The first capacitor electrode 64 and the second capacitor electrode 65 shown in Fig. 6 are the first capacitor electrode 64 and the second capacitor electrode 65 of the trench capacitor 60 described with reference to Fig. 8 that are exposed at the capacitor portion bonding surface 51. The first capacitor electrode 64 and the second capacitor electrode 65 are separated from each other at the capacitor portion bonding surface 51 by the capacitor portion insulating portion 52.

In the example shown in FIG. 6, the first capacitor electrode 64 and the second capacitor electrode 65 are rectangular in shape. However, the shapes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to rectangular. Also, in the example shown in FIG. 6, the size of the first capacitor electrode 64 is smaller than the size of the second capacitor electrode 65. However, the sizes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to the example shown in FIG. 6.

The material of the capacitor electrode 62 is, for example, copper. However, the material of the capacitor electrode 62 is not limited to copper.

(Connection wiring)
The connection wiring 77 is a wiring that electrically connects the through electrode 54 and the capacitor electrode 62. The connection wiring 77 includes a first connection wiring 78 and a second connection wiring 79.

The through electrode 54 adjacent to the first capacitor electrode 64 is called the first through electrode 55. The first connection wiring 78 is the connection wiring 77 that connects the first through electrode 55 and the first capacitor electrode 64.

The through electrode 54 adjacent to the second capacitor electrode 65 is called the second through electrode 56. The second connection wiring 79 is the connection wiring 77 that connects the second through electrode 56 and the second capacitor electrode 65.

(power line and ground line)
6, for example, the first through electrode 55 can correspond to a power line, and the second through electrode 56 can correspond to a ground line, thereby allowing the trench capacitor 60 to be connected between the power line and the ground line.

Here, transistor operation involves the supply and release of charge to the transistor. This causes switching noise to occur on the power line. Reducing switching noise is important to ensure stable, high-speed transistor operation. To achieve this, it is effective to install a large-capacity capacitor capable of holding charge as close to the transistor as possible. In the logic semiconductor device 1 of this embodiment, power lines from the transistor layer 14 can be connected to the trench capacitor 60 without using bumps or the like. This eliminates the connection distance of several hundred micrometers to millimeters that would previously have been required using bumps.

Note that the above-described method of connecting the trench capacitor 60 to the line is an example. The method of connecting the trench capacitor 60 to the line is not limited to this.

The material of the connection wiring 77 is, for example, copper. However, the material of the connection wiring 77 is not limited to copper.

(Tip joint surface)
Next, the chip bonding surface 11 will be described with reference to Figure 7. The chip insulating portion 18 is exposed on the chip bonding surface 11. Furthermore, wiring electrodes 26 and pads are arranged on the chip bonding surface 11. In this embodiment, the pads are dummy pads 20. In other words, on the chip bonding surface 11, the wiring electrodes 26 and dummy pads 20 are arranged within the chip insulating portion 18. The chip bonding surface 11 is covered with the chip insulating portion 18, the wiring electrodes 26, and the dummy pads 20.

(wiring electrode)
The wiring electrode 26 is an electrode electrically connected to a wiring portion formed in the wiring layer 16. The wiring electrode 26 is a portion where the end of the wiring portion is exposed on the chip portion bonding surface 11.

The wiring electrode 26 is bonded to the through electrode 54 on the capacitor portion bonding surface 51. In other words, the wiring electrode 26 is electrically connected to the through electrode 54 on the capacitor portion bonding surface 51.

The wiring electrode 26 has the same planar shape as the through electrode 54. In the examples shown in Figures 6 and 7, the planar shapes of the wiring electrode 26 and the through electrode 54 are both circular. Furthermore, the position of the wiring electrode 26 on the chip portion bonding surface 11 is the same as the position of the through electrode 54 on the capacitor portion bonding surface 51.

By configuring the planar shape and arrangement of the wiring electrode 26 as described above, the wiring electrode 26 and the through electrode 54 can be bonded to each other without any waste.

The material of the wiring electrode 26 can be the same as the material forming the wiring portion. An example of a material for the wiring electrode 26 is copper. However, the material for the wiring electrode 26 is not limited to copper. Furthermore, the material for the wiring electrode 26 may be different from the material forming the wiring portion.

(dummy pad)
The dummy pad 20 is a pad formed of a conductor on the chip portion bonding surface 11. The dummy pad 20 may be a floating pad (floating island pad) that is not connected to any other conductor. The dummy pad 20 is bonded to the capacitor electrode 62. The planar shape of the dummy pad 20 is the same as the planar shape of the capacitor electrode 62. The position of the dummy pad 20 on the chip portion bonding surface 11 is the same as the position of the capacitor electrode 62 on the capacitor portion bonding surface 51.

The dummy pads 20 include a first dummy pad 21 and a second dummy pad 22. The first dummy pad 21 is a dummy pad 20 that is bonded to the first capacitor electrode 64. The second dummy pad 22 is a dummy pad 20 that is bonded to the second capacitor electrode 65.

The material of the dummy pad 20 can be the same as the material of the capacitor electrode 62. For example, if the material of the capacitor electrode 62 is copper, it is preferable that the material of the dummy pad 20 is also copper. Note that the pad formed on the chip portion bonding surface 11 and bonded to the capacitor electrode 62 is not limited to a floating pad, but may also be a pad connected to a wiring. For example, this pad may be connected to the wiring electrode 26 on the chip portion bonding surface 11 by a connecting wiring (not shown). In this case, the connecting wiring 77 does not need to be formed on the capacitor portion bonding surface 51.

(Bonding of the capacitor bonding surface and the chip bonding surface)
Here, we will explain the bonding between the capacitor portion bonding surface 51 and the chip portion bonding surface 11. The capacitor portion bonding surface 51 and the chip portion bonding surface 11 are directly bonded to each other. As mentioned above, being directly bonded means that they are bonded in contact with each other without any other material, such as an adhesive, a solder bump, or a liquid curable resin such as underfill, sandwiched between them.

(hybrid bonding)
An example of direct bonding is hybrid bonding. A case will be described in which the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are hybrid bonded. To perform hybrid bonding, it is preferable that the two surfaces to be bonded are made of the same material.

(Capacitor insulation and chip insulation)
The capacitor portion insulating portion 52 on the capacitor portion bonding surface 51 is an insulating portion made of silicon. Therefore, the material of the chip portion insulating portion 18 on the chip portion bonding surface 11 is made of silicon, the same as that of the capacitor portion insulating portion 52. This results in a hybrid bond between the capacitor portion insulating portion 52 and the chip portion insulating portion 18.

Hybrid bonding between capacitor parts is formed, for example, as follows. First, the hydroxyl groups at the ends of the silicon that make up the capacitor part insulating part 52 and the chip part insulating part 18 bond together through hydrogen bonding. Then, the interface between the capacitor part bonding surface 51 and the chip part bonding surface 11 is heated. This heating causes dehydration from the hydrogen bonds, and the capacitor part insulating part 52 and the chip part insulating part 18 are bonded together through siloxane bonding.

Note that the materials for the capacitor portion insulating portion 52 and the tip portion insulating portion 18 are not limited to those mentioned above. The materials for the capacitor portion insulating portion 52 and the tip portion insulating portion 18 can also be, for example, silicon oxide or silicon carbonitride. These materials can also be used as insulating materials for hybrid bonding.

(Through electrodes and wiring electrodes)
Next, the bonding between the through electrode 54 and the wiring electrode 26 will be described. For example, assume that the material of the through electrode 54 and the material of the wiring electrode 26 are both copper. In this case, by bringing the through electrode 54 and the wiring electrode 26 into contact with each other, the copper diffuses into each other, creating a diffusion bond. The through electrode 54 and the wiring electrode 26 can be bonded by this diffusion bond.

In this way, when bonding the capacitor portion bonding surface 51 and the chip portion bonding surface 11, hybrid bonding can be achieved by using the same material for the contacting parts of the capacitor portion bonding surface 51 and the chip portion bonding surface 11.

Note that the above description of the bonding is an example. The materials of each part can be changed as appropriate. For example, the material of the through electrode 54 and the wiring electrode 26 is not limited to copper.

(dummy pad)
The role of the dummy pad 20 in hybrid bonding will be described below. The dummy pad 20 can increase the bonding strength between the capacitor portion bonding surface 51 and the chip portion bonding surface 11.

As mentioned above, in hybrid bonding between the capacitor portion bonding surface 51 and the chip portion bonding surface 11, it is preferable that the materials of the contacting parts of the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are the same. Here, as shown in FIG. 6, a capacitor electrode 62 is formed on the capacitor portion bonding surface 51. The capacitor electrode 62 is typically made of a metal such as copper. If a dummy pad 20 is not formed on the chip portion bonding surface 11, the chip portion bonding surface 11 with which the capacitor electrode 62 contacts becomes the chip portion insulating portion 18. The chip portion insulating portion 18 is made of an insulating material. Therefore, no hybrid bonding bond is created between the capacitor electrode 62 and the chip portion insulating portion 18. This is because one is a metal material and the other is an insulating material.

If there are any areas where bonding does not occur between the capacitor portion bonding surface 51 and the chip portion bonding surface 11, the bonding strength between the silicon chip portion 10 and the capacitor portion 50 may be weakened.

In the silicon chip portion 10 of this embodiment, a dummy pad 20 is formed on the chip portion bonding surface 11. The dummy pad 20 is positioned so that it overlaps with the capacitor electrode 62 when the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are bonded. The dummy pad 20 is also formed from the same material as the capacitor electrode 62. Therefore, when the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are bonded, a bond can be formed between the dummy pad 20 and the capacitor electrode 62. This increases the bonding strength between the capacitor portion bonding surface 51 and the chip portion bonding surface 11.

(Manufacturing method)
A manufacturing method of the logic semiconductor device 1 of this embodiment will be described. The logic semiconductor device 1 is manufactured by bonding a silicon chip portion 10 and a capacitor portion 50. Specifically, as shown in FIG. 3 , by bringing a chip wafer 310 and a capacitor wafer 350 into contact with each other, the individual silicon chip portions 10 formed on the chip wafer 310 are bonded to the individual capacitor portions 50 formed on the capacitor wafer 350. The silicon chip portions 10 and the capacitor portions 50 can also be manufactured using conventional techniques. Here, the bonding of the silicon chip portions 10 and the capacitor portions 50 will be described.

The silicon chip unit 10 and the capacitor unit 50 can be bonded using hybrid bonding. First, a chip wafer 310 on which the silicon chip unit 10 is formed and a capacitor wafer 350 on which the capacitor unit 50 is formed are prepared. Next, the chip wafer bonding surface 311 of the chip wafer 310 and the capacitor wafer bonding surface 351 of the capacitor wafer 350 are planarized using CMP (chemical mechanical planarization) or similar. The silicon chip unit 10 of the chip wafer 310 and the capacitor unit 50 of the capacitor wafer 350 are then aligned. The chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 are then brought closer together, more specifically, the chip unit bonding surface 11 and the capacitor unit bonding surface 51 are brought closer together to bond the chip unit bonding surface 11 and the capacitor unit bonding surface 51. During this process, heat or pressure may be applied to the interface between the chip unit bonding surface 11 and the capacitor unit bonding surface 51. After bonding, annealing may also be performed. After bonding, the resulting semiconductor device is diced or otherwise separated into individual pieces to obtain individual logic semiconductor devices 1.

Note that the method for manufacturing the logic semiconductor device 1 is not limited to the method described above. In the above description, the silicon chip portion 10 and the capacitor portion 50 are bonded together while they are formed on the chip wafer 310 or the capacitor wafer 350, respectively, and then singulated to obtain individual logic semiconductor devices 1. Alternatively, the silicon chip portion 10 and the capacitor portion 50 may be cut out from the chip wafer 310 or the capacitor wafer 350, respectively, and the singulated silicon chip portion 10 and capacitor portion 50 may be bonded to obtain the logic semiconductor device 1. Alternatively, one may be in the form of a wafer and the other in the form of a chip, and these may be bonded together by hybrid bonding or the like. For example, silicon chip portions 10 singulated by dicing may be bonded to the capacitor wafer 350 by hybrid bonding or the like.

The above describes an embodiment of the present invention. The present invention is not limited to the above embodiment, and various modifications, variations, and combinations are possible.

(1) In a logic semiconductor device, a silicon substrate portion, a transistor layer, a wiring layer, and a capacitor portion in which a through via and a capacitor are formed are formed in this order.
(2) The logic semiconductor device, wherein the wiring layer and the capacitor section are in direct contact with each other.
(3) The logic semiconductor device as described above, wherein the capacitor is a trench type capacitor.
(4) When the surface of the capacitor portion that contacts the wiring layer is a capacitor portion bonding surface,
a capacitor electrode that is an electrode of the capacitor is exposed on the joint surface of the capacitor portion;
When a surface of the wiring layer that contacts the capacitor portion is defined as a wiring layer bonding surface,
In the logic semiconductor device, a pad made of metal is formed on the wiring layer junction surface at a portion in contact with the capacitor electrode.
(5) A method for manufacturing a logic semiconductor device includes the steps of: creating a chip wafer on which a plurality of silicon chip portions each having a silicon substrate portion, a transistor layer, and a wiring layer in that order are formed;
A step of producing a capacitor wafer having a plurality of capacitor portions each having a through via and a capacitor formed therein;
bringing the chip wafer and the capacitor wafer into contact with each other and bonding the wiring layer and the capacitor portion;
The method includes cutting out logic semiconductor devices each having a silicon chip portion and a capacitor portion bonded together from the chip wafer and the capacitor wafer.

1 Logic semiconductor device 10 Silicon chip portion 11 Chip portion bonding surface 11R Back surface of chip portion bonding surface 12 Silicon substrate portion 14 Transistor layer 16 Wiring layer 18 Chip portion insulating portion 20 Dummy pad 21 First dummy pad 22 Second dummy pad 26 Wiring electrode 50 Capacitor portion 51 Capacitor portion bonding surface (wiring layer bonding surface)
52 Capacitor section insulating section 53 Through via 54 Through electrode 55 First through electrode 56 Second through electrode 58 Capacitor section rear surface 59 Device solder section 60 Trench capacitor (capacitor)
62 Capacitor electrode 64 First capacitor electrode 65 Second capacitor electrode 66 Dielectric layer 68 First electrode layer 69 Second electrode layer 77 Connection wiring 78 First connection wiring 79 Second connection wiring 100 Semiconductor package 110 Package substrate 112 Package wiring 114 Package insulating part 116 Package solder part 200 Semiconductor package 210 Silicon chip 212 Silicon chip solder part 220 Interposer 222 Through via 224 Trench capacitor 226 Interposer solder part 310 Chip wafer 311 Chip wafer bonding surface 312 Chip wafer back surface 350 Capacitor wafer 351 Capacitor wafer bonding surface

Claims (7)

A logic semiconductor device in which a silicon substrate portion, a transistor layer, a wiring layer, and a capacitor portion in which a through via and a capacitor are formed are formed in this order. The logic semiconductor device according to claim 1, wherein the wiring layer and the capacitor section are in direct contact. The logic semiconductor device according to claim 1 or 2, wherein the capacitor is a trench capacitor. When a surface of the capacitor portion that is in contact with the wiring layer is defined as a capacitor portion bonding surface,
a capacitor electrode that is an electrode of the capacitor is exposed on the joint surface of the capacitor portion;
When a surface of the wiring layer that contacts the capacitor portion is defined as a wiring layer bonding surface,
3. The logic semiconductor device according to claim 1, wherein a pad made of metal is formed on a portion of said wiring layer junction surface in contact with said capacitor electrode. a through electrode is disposed on the capacitor portion bonding surface,
the capacitor electrode is connected to the through electrode corresponding to a power supply line and the through electrode corresponding to a ground line;
5. The logic semiconductor device according to claim 4. a step of producing a chip wafer on which a plurality of silicon chip portions each having a silicon substrate portion, a transistor layer, and a wiring layer in that order are formed;
A step of producing a capacitor wafer having a plurality of capacitor portions each having a through via and a capacitor formed therein;
bringing the chip wafer and the capacitor wafer into contact with each other and bonding the wiring layer and the capacitor portion;
A method for manufacturing a logic semiconductor device, comprising the step of cutting out logic semiconductor devices each having a silicon chip portion and a capacitor portion bonded together from the chip wafer and the capacitor wafer. The bonding is a direct bonding by hybrid bonding.
7. The method for manufacturing a logic semiconductor device according to claim 6.