WO2025185848A1

WO2025185848A1 - Light-emitting semiconductor chip

Info

Publication number: WO2025185848A1
Application number: PCT/EP2024/084825
Authority: WO
Inventors: Johannes Saric; Wolfgang Schmid
Original assignee: Ams Osram International GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2024-03-07
Filing date: 2024-12-05
Publication date: 2025-09-12
Anticipated expiration: 2026-09-07
Also published as: EP4643618A1; WO2025185848A8

Abstract

A light-emitting semiconductor chip is specified, comprising - a semiconductor body (1) with a radiation exit surface (11), - a passivation (2) on the radiation exit surface (11), - a contact structure (3) on the passivation (2), - at least one opening (4) in the passivation (2), wherein - the contact structure (3) contacts the semiconductor body (1) at the radiation exit surface (11) through the at least one opening (4).

Description

LIGHT-EMITTING SEMICONDUCTOR CHIP

A light-emitting semiconductor chip is speci fied .

An obj ect to be achieved is to speci fy a light-emitting semiconductor chip having enhanced ef ficiency .

The light-emitting semiconductor chip is , for example , a light-emitting diode . The light-emitting semiconductor chip produces electromagnetic radiation during operation . For example , the electromagnetic radiation lies in the spectral range between infrared radiation and UV radiation . In particular, the electromagnetic radiation can be visible light .

According to one aspect of the light-emitting semiconductor chip, the light-emitting semiconductor chip comprises a semiconductor body with a radiation exit surface . The semiconductor body is , for example , at least partly formed by an epitaxial method like MOVPE or MBE .

The semiconductor body has a radiation exit surface through which radiation produced during operation leaves the semiconductor body . For example , the radiation exit surface is given by a main surface of the semiconductor body or is part of a main surface of the semiconductor body . For example , the semiconductor body has a cuboidal shape , and the radiation exit surface is part of a top surface or is given by the top surface of the cuboid . According to at least one aspect of the light-emitting semiconductor chip, the light-emitting semiconductor chip comprises a passivation on the radiation exit surface of the semiconductor body . For example , the passivation is , at least in places , in direct contact with the radiation exit surface of the semiconductor body and is therefore in direct contact with the semiconductor body .

It is possible that the passivation only covers part of the radiation exit surface or the entire radiation exit surface .

Further, it is also possible that the passivation is only applied at the radiation exit surface or that the passivation covers other surfaces of the semiconductor body like , for example , side surfaces which connect the radiation exit surface with a bottom surface of the semiconductor body .

The passivation is , for example , formed with an electrically insulating material . In this context , the passivation can be electrically insulating . Further, the passivation can be configured to protect the surface parts on which it is applied from mechanical and/or chemical damage .

For example , the passivation is formed with materials like SiaN4 and/or SiCy . For example , the passivation can be applied by a deposition process like sputtering or chemical vapor deposition .

According to at least one aspect of the light-emitting semiconductor chip, the light-emitting semiconductor chip comprises a contact structure on the passivation . The contact structure is , for example , at least in places , in direct contact with the passivation . The contact structure is formed with an electrically conducting material like , for example , a metal . The contact structure is configured to conduct electrical current . Further, the contact structure can be configured to spread the current over the radiation exit surface of the semiconductor chip .

According to at least one aspect of the light-emitting semiconductor chip, the semiconductor chip comprises at least one opening in the passivation . In the region of the at least one opening, no material of the passivation is present , for example it has been removed . The at least one opening is laterally surrounded by material of the passivation .

For example , the at least one opening is laterally completely surrounded by material of the passivation . Here , " laterally" denotes a lateral direction which, for example , is parallel to the radiation exit surface and/or a main surface of the light-emitting semiconductor chip . The lateral direction is perpendicular to a vertical direction which, for example , is parallel to a growth direction of the semiconductor chip .

Each of the at least one opening extends completely through the passivation . In this way, the radiation exit surface , and therefore the semiconductor body, is freely accessible at a bottom of the opening . In particular, the light-emitting semiconductor chip comprises a plurality of at least one opening in the passivation .

According to at least one aspect of the light-emitting semiconductor chip, the contact structure contacts the semiconductor body at the radiation exit surface through the at least one opening . This means that at least in places - at the bottom of each opening - the contact structure is in direct contact with the radiation exit surface and, as a result , electrical current can be imprinted into the semiconductor body by the contact structure through the at least one opening . It is also possible that the contact structure contacts the semiconductor body solely through the at least one opening in the passivation . This means that in this case contact is only made through the at least one opening and not at any other part of the radiation exit surface of the semiconductor chip .

It is possible for the contact structure to contact the semiconductor body directly through the at least one opening . It is also possible for the contact structure to contact the semiconductor body via a contact metal disposed in each of the at least one opening . The contact metal comprises , for example , a metal layer or a stack of metal layers .

According to at least one aspect of the light-emitting semiconductor chip, the light-emitting semiconductor chip comprises a semiconductor body with a radiation exit surface , a passivation on the radiation exit surface , a contact structure on the passivation, at least one opening in the passivation, wherein the contact structure contacts the semiconductor body at the radiation exit surface through the at least one opening .

The herein described light-emitting semiconductor chip is based, inter alia, on the following observations :

For example , thin- film light-emitting diodes from which a growth substrate is removed may have contact structures on the semiconductor that serve as an electrical contact on the one hand and on the other hand pre-distribute the current , especially over large chips , so that only lateral current flow is required over a limited area in the semiconductor itsel f .

Due to the current distribution, a large cross-section is required in the contact structures in order to avoid electromigration and to keep the series resistance in the contact structures low .

As the contact structures cannot be manufactured to any height , they have a greater width than would be necessary for the electrical connection .

Further, contacting the radiation exit surface of the semiconductor body via a contact structure leads to an area with a rough interface at places where the contact structure is in direct contact with the semiconductor body . This rough interface leads to a high absorption of electromagnetic radiation produced in the semiconductor chip . The solution described here , where contact is made through at least one opening in the passivation, allows the area of direct contact between the contact structure and the semiconductor body to be constricted to the at least one opening . Thus , the area where a rough interface is formed between the contact structure and the semiconductor body is constricted to the at least one opening and therefore there is a smaller area of high absorption of electromagnetic radiation produced in the semiconductor chip . This leads to a higher ef ficiency of the semiconductor chip .

Further, places in the passivation where no opening is formed and which are covered by the contact structure show an increased reflectivity . The reflected light is reflected back into the semiconductor body and can be used via photon recycling for further re-emission or is reflected in the semiconductor body in such a way that it can leave the semiconductor body subsequently . Both ef fects lead to enhanced brightness and ef ficiency of the light-emitting semiconductor chip .

According to one aspect of the light-emitting semiconductor chip, the passivation is permeable to electromagnetic radiation generated during operation . This means that the passivation is transparent or translucent for the electromagnetic radiation . For example , the transparency of the passivation is at least 60% , for example at least 90% .

According to at least one aspect of the light-emitting semiconductor chip, the passivation acts as an antireflection layer in places where the passivation is free of the contact structure . In this case , the passivation for example covers not only parts of the radiation exit surface to which the contact structure is applied but also parts of the radiation exit surface where no contact structure is applied . There , the passivation acts as an anti-reflection layer and therefore has an anti-reflective ef fect . This means that less electromagnetic radiation is reflected when impinging on the radiation exit surface with such a passivation than would be the case without such a passivation . In this way, the passivation further increases the ef ficiency of the light-emitting semiconductor chip .

I f only the radiation exit side of the semiconductor chip is considered, the simplest anti-reflection passivation would be a layer that is about L/ 4n thick, where L is the wavelength of the emitted electromagnetic radiation . Ideally it would be slightly thicker because oblique directions of incidence must also be taken into account . Here , n is the geometric mean between the refractive index of the semiconductor body, e . g . 3 . 2 , and the material surrounding the semiconductor chip at its application side , e . g . 1 . 5 .

According to at least one aspect of the light-emitting semiconductor chip, the passivation acts as a reflectionenhancing layer in places where the passivation is covered by the contact structure . In this way, more electromagnetic radiation is reflected when it impinges on the contact structure in places where the passivation layer is applied between the contact structure and the radiation exit surface than in places without the passivation . In this way, the passivation further enhances the ef ficiency of the semiconductor chip .

According to at least one aspect of the light-emitting semiconductor chip, the passivation comprises two or more layers , at least in places . By forming the passivation with more than one layer, at least in places , it is possible to tailor the optical properties of the passivation in a desired way . For example , in places where the passivation is not covered by the contact structure , the optical properties can be configured in such a way that the passivation acts as an anti-reflection layer . In places where the passivation is covered by the contact structure , the passivation can be configured to act as a reflection-enhancing layer .

According to at least one aspect of the light-emitting semiconductor chip, the contact structure comprises a plurality of contact tracks , and the passivation is thinner and/or comprises fewer layers between two adj acent contact tracks than beneath each of the two adj acent contact tracks .

The contact tracks are thin lattice stripes , for example , which extend over the radiation exit surface and distribute the electric current in this way over a large area of the semiconductor body . Between the contact tracks are regions of the radiation exit surface which are covered by a thinner passivation or a passivation with a smaller number of layers than the passivation beneath each of the contact tracks . In this way, the passivation can be tailored to be anti- reflective between the contact tracks and reflective beneath the contact tracks .

According to at least one aspect of the light-emitting semiconductor chip, the passivation covers at least 50% of the radiation exit surface . It is also possible that the passivation covers the entire radiation exit surface . Such a passivation can enhance the optical properties of the semiconductor chip, for example by being anti-reflective in places where the contact structure is not applied to the radiation exit surface . Further, such a passivation may protect the semiconductor body against mechanical and/or chemical damage .

According to at least one aspect of the light-emitting semiconductor chip, the radiation exit surface is free of the passivation layer, at least in places ; in particular, the contact structure comprises a plurality of contact tracks , and the radiation exit surface is free from the passivation layer between two adj acent tracks , in particular between each of two adj acent tracks . In this way, the passivation is for example only applied in regions where the contact structure is applied to the radiation exit surface . In this way, less material of the passivation layer has to be applied to the semiconductor body .

According to at least one aspect of the light-emitting semiconductor chip, at least 30% and at most 80% of the contact structure contacts the semiconductor body through the at least one opening . This means that , by the passivation and the at least one opening in the passivation, the contact area between the contact structure and the semiconductor body is reduced to between at least 30% and at most 80% of the contact structure , and therefore the area of rough interfaces between the contact structure and the semiconductor body is reduced and hence the optical properties are enhanced .

According to at least one aspect of the light-emitting semiconductor chip, the light-emitting semiconductor chip comprises a plurality of openings .

According to at least one aspect of the light-emitting semiconductor chip, some of the openings are arranged equidistant along a line . For example , the openings are arranged along contact tracks , wherein each opening has the same si ze and the openings are arranged equidistant to each other along the contact track . Here , it is possible that the openings are arranged along a straight line . In such a way, current can be imprinted into the semiconductor body in a regular fashion, which leads to a homogenous brightness over the radiation exit surface .

Alternatively, the openings are not equidistant . This makes it possible to tailor the current imprint in the semiconductor body to compensate for changes in electrical resistance along the contact tracks .

According to at least one aspect of the light-emitting semiconductor chip, the radiation exit surface is part of an n-doped region of the semiconductor body, and the semiconductor body is based on an arsenide compound semiconductor material or a phosphide compound semiconductor material .

'Based on phosphide compound semiconductor material ' in this context means that the semiconductor layer sequence or at least a part thereof , particularly preferably at least the n- doped region, preferably comprises Al_nGa_mIni-_n-mP or As_nGa_mIni-_n_ _mP, where 0 < n < 1 , 0 < m < 1 and n+m < 1 . This material does not necessarily have to have a mathematically exact composition according to the above formula . Rather, it can have one or more dopants and additional components . For the sake of simplicity, however, the above formula only contains the essential components of the crystal lattice (Al or As , Ga, In, P ) , even i f these may be partially replaced by small quantities of other substances .

'Based on arsenide compound semiconductor material ' in this context means that the semiconductor layer sequence or at least a part thereof , particularly preferably at least the n- doped region, preferably comprises AlnGamlnx-n-mAs , where 0 < n < 1 , 0 < m < 1 and n+m < 1 . This material does not necessarily have to have a mathematically exact composition according to the above formula . Rather, it can have one or more dopants as well as additional components . For the sake of simplicity, the above formula only contains the essential components of the crystal lattice (Al or As , Ga, In) , even i f these may be partially replaced by small quantities of other substances .

For example , InGaAlP or AlGaAs or other combinations of these materials are used to form the semiconductor body . In particular, for an n-doped region of these material systems , a rough interface is observed in places where a contact structure is in direct contact with the semiconductor body, and thus the here described solution is particularly advantageous .

According to at least one aspect of the light-emitting semiconductor chip, the contact structure comprises gold, which is in direct contact with the semiconductor body at contact locations in the at least one opening . For example , the contact structure is formed with AuGe and/or AuPd and/or PdGe at the contact locations in the at least one opening . The contact locations can then be covered by a transparent conductive oxide , like ITO, and spreading metals , which for example comprise Au or a layer sequence comprising Au like Au/Ti/Pt/Au .

According to at least one aspect of the light-emitting semiconductor chip, the contact structure or a contact metal is annealed to the semiconductor body in the at least one opening .

For example , the passivation is opened locally for forming the at least one opening . Then, a contact metal like , for example , AuGe or AuPd is deposited using a mask and the mask is li fted of f . Subsequently, the contact metal is annealed by raising the temperature of the semiconductor body as a whole or only in the region of the contact locations . Subsequently, the remaining contact structure is applied using a lithographic process . Thereby, for example , ITO is deposited, and the spreading metals are subsequently applied to the ITO .

This results in a contact structure where the roughness of the interface between the semiconductor body and the contact structure is enhanced at the contact locations but the stack of passivation and contact structure has a higher reflectivity outside the at least one opening .

According to at least one embodiment of the light-emitting semiconductor chip, a contact metal in the at least one opening comprises a first layer sequence in direct contact with the semiconductor body and a second layer sequence at a side of the first layer sequence which faces away from the semiconductor body .

For example , the passivation is opened locally for forming the at least one opening . The at least one opening has , for example , a diameter and/or a lateral extension of at least 2 pm, for example at least 3 pm, for example 4 pm . The contact metal is disposed in this opening .

The contact metal comprises a first layer sequence which is in direct contact with the semiconductor body . The first layer sequence comprises , for example , layers of the following materials : Au, Ge , Ni , Pd . The thickness of the first layer sequence is , for example , at least 100 nm, for example 200 nm or more .

On top of the first layer sequence , the second layer sequence is formed which comprises , for example , layers of at least one of the following materials : Ti , Pt , Au . According to at least one embodiment of the light-emitting semiconductor chip, the first layer sequence is annealed to the semiconductor body . That is to say, the light-emitting semiconductor chip is heated to a few hundred degrees Celsius at a sintering step and at this sintering temperature the metals of the first layer sequence penetrate into the semiconductor body and/or displace the atoms there . As a result , the layers of the first layer sequence are no longer clearly recogni zable or no longer clearly separated vertically, but form e . g . three-dimensional structures .

However, the layers in the second layer sequence are not alloyed after the described sintering, but remain as a locally vertically separable layer sequence . This second layer sequence allows for a good electrical contact between the first layer sequence and therefore the semiconductor body and the contact structure . Without the second layer sequence the alloying process of the first layer sequence may be disrupted, resulting in a poor electrical contact .

As a result , the forward voltage of the semiconductor chip can be adj usted with such a second layer sequence and, for example , a particularly low forward voltage is possible .

According to at least one aspect of the light-emitting semiconductor chip, the contact structure comprises a first sublayer which is in direct contact with the passivation and the contact metal , in particular with the second layer sequence , and a second sublayer which is in direct contact with the first sublayer . Here it is possible that the first sublayer is applied before or after the contact metal , in particular the first layer sequence of the contact metal , is annealed to the semiconductor body . For example , the first sublayer is much thinner than the second sublayer . The first sublayer then, for example , ensures a good adhesion of the contact structure to the passivation with which the first sublayer is in direct contact .

According to at least one aspect of the light-emitting semiconductor chip, the first sublayer is formed with a transparent conductive oxide and has a thickness of at most 200 nm, for example at most 100 nm, for example 20 nm or less . In this way, the first sublayer can conformally cover the contact metal .

In the following, the here described semiconductor chip is explained in more detail with respect to exemplary embodiments and corresponding figures .

Figure 1 shows a schematic plan view of a light-emitting semiconductor chip according to an exemplary embodiment .

Figure 2 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 3 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 4 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips . Figure 5 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 6 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 7 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 8 shows a schematic sectional view for a further exemplary embodiment of here described light-emitting semiconductor chips .

Figure 9A shows a schematic plan view of a light-emitting semiconductor chip according to an exemplary embodiment .

Figure 9B shows a schematic sectional view for the exemplary embodiment of figure 9A.

Figures 10A and 10B show schematic sectional views for a further exemplary embodiment of a here described lightemitting semiconductor chip .

In these exemplary embodiments and figures , similar or similarly acting constituent parts are provided with the same reference symbols . The elements illustrated in the figures and their si ze relationships among one another should not be regarded as true to scale . Rather, individual elements may be represented with an exaggerated si ze for the sake of better representability and/or for the sake of better understanding . Figure 1 shows a schematic plan view of an embodiment of a here described light-emitting semiconductor chip . The plan view shows the light-emitting semiconductor chip with a semiconductor body 1 which has a radiation exit surface 11 which is given by a main surface of the semiconductor body 1 . The light-emitting diode chip further comprises a passivation 2 on the radiation exit surface 11 . Further, a contact structure 3 is , at least in places , applied onto the passivation 2 on a side of the passivation 2 which faces away from the radiation exit surface 11 .

The passivation 2 has at least one opening 4 , and the contact structure 3 contacts the semiconductor body 1 at the radiation exit surface 11 through the at least one opening 4 .

This is shown in more detail in the sectional view of Figure 2 along line AA' . The semiconductor body 1 comprises , for example , an n-doped region 12 , and the radiation exit surface 11 is given by the upper surface of the n-doped region 12 which faces away from an active region 13 . During operation, electromagnetic radiation is generated in the active region 13 . A p-doped layer 14 is present on the side of the active region 13 facing away from the n-doped region 12 .

The openings 4 are arranged along contact tracks 32 , wherein each opening 4 for example has the same si ze and the openings 4 are arranged equidistant to each other along the contact track 32 . Alternatively, the openings 4 are not equidistant . This makes it possible to tailor the current imprint in the semiconductor body to compensate for changes in electrical resistance along the contact tracks 32 . The semiconductor chip may further comprise a carrier 5 on the side of the p-doped region 14 which faces away from the active region 13 . For example , the semiconductor chip is a thin film chip from which the growth substrate has been removed . As an alternative , the carrier 5 can be part of a growth substrate .

The passivation 2 comprises the at least one opening 4 , in which, at a contact location 31 , a contact metal 33 is in direct contact with the n-doped region 12 at the radiation exit surface 11 .

The contact metal 33 is , for example , given by a gold- containing material like AuGe or AuPd or Au . On the side facing away from the semiconductor body 1 , the contact structure 3 further comprises , for example , a TCO layer which for example is formed with ITO and spreading metals like Au or Au/Ti/Pt/Au .

Figure 3 shows a sectional view of an embodiment of the light-emitting semiconductor chip along line BB ' . It becomes clear from this figure that in this embodiment of the lightemitting semiconductor chip, no passivation layer 2 is present outside the contact structure 3 . This means that parts of the radiation exit surface 11 which are not covered by the contact structure 3 are free of the passivation 2 .

The passivation layer 2 beneath the contact structure 3 acts as a reflection-enhancing layer such that light impinging on it is reflected back into the semiconductor body 1 . The interface between the semiconductor body 1 and the contact metal 33 is rough and therefore light-absorbing only at the contact location . For example , the at least one opening 4 in the passivation 2 are configured in such a way that at least 30% and at most 80% , for example 50% , of the contact structure 3 contacts the semiconductor body 1 through the at least one opening 4 . This means that , by using a passivation layer with at least one opening, the contact area between the contact structure 3 and the semiconductor body 1 can be reduced to 80% or below, and therefore the area of absorption is largely reduced .

In connection with the sectional views of Figures 4 and 5 , a further embodiment of a here described light-emitting semiconductor chip is described .

In Figure 4 , a sectional view along line AA' is shown and in Figure 5 a sectional view along line BB ' is shown . As can be seen from Figure 5 , in this embodiment the passivation 2 covers regions of the radiation exit surface 11 which are not covered by the contact structure 3 , for example regions between adj acent contact tracks 32 .

With respect to Figures 6 , 7 and 8 , further embodiments of a here described light-emitting semiconductor chip are explained in more detail .

In these embodiments , the passivation layer 2 , at least in some places , comprises more than one layer, for example a first layer 21 and a second layer 22 .

Such a passivation can for example be tailored to form an anti-reflection passivation in places which are not covered by the contact structure 3 . If only the radiation exit side of the semiconductor chip is considered, the simplest anti-reflection passivation would be a layer that is about L/4n thick, where L is the wavelength of the emitted electromagnetic radiation.

Ideally it would be slightly thicker because oblique directions of incidence must also be taken into account.

Here, n is the geometric mean between the refractive index of the semiconductor body, e.g. 3.2, and the material surrounding the semiconductor chip at its application side, e.g. 1.5.

Preferably, however, the refractive index is quite small in the area of the contact structure, i.e. the angle of total reflection is quite small and only a small amount of electromagnetic radiation reaches the contact structure. At the same time, the layer should be so thick that only a small proportion of evanescent waves reach the metal bar.

If the refractive index is reduced and the thickness of the layer is increased, the reflectivity properties below the metal web improve but the transmission in the outcoupling area suffers as a result.

An advantageous passivation 2 as shown in the embodiment of Figure 7 with two layers 21, 21 consists of a first layer 21 facing the semiconductor body 1 with a slightly higher refractive index nl and a second layer 22 with a slightly lower refractive index n2 with the relationship n (semiconductor body) > nl > n2 > n (surrounding material) .

The passivation 2 acts as an anti-reflection layer in the area of the radiation exit surface 11 not covered by the contact structure 3 , whereby the reflected partial waves are essentially destructively superimposed at the three transitions . In the area where the contact structure 3 is present , the low refractive index n2 improves the reflectivity properties .

Advantageously, the refractive index n2 is quite small and may even assume the value of the refractive index of the surrounding material in extreme cases . This layer is then optically invisible in the decoupling area . This allows any thickness to be selected .

In the area of the contact structure 3 , in particular the contact tracks 32 , the low refractive index and suitable thickness , preferably >> L/ 4n, where L is the peak wavelength of the emitted electromagnetic radiation for both layers 21 , 22 together help to optimi ze the reflectivity there .

For example , the first layer 21 could be a silicon nitride layer with nl > 2 and the second layer could be a silicon oxide with nl ~ 1 . 5 .

Of course , it is also possible that more than two layers form the passivation 2 .

In a further embodiment , Figure 8 , the passivation can consist of more than one layer only beneath the contact structure . In this case , the second layer 22 may have been selectively removed and only remains beneath the contact structure 3 .

Figure 9A shows a schematic plan view of a light-emitting semiconductor chip according to an exemplary embodiment . Figure 9B shows a schematic sectional view for the exemplary embodiment of figure 9A.

The plan view of Figure 9A shows the light-emitting semiconductor chip with a semiconductor body 1 which has a radiation exit surface 11 which is given by a main surface of the semiconductor body 1 . The light-emitting diode chip further comprises a passivation 2 on the radiation exit surface 11 . Further, a contact structure 3 is , at least in places , applied onto the passivation 2 on a side of the passivation 2 which faces away from the radiation exit surface 11 .

The passivation 2 has openings 4 , and the contact structure 3 contacts the semiconductor body 1 at the radiation exit surface 11 through the openings 4 .

This is shown in more detail in the sectional view of Figure 9B along line AA' . The semiconductor body 1 comprises , for example , an n-doped region 12 , and the radiation exit surface 11 is given by the upper surface of the n-doped region 12 which faces away from an active region 13 . During operation, electromagnetic radiation is generated in the active region 13 . A p-doped layer 14 is present on the side of the active region 13 facing away from the n-doped region 12 .

In the embodiment of figures 9A and 9B, exactly one opening 4 is arranged in each contact track 32 . The opening 4 has a smaller width than the contact track 32 in which the opening 4 is formed . Furthermore , the lengths of the openings 4 can be smaller than the lengths of the tracks 32 . In particular, the total area of all the openings 4 is smaller than the total area of the contact structure 3 . The semiconductor chip may further comprise a carrier 5 on the side of the p-doped region 14 which faces away from the active region 13 . For example , the semiconductor chip is a thin film chip from which the growth substrate has been removed . As an alternative , the carrier 5 can be part of a growth substrate .

The passivation 2 comprises the openings , in which, at a contact location 31 , a contact metal 33 is in direct contact with the n-doped region 12 at the radiation exit surface 11 .

Figures 10A and 10B show a sectional view of an embodiment of the light-emitting semiconductor chip along line BB' for embodiments like , for example , shown in Figures 1 and 9A.

Figure 10A shows the embodiment before or without annealing of the contact metal 33 to the semiconductor body 1 . Figure 10B shows an embodiment after annealing of the contact metal 33 to the semiconductor body 1 .

In the embodiments of Figures 10A and 10B, the contact metal 33 is arranged in the at least one opening 4 .

The contact metal 33 comprises a first layer sequence 337 which is in direct contact with the semiconductor body 1 and a second layer sequence 338 at the side of the first layer sequence 337 which faces away from the semiconductor body 1. The first layer sequence 337, for example, comprises a first contact layer 331 which comprises or consists of Au, a second contact layer 322 which comprises or consists of Ge and a third contact layer 333 which comprises or consists of Ni . Further, it is possible to include a further layer which can be, for example, formed with Pd. However, also a different order of the layers might be possible.

Moreover, for example, the first contact layer 331 can comprise or consist of Ni . Further, it is possible that instead of a Au-layer and a Ge-layer, a AuGe layer with a higher content of Au than Ge is applied.

Further, for example, the first layer sequence 337 may comprise a layer of lOOnm AuGe alloy with a 88%/12% ratio (evaporated from the alloy) , a 30nm Ni-layer and a 100 nm Au- layer. Alternatively, the first two layers are swapped (first Ni, then the alloy) .

The third contact layer 333 has a thickness of a few tens of nanometers and the first contact layer 331 and the second contact layer 332 each have a thickness of a few 100 nm.

The contact metal 333 is surrounded by the passivation 2 which is, for example, given by a layer with a thickness of about 100 nm which is formed with a silicon oxide. The opening 4 has, for example, a diameter or a lateral extension of 4 pm. The semiconductor body is, for example, based on InGaAlP. The second layer sequence 338 comprises , in the embodiment of Figures 10A and 10B, a fourth contact layer 334 which may comprise or consists of Ti and has a thickness of greater than 100 nm and a fi fth contact layer 335 which, for example , comprises or consists of Pt and has a thickness of about 100 nm . Further, the second layer sequence 338 comprises a sixth contact layer 336 which, for example , comprises or consists of Au and has a thickness of about 100 nm .

The contact metal 33 may be sintered at a few 100 ° C before or after a first sublayer 34 of the contact structure 3 is applied . During sintering, the metals of the first , the second and the third contact layer partially penetrate into the semiconductor body 1 and/or displace the atoms there . Hence , these layers are no longer clearly recogni zable or no longer clearly separated vertically, as shown in Figure 10B . By way of contrast , the fourth, the fi fth and the sixth contact layer of the second layer sequence 338 are not alloyed and consequently locally vertically separable layers remain detectable .

The light-emitting semiconductor chip according to the embodiment of Figures 10A and 10B further comprises the contact structure 3 which comprises the first sublayer 34 which is in direct contact with the passivation 2 and the contact metal 33 , in particular with the second layer sequence 338 and a second sublayer 35 which is in direct contact with the first sublayer 34 .

The first sublayer 34 is , for example , formed with a transparent conductive oxide . For example , the first sublayer 34 consists of or comprises ITO . This ensures a good adhesion to the passivation 2 . The layer thickness of the first sublayer 34 is for example between 1 and 100 nm, for example 50 nm . On parts of the first sublayer 34 , a second sublayer 35 is placed which, for example , comprises or consists of Au and has a thickness of over 100 nm, particularly preferably over 1000 nm .

The second layer sequence 338 ensures a good electrical contact between the semiconductor body 1 and the contact structure 3 and a good current distribution in the contact structure 3 . As can be seen for example in Figures 10A and 10B, it is possible that the second sublayer 35 only covers a part of the first sublayer 34 in the central region over the contact metal 33 .

This patent application claims the priority of German patent application 102024106549 . 4 , the disclosure content of which is hereby incorporated by reference .

Alternatively or additionally to the features described in connection with the figures , the embodiments shown in the figures can comprise further features described in the general part of the description . Moreover, features and embodiments of the figures can be combined with each other, even i f such combination is not explicitly described .

The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments . Rather, the invention encompasses any new feature and also any combination of features , which in particular includes any combination of features in the patent claims and any combination of features in the exemplary embodiments , even i f this feature or this combination itsel f is not explicitly speci fied in the patent claims or exemplary embodiments .

References

1 semiconductor body

11 radiation exit surface

12 n-doped region

13 active region

14 p-doped region

2 passivation

21 layer

22 layer

3 contact structure

31 contact location

32 contact track

33 contact metal

331 first contact layer

332 second contact layer

333 third contact layer

334 fourth contact layer

335 fi fth contact layer

336 sixth contact layer

337 first layer sequence

338 second layer sequence

34 first sublayer

35 second sublayer

4 opening

5 carrier

Claims

1. A light-emitting semiconductor chip comprising a semiconductor body (1) with a radiation exit surface (11) , a passivation (2) on the radiation exit surface (11) , a contact structure (3) on the passivation (2) , at least one opening (4) in the passivation (2) , wherein the contact structure (3) contacts the semiconductor body (1) at the radiation exit surface (11) through the at least one opening (4) .

2. The light-emitting semiconductor chip according to the previous claim, wherein the passivation (2) is permeable to electromagnetic radiation generated during operation.

3. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the passivation (2) acts as an anti-reflection layer in places where the passivation (2) is free of the contact structure (3) .

4. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the passivation (2) acts as a reflection-enhancing layer in places where the passivation (2) is covered by the contact structure (3) .

5. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the passivation (2) comprises two or more layers (21, 22) at least in places.

6. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) comprises a plurality of contact tracks (32) , and the passivation (2) is thinner and/or comprises fewer layers between two adjacent contact tracks (32) than beneath each of the two adjacent contact tracks (32) .

7. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the passivation (2) covers at least 50% of the radiation exit surface (11) .

8. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) comprises a plurality of contact tracks (32) , and the radiation exit surface (11) is free of the passivation (2) between two adjacent tracks.

9. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) comprises a plurality of contact tracks (32) , and a plurality of openings (4) in each contact track (32) .

10. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) comprises a plurality of contact tracks (32) , and exactly one opening (4) in each contact track (32) .

11. The light-emitting semiconductor chip according to at least one of the previous claims, wherein at least 30% and at most 80% of the contact structure (3) contacts the semiconductor body (1) through the at least one opening (4) .

12. The light-emitting semiconductor chip according to at least one of the previous claims with a plurality of openings (4) , wherein some of the openings (4) are arranged equidistant along a line.

13. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the radiation exit surface (11) is part of an n-doped region (12) of the semiconductor body (1) , and the semiconductor body (1) is based on an arsenide compound semiconductor material or a phosphide compound semiconductor material.

14. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) or a contact metal (33) in the at least one opening (4) comprises gold, which is in direct contact with the semiconductor body (1) at contact locations (31) in the at least one opening (4) .

15. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) or a contact metal (33) is annealed to the semiconductor body (1) in the at least one opening (4) .

16. The light-emitting semiconductor chip according to at least one of the previous claims, wherein a contact metal (33) in the at least one opening (4) comprises a first layer sequence (337) in direct contact with the semiconductor body (1) and a second layer sequence (338) at a side of the first layer sequence (337) which faces away from the semiconductor body ( 1 ) .

17. The light-emitting semiconductor chip according to the previous claim, wherein the first layer sequence (337) is annealed to the semiconductor body (1) .

18. The light-emitting semiconductor chip according to at least one of the previous claims, wherein the contact structure (3) comprises a first sublayer (34) which is in direct contact with the passivation (2) and the contact metal (33) , in particular with the second layer sequence (338) , and a second sublayer (35) which is in direct contact with the first sublayer (34) .

19. The light-emitting semiconductor chip according to the previous claim, wherein the first sublayer (34) is formed with a transparent conductive oxide and has a thickness of at mo st 200 nm .