WO2025185504A1 - Multi-chip packaging structure, optical module, and optical communication system - Google Patents

Abstract

Provided in the present application are a multi-chip packaging structure, an optical module, and an optical communication system. The multi-chip packaging structure comprises a substrate (100), the top surface of the substrate (100) being configured with a plurality of chips, and the plurality of chips comprising at least one electrical chip (140) and an optical chip (130), wherein the top surface of the substrate (100) comprises a first region (110) and a second region (120), the distance between the first region (110) and the bottom surface of the substrate (100) is greater than the distance between the second region (120) and the bottom surface of the substrate (100), the first region (110) is used for configuring the electrical chip (140) among the at least one electrical chip, the second region is configured with the optical chip (130), and the material of the first region (110) is different from the material of the second region (120). In the technical solution of the present application, two surfaces are provided on the substrate (100), so as to distinguish between a surface used for packaging the electrical chip (140) and a surface used for packaging the optical chip (130), and the optical chip (130) is correspondingly disposed on one of the two surfaces on the basis of the actual material of the optical chip (130). Therefore, stress-related packaging risks are reduced, the reliability of the packaging structure is improved, and the space of the packaging structure is also saved.

Description

A multi-chip packaging structure, optical module and optical communication system

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 5, 2024, with application number 202410254054.4 and invention name “A multi-chip packaging structure, optical module and optical communication system”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of optical communications, and in particular to a multi-chip packaging structure, an optical module, and an optical communication system.

Background Art

Optical-to-electronic hybrid integration is a new optical technology that combines optical and electrical components to achieve seamless connectivity and interconnection between optical and electrical signals. Co-packaged optics (CPO) combines switch chips and optical engines in a single package, increasing interconnect density and meeting the demands of modern computing and applications, such as ultra-large bandwidth, low latency, and high flexibility.

Currently, optoelectronic co-packaging solutions mainly fall into three directions: 2D, 2.5D, and 3D. Among them, the 2D solution places multiple chips such as switch chips, electrical chips, and optical chips on a substrate. Although it is easy to package, under this solution, the substrate needs to bear the fan-out of the switch chip and use organic materials and other materials with a serious mismatch in thermal expansion coefficient with the optical chip, resulting in reliability risks in the packaging structure. The 2.5D solution further sets an interposer on the substrate and sets the optical chip on the interposer. Although it improves the reliability of the packaging structure, it does not eliminate the stress risk of the packaging structure. The 3D solution stacks multiple chips flip-chip together. Although it saves packaging space, it cannot solve the material mismatch problem between the optical chip and the substrate. As can be seen from the above, how to reduce the size of optoelectronic co-packaging and improve the reliability of the packaging structure is an urgent problem to be solved.

Summary of the Invention

The present application provides a multi-chip packaging structure. An embodiment of the present application provides a multi-chip packaging structure. By setting a stress-adaptive surface for the optical chip separately in the substrate, the reliability of the packaging structure is improved while saving the common packaging space.

In a first aspect, a multi-chip packaging structure is provided, comprising: a substrate, a top surface of which is configured with a plurality of chips, the plurality of chips including at least one electrical chip and an optical chip; wherein the top surface of the substrate comprises a first area and a second area, the first area being used to configure the electrical chip of the at least one electrical chip, the second area being configured with the optical chip, and the material of the first area being different from the material of the second area.

In current integration schemes, the optical chip and the electrical chip are placed on the same surface. To simultaneously handle the work of multiple chips (e.g., fan-out of a dedicated integrated circuit), the substrate surface must be made of an organic material with a significant thermal expansion mismatch with the optical chip. In the technical solution of this application, two surfaces are provided in the substrate to distinguish the surfaces used to package the electrical chip and the optical chip in the packaging structure. One of the two surfaces is then provided based on the actual material of the optical chip. This reduces the risk of stress packaging, improves the reliability of the packaging structure, and saves packaging structure space.

In combination with the first aspect, in certain implementations of the first aspect, the distance between the first region and the bottom surface of the substrate is greater than the distance between the second region and the bottom surface of the substrate, thereby further saving packaging structure space.

In conjunction with the first aspect, in certain implementations of the first aspect, the substrate includes a first build-up layer group, a core layer, a second build-up layer group, and an interposer. The first build-up layer group includes a plurality of stacked build-up layers, with the bottom surface of the first build-up layer group forming the bottom surface of the substrate. The core layer is disposed on the top surface of the first build-up layer group. The second build-up layer group includes a plurality of stacked build-up layers, with the second build-up layer group disposed on the top surface of the core layer. The second build-up layer group includes a first build-up layer, which is located at the bottom of the second build-up layer group, with the bottom surface of the first build-up layer in contact with the core layer. The top surface of the first build-up layer includes a third region and a fourth region. The third region is configured with the build-up layers of the second build-up layer group, excluding the first build-up layer, and the fourth region is configured with the interposer. The second build-up layer group includes a second build-up layer, which is located at the top of the second build-up layer group. The first region includes the top surface of the second build-up layer, and the second region includes the top surface of the interposer. Thus, the first region for accommodating an electrical chip is formed by the build-up layers of the substrate itself, and the second region for accommodating an optical chip is formed by hollowing out an inner concave surface in the substrate and embedding the interposer. This forms a substrate for optoelectronic hybrid integration.

In some implementations, the total thickness of the first buildup layer group is the same as the total thickness of the second buildup layer group, thereby ensuring stress balance of the substrate and preventing warping of the substrate through the symmetry of the substrate in the vertical direction.

In some implementations, the second buildup layer group includes at least one third buildup layer, the third buildup layer covering a third region of the top surface of the interposer; and at least one third buildup layer includes a via, the projection of the via on the top surface of the interposer being located within the third region. By providing a buildup layer covering the interposer in the second buildup layer group and providing corresponding vias, signal integrity and interference immunity can be improved between chips configured in the first region and chips configured in the second region.

In some implementations, the at least one electrical chip includes a first electrical chip disposed on a top surface of the second build-up layer. The first electrical chip is electrically connected to the optical chip via vias. Placing the optical chip in the second region of the substrate improves operational reliability and saves packaging space.

In some implementations, the at least one electrical chip includes a first electrical chip, wherein the first electrical chip is attached to an interposer, and the optical chip is attached to the interposer, and the first electrical chip and the optical chip are electrically connected via the interposer. By arranging the electrical chip and the optical chip together in the second region of the substrate, the interconnection performance between the optical chip and the electrical chip can be improved, and overall power consumption can be reduced.

In some implementations, the at least one electrical chip includes a first electrical chip, wherein the optical chip is attached to the interposer, the first electrical chip is located above the optical chip, and the optical chip is electrically connected to the first electrical chip. Stacking the optical chip and the electrical chip in the second region of the substrate further saves space and improves interconnection performance between the optical chip and the electrical chip.

In some implementations, the multi-chip further includes a first electrical chip, wherein the first electrical chip is attached to the interposer, and the optical chip is located above the first electrical chip, and the optical chip is electrically connected to the first electrical chip. By stacking the optical chip and the electrical chip in the second region of the substrate, further space can be saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In some implementations, the at least one electrical chip further includes a second electrical chip, which is disposed on a top surface of the second build-up layer group and electrically connected to the first electrical chip. Through the above solution, multiple chips can be interconnected in a package structure.

In conjunction with the first aspect, in certain implementations of the first aspect, the substrate includes a third buildup group, a core layer, and a fourth buildup group, wherein: the third buildup group includes multiple stacked buildups, the bottom surface of the third buildup group forming the bottom surface of the substrate; the core layer is disposed on the top surface of the third buildup group; the top surface of the core layer includes a fifth region and a sixth region, the fifth region being configured with a fourth buildup group, the fourth buildup group including multiple stacked buildups; the first region includes the top surface of the fourth buildup group, and the second region includes the sixth region. A first region for accommodating an electrical chip is formed using the buildup layers of the substrate itself, and after a concave surface is hollowed out in the substrate, a second region for accommodating an optical chip is formed using the core layer, thereby forming a substrate for optoelectronic hybrid integration.

In some implementations, the total thickness of the third build-up layer group is the same as the total thickness of the fourth build-up layer group, thereby ensuring stress balance of the substrate and preventing warping of the substrate through the symmetry of the entire substrate in the vertical direction.

In some implementations, a via is provided in the third build-up layer group, so that the chips arranged in the first area and the second area are electrically connected through the via.

In some implementations, the at least one electrical chip further includes a first electrical chip, wherein the first electrical chip is disposed on a top surface of the core layer and is electrically connected to the optical chip via vias. Placing the optical chip in the second region of the substrate can improve the reliability of the optical chip and save packaging space.

In some implementations, the at least one electrical chip further includes a first electrical chip, wherein the first electrical chip is attached to the core layer, and the optical chip is attached to the core layer, and the first electrical chip and the optical chip are electrically connected via the core layer. By arranging the electrical chip and the optical chip together in the second region of the substrate, the interconnection performance between the optical chip and the electrical chip can be improved, thereby reducing overall power consumption.

In some implementations, the multi-chip further includes a first electrical chip, wherein the optical chip is attached to the core layer, the first electrical chip is located above the optical chip, and the optical chip is electrically connected to the first electrical chip. By stacking the optical chip and the electrical chip in the second region of the substrate, further space can be saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In some implementations, the at least one electrical chip further includes a first electrical chip, wherein the first electrical chip is attached to the core layer, and the optical chip is located above the first electrical chip, and the optical chip is electrically connected to the first electrical chip. By stacking the optical chip and the electrical chip in the second region of the substrate, further space can be saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In some implementations, the at least one electrical chip further includes a second electrical chip, which is disposed on a top surface of the fourth build-up layer group and electrically connected to the first electrical chip. Through the above solution, multiple chips can be interconnected in a package structure.

In some implementations, the optical chip is made of silicon, silicon nitride, indium phosphate, or indium phosphide, and the second region is made of silicon or silicon dioxide. This ensures that the thermal expansion coefficient of the second region matches that of the optical chip, avoiding the need for underfill glue between the optical chip and the second region and preventing glue from overflowing into microstructures such as undercuts in the optical chip, thereby improving the reliability of the optical chip.

Some implementations also include an airtight packaging device, within which the optical chip is located. This ensures proper operation of the optical chip when using materials sensitive to dust and moisture, such as indium phosphide. By placing the airtight device on the concave surface of the substrate, the optical chip can be hermetically sealed while also ensuring interconnection with other chips, potentially enabling applications at higher transmission rates.

In a second aspect, an optical module is provided, comprising an optoelectronic component for sending and/or receiving optical signals, wherein the optoelectronic component comprises the first aspect and any possible packaging structure thereof.

According to a third aspect, an optical communication system is provided, comprising an electronic device and the optical module according to the second aspect, wherein the electronic device is connected to the optical module.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a multi-chip packaging structure provided in an embodiment of the present application.

FIG2 is a schematic diagram of a substrate structure provided in an embodiment of the present application.

FIG3 is a schematic diagram of a multi-chip arrangement in a packaging structure provided in an embodiment of the present application.

FIG4 is a schematic diagram of another substrate structure provided in an embodiment of the present application.

FIG5 is a schematic diagram of a multi-chip arrangement in a packaging structure provided in an embodiment of the present application.

FIG6 is a schematic diagram of another packaging structure provided in an embodiment of the present application.

FIG7 is a schematic diagram of signal interaction between multiple chips in an optical module provided in an embodiment of the present application.

FIG8 is an optical communication system provided in an embodiment of the present application.

DETAILED DESCRIPTION

The technical solution in this application will be described below with reference to the accompanying drawings.

In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

In the description of the embodiments of the present application, the terms "upper", "lower", "vertical", "horizontal", etc. indicate orientations or positional relationships that are defined relative to the orientations or positions of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. They may change accordingly according to changes in the orientation of the components placed in the drawings, and therefore cannot be understood as limitations on the present application.

The terms "including" and "having" and any variations thereof in the embodiments of the present application shown below are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or apparatus.

In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. An embodiment or design described as "exemplary" or "for example" should not be construed as being more preferred or advantageous than other embodiments or designs. The use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner to facilitate understanding.

In the embodiments of the present application, the same reference numerals are used to represent the same component or the same part. In addition, the various parts in the drawings are not drawn to scale, and the sizes and dimensions of the parts shown in the drawings are only exemplary and should not be understood as limiting the present application.

It should be understood that in the present application, "electrical connection" can be understood as physical contact and electrical conduction between components, and can also be understood as a form of connection between different components in a circuit structure through physical lines such as substrate lines, pads or wires that can transmit electrical signals. In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "configuration", "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

Optical-to-electronic hybrid integration is a new optical technology that combines optical and electrical components to achieve seamless connectivity and interconnection between optical and electrical signals. Co-packaged optics (CPO) combines switch chips and optical engines in a single package, increasing interconnect density and meeting the demands of modern computing and applications, such as ultra-large bandwidth, low latency, and high flexibility.

Currently, optoelectronic co-packaging solutions mainly fall into three directions: 2D, 2.5D, and 3D. Among them, the 2D solution places multiple chips such as switch chips, electrical chips, and optical chips on a substrate. Although it is easy to package, under this solution, the substrate needs to bear the fan-out of the switch chip and use organic materials and other materials with a serious mismatch in thermal expansion coefficient with the optical chip, resulting in reliability risks in the packaging structure. The 2.5D solution further sets an interposer on the substrate and sets the optical chip on the interposer. Although it improves the reliability of the packaging structure, it does not eliminate the stress risk of the packaging structure. The 3D solution stacks multiple chips flip-chip together. Although it saves packaging space, it cannot solve the material mismatch problem between the optical chip and the substrate. As can be seen from the above, how to reduce the size of optoelectronic co-packaging and improve the reliability of the packaging structure is an urgent problem to be solved.

In view of the above problems, an embodiment of the present application provides a multi-chip packaging structure, which improves the reliability of the packaging structure while saving the common packaging space by setting a stress-adaptive surface for the optical chip separately in the substrate.

Figure 1 illustrates a multi-chip package structure provided by an embodiment of the present application. As shown in Figure 1 , the package structure includes a substrate 100 and multiple chips. The multiple chips are disposed on the top surface of the substrate, and the multiple chips include at least one electrical chip 140 and an optical chip 130.

The top surface of substrate 100 includes a first region 110 and a second region 120. The materials of first region 110 and second region 120 are conductive, and the material of first region 110 is different from the material of second region 120. First region 110 is used to accommodate an electrical chip 140 of at least one electrical chip, while the second region is configured with an optical chip 130. It should be understood that the term "configured" as used herein refers to the material of first region 110 being configured to correspond to the operational requirements of the electrical chip, and does not limit the placement of electrical chips on this surface.

In current integration schemes, the optical chip and the electrical chip are placed on the same surface. To simultaneously handle the work of multiple chips (e.g., fan-out of a dedicated integrated circuit), the substrate surface must be made of an organic material with a significant thermal expansion mismatch with the optical chip. In the technical solution of this application, two surfaces are provided in the substrate to distinguish the surfaces used to package the electrical chip and the optical chip in the packaging structure. One of the two surfaces is then provided based on the actual material of the optical chip. This reduces the risk of stress packaging, improves the reliability of the packaging structure, and saves packaging structure space.

In some implementations, the optical chip 130 is made of silicon, silicon nitride, indium phosphate, or indium phosphide. The second region 120 is made of silicon or silicon dioxide (also known as glass). This ensures that the thermal expansion coefficient of the second region matches that of the optical chip, avoiding the need for underfill glue between the optical chip and the second region and preventing glue from overflowing into microstructures such as undercuts in the optical chip, thereby improving the reliability of the optical chip.

In some implementations, the packaging structure further includes an airtight packaging device 150, and the optical chip 130 is located in the airtight packaging device 150. The airtight packaging device can be specifically an airtight box or a tube cap (TO can), etc., which is determined according to actual conditions. Thus, when the optical chip uses materials such as indium phosphide that are sensitive to dust and water vapor, the normal operation of the optical chip is guaranteed. By arranging the airtight device on the second area, it is possible to achieve airtight packaging of the optical chip while ensuring the interconnection between the optical chip and other chips, thereby improving the application possibility of the optical chip at higher transmission rates.

It should be understood that Figure 1 illustrates a scenario where the distance between the first region 110 and the bottom surface of the substrate 100 is greater than the distance between the second region 120 and the bottom surface of the substrate 100. In this scenario, the optical chip is specifically disposed in the second region of the substrate, further saving packaging space. Furthermore, the distance between the first region and the bottom surface of the substrate can also be equal to or greater than the distance between the second region and the bottom surface of the substrate, depending on actual circumstances.

The packaging structure of the present application is described below with reference to specific substrate examples in Figures 2 to 6 .

Figure 2 is a schematic diagram of a substrate structure provided in an embodiment of the present application. The substrate shown in Figure 2 can be a high-density packaging substrate. The number of substrate layers shown in the figure is 7-2-7. The actual number of layers in the substrate is determined based on actual conditions and is not limited by this application. As shown in Figure 2, the substrate includes a first buildup layer group 210, a core layer 220, a second buildup layer group 230, and an interposer layer 240.

The first build-up layer group 210 includes a plurality of stacked build-up layers, and the bottom surface of the first build-up layer group 210 forms the bottom surface of the substrate.

The core layer 220 is disposed on the top surface of the first buildup layer group 210 .

Second buildup group 230 includes a plurality of stacked buildup layers, disposed on top of core layer 220. It includes a first buildup layer 231, which is located at the bottom of second buildup group 230. The bottom surface of first buildup layer 231 is in contact with core layer 220. The top surface of first buildup layer 231 includes a third region and a fourth region. The third region is configured with the buildup layers of second buildup group 230, excluding first buildup layer 231. The fourth region is configured with interposer 240.

Second build-up layer group 230 includes second build-up layer 232 . Second build-up layer 232 is located on the top of second build-up layer group 230 . First region 250 includes the top surface of second build-up layer 232 . Second region 260 includes the top surface of the interposer.

In the substrate shown in Figure 2, a first region for arranging an electrical chip is formed by the built-up layers of the substrate itself. After a concave surface is hollowed out in the substrate, an interposer is embedded to form a second region for arranging an optical chip, thereby forming a substrate for optoelectronic hybrid integration. Figure 2 (a) specifically illustrates a case where, after the interposer is embedded, the distance between the second region and the bottom surface is smaller than the distance between the first region and the bottom surface. Figure 2 (b) illustrates a case where, after the interposer is embedded, the distance between the second region and the bottom surface is larger than the distance between the first region and the bottom surface.

The core layer (core) can be composed of an insulating material. The top and bottom surfaces of the core layer 220 are covered with a conductive medium, such as copper or other metals. The core layer 220 provides mechanical support and can also serve as a signal layer, power layer, or conductive layer. The thickness of the core layer 220 can be greater than that of the buildup layers. The material of the core layer 220 can be an organic material, such as a solid resin.

The build-up layers in the first build-up group 210 and the second build-up group 230 are manufactured using a build-up process, which involves coating an insulating dielectric and then copper plating or other processes to form conductive wires and connection holes, accumulating layer by layer to form multiple layers. That is, the interior of the build-up layer is an insulating dielectric, and the top and bottom surfaces are covered with conductive dielectric portions. The build-up layers in the first build-up group 210 and the second build-up group 230 can be made of the same material. Furthermore, the build-up layers in the first build-up group 210 and the second build-up group 230 can have the same thickness. The build-up layer material can be an organic material, such as a solid resin. The top surface of the build-up layer at the top of the second build-up group 230 can be provided with pads and traces. The interiors of the first build-up group 210 and the second build-up group 230 can be provided with traces, vias, etc.

The interposer can serve as an intermediary for electrically connecting the chip disposed in the second region 260 with other chips. The top and bottom surfaces of the interposer 240 are covered with a conductive medium, such as copper or other metals. Depending on actual needs, the interposer 240 can be provided with pads and circuits on its top surface, and circuits can be provided within it. The interposer 240 can be made of a material that matches the thermal expansion coefficient of the optical chip. For example, the interposer 240 can be silicon or silicon dioxide. Silicon dioxide can also specifically refer to glass.

In some implementations, the total thickness of the first build-up layer group 210 is the same as the total thickness of the second build-up layer group 230. Thus, the symmetry of the substrate in the vertical direction ensures stress balance of the substrate and prevents warping of the substrate.

In some implementations, the second buildup group 230 includes at least one third buildup layer, which covers the third area of the top surface of the interposer 240. A via 270 is provided in at least one third buildup layer, and the projection of the via 270 on the top surface of the interposer 240 is located in the third area. The via 270 runs through all third buildups in at least one third buildup layer. As a result, the chips configured in the first area 250 and the second area 260 are electrically connected through the via 270. By providing a buildup layer covering the interposer in the second buildup group and correspondingly providing vias, the transmission signal integrity and anti-interference performance between the chip configured in the first area and the chip configured in the second area can be improved. In addition, the chips configured in the first area and the second area can also be electrically connected through leads or other methods, and this application does not limit this.

FIG3 is a schematic diagram of a multi-chip arrangement in a packaging structure provided by an embodiment of the present application. In the cases of (a), (b), (c), and (d) in FIG3 , the multiple chips in the packaging structure specifically include a first electrical chip 310 and an optical chip 320. The optical chip 320 can be a photonic integrated circuit (PIC), and the first electrical chip 310 can be an electronic integrated circuit (EIC). In the cases of (e), (f), (g), and (h) in FIG3 , the multiple chips in the packaging structure specifically include an optical chip 320, a first electrical chip 310, and a second electrical chip 360. The optical chip 320 can be a photonic integrated circuit (PIC), the first electrical chip 310 can be an electronic integrated circuit (EIC), and the second electrical chip 360 can be an application-specific integrated circuit (ASIC) or a digital signal processing chip (DSP).

In the case shown in Figure 3(a), the first electrical chip 310 is disposed on the top surface of the second build-up layer group 340 and is electrically connected to the optical chip 320 through vias 350. By placing the optical chip in the second region of the substrate, the reliability of the optical chip can be improved and packaging space can be saved.

In the case shown in (b) of Figure 3, the first electrical chip 310 is attached to the interposer 330, and the optical chip 320 is attached to the interposer 330, and the first electrical chip 310 and the optical chip 320 are electrically connected through the interposer 330. In some implementations, the side of the first electrical chip 310 and the optical chip 320 attached to the interposer 330 may be provided with bumps, bumps, or studs, and connected to the pads and/or lines of the interposer 330 through the bumps, bumps, or studs. In some implementations, the first electrical chip 310 and the optical chip 320 are connected to the pads and/or lines of the interposer 330 through leads. In addition, the first electrical chip 310 and the optical chip 320 may also be electrically connected in other ways, which is not limited in this application. By arranging the electrical chip and the optical chip together in the second area of the substrate, the interconnection performance between the optical chip and the electrical chip can be improved and the overall power consumption can be reduced.

In the case shown in (c) of Figure 3, the optical chip 320 is attached to the interposer 330, the first electrical chip 310 is located on the optical chip 320, and the optical chip 320 is electrically connected to the first electrical chip 310. In some implementations, the side of the first electrical chip 310 attached to the optical chip 320 is provided with bumps, bumps, convex columns, etc., and the first electrical chip 310 is flipped on the optical chip 320. In some implementations, another substrate is provided between the first electrical chip 310 and the optical chip 320. The first electrical chip 310 and the optical chip 320 are electrically connected through the other substrate. In addition, the first electrical chip 310 and the optical chip 320 can also be electrically connected in other ways, which is not limited in this application. By stacking the optical chip and the electrical chip in the second area of the substrate, space can be further saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In the case shown in (d) of Figure 3, the first electrical chip 310 is attached to the interposer 330, the optical chip 320 is located on the first electrical chip 310, and the optical chip 320 is electrically connected to the first electrical chip 310. In some implementations, the side of the optical chip 320 attached to the electrical chip is provided with bumps, bumps, convex columns, etc., and the optical chip 320 is flipped on the electrical chip. In some implementations, another substrate is provided between the optical chip 320 and the first electrical chip 310. The optical chip 320 and the first electrical chip 310 are electrically connected through another substrate. In addition, the optical chip 320 and the first electrical chip 310 can also be electrically connected in other ways, which is not limited in this application. By stacking the optical chip and the electrical chip in the second area of the substrate, space can be further saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In the case of Figure 3 (e), the second electrical chip 360 is disposed on the top surface of the second build-up layer 340. The first electrical chip 310 and the second electrical chip 360 are electrically connected via pads, traces, and vias 350 disposed on the top surface of the second build-up layer 340. The remaining configuration of the first electrical chip 310 and the optical chip 320 is similar to that of Figure 3 (a) and will not be further described here. This solution enables the interconnection of multiple chips within a package structure.

In the case of Figure 3(f), the second electrical chip 360 is disposed on the top surface of the second build-up layer 340. The first electrical chip 310 and the second electrical chip 360 are electrically connected via pads, traces, and vias 350 disposed on the top surface of the second build-up layer 340. The remaining configuration of the first electrical chip 310 and the optical chip 320 is similar to that of Figure 3(b) and will not be further described here. This solution enables the interconnection of multiple chips within a package structure.

In the case of (g) in Figure 3, the second electrical chip 360 is arranged on the top surface of the second stacking group 340. A through hole 370 is provided in the optical chip 320, which can be a through silicon via (TGV) or a through glass via (TSV). The first electrical chip 310 and the second electrical chip 360 are electrically connected through the pads, circuits, vias 350, interposer 330, and through holes 370 provided on the top surface of the second stacking group 340. The configuration scheme of the remaining first electrical chip 310 and optical chip 320 is similar to that of (c) in Figure 3 and will not be repeated here. Through the above scheme, the interconnection of multiple chips in the packaging structure can be achieved.

In the case of Figure 3 (h), the second electrical chip 360 is disposed on the top surface of the second build-up layer 340. The first electrical chip 310 and the second electrical chip 360 are electrically connected via pads, traces, and vias 350 provided on the top surface of the second build-up layer 340. The remaining configuration of the first electrical chip 310 and the optical chip 320 is similar to that of Figure 3 (d) and will not be further described here. This solution enables the interconnection of multiple chips within a package structure.

Figure 4 is a schematic diagram of another substrate structure provided by an embodiment of the present application. The substrate shown in Figure 4 can be a high-density packaging substrate. The number of substrate layers shown in the figure is 7-2-7. The actual number of layers in the substrate is determined based on actual conditions and is not limited by this application. As shown in Figure 4, the substrate includes a third buildup layer group 410, a core layer 420, and a fourth buildup layer group 430.

The third build-up layer group 410 includes a plurality of stacked build-up layers, and the bottom surface of the third build-up layer group 410 forms the bottom surface of the substrate.

The core layer 420 is disposed on the top surface of the third buildup layer group 410 .

The top surface of core layer 420 includes a fifth region and a sixth region. The fifth region is provided with fourth buildup group 430 , which includes a plurality of stacked buildup layers. Core layer 420 is larger than the buildup layers in fourth buildup group 430 .

The first region 450 includes the top surface of the fourth build-up layer group 430 , and the second region 460 includes the sixth region.

In the substrate shown in FIG4 , a first area for configuring an electrical chip is formed by the buildup layer of the substrate itself, and after a second area is dug out in the substrate, a second area for configuring an optical chip is formed using a core layer, thereby forming a substrate for optoelectronic hybrid integration.

The core layer 420 may be composed of an insulating material. The top and bottom surfaces of the core layer 420 are covered with a conductive medium, such as copper or other metals. The core layer 420 is used to provide mechanical support while also serving as a signal layer, a power supply layer, or a conductive layer. The core layer 420 may be provided with a pad or a dropout in its sixth region, or a circuit may be provided inside the core layer 420, depending on actual needs. The thickness of the core layer 420 may be greater than that of the buildup layer. The core layer 420 may be made of a material that is compatible with the thermal expansion coefficient of the optical chip. For example, the core layer 420 may be silicon or silicon dioxide. Silicon dioxide may also specifically refer to glass.

The layers in the third and fourth build-up groups 410 and 430 are manufactured using a build-up process, which involves applying an insulating dielectric and then copper plating or other processes to form conductive traces and connection holes. This build-up process creates multiple layers. Specifically, the interior of the layers is an insulating dielectric, while the top and bottom surfaces are covered with a conductive dielectric. The layers in the third and fourth build-up groups 410 and 430 can be made of the same material. Furthermore, the layers in the third and fourth build-up groups 410 and 430 can have the same thickness. The layers can be made of organic materials, such as solid resins.

In some implementations, the total thickness of the third build-up layer group 410 is the same as the total thickness of the fourth build-up layer group 430. Thus, the symmetry of the substrate in the vertical direction ensures stress balance of the substrate and prevents warping of the substrate.

In some implementations, a via 440 is provided in the third build-up layer group 410. The via 440 extends through the third build-up layer group 410. The via 440 may be located on a side of the third build-up layer group 410 adjacent to the second region 460. This allows for electrical connection between the chips disposed in the first region 450 and the second region 460 through the via 440.

Figure 5 is a schematic diagram of a multi-chip arrangement in a packaging structure provided by an embodiment of the present application. In the cases of (a), (b), (c) and (d) in Figure 5, the multiple chips in the packaging structure specifically include a first electrical chip 510 and an optical chip 520. Among them, the optical chip 520 can be a photonic integrated chip, and the first electrical chip 510 can be an electronic integrated chip. In the cases of (e), (f), (g) and (h) in Figure 5, the multiple chips in the packaging structure specifically include an optical chip 520, a first electrical chip 510 and a second electrical chip 570. Among them, the optical chip 520 can be a photonic integrated chip, the first electrical chip 510 can be an electronic integrated chip, and the second electrical chip 570 can be a dedicated integrated chip, or a digital signal processing chip.

In the case shown in Figure 5(a), the first electrical chip 510 is disposed on the top surface of the fourth build-up layer group 530 and is electrically connected to the optical chip 520 through vias 560. By placing the optical chip in the second region of the substrate, the operating reliability of the optical chip can be improved and packaging space can be saved.

In the case shown in FIG5(b), the first electrical chip 510 is attached to the top surface of the core layer 550 (which can also be understood as the sixth region), and the optical chip 520 is attached to the top surface of the core layer 550. The first electrical chip 510 and the optical chip 520 are electrically connected via pads and circuits provided on the top surface of the core layer 550. In some implementations, the side of the first electrical chip 510 and the optical chip 520 that is attached to the top surface of the core layer 550 may be provided with bumps, blocks, or columns, and connected to the pads and circuits on the top surface of the core layer 550 via the bumps, blocks, or columns. In some implementations, the first electrical chip 510 and the optical chip 520 are connected to the pads and circuits on the top surface of the core layer 550 via wires. In addition, the first electrical chip 510 and the optical chip 520 may also be electrically connected via other methods, which are not limited in this application. By arranging the electrical chip and the optical chip together in the second area of the substrate, the interconnection performance between the optical chip and the electrical chip can be improved and the overall power consumption can be reduced.

In the case shown in (c) of Figure 5 , the optical chip 520 is attached to the top surface of the core layer 550 (which can also be understood as the sixth area), the first electrical chip 510 is located above the optical chip 520, and the optical chip 520 is electrically connected to the first electrical chip 510. In some implementations, the side of the first electrical chip 510 that is attached to the optical chip 520 is provided with bumps, bumps, convex columns, etc., and the first electrical chip 510 is flip-chip mounted on the optical chip 520. In some implementations, another substrate is provided between the first electrical chip 510 and the optical chip 520. The first electrical chip 510 and the optical chip 520 are electrically connected through the other substrate. In addition, the first electrical chip 510 and the optical chip 520 can also be electrically connected in other ways, which is not limited in this application. By stacking the optical chip and the electrical chip in the second area of the substrate, space can be further saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In the case shown in (d) of Figure 5 , the first electrical chip 510 is attached to the top surface of the core layer 550 (which can also be understood as the sixth area), the optical chip 520 is located on the first electrical chip 510, and the optical chip 520 is electrically connected to the first electrical chip 510. In some implementations, the side of the optical chip 520 that is attached to the electrical chip is provided with bumps, bumps, convex columns, etc., and the optical chip 520 is flipped on the electrical chip. In some implementations, another substrate is provided between the optical chip 520 and the first electrical chip 510. The optical chip 520 and the first electrical chip 510 are electrically connected through another substrate. In addition, the optical chip 520 and the first electrical chip 510 can also be electrically connected in other ways, which is not limited in this application. By stacking the optical chip and the electrical chip in the second area of the substrate, space can be further saved and the interconnection performance between the optical chip and the electrical chip can be improved.

In the case of Figure 5(e), the second electrical chip 570 is disposed on the top surface of the fourth buildup layer 530. The first electrical chip 510 and the second electrical chip 570 are electrically connected via pads and circuits disposed on the top surface of the fourth buildup layer 530. The remaining configuration of the first electrical chip 510 and the optical chip 520 is similar to that of Figure 5(a) and will not be further described here. This solution enables the interconnection of multiple chips within a package structure.

In the case of Figure 5(f), the second electrical chip 570 is disposed on the top surface of the fourth buildup layer 530. The first electrical chip 510 and the second electrical chip 570 are electrically connected via pads, traces, and vias 560 disposed on the top surface of the fourth buildup layer 530. The remaining configuration of the first electrical chip 510 and the optical chip 520 is similar to that of Figure 5(b) and will not be further described here. This solution enables the interconnection of multiple chips within a package structure.

In the case of (g) in Figure 5, the second electrical chip 570 is arranged on the top surface of the fourth stacking group 530 (which can also be understood as the sixth area). A through hole 580 is provided in the optical chip 520. The first electrical chip 510 and the second electrical chip 570 are electrically connected through the pads and lines provided on the top surface of the fourth stacking group 530, the vias 560, the pads and lines provided on the top surface of the interposer, and the through holes 580. The configuration scheme of the remaining first electrical chips 510 and optical chips 520 is similar to that of (c) in Figure 5 and will not be repeated here. Through the above scheme, the interconnection of multiple chips in the packaging structure can be achieved.

In the case of Figure 5 (h), the second electrical chip 570 is disposed on the top surface of the fourth build-up layer group 530. The first electrical chip 510 and the second electrical chip 570 are electrically connected through the top surface of the fourth build-up layer group 530 and the via 560. The remaining configuration of the first electrical chip 510 and the optical chip 520 is similar to that of Figure 5 (d) and will not be further described here. Through the above scheme, multiple chips can be interconnected in a package structure.

Figure 6 is a schematic diagram of another packaging structure provided by an embodiment of the present application. When multiple chips are configured in the packaging structure, a heat sink, a cooler, a sealing device, etc. can be provided in the packaging structure according to actual configuration requirements.

As shown in (a) of Figure 6, taking the situation in (f) of Figure 3 as an example, a heat sink 611 can also be provided on the first electrical chip 610 to dissipate heat for the first electrical chip. In addition, a refrigerator 621 can be provided on the optical chip 620 to cool the optical chip. A capacitor 630 can also be provided in the packaging structure to improve the transmission performance of the signal. The bottom of the second electrical chip 640 can be filled with glue to achieve stress balance and improve the reliability of the packaging structure. A sealing device 650 can also be provided in the packaging structure. The sealing device 650 can be made of glass material to achieve local airtight packaging.

In addition, FIG6(b) shows another packaging structure configuration scheme. For example, FIG5(f) or other packaging structures can be configured with reference to FIG6(a). The specific configuration of the heat sink 611, the cooler 621, the capacitor 630, and the sealing device 650 is similar to that described above and will not be repeated here.

In addition, an embodiment of the present application provides an optical module. The optical module can be in an optical transmission form, an optical reception form, an optical transceiver form, a multi-transmit and multi-receiver form, etc. The optical module includes an optoelectronic component, which is used to send and/or receive optical signals. The packaging structure provided in the embodiment of the present application can be used to form an optoelectronic component. According to actual needs, optical devices such as lasers, optical modulators, beam splitters, couplers, optical detectors, coupling prisms, etc. can also be set in the optoelectronic component to realize the function of sending and receiving optical signals. In addition, according to actual needs, electrical devices such as resistors, capacitors, amplifiers, processors, and drivers can also be set in the packaging structure to realize the processing process in the conversion process between optical signals and electrical signals. In addition, the multiple chips in the packaging structure can also include clock data recovery chips, driver chips, laser chips, detector chips, etc., which are determined according to actual conditions. In addition, multiplexing/demultiplexing devices can also be set according to the actual type of optical module.

FIG7 is a schematic diagram of signal interaction between multiple chips in an optical module provided in an embodiment of the present application.

The scenario shown in Figure 7(a) is applicable to scenarios such as linear drive pluggable optics (LPO). Optical chip 710 can be used to receive a first optical signal and convert it into a first electrical signal. First electrical chip 720 can be used to amplify the first electrical signal. Alternatively, first electrical chip 720 can be used to receive and amplify a second electrical signal, and optical chip 710 can receive the amplified second electrical signal and convert it into a second optical signal for output.

As shown in Figure 7(b), optical chip 710 is used to receive a third optical signal and convert it into a third electrical signal. First electrical chip 720 is used to amplify the third electrical signal. Second electrical chip 730 is used to process the amplified third electrical signal into a first data signal and then forward and exchange the data. Alternatively, second electrical chip 730 is used to receive and process the second data signal and convert it into a fourth electrical signal, while first electrical chip 720 is used to amplify the fourth electrical signal. Optical chip 710 is used to receive the amplified fourth electrical signal and convert it into a fourth optical signal for output.

FIG8 is an optical communication system provided by an embodiment of the present application. As shown in FIG8 , the optical system may include an electronic device and an optical module as shown in FIG7 .

The electronic device may include an optical switch, a fiber optic router, or a fiber optic network card. The electronic device may include multiple ports, each corresponding to an optical transmission channel. The ports are connected to optical modules, thereby enabling multi-channel, high-speed optical signal transmission. An optical switch can be used to exchange data between multiple optical transmission channels. A fiber optic router can convert signal light into data signals and forward and route the data signals. A fiber optic network card can be used in Ethernet networks to connect computers to optical fibers.

In addition, the electronic equipment may also be optical access equipment, optical transmission equipment, optical terminal equipment, etc., specifically optical modems, routers, access points, switches, optical line terminals (OLT), optical network units (ONU), and optical distribution networks (ODN), etc. The applicable network may specifically be a passive optical network (PON), such as the next-generation PON (NG-PON), NG-PON1, NG-PON2, gigabit-capable PON (GPON), wavelength-division multiplexing (WDM) PON, time-and wavelength-division multiplexing (TWDM) PON, point-to-point (P2P) WDM PON (P2P-WDM PON), etc.

Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program codes.

The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims (21)

A multi-chip packaging structure, characterized by comprising a substrate and a plurality of chips, wherein: The plurality of chips are arranged on the substrate, and the plurality of chips include at least one electrical chip and an optical chip; The top surface of the substrate includes a first area and a second area, the first area is used to configure the electrical chip of the at least one electrical chip, the second area is configured with the optical chip, and the material of the first area is different from that of the second area. The package structure according to claim 1, wherein the substrate comprises a first build-up layer group, a core layer, a second build-up layer group, and an interposer, wherein: The first build-up layer group includes a plurality of stacked build-up layers, and the bottom surface of the first build-up layer group forms the bottom surface of the substrate; The core layer is disposed on the top surface of the first buildup layer group; The second buildup group includes a plurality of stacked buildup layers, the second buildup group is disposed on the top surface of the core layer, the second buildup group includes a first buildup layer, the first buildup layer is located at the bottom of the second buildup group, the bottom surface of the first buildup layer is in contact with the core layer, the top surface of the first buildup layer includes a third region and a fourth region, the third region is configured with buildup layers in the second buildup group except the first buildup layer, and the fourth region is configured with the intermediate layer; The second build-up layer group includes a second build-up layer, the second build-up layer is located on top of the second build-up layer group, the first region includes a top surface of the second build-up layer, and the second region includes a top surface of the interposer. The package structure according to claim 2, wherein the total thickness of the first build-up layer group is the same as the total thickness of the second build-up layer group. The packaging structure according to claim 2 or 3, wherein: The second build-up layer group includes at least one third build-up layer, wherein the third build-up layer covers a third region of the top surface of the interposer; A via is provided in the at least one third build-up layer, and a projection of the via on the top surface of the interposer is located in the third region. The packaging structure according to claim 4 is characterized in that the at least one electrical chip includes a first electrical chip, the first electrical chip is arranged on the top surface of the second stacking group, and the first electrical chip is electrically connected to the optical chip through the via. The packaging structure according to any one of claims 2 to 4, wherein the at least one electrical chip comprises a first electrical chip, wherein: The first electrical chip is attached to the interposer, and the optical chip is attached to the interposer. The first electrical chip and the optical chip are electrically connected through the interposer. The packaging structure according to any one of claims 2 to 4, wherein the at least one electrical chip comprises a first electrical chip, wherein: The optical chip is attached to the intermediate layer, the first electrical chip is located on the optical chip, and the optical chip is electrically connected to the first electrical chip. The packaging structure according to any one of claims 2 to 4, wherein the multi-chip further comprises a first electrical chip, wherein: The first electrical chip is attached to the intermediate layer, the optical chip is located on the first electrical chip, and the optical chip is electrically connected to the first electrical chip. The packaging structure according to any one of claims 6 to 8 is characterized in that the at least one electric chip further includes a second electric chip, the second electric chip is arranged on the top surface of the second stacking group, and the second electric chip is electrically connected to the first electric chip. The package structure according to claim 1, wherein the substrate comprises a third build-up layer group, a core layer, and a fourth build-up layer group, wherein: The third build-up layer group includes a plurality of stacked build-up layers, and the bottom surface of the third build-up layer group forms the bottom surface of the substrate; The core layer is arranged on the top surface of the third buildup layer group; The top surface of the core layer includes a fifth region and a sixth region, the fifth region is provided with the fourth buildup layer group, and the fourth buildup layer group includes a plurality of stacked buildup layers; The first region includes the top surface of the fourth build-up layer group, and the second region includes the sixth region. The package structure according to claim 10, wherein the total thickness of the third build-up group is the same as the total thickness of the fourth build-up group. The packaging structure according to claim 10 or 11, characterized in that a via is provided in the third build-up layer group. The packaging structure according to claim 12 is characterized in that the at least one electric chip further includes a first electric chip, wherein: the first electric chip is arranged on the top surface of the core layer, and the first electric chip is electrically connected to the optical chip through the via. The packaging structure according to any one of claims 10 to 12, characterized in that the at least one electrical chip further comprises a first electrical chip, wherein: The first electrical chip is attached to the core layer, and the optical chip is attached to the core layer. The first electrical chip and the optical chip are electrically connected through the core layer. The packaging structure according to any one of claims 10 to 12, wherein the multi-chip further comprises a first electrical chip, wherein: The optical chip is attached to the core layer, the first electrical chip is located on the optical chip, and the optical chip is electrically connected to the first electrical chip. The packaging structure according to any one of claims 10 to 12, characterized in that the at least one electrical chip further comprises a first electrical chip, wherein: The first electrical chip is attached to the core layer, the optical chip is located on the first electrical chip, and the optical chip is electrically connected to the first electrical chip. The packaging structure according to any one of claims 14 to 16 is characterized in that the at least one electric chip further includes a second electric chip, the second electric chip is arranged on the top surface of the fourth build-up group, and the second electric chip is electrically connected to the first electric chip. The packaging structure according to any one of claims 1 to 17, wherein: The material of the optical chip is any one of silicon, silicon nitride, indium phosphate or indium phosphide; The material of the second region is either silicon or silicon dioxide. The packaging structure according to any one of claims 1 to 18 is characterized in that it further includes an airtight packaging device, and the optical chip is located in the airtight packaging device. An optical module, characterized in that it includes an optoelectronic component, wherein the optoelectronic component is used to send and/or receive optical signals, and the optoelectronic component includes the packaging structure according to any one of claims 1 to 19. An optical communication system, comprising an electronic device and the optical module according to claim 20, wherein the electronic device is connected to the optical module.