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WO2025171355A1 - Ensembles de refroidissement intégrés pour boîtier de dispositif avancé et leurs procédés de fabrication - Google Patents

Ensembles de refroidissement intégrés pour boîtier de dispositif avancé et leurs procédés de fabrication

Info

Publication number
WO2025171355A1
WO2025171355A1 PCT/US2025/015138 US2025015138W WO2025171355A1 WO 2025171355 A1 WO2025171355 A1 WO 2025171355A1 US 2025015138 W US2025015138 W US 2025015138W WO 2025171355 A1 WO2025171355 A1 WO 2025171355A1
Authority
WO
WIPO (PCT)
Prior art keywords
cold plate
semiconductor device
package
adhesive
device package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/US2025/015138
Other languages
English (en)
Inventor
Belgacem Haba
Ron Zhang
Bongsub LEE
Kyong-Mo Bang
Suhail Jaan Sadiq
Thomas Workman
Rajesh Katkar
Cyprian Emeka Uzoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Technologies LLC
Original Assignee
Adeia Semiconductor Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/908,493 external-priority patent/US20250253206A1/en
Application filed by Adeia Semiconductor Technologies LLC filed Critical Adeia Semiconductor Technologies LLC
Publication of WO2025171355A1 publication Critical patent/WO2025171355A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler

Definitions

  • the combined thermal resistance of (i) the thermal resistance of interfacial boundary regions between a TIM(s) and the chip and/or the heat dissipation device(s), and (ii) the thermal resistance of a thermal interface material(s) itself can inhibit heat transfer from the chip to the heat dissipation devices, undesirably reducing the cooling efficiency of the cooling system.
  • a first general aspect includes, a device package including an integrated cooling assembly.
  • the integrated cooling assembly includes a semiconductor portion and a metal cold plate attached to the semiconductor portion.
  • the semiconductor portion includes a semiconductor device.
  • the metal cold plate includes a base surface spaced apart from the semiconductor device to collectively define a coolant channel therebetween.
  • the metal cold plate further includes a side wall extending downwardly from the base surface to define a perimeter of the coolant channel.
  • the metal cold plate further includes a plurality of cavity dividers extending downwardly from the base surface towards the semiconductor device.
  • Implementations of the device package may include one or more of the following features.
  • the cavity dividers may be attached to the semiconductor device using adhesive.
  • Implementations of the device package may include one or more of the following features.
  • the semiconductor device may be disposed on a substrate.
  • the side wall of the metal cold plate may extend downwardly from the base surface to the substrate.
  • the side wall may be attached to the substrate using adhesive.
  • Implementations of the device package may include one or more of the following features.
  • the metal cover may be attached to the manifold using adhesive along edges of the metal cover.
  • the cavity dividers may be attached to a surface of the metal cover using adhesive.
  • a fourth general aspect includes a method of manufacturing the device package of the second general aspect. The method including attaching the manifold to a substrate including the semiconductor device to form the integrated cooling assembly, wherein the integrated cooling assembly includes a cooling channel.
  • FIG. 2A is a schematic plan view of an example of a system panel, in accordance with embodiments of the present disclosure
  • FIG. 2B is a schematic partial sectional side view of a device package mounted on a PCB, in accordance with embodiments of the present disclosure
  • FIG. 2C is a schematic exploded isometric view of the device package in FIG. 2B, in accordance with some embodiments of the disclosure.
  • FIGs. 2E and 2F are schematic sectional views of the device package of FIG. 2C, in accordance with some embodiments of the disclosure.
  • FIG. 2G is a schematic exploded isometric view of the device package in FIG. 2B;
  • FIG. 2H is a schematic sectional view of an example device package, in accordance with embodiments of the present disclosure, that may be used with the system panel;
  • FIG. 21 is a schematic sectional view of an integrated cooling assembly of the device package, in accordance with embodiments of the present disclosure;
  • FIG. 3 A is a schematic top view and sectional views of an integrated cooling assembly, in accordance with some embodiments of the disclosure.
  • FIGs. 3B and 3C are schematic sectional views of examples of the integrated cooling assembly of FIG. 3 A, in accordance with some embodiments of the disclosure.
  • FIG. 4 is schematic sectional views of an example of an integrated cooling assembly, in accordance with some embodiments of the disclosure.
  • FIGs. 5B-5D are schematic sectional views of examples of the device package of FIG. 5 A, in accordance with some embodiments of the disclosure.
  • FIG. 6A is a schematic exploded isometric view of a device package, in accordance with some embodiments of the disclosure.
  • FIGs. 6B and 6C are schematic sectional views of examples of the device package of FIG. 6A, in accordance with some embodiments of the disclosure.
  • FIGs. 7A-7B show example methods that can be used to manufacture the integrated cooling assemblies described herein;
  • Embodiments herein provide for integrated cooling assemblies embedded within a device package.
  • the integrated cooling assemblies have an elegant design which minimizes or reduces the system thermal resistance, reduces the complexity of integrated cooling assembly manufacturing and reduces the overall manufacturing costs of such. Manufacturing efficiency is improved by forming cavity dividers in a metal cold plate (or in a molding material having a metal cover attached thereto) to define plural cavity coolant channels through which coolant fluid flows in order to remove heat from a surface of a semiconductor device.
  • the term “substrate” means and includes any workpiece, wafer, or article that provides a base material or supporting surface from which or upon which components, elements, devices, assemblies, modules, systems, or features of the heatgenerating devices, packaging components, and cooling assembly components described herein may be formed or mounted.
  • substrate also includes semiconductor substrates that provide a supporting material upon which elements of a semiconductor device are fabricated or attached, and any material layers, features, and/or electronic devices formed thereon, therein, or therethrough. Examples of substrate material that may be used in applications that generate high thermal density include, but are not limited to, Si, GaN, SiC, InP, GaP, InGaN, AlGalnP, AlGaAs, etc.
  • the semiconductor substrates herein generally have a “device side,” e.g., the side on which semiconductor device elements are fabricated, such as transistors, resistors, and capacitors, and a “backside” that is opposite the device side.
  • the term “active side” should be understood to include a surface of the device side of the substrate and may include the device side surface of the semiconductor substrate and/or a surface of any material layer, device element, or feature formed thereon or extending outwardly therefrom, and/or any openings formed therein.
  • the material(s) that forms the active side may change depending on the stage of device fabrication and assembly.
  • direct bonding includes the bonding of a single material on the first of the two or more elements and a single material on a second one of the two or more elements, where the single material on the different elements may or may not be the same. For example, bonding a layer of one inorganic dielectric (e.g., silicon oxide) to another layer of the same or different inorganic dielectric.
  • inorganic dielectric e.g., silicon oxide
  • the cold plate is formed with recessed surfaces that define one or more fluid cavities (e.g., coolant channel(s), coolant channel volume(s), or coolant chamber volume(s)) between the cold plate and the semiconductor device.
  • each fluid cavity may be defined by cavity dividers and/or sidewalls of the cold plate.
  • cavity dividers may be spaced apart from each other and extend laterally between opposing cold plate sidewalls (e.g., in one direction between a first pair of opposing cold plate sidewalls, or in two directions between orthogonal pairs of opposing cold plate sidewalls).
  • the cavity dividers and the cold plate sidewalls may collectively define adjacent fluid cavities therebetween.
  • a more thermally conductive molding material and/or a higher loading of the thermally conductive particles in the molding material may improve the thermal properties of the mold matrix and efficiency of the cooling system.
  • the cold plate may be attached to the semiconductor portion or a substrate on which the semiconductor device is disposed on, by use of a sealing material layer or adhesive 242 or adhesive 333, or adhesive 433, or adhesive 436.
  • the adhesive is a compliant adhesive layer.
  • thermohydraulic and heat transfer properties will alter the temperatures where phase change occurs, as well as meeting design temperature and pressure conditions for the component being cooled or warmed and the thermal solution being deployed. Additionally, multiple combinations of the fluid phases may be employed in various hybrid configurations to meet the particular cooling or warming needs of a respective implementation and still be within the scope of the contemplated embodiments.
  • the volume concentration of these micro or nanoparticles may be less than 1%, less than 0.2%, or less than 0.05%. Depending upon the liquid and mi cro/nanop article type chosen for the cooling fluid, higher volume concentrations of 10% or less, 5% or less, or 2% or less may be used.
  • the cooling fluids may also contain small amounts of glycol or glycols (e.g. propylene glycol, ethylene glycol etc.) to reduce frictional shear stress and drag coefficient in the cooling fluid within the integrated cooling assembly.
  • glycol or glycols e.g. propylene glycol, ethylene glycol etc.
  • the availability of different base fluids e.g., water, ethylene glycol, mineral or other stable oils, etc.
  • different nanomaterials provide a variety of nanomaterial options for nanofluid solutions to be used in the various embodiments.
  • nanomaterial option groups such as aforementioned metals (e.g., Cu, Ag, Fe, Au, etc.), metal oxides (e.g., TiCh, AI2O3, CuO, etc.), carbons (e.g. CNTS, graphene, diamond, graphite. . .etc.), or a mixture of different types of nanomaterials.
  • Metal nanoparticles Cu, Ag, Au
  • metal oxide nanoparticles AI2O3, TiC>2, CuO
  • carbon-based nanoparticles are commonly employed elements.
  • Silicon oxide nanoparticles may also be used.
  • Using cooling fluids with micro and/or nanoparticles when practicing the various embodiments disclosed herein can result in increased heat removal efficiencies and effectiveness.
  • the architectures and embodiments disclosed herein can be used where the indirect thermal solutions supporting them are repurposed or operated in a hybrid configuration to provide warming fluids or heat transfer media to accomplish the warm-up or heat-up scenario.
  • These scenarios are controlled by systems not shown here to bring temperatures up at a speed or timing that enables the materials to avoid the excessive thermal expansion or unequal thermal expansion that may occur among the materials of the semiconductor or packaging being serviced by the thermal solution. Once the component or packaging is brought up into the normal operating range, it can be safely started and brought to a useful operational state.
  • each coolant chamber volume and/or coolant channel may be connected between a separate inlet opening and a separate outlet opening.
  • the coolant fluid may be directed to the separate inlet openings and from the separate outlet openings using a manifold disposed above the openings in the Z-axis direction.
  • a cross-section of the coolant chamber volume(s) and/or coolant channel(s) in the Y- Z plane is wide enough to allow for a pressure drop of 0-20 psi, 3-15 psi, or 4-10 psi.
  • FIG. 2H is a schematic sectional view in the Y-Z plane of the integrated cooling assembly 213.
  • the cold plate 207 comprises a patterned side that faces towards the semiconductor device 204 and an opposite side that faces towards the package cover 208 (not shown).
  • the patterned side comprises a coolant chamber volume having plural coolant channels 211, which extend laterally between the inlet and outlet openings of the cold plate 207.
  • Each coolant channel 211 comprises cavity sidewalls that define a corresponding coolant channel 211.
  • Portions of the cold plate 207 between the cavity sidewalls form the support features 207D (e.g., cavity dividers 207D).
  • arrows 228A and 228B illustrate two different heat transfer paths in the integrated cooling assembly 213.
  • a first heat transfer path illustrated by arrow 228B shows heat generated by the semiconductor device 204 transferring directly from the semiconductor material of the semiconductor device 204 to coolant fluid flowing through the cold plate 207.
  • a second heat transfer path illustrated by arrows 228A shows heat generated by the semiconductor device 204 being transferred from semiconductor material (e.g., silicon material) of the semiconductor device 204 to adhesive 242 to the cold plate 207 structure, propagated throughout the material of the cold plate 207 structure (shown as dashed lines), and being transferring into coolant fluid flowing through the cold plate 207.
  • semiconductor material e.g., silicon material
  • the CTEs of the cold plate 207, the substrate 202, and/or the semiconductor device 204 are matched so that the CTE of the substrate 202 and/or the semiconductor device 204 is within about +/- 20% or less of the CTE of the cold plate 207, such as within +/- 15% or less, within +/- 10% or less, or within about +/- 5% or less when measured across a desired temperature range.
  • the CTEs are matched across a temperature range from about -60°C to about 100°C or from about -60°C to about 175 °C.
  • connector features formed in the package cover 208 such as threads formed in the sidewalls of the inlet and outlet openings 212 of the package cover 208 and/or protruding features 214 that surround the inlet and outlet openings 212 and extend upwardly from a surface of the lateral portion 208B.
  • the package cover 208 is formed of semi-rigid or rigid material so that at least a portion of the downward force exerted on the package cover 208 by the mounting frame is transferred to a supporting surface of the package substrate 202 and not transferred to the cold plate 207 and the semiconductor device 204 therebelow.
  • the package cover 208 is formed of a thermally conductive metal, such as aluminum or copper.
  • the package cover 208 functions as a heat spreader that redistributes heat from one or more electronic components of the semiconductor device 204.
  • the package cover 208 and/or a manifold may consist of or comprise a thermally insulating material or materials.
  • the package cover 208 and/or the manifold may function as a thermal insulator to retain heat or cold.
  • the package cover 208 and/or the manifold may be insulating to minimize or reduce the flow of thermal energy (e.g., thermal flux) between components (e.g., semiconductor devices, semiconductor device stacks, device packages, etc.).
  • the package cover 208 and/or the manifold may minimize or reduce the flow of thermal energy between a first semiconductor device and a second semiconductor device.
  • FIG. 3B and 3C are schematic sectional views of examples of the integrated cooling assembly of FIG. 3A.
  • both FIGs. 3B and 3C show the cavity dividers 206D separated from a surface of the semiconductor device 303 to define a gap therebetween.
  • Lower surfaces of the cavity dividers 206D may be close enough to the semiconductor device 303 so that the fluid is retained (or primarily remains) within separate cavity coolant channels while traveling across the backside of the semiconductor device 303 (e.g., less than about 2%, or less than about 1%, or less than about 0.5%, or less than about 0.1% of the coolant fluid flow may travel from one channel to another channel of the cavity coolant channels).
  • the cover 508 comprises a base surface, which faces a semiconductor device, and an opposite second surface.
  • Inlet and outlet openings 508A are formed through the cover 508 by extending between the base surface and the opposite second surface. Coolant fluid enters the integrated cooling assembly through the inlet opening 508A, flows through channels defined by the cavity dividers 507B, and exits the integrated cooling assembly via the outlet opening 508A.
  • the cover 508 may retain the fluid in the coolant channel 210 as the fluid flows between the inlet/outlet openings 508 A.
  • the cavity dividers 507B are attached to the base surface of the cover 508 using adhesive 546.
  • the cover 508 may be attached to the manifold 507 using adhesive 546.
  • adhesive 546 may be disposed between the base surface of the cover 508 and the manifold 507.
  • adhesive 546 may be used instead of adhesive 548.
  • both adhesive 546 and adhesive 548 may be used to attach the cover 508 to the manifold 507.
  • a non-adhesive material may be used instead of adhesive 546, e.g., pressed between the cover 508 and the manifold 507.
  • Method 70 is a method of manufacturing a device package 201 in which the metal cold plate 206 is attached to a substrate 202 comprising the semiconductor device 303 to form an integrated cooling assembly comprising a cooling channel.
  • Method 80 is a method of manufacturing a device package 501 or device package 601 in which the manifold 507 is attached to a substrate comprising the semiconductor device 303 to form the integrated cooling assembly comprising a cooling channel.
  • the method 80 may include attaching the manifold 507 to a substrate comprising the semiconductor device 303.
  • the substrate may comprise the semiconductor device 303 disposed in a molding material 305.
  • FIG. 8B is a schematic side sectional view in the X-Z plane of an example of a multicomponent device package 891 that includes a cold plate 807 attached to the backside surfaces of two or more devices 804 A, 804B.
  • the multi-component device package 891 may be similar to the device package 291 described above, and therefore the description of similar features is omitted for brevity.
  • FIG. 8B shows a multi-component device package 891 which is similar to the device package 801 of FIG. 8 A, except it includes a sealing material layer 822.
  • the sealing material layer 822 is similar to the sealing material layer 222.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un boîtier de dispositif comprenant un ensemble de refroidissement intégré. L'ensemble de refroidissement intégré comprend une partie semi-conductrice et une plaque froide métallique fixée à la partie semi-conductrice. La partie semi-conductrice comprend un dispositif à semi-conducteur. La plaque froide métallique comprend une surface de base espacée du dispositif à semi-conducteur pour définir collectivement un canal de fluide de refroidissement entre celles-ci. La plaque froide métallique comprend en outre une paroi latérale s'étendant vers le bas à partir de la surface de base pour définir un périmètre du canal de fluide de refroidissement. La plaque froide métallique comprend en outre des diviseurs de cavité s'étendant vers le bas à partir de la surface de base vers le dispositif à semi-conducteur.
PCT/US2025/015138 2024-02-07 2025-02-07 Ensembles de refroidissement intégrés pour boîtier de dispositif avancé et leurs procédés de fabrication Pending WO2025171355A1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US202463550778P 2024-02-07 2024-02-07
US63/550,778 2024-02-07
US202463575134P 2024-04-05 2024-04-05
US63/575,134 2024-04-05
US202463670330P 2024-07-12 2024-07-12
US63/670,330 2024-07-12
US18/908,493 US20250253206A1 (en) 2024-02-07 2024-10-07 Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same
US18/908,493 2024-10-07

Publications (1)

Publication Number Publication Date
WO2025171355A1 true WO2025171355A1 (fr) 2025-08-14

Family

ID=94870876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2025/015138 Pending WO2025171355A1 (fr) 2024-02-07 2025-02-07 Ensembles de refroidissement intégrés pour boîtier de dispositif avancé et leurs procédés de fabrication

Country Status (1)

Country Link
WO (1) WO2025171355A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060250774A1 (en) * 2005-05-06 2006-11-09 International Business Machines Corporation Cooling apparatus, cooled electronic module and methods of fabrication thereof employing an integrated coolant inlet and outlet manifold
US20080264604A1 (en) * 2007-04-24 2008-10-30 International Business Machines Corporation Cooling appartaus, cooled electronic module and methods of fabrication employing a manifold structure with interleaved coolant inlet and outlet passageways
US20180026017A1 (en) * 2016-07-22 2018-01-25 Invensas Corporation Dies-on-Package Devices and Methods Therefor
US20230207426A1 (en) * 2015-09-30 2023-06-29 Microfabrica Inc. Micro Heat Transfer Arrays, Micro Cold Plates, and Thermal Management Systems for Semiconductor Devices, and Methods for Using and Making Such Arrays, Plates, and Systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060250774A1 (en) * 2005-05-06 2006-11-09 International Business Machines Corporation Cooling apparatus, cooled electronic module and methods of fabrication thereof employing an integrated coolant inlet and outlet manifold
US20080264604A1 (en) * 2007-04-24 2008-10-30 International Business Machines Corporation Cooling appartaus, cooled electronic module and methods of fabrication employing a manifold structure with interleaved coolant inlet and outlet passageways
US20230207426A1 (en) * 2015-09-30 2023-06-29 Microfabrica Inc. Micro Heat Transfer Arrays, Micro Cold Plates, and Thermal Management Systems for Semiconductor Devices, and Methods for Using and Making Such Arrays, Plates, and Systems
US20180026017A1 (en) * 2016-07-22 2018-01-25 Invensas Corporation Dies-on-Package Devices and Methods Therefor

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