WO2025169613A1 - Imaging element, electronic apparatus - Google Patents

Abstract

[Problem] To provide an imaging element that has an improved FD-boosting function. [Solution] An imaging element 101 includes a plurality of photoelectric conversion units PD, a plurality of floating diffusions FD, a plurality of transfer gates TG that transfer charge that has been generated at the photoelectric conversion units PD to the floating diffusions FD, an FD connection region 50 that is a wiring region that connects the plurality of floating diffusions FD, an FD-boosting region 60 that is a wiring region that is for boosting the FD connection region 50, a plurality of first wiring paths 61 that electrically connect gate signal lines of the plurality of transfer gates TG and the FD-boosting region 60, and a second wiring path 62 that electrically connects the FD-boosting region 60 and a ground GND via a resistance. The FD connection region 50 and the FD-boosting region 60 are formed from an N-type semiconductor region, and the first wiring paths 61 have a PN junction that is formed from a P-type semiconductor region and an N-type semiconductor region.

Description

Imaging devices, electronic devices

This disclosure relates to imaging elements and electronic devices that capture images through photoelectric conversion.

Imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital still cameras, digital video cameras, and other devices.

A CMOS image sensor has multiple pixels. Light incident on each pixel of a CMOS image sensor is photoelectrically converted in the photodiode of each pixel, generating an electric charge. The electric charge generated in the photodiode of each pixel is transferred to a floating diffusion (FD) via a transfer transistor.

In such CMOS image sensors, it has been proposed to provide boost wiring (FD boost wiring) to boost the voltage of the floating diffusion FD (see Patent Document 1). This FD boost wiring boosts the FD when charge is transferred to the FD via the transfer transistor, thereby ensuring the dynamic range of the FD and preventing deterioration of the pumping characteristics.

Japanese Patent Application Laid-Open No. 2020-21987

The objective of the technology disclosed herein is to provide an image sensor with an improved FD boost function.

An imaging element according to one aspect of the present disclosure includes a plurality of photoelectric conversion units that generate charges according to the amount of received light through photoelectric conversion; a plurality of floating diffusions that hold the charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect the gate signal lines of the plurality of transfer gates to the FD boost region; and a second wiring path that electrically connects the FD boost region to ground via a resistor, wherein the FD connection region and the FD boost region are formed from N-type semiconductor regions, and the first wiring path has a PN junction formed from a P-type semiconductor region and an N-type semiconductor region. The FD boost region may be arranged to surround the FD connection region in a front view.

The imaging element may have a first semiconductor substrate, an interlayer insulating layer stacked on the upper surface of the first semiconductor substrate, and a second semiconductor substrate stacked on the upper surface of the interlayer insulating layer, and the photoelectric conversion section and the floating diffusion may be formed within the first semiconductor substrate, and the N-type semiconductor regions of the FD connection region and the FD boost region, and the P-type semiconductor region and N-type semiconductor region of the PN junction may be formed within the second semiconductor substrate.

The image sensor may have the FD connection region and the FD boost region formed of N-type polysilicon regions, and may have a first semiconductor substrate, an interlayer insulating layer stacked on the upper surface of the first semiconductor substrate, and a second semiconductor substrate stacked on the upper surface of the interlayer insulating layer, wherein the photoelectric conversion unit and the floating diffusion are formed in the first semiconductor substrate, the N-type polysilicon regions of the FD connection region and the FD boost region are formed in the interlayer insulating layer, and the P-type semiconductor region and N-type semiconductor region of the PN junction are formed in the second semiconductor substrate. At least one of a plurality of transistors constituting a readout circuit may be formed on the second semiconductor substrate.

Furthermore, an imaging element according to one aspect of the present disclosure includes a plurality of photoelectric conversion units that generate charges according to the amount of received light through photoelectric conversion, a plurality of floating diffusions that hold the charges transferred from the photoelectric conversion units, a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions, an FD connection region that is a wiring region that connects the plurality of floating diffusions, an FD boost region that is a wiring region for boosting the FD connection region, and a plurality of gate signal lines that electrically connect the gate signal lines of the plurality of transfer gates to the FD boost region. and a FD boost power supply electrically connected to the FD boost region that can switch between a ground voltage and an ON voltage for the transfer gate, wherein the FD connection region and the FD boost region are formed of N-type semiconductor regions, and the first wiring path has a PN junction formed of a P-type semiconductor region and an N-type semiconductor region, and the FD boost power supply supplies the ON voltage to the FD boost region when any of the multiple transfer gates is ON, and supplies the ground voltage to the FD boost region when all of the multiple transfer gates are OFF. The FD boost region may be arranged to surround the FD connection region in a front view.

The imaging element may have a plurality of FD shared units, which are structural units each having the plurality of photoelectric conversion units, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths, and the plurality of FD shared units may be arranged side by side in one direction when viewed from the front, the FD boost regions of two FD shared units adjacent in the one direction may be connected to each other, and the FD boost power supply may be connected to the FD boost region of the FD shared unit located outermost among the plurality of FD shared units arranged side by side in the one direction.

An electronic device according to one aspect of the present disclosure is an electronic device equipped with the imaging element.

FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. FIG. 2 is a diagram showing the circuit configuration of a pixel and a readout circuit. FIG. 2 is a planar layout diagram of a part of a pixel region in a pixel array section. FIG. 2 is a planar layout diagram showing the configuration of the image sensor according to the first embodiment. 5 is a longitudinal cross-sectional view showing the configuration of the image sensor of the first embodiment, showing a cross section taken along the line AB in FIG. 4. 5 is a longitudinal cross-sectional view showing the configuration of the image sensor of the first embodiment, showing a cross section taken along the line CDE in FIG. 4. 5 is a longitudinal cross-sectional view showing the configuration of the image sensor of the first embodiment, showing a cross section taken along the line CDF in FIG. 4. FIG. 2 is a diagram illustrating the circuit configuration and operation of the image sensor according to the first embodiment. 5A to 5C are longitudinal cross-sectional views illustrating an example of a method for manufacturing the image sensor according to the first embodiment. FIG. 9B is a longitudinal cross-sectional view continuing from FIG. 9A. FIG. 9C is a longitudinal cross-sectional view continuing from FIG. 9B. FIG. 9D is a longitudinal cross-sectional view continuing from FIG. 9C. FIG. 9D is a longitudinal cross-sectional view continuing from FIG. 9D. FIG. 9B is a longitudinal cross-sectional view continuing from FIG. 9E. FIG. 9F is a longitudinal cross-sectional view continuing from FIG. 9F. FIG. 9C is a longitudinal cross-sectional view continuing from FIG. 9G. FIG. 9C is a longitudinal cross-sectional view continuing from FIG. 9H. FIG. 9I is a longitudinal cross-sectional view continuing from FIG. 9I. FIG. 9J is a longitudinal cross-sectional view continuing from FIG. 9J. FIG. 10 is a planar layout diagram showing the configuration of an image sensor according to a modified example of the first embodiment. 11 is a longitudinal cross-sectional view showing the configuration of an image sensor according to a modified example of the first embodiment, showing a cross section taken along the line AB in FIG. 10. 11 is a longitudinal cross-sectional view showing the configuration of an image sensor according to a modified example of the first embodiment, taken along the line CDE in FIG. 10. 11 is a longitudinal cross-sectional view showing the configuration of an image sensor according to a modified example of the first embodiment, taken along the line CDF in FIG. 10. FIG. 10 is a planar layout diagram of an image sensor according to a second embodiment, showing the configuration of a first layer. FIG. 10 is a planar layout diagram of an image sensor according to a second embodiment, showing the configuration of a second layer. FIG. 10 is a planar layout diagram of an image sensor according to a second embodiment, showing the arrangement of connection wiring. 14A to 14C are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the line AB in FIGS. 14A to 14C. 14A to 14C are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the line CDEDF in FIGS. 14A to 14C. 14A to 14C are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the line CDEG in FIGS. 14A to 14C. 14A to 14C are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the line HI in FIGS. 14A to 14C. 10A to 10C are longitudinal cross-sectional views showing an example of a manufacturing method of the image sensor according to the second embodiment. FIG. 19B is a longitudinal cross-sectional view continuing from FIG. 19A. FIG. 19C is a longitudinal cross-sectional view continuing from FIG. 19B. FIG. 19D is a longitudinal cross-sectional view continuing from FIG. 19C. FIG. 19D is a longitudinal cross-sectional view continuing from FIG. 19D. FIG. 19B is a longitudinal cross-sectional view continuing from FIG. 19E. FIG. 19F is a longitudinal cross-sectional view continuing from FIG. 19F. FIG. 11 is a planar layout diagram showing the configuration of an image sensor according to a third embodiment. FIG. 10 is a planar layout diagram showing the configuration of an image sensor according to a fourth embodiment. FIG. 13 is a diagram showing the circuit configuration of a pixel of an image sensor according to a fifth embodiment. FIG. 13 is a planar layout diagram of a part of a pixel region in a pixel array section of an image sensor according to a fifth embodiment. FIG. 1 is a block diagram showing an example of the configuration of a camera as an electronic device. 1 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile object control system; FIG. 2 is a diagram illustrating an example of an installation position of an imaging unit.

Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. The description will be made in the following order.
1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Application example to electronic devices 7. Application example to mobile objects 8. Summary

1. First embodiment
First, the image sensor 101 of the first embodiment will be described.

(Basic configuration of the image sensor 101)
The image sensor 101 of the first embodiment is a rolling shutter type back-illuminated image sensor using a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

A back-illuminated image sensor is an image sensor in which the back surface of a semiconductor substrate serves as the light-receiving surface where light from the subject enters. In a back-illuminated image sensor, a photoelectric conversion unit such as a photodiode that receives light from the subject and converts it into an electrical signal is located for each pixel between the light-receiving surface and a wiring layer containing wiring such as transistors that drive each pixel.

Note that the technology disclosed herein may also be applicable to image sensors using imaging methods other than CMOS image sensors. Furthermore, the technology disclosed herein may also be applied to image sensors using global shutter methods, in addition to rolling shutter methods. The image sensor 101 of the fifth embodiment described below is a global shutter type image sensor.

Figure 1 is a block diagram showing the general configuration of the image sensor 101 of this embodiment.

As will be described later, the image sensor 101 of this embodiment is formed on a semiconductor substrate 11, and therefore is technically a solid-state image sensor, but hereinafter it will be simply referred to as an image sensor.

The image sensor 101 includes, for example, a pixel array unit 111, a vertical drive unit 112, a ramp wave module 113, a column signal processing unit 114, a clock module 115, a data storage unit 116, a horizontal drive unit 117, a system control unit 118, and a signal processing unit 119.

The pixel array section 111 has a plurality of pixels 121, each of which includes a photoelectric conversion element that generates and accumulates an electric charge according to the amount of light incident from the subject. As shown in Figure 1, the plurality of pixels 121 are arranged in both the horizontal direction (row direction) and the vertical direction (column direction).

The pixel array section 111 also has pixel drive lines 122 and vertical signal lines 123. The pixel drive lines 122 are wired along the row direction for each pixel row made up of pixels 121 arranged in a row in the row direction. The vertical signal lines 123 are wired along the column direction for each pixel column made up of pixels 121 arranged in a row in the column direction.

The vertical drive unit 112 is composed of a shift register, an address decoder, etc. The vertical drive unit 112 supplies signals, etc. to the multiple pixels 121 via the multiple pixel drive lines 122, thereby driving all of the multiple pixels 121 in the pixel array unit 111 simultaneously, or driving them on a pixel row basis.

The ramp wave module 113 generates a ramp wave signal used for A/D (Analog/Digital) conversion of pixel signals and supplies it to the column signal processing unit 114.

The column signal processing unit 114 is composed of a shift register, address decoder, etc., and performs noise removal processing, correlated double sampling processing, A/D conversion processing, etc. to generate pixel signals. The column signal processing unit 114 supplies the generated pixel signals to the signal processing unit 119.

The clock module 115 supplies operating clock signals to each part of the image sensor 101.

The horizontal drive unit 117 sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 114. Through selective scanning by this horizontal drive unit 117, pixel signals that have been signal-processed for each unit circuit in the column signal processing unit 114 are output sequentially to the signal processing unit 119.

The system control unit 118 consists of a timing generator that generates various timing signals. Based on the timing signals generated by the timing generator, the system control unit 118 controls the driving of the vertical drive unit 112, ramp wave module 113, column signal processing unit 114, clock module 115, and horizontal drive unit 117.

The signal processing unit 119 performs signal processing such as arithmetic processing on the pixel signals supplied from the column signal processing unit 114 while temporarily storing data in the data storage unit 116 as necessary, and outputs an image signal made up of each pixel signal.

The image sensor 101 is composed of multiple semiconductor substrates. For example, the image sensor 101 is composed by stacking a semiconductor substrate on which the pixel array section 111 is formed and a semiconductor substrate on which the vertical drive section 112, ramp wave module 113, column signal processing section 114, clock module 115, data storage section 116, horizontal drive section 117, system control section 118, and signal processing section 119 are formed. It is also possible to form some of the elements that make up the pixel array section 111 on a separate semiconductor substrate. As described below, in the image sensor 101 of the first embodiment, some of the elements that make up the pixel array section 111 (specifically, the reset transistor RST, amplification transistor AMP, and selection transistor SEL that make up the readout circuit 124 described below) are formed on a separate semiconductor substrate.

FIG. 2 is a diagram showing the circuit configuration of the pixel 121 and readout circuit 124. FIG. 3 is a planar layout diagram of a portion of the pixel area in the pixel array section 111. FIG. 3 shows a 2 x 2, or four-pixel area. The pixel shown in FIG. 3 has a structure in which two photodiodes PD are arranged within one pixel (a so-called dual photodiode structure).

The image sensor 101 of the first embodiment has a dual photodiode structure that enables phase difference detection in all pixels of the pixel array section 111, thereby improving the accuracy of phase difference detection. Furthermore, because the image sensor 101 of the first embodiment can capture images in all pixels, it is possible to avoid degradation of captured images caused by phase difference detection pixels.

The technology disclosed herein can be applied not only to pixels with a dual photodiode structure, but also to regular pixels with one photodiode PD per pixel.

As shown in Figures 2 and 3, in the image sensor 101 of the first embodiment, four pixels 121 share one readout circuit 124.

The pixel 121 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD. In the illustrated example, two pixels 121 share one floating diffusion FD.

The readout circuit 124 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

Note that the planar layout diagram of Figure 3 does not show the reset transistor RST, amplification transistor AMP, and selection transistor SEL that make up the readout circuit 124. This is because, in the example shown in Figure 3, these transistors are formed on a semiconductor substrate (a third semiconductor substrate 31, described below) separate from the semiconductor substrate (a first semiconductor substrate 11, described below) on which the main parts of the pixel array section 111 (such as the photodiode PD, transfer transistor TR, and floating diffusion FD) are arranged.

The photodiode PD generates an electric charge according to the amount of light received through photoelectric conversion. The photodiode PD corresponds to a specific example of a "photoelectric conversion unit" in this disclosure. The anode of the photodiode PD is connected to ground GND. The cathode of the photodiode PD is connected to the drain of the transfer transistor TR.

The transfer transistor TR transfers the charge (pixel signal) photoelectrically converted by the photodiode PD to the floating diffusion FD. The transfer transistor TR has a transfer gate TG (gate electrode). The source of the transfer transistor TR is connected to the cathode of the photodiode PD. The drain of the transfer transistor TR is connected to the floating diffusion FD. The transfer gate TG is connected to the pixel drive line 122.

The floating diffusion FD is a floating diffusion region that temporarily holds the charge transferred from the photodiode PD via the transfer transistor TR. The floating diffusion FD is connected to the drain of the transfer transistor TRG, the source of the reset transistor RST, and the gate of the amplification transistor AMP.

As mentioned above, in the illustrated example, two pixels 121 share one floating diffusion FD. Furthermore, the two floating diffusions FD, each shared by two pixels 121, are electrically connected by wiring. Therefore, it can be said that these two floating diffusions FD essentially constitute one floating diffusion. In other words, it can be said that the four pixels 121 essentially share one floating diffusion consisting of the two floating diffusions FD and wiring.

In the illustrated example, pixel 121 has a dual photodiode structure, so four photodiodes share one floating diffusion FD. Also, eight photodiodes PD essentially share one floating diffusion consisting of two floating diffusions FD and wiring.

In this specification, a group of pixels 121 that essentially share one floating diffusion (in the illustrated example, consisting of two floating diffusions FD and the wiring connecting them) is referred to as an "FD sharing unit (150)." In the illustrated example, the FD sharing unit 150 has four pixels 121 and two floating diffusions PD connected by wiring. However, the FD sharing unit 150 of the technology disclosed herein is not limited to being composed of four pixels 121. Furthermore, the number of floating diffusions PD included in one FD sharing unit 150 is not limited to two.

The reset transistor RST initializes (resets) each region from the photodiode PD to the floating diffusion FD in response to a control signal applied to its gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD. The source of the reset transistor RST is connected to the floating diffusion FD.

For example, when the transfer transistor TR and reset transistor RST are turned on, the potentials of the photodiode PD and floating diffusion FD are reset to the potential level of the power supply line VDD. In other words, turning on the reset transistor RST initializes the photodiode PD and floating diffusion FD.

The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as the input of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD. In other words, the amplifier transistor AMP has a source connected to the vertical signal line VSL (123) via the selection transistor SEL, and thus forms a source follower circuit with the constant current source connected to one end of the vertical signal line VSL (123).

The source of the selection transistor SEL is connected to the vertical signal line VSL (123), and the drain is connected to the source of the amplification transistor AMP. A control signal is supplied to the gate electrode of the selection transistor SEL as a selection signal. When the control signal is turned on, the selection transistor SEL becomes conductive, and the pixel 121 connected to the selection transistor SEL becomes selected. When the pixel 121 becomes selected, the pixel signal output from the amplification transistor AMP is read out to the column signal processing unit 114 via the vertical signal line VSL (123).

Note that the planar layout of the transfer gate TG of the transfer transistor TR in the pixel 121 is not limited to that shown in Figure 3. If the arrangement of the transfer gate TG in the pixel 121 changes, the location of the photodiode PD located below it will also change.

The basic configuration of the image sensor 101 has been explained above.

(Specific configuration of the image sensor 101 according to the first embodiment)
Next, a specific configuration of the image sensor 101 according to the first embodiment will be described.

Figure 4 is a planar layout diagram showing the configuration of the image sensor 101 of the first embodiment.

FIG. 5 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, taken along the path A-B in FIG. 4. FIG. 6 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, taken along the path C-D-E in FIG. 4. FIG. 7 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, taken along the path C-D-F in FIG. 4.

Figure 8 is a diagram showing the circuit configuration and operation of the image sensor 101 of the first embodiment.

First, we will briefly explain the configuration related to the function of boosting the floating diffusion FD.

As shown in FIG. 8, the FD sharing unit 150 of the image sensor 101 has an FD connection region 50, an FD boost region 60, a first wiring path 61, and a second wiring path 62.

The FD connection region 50 is a wiring region that connects two floating diffusions FD included in a PD sharing unit. In the example shown in Figures 4 to 7, the FD connection region 50 is composed of an N-type semiconductor region 21N. Furthermore, each floating diffusion FD and the FD connection region 50 are electrically connected by vertical wiring 41, 42.

The FD boost region 60 is a wiring region for boosting the floating diffusion FD. The FD boost region 60 is arranged to surround the FD connection region 50. In the example shown in Figures 4 to 7, the FD boost region 60 is composed of an N-type semiconductor region 21N.

The first wiring paths 61 are wiring paths that electrically connect the gate signal lines (V _GT ) of the respective transfer gates TG to the FD boosting regions 60. The first wiring paths 61 also have PN junctions. The first wiring paths 61 are provided for each transfer gate TG. In other words, the FD sharing unit 150 of the image sensor 101 has the same number of first wiring paths 61 as the number of transfer gates TG.

In the example shown in Figures 4 to 7, the first wiring path 61 is composed of the vertical wiring 43 and the P-type semiconductor region 21P. The PN junction of the first wiring path 61 is composed of the P-type semiconductor region 21P of the first wiring path 61 and the N-type semiconductor region 21N of the FD boost region 60.

The second wiring path 62 is a wiring path that electrically connects the FD boost region 60 and ground GND. The second wiring path 62 also has a resistance R. In the example shown in Figures 4 to 7, the second wiring path is composed of an N-type semiconductor region 21N and an intrinsic semiconductor region (resistance region) 21I, and the intrinsic semiconductor region (resistance region) 21I functions as a resistor.

8, when the gate voltage V _GT of one of the multiple transfer gates TG present in the PD sharing unit becomes the ON voltage V _ON , a forward bias is applied to the PN junction of the first wiring path 61 connected to the gate signal line (V _GT ) of that transfer gate TG. As a result, a current i flows from that gate signal line (V _GT ) to the FD boost region 60, and the potential of the FD boost region 60 rises. As the potential of the FD boost region 60 rises, the FD connection region 50 surrounded by the FD boost region 60 is also boosted.

Furthermore, when a current i flows from the gate signal line (V _GT ) at the ON voltage V _ON to the FD boost region 60 and the potential of the FD boost region 60 rises, a reverse bias is applied to the PN junction of the first wiring path 61 connecting the gate signal line (V _GT ) at the OFF voltage V _OFF and the FD boost region 60. Therefore, the current i does not flow from the FD boost region 60 to the gate signal line (V _GT ) of another transfer gate TG.

As described above, the FD boost region 60 is connected to ground GND via the second wiring path 62 having the resistance R. Therefore, when the gate voltages V _GT of all the transfer gates TG are at the OFF voltage V _OFF , the GND voltage V _GND is applied to the FD boost region 60 via the second wiring path 62. In other words, when the gate voltages V _GT of all the transfer gates TG are at the OFF voltage V _OFF , the FD boost region 60 has the potential of ground GND.

With this configuration, the image sensor 101 of the first embodiment can boost the voltage of the floating diffusion FD when applying an ON voltage _VON to the transfer gate TG to read out a pixel signal from the photodiode PD.

Next, we will explain in detail the specific configuration of the image sensor 101 of the first embodiment.

Fig. 4 shows a planar layout of the FD sharing unit 150 of the image sensor 101. The vertical cross-sectional view of Fig. 5 shows a cross-section along a path connecting two floating diffusions FD. The vertical cross-sectional view of Fig. 6 shows a cross-section along a path when a current i flows from a gate signal line (V _GT ) to ground GND. The vertical cross-sectional view of Fig. 7 shows a cross-section along a path connecting two transfer gates TG (gate signal lines (V _GT )).

In this specification, the light-receiving surface side of the image sensor 101 is referred to as the "lower" side, and the side opposite the light-receiving surface side is referred to as the "upper" side. Furthermore, for each part that makes up the image sensor 101, the lower surface will be referred to as the "lower surface" and the upper surface will be referred to as the "upper surface." The up-and-down direction will also be referred to as the "vertical direction," and the direction perpendicular to the up-and-down direction will also be referred to as the "horizontal direction."

The imaging element 101 of the first embodiment has a first layer 10, a second layer 20 stacked on the first layer, and a third layer 30 stacked on the second layer 20.

The first layer 10 includes a first semiconductor substrate 11, a photodiode PD, a floating diffusion FD, a transfer gate TG, an interlayer insulating layer 12, vertical wiring 41, and a pad electrode 41a.

The first semiconductor substrate 11 is, for example, a single-crystal silicon substrate.

The photodiode PD is formed in the first semiconductor substrate 11. The photodiode PD is formed, for example, by providing a P-type well in an N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well.

The floating diffusion FD is formed in a region near the top surface of the first semiconductor substrate 11. The floating diffusion FD is configured, for example, as a high-concentration N-type region provided in a P-type well.

In the examples of Figures 5 to 7, the gate electrode TG is formed of a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11. The gate electrode TG may also have a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11 and a vertical gate electrode extending in the depth direction of the semiconductor substrate 11.

The interlayer insulating layer 12 is laminated on the upper surface side of the first semiconductor substrate 11. The interlayer insulating layer 12 is made of an insulating material such as SiO ₂ (silicon oxide).

The vertical wiring 41 is a wiring that extends vertically and is connected to the upper surfaces of the floating diffusion FD and transfer gate TG. The vertical wiring 41 extends from the upper surfaces of the floating diffusion FD and transfer gate TG to the upper surface of the interlayer insulating layer 12. The pad electrode 41a is formed at the upper end of the vertical wiring 41. The pad electrode 41a is joined to a pad electrode 42a formed at the lower end of the vertical wiring 42 of the second layer 20, which will be described later. The vertical wiring 41 and pad electrode 41a are made of a metal material, such as copper or aluminum.

Although not shown in the figure, an element isolation section that electrically isolates adjacent pixels 121 is provided within the first semiconductor substrate 11. Furthermore, a fixed charge film, a color filter, and a light-receiving lens are provided on the underside of the first semiconductor substrate 11. The fixed charge film is a film that has a negative fixed charge to suppress the generation of dark current caused by the interface state on the back surface of the semiconductor substrate. A color filter and a light-receiving lens are provided for each pixel 121.

The second layer 20 has an N-type semiconductor region 21N that constitutes the FD connection region 50, an N-type semiconductor region 21N that constitutes the FD boost region 60, a P-type semiconductor region 21P that constitutes the first wiring path 61, a region consisting of the N-type semiconductor region 21N and an intrinsic semiconductor region (resistance region) 21I that constitutes the second wiring path 62, interlayer insulating layers 22 and 23, vertical wiring 42 and 43, and a pad electrode 42a.

The N-type semiconductor region 21N, P-type semiconductor region 21P, and intrinsic semiconductor region (resistance region) 21I of the second layer 20 are regions formed within the second semiconductor substrate 21. The second semiconductor substrate 21 is, for example, a single-crystal silicon substrate.

The N-type semiconductor region 21N is a region made of an N-type semiconductor. The N-type semiconductor region 21N is, for example, a region made of N-type single crystal silicon (an N-type single crystal polysilicon region). The P-type semiconductor region 21P is a region made of a P-type semiconductor. The P-type semiconductor region 21P is, for example, a region made of P-type single crystal silicon (a P-type single crystal silicon region). The intrinsic semiconductor region (resistance region) 21I is a region made of an intrinsic semiconductor. The intrinsic semiconductor region (resistance region) 21I is, for example, a region made of intrinsic single crystal silicon (an intrinsic single crystal silicon region). However, the intrinsic semiconductor region (resistance region) 21I only needs to have a certain resistance, and may be doped with a small amount of impurity.

As shown in Figure 4, the N-type semiconductor region 21N that constitutes the FD connection region 50 has a strip-like shape when viewed from the front. In other words, the FD connection region 50 has a strip-like shape when viewed from the front. The FD connection region 50 is electrically connected to the floating diffusion FD by vertical wiring 42, 41 that extends downward from near both ends of the strip-like shape.

In this specification, "front view" refers to observation from a direction perpendicular to the top surface of the image sensor 101.

As shown in Figure 4, the N-type semiconductor region 21N that constitutes the FD boost region 60 has a hollow rectangular shape when viewed from the front, and surrounds the N-type semiconductor region 21N that constitutes the FD boost region 60. In other words, the N-type semiconductor region 21N that constitutes the FD boost region 60 has a strip-like shape when viewed from the front, and can be said to surround the N-type semiconductor region 21N that constitutes the FD boost region 60 along a rectangular path.

In other words, when viewed from the front, the FD boost region 60 has a rectangular shape with a hollow center, which surrounds the FD boost region 60. Furthermore, the FD boost region 60 has a band-like shape, which can be said to surround the FD boost region 60 along a rectangular path.

4, the P-type semiconductor region 21P constituting the first wiring path 61 has a strip-like shape in a front view. One end of the strip-like P-type semiconductor region 21P is electrically connected to the gate signal line (V _GT ) via a vertical wiring 43, and is also electrically connected to the transfer gate TG via vertical wirings 42 and 41. The other end is connected to the long side of the rectangle of the N-type semiconductor region 21N constituting the FD boosting region 60.

A PN junction is formed by the P-type semiconductor region 21P that constitutes the first wiring path 61 and the N-type semiconductor region 21N that constitutes the FD boost region 60. This PN junction allows a current i to flow from the gate signal line (V _GT ) to the FD boost region 60, while preventing the current i from flowing from the FD boost region 60 to the gate signal line (V _GT ).

As shown in FIG. 4, the region consisting of the N-type semiconductor region 21N and the intrinsic semiconductor region (resistance region) 21I that constitutes the second wiring path 62 has a strip-like shape when viewed from the front. One end of the strip-like region consisting of the N-type semiconductor region 21N and the intrinsic semiconductor region (resistance region) 21I is connected to the center of the long rectangular side of the N-type semiconductor region 21N that constitutes the FD boost region 60. The other end is electrically connected to ground GND via vertical wiring 43.

The interlayer insulating layers 22 and 23 are laminated on the upper and lower surfaces of the second semiconductor substrate 21. The interlayer insulating layers 22 and 23 are made of an insulating material such as SiO ₂ (silicon oxide).

The vertical wiring 42 is a wiring extending in the vertical direction that is connected to the lower surfaces of the N-type semiconductor region 21N of the FD connection region 50 and the P-type semiconductor region 21P of the first wiring path 61. The vertical wiring 42 extends from the lower surfaces of the N-type semiconductor region 21N and the P-type semiconductor region 21P to the lower surface of the interlayer insulating layer 23. The pad electrode 42a is formed at the lower end of the vertical wiring 42. The pad electrode 42a is joined to the pad electrode 41a formed at the upper end of the vertical wiring 41 of the first layer 10 described above. The vertical wiring 42 and pad electrode 42a are made of a metal material such as copper or aluminum.

The vertical wiring 43 is wiring that extends vertically and is connected to the upper surfaces of the N-type semiconductor region 21N of the FD connection region 50, the P-type semiconductor region 21P of the first wiring path 61, and the N-type semiconductor region 21N of the second wiring path 62. The vertical wiring 43 extends from the upper surfaces of these N-type semiconductor regions 21N and P-type semiconductor regions 21P to the wiring layer 39 of the third layer 30, which will be described later. The vertical wiring 43 is made of a metal material, such as copper or aluminum.

The third layer 30 includes a third semiconductor substrate 31, an interlayer insulating layer 32, an insulating layer inside the through-hole 34, vertical wiring 43, and a wiring layer 39. The third layer 30 also includes transistors that constitute the readout circuit 124, which are formed on the third semiconductor substrate 31.

The third semiconductor substrate 31 is, for example, a single-crystal silicon substrate.

The interlayer insulating layer 31 is laminated on the upper surface side of the third semiconductor substrate 31. The interlayer insulating layer 31 is made of an insulating material such as SiO ₂ (silicon oxide).

The through-hole insulating layer 34 is an insulating layer provided inside a through-hole provided in the third semiconductor substrate 31 to pass the vertical wiring 43. The through-hole insulating layer 34 is made of an insulating material such as SiN (silicon nitride) or _SiO2 (silicon oxide).

The vertical wiring 43 is wiring that extends vertically from the wiring layer 39 to the second layer 20. The vertical wiring 43 is made of a metal material such as copper or aluminum.

The wiring layer 39 is a layer on which various wirings are formed. The wiring layer 39 is laminated on the upper surface of the interlayer insulating layer 32.

Furthermore, the reset transistor RST, amplification transistor AMP, selection transistor SEL, etc. that constitute the readout circuit 124 are formed on the third semiconductor substrate 31.

The image sensor 101 of the first embodiment has the above configuration.

In a conventional configuration in which FD boost wiring is provided, the need to lay FD boost wiring and wiring connecting the power supply and the FD boost wiring poses a problem of constricting the wiring layout of the CMOS image sensor. However, the image sensor 101 of the first embodiment described above forms the FD boost regions 60 and 21N in the semiconductor region and uses the ON voltage _VON of the transfer gate TG to boost the floating diffusion FD, thereby minimizing the constraints on the wiring layout.

Furthermore, in the image sensor 101 of the first embodiment, the FD connection regions 50, 21N are surrounded by FD boost regions 60, 21N to which the ON voltage _{V_ON} or the GND voltage _{V_GND} of the transfer gate TG is applied. Therefore, the image sensor 101 of the first embodiment is less susceptible to the influence of crosstalk of signals from the surrounding FD sharing units 150.

Note that the FD boost region 60 of the technology disclosed herein does not necessarily have to be arranged to surround the FD connection region 50. The FD boost region 60 only needs to be arranged in a manner that allows it to boost the FD connection region 50 and the floating diffusion FD. Therefore, the FD boost region 60 only needs to be arranged adjacent to the FD connection region 50.

However, from the perspective of reducing the influence of signal crosstalk from the surrounding FD sharing units 150 described above, it is preferable that the FD boost region 60 be arranged so as to surround the FD connection region 50 when viewed from the front.

(Method for manufacturing the image sensor 101 according to the first embodiment)
Next, an example of a method for manufacturing the image sensor 101 according to the first embodiment will be described.

Figures 9A to 9K are vertical cross-sectional views showing an example of a manufacturing method for the image sensor 101 of the first embodiment.

The imaging element 101 of the first embodiment is manufactured by bonding together a laminate constituting the first layer 10 and a laminate constituting the second layer 20 and third layer 30, which are molded separately.

In forming the laminate that constitutes the first layer 10, first, as shown in FIG. 9A, a photodiode PD, floating diffusion FD, transfer gate TG, and high-concentration P-type region 10c are formed on the first semiconductor substrate 21. The high-concentration P-type region 10c is an area that is electrically connected to ground GND.

The first semiconductor substrate 21 is, for example, a single-crystal silicon substrate. The photodiode PD is formed, for example, by providing a P-type well in the N-type semiconductor substrate 21 and providing a low-concentration N-type region within the P-type well. The floating diffusion FD is, for example, configured as a high-concentration N-type region provided within the P-type well.

Next, as shown in Figure 9B, an interlayer insulating layer 12, vertical wiring 41, and pad electrodes 41a are formed on the first semiconductor substrate 11.

The interlayer insulating layer 12 is formed by laminating insulating materials such as SiO ₂ (silicon oxide) etc. The vertical wiring 41 and the pad electrode 41a are made of a metal material such as copper or aluminum.

The interlayer insulating layer 12, vertical wiring 41, and pad electrode 41a can be formed by appropriately using well-known techniques such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), sputtering, plating, dry etching, and wet etching. The same applies to the processes below for which explanations of the formation methods are omitted.

In this way, a laminate that constitutes the first layer 10 of the imaging element 101 is formed.

In forming the laminate that constitutes the second layer 20 and the third layer 30, first, as shown in Figure 9C, an N-type semiconductor region 21N, a P-type semiconductor region 21P, and an intrinsic semiconductor region (resistance region) 21I that constitute the FD connection region 50, the FD boost region 60, the first wiring path 61, and the second wiring path 62 are formed near the top surface of the second semiconductor substrate 21.

Then, the substrate material is removed from areas near the top surface of the second semiconductor substrate 21, excluding the N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I. An interlayer insulating layer 22 is then laminated on the second semiconductor substrate 21.

The second semiconductor substrate 21 is, for example, a single-crystal silicon substrate. The N-type semiconductor region 21N is, for example, a region made of single-crystal silicon doped with phosphorus. The P-type semiconductor region 21P is, for example, a region made of single-crystal silicon doped with boron. The intrinsic semiconductor region (resistance region) 21I is, for example, a region made of single-crystal silicon not doped with impurities. However, the intrinsic semiconductor region (resistance region) 21I only needs to have a certain resistance, and may be doped with a small amount of impurities. The interlayer insulating layer 12 is formed by stacking insulating materials such as SiO ₂ (silicon oxide).

Next, as shown in FIG. 9D, a third semiconductor substrate 31 is laminated on the interlayer insulating layer 22. The third semiconductor substrate 31 is, for example, a single-crystal silicon substrate.

Next, as shown in Figure 9E, the upper surface of the third semiconductor substrate 31 stacked on the interlayer insulating layer 22 is thinned. Thinning of the third semiconductor substrate 31 can be achieved by, for example, CMP (Chemical Mechanical Polishing).

9F , through holes for the vertical wiring 43 to be formed later are formed in the third semiconductor substrate 31, and an in-through-hole insulating layer 34 is formed in the through holes. The in-through-hole insulating layer 34 is made of an insulating material such as SiN (silicon nitride) or _SiO2 (silicon oxide). In addition, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, etc. that constitute the readout circuit 124 are formed on the third semiconductor substrate 31.

9G, an interlayer insulating layer 32 and vertical wiring 43 are formed on the third semiconductor substrate 31. The interlayer insulating layer 32 is formed by stacking insulating materials such as _SiO2 (silicon oxide). The vertical wiring 43 is made of a metal material such as copper or aluminum. Thereafter, a wiring layer 39 is formed on the interlayer insulating layer 32.

Next, as shown in 9H, the underside of the second semiconductor substrate 21 is thinned. Thinning of the second semiconductor substrate 21 can be achieved, for example, by CMP. As a result, only the N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I remain in the second semiconductor substrate 21.

Next, as shown in FIG. 9I, an interlayer insulating layer 23, vertical electrodes 42, and pad electrodes 42a are formed on the underside of the interlayer insulating layer 22, N-type semiconductor region 21N, P-type semiconductor region 21P, and intrinsic semiconductor region (resistance region) 21I. The vertical wiring 42 and pad electrodes 42a are made of a metal material such as copper or aluminum.

In this way, a laminate that constitutes the second layer 20 and third layer 30 of the imaging element 101 is formed.

Then, as shown in Figures 9J and 9K, the upper surface of the laminate constituting the first layer 10 is bonded to the lower surfaces of the laminates constituting the second layer 20 and third layer 30. At this time, the pad electrode 41a formed on the upper surface of the first layer 10 and the pad electrode 42a formed on the lower surface of the second layer 20 are bonded.

In this way, the image sensor 101 of the first embodiment can be manufactured.

To summarize the above, the image sensor 101 of the first embodiment has a photodiode PD (photoelectric conversion unit), multiple floating diffusions FD, multiple transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, multiple first wiring paths 61 electrically connecting the gate signal lines (V _GT ) of the multiple transfer gates TG to the FD boost region 60, and a second wiring path 62 electrically connecting the FD boost region 60 to ground GND via a resistor. The first wiring path 61 has a PN junction formed of a P-type semiconductor region and an N-type semiconductor region.

The image sensor 101 of the first embodiment also has a first semiconductor substrate 21, interlayer insulating layers 12 and 23, and a second semiconductor substrate 21. The photodiode PD (photoelectric conversion unit) and floating diffusion FD are formed within the first semiconductor substrate 21, and the N-type semiconductor region 21N of the FD connection region 50 and FD boost region 60, and the P-type semiconductor region 21P and N-type semiconductor region 21N of the PN junction are formed within the second semiconductor substrate 21.

This type of image sensor 101 minimizes the burden on the wiring layout.

Furthermore, in the image sensor 101 of the first embodiment, the FD boosting region 60 is arranged to surround the FD connection region 50 when viewed from the front. In this type of image sensor 101, the effects of crosstalk are suppressed.

(Modification of the image sensor 101 of the first embodiment)
Next, a modification of the image sensor 101 of the first embodiment will be described.

Figure 10 is a planar layout diagram showing the configuration of an image sensor 101 according to a modified example of the first embodiment.

Figures 11 to 13 are longitudinal cross-sectional views showing the configuration of an image sensor 101 according to a modified example of the first embodiment. Figure 11 shows a cross-section along the path A-B in Figure 10. Figure 12 shows a cross-section along the path C-D-E in Figure 10. Figure 13 shows a cross-section along the path C-D-F in Figure 10.

The imaging element 101 of this modified example has the same configuration as this embodiment, except for the points described below.

In the first embodiment, as shown in FIG. 5, the N-type semiconductor region 21N that constitutes the FD connection region 50 is electrically connected to the floating diffusion FD via vertical wiring 42, 41.

On the other hand, in the image sensor 101 of the modified example, as shown in Figure 11, the N-type semiconductor region 21N that constitutes the FD connection region 50 is electrically connected to the floating diffusion FD via vertical wiring 45 made of N-type polysilicon.

In the first embodiment, as shown in FIGS. 6 and 7 , the P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the transfer gate TG via the vertical wirings 42 and 41 extending downward, and is electrically connected to the gate voltage V _GT of the transfer gate TG via the vertical wiring 43 extending upward.

On the other hand, in the image sensor 101 of the modified example, as shown in Figures 12 and 13, the P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the transfer gate TG via a vertical wiring 45 made of P-type polysilicon extending downward. The P-type semiconductor region 21P constituting the first wiring path 61 is not connected to the vertical wiring connected to the gate voltage _VGT of the transfer gate TG. In the image sensor 101 of the modified example, as shown in Figures 12 and 13, the vertical wiring 44 connected to the gate voltage _VGT of the transfer gate TG is connected to the transfer gate TG. In other words, in the image sensor 101 of the modified example, the P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the gate voltage _VGT of the transfer gate TG via the transfer gate TG.

As such, the configuration of the first wiring path 61 of the technology disclosed herein is not limited to the configuration of the first embodiment. The first wiring path 61 of the technology disclosed herein is a wiring path that electrically connects the transfer gate TG and the FD boost region 60, and may be any wiring path that has a PN junction.

2. Second embodiment
Next, an image sensor according to a second embodiment will be described.

The image sensor 101 of the second embodiment has the same configuration as that of the first embodiment, except for the configuration described below.

(Specific Configuration of the Image Sensor 101 of the Second Embodiment)
14A to 14C are planar layout diagrams of the image sensor 101 of the second embodiment. Fig. 14A shows the configuration of the first layer 10. Fig. 14B shows the configuration of the second layer 20. Fig. 14C shows the arrangement of connection wirings 291 and 292.

FIGS. 15 to 18 are longitudinal cross-sectional views showing the configuration of the image sensor 101 of the second embodiment. FIG. 15 shows a cross-section along the path A-B in FIGS. 14A to 14C. FIG. 16 shows a cross-section along the path C-D-E-D-F in FIGS. 14A to 14C. FIG. 17 shows a cross-section along the path C-D-E-G in FIGS. 14A to 14C. FIG. 18 shows a cross-section along the path H-I in FIGS. 14A to 14C.

Furthermore, the circuit configuration and operation of the image sensor 101 of the first embodiment shown in Figure 8 also apply to the image sensor 101 of the second embodiment.

First, we will briefly explain the configuration related to the function of boosting the floating diffusion FD.

As shown in FIG. 8 , the FD sharing unit 150 of the image sensor 101 of the second embodiment also has an FD connection region 50, an FD boost region 60, a first wiring path 61, and a second wiring path 62, similar to the first embodiment.

The FD connection region 50 is a wiring region that connects two floating diffusions FD included in a PD sharing unit. In the example shown in Figures 14A to 18, the FD connection region 50 is composed of an N-type polysilicon region 15N. Furthermore, each floating diffusion FD and the FD connection region 50 are electrically connected by vertical wiring 46.

The FD boost region 60 is a wiring region for boosting the floating diffusion FD. The FD boost region 60 is a wiring region arranged to surround the FD connection region 50. In the example shown in Figures 14A to 18, the FD boost region 60 is composed of an N-type polysilicon region 15N.

The first wiring paths 61 are wiring paths that electrically connect the gate signal lines (V _GT ) of the respective transfer gates TG to the FD boosting region 60. The first wiring paths 61 also have PN junctions. The first wiring paths 61 are provided for each transfer gate TG. In other words, the shared unit of the image sensor 101 has the same number of first wiring paths 61 as the number of transfer gates TG.

In the example shown in Figures 14A to 18, the first wiring path 61 is composed of the vertical wiring 48 - P-type semiconductor region 21P - N-type semiconductor region - vertical wiring 48 - connection wiring 292 - vertical wiring 47. Furthermore, the PN junction of the first wiring path 61 is composed of the P-type semiconductor region 21P and N-type semiconductor region 21N within the first wiring path 61.

The second wiring path 62 is a wiring path that electrically connects the FD boost region 60 and ground GND. The second wiring path 62 also has a resistor R. In the example shown in Figures 14A to 18, the second wiring path is composed of an N-type polysilicon region 15N and an intrinsic polysilicon region (resistance region) 15I, and the intrinsic polysilicon region (resistance region) 15I functions as a resistor.

8 , with this configuration, when the gate voltage V _GT of one of the multiple transfer gates TG present in the PD sharing unit becomes the ON voltage V _ON , a forward bias is applied to the PN junction of the first wiring path 61 connected to the gate signal line (V _GT ) of that transfer gate TG. As a result, a current i flows from that gate signal line (V _GT ) to the FD boost region 60, and the potential of the FD boost region 60 rises. With this rise in the potential of the FD boost region 60, the FD connection region 50 surrounded by the FD boost region 60 is also boosted.

Furthermore, when a current i flows from the gate signal line (V _GT ) at the ON voltage V _ON to the FD boost region 60 and the potential of the FD boost region 60 rises, a reverse bias is applied to the PN junction of the first wiring path 61 connecting the gate signal line (V _GT ) at the OFF voltage V _OFF and the FD boost region 60. Therefore, the current i does not flow from the FD boost region 60 to the gate signal line (V _GT ) of another transfer gate TG.

As described above, the FD boost region 60 is connected to ground GND via the second wiring path 62 having the resistance R. Therefore, when the gate voltages V _GT of all the transfer gates TG are at the OFF voltage V _OFF , the GND voltage V _GND is applied to the FD boost region 60 via the second wiring path 62. In other words, when the gate voltages V _GT of all the transfer gates TG are at the OFF voltage V _OFF , the FD boost region 60 has the potential of ground GND.

With this configuration, the image sensor 101 of the first embodiment can boost the voltage of the floating diffusion FD when applying an ON voltage _VON to the transfer gate TG to read out a pixel signal from the photodiode PD.

Next, we will explain in detail the specific configuration of the image sensor 101 of the second embodiment.

14A to 14C show the planar layout of the FD sharing unit 150 of the image sensor 101. The vertical cross-sectional view of Fig. 15 shows a cross-section along a path connecting two floating diffusions FD. The vertical cross-sectional view of Fig. 16 shows a cross-section along a path when a current i flows from a gate signal line (V _GT ) to ground GND. The vertical cross-sectional views of Fig. 17 and Fig. 18 show cross-sections along a path connecting two transfer gates TG (gate signal lines (V _GT )).

The imaging element 101 of the second embodiment has a first layer 10 and a second layer 20 stacked on the first layer.

The first layer 10 includes a first semiconductor substrate 11, a photodiode PD, a floating diffusion FD, a transfer gate TG, an interlayer insulating layer 12, a polysilicon wiring layer 15, and vertical wiring 46 and 47.

The first semiconductor substrate 11 is, for example, a single-crystal silicon substrate.

The photodiode PD is formed in the first semiconductor substrate 11. The photodiode PD is formed, for example, by providing a P-type well in an N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well.

The floating diffusion FD is formed in a region near the top surface of the first semiconductor substrate 11. The floating diffusion FD is configured, for example, as a high-concentration N-type region provided in a P-type well.

In the examples of Figures 14A to 18, the gate electrode TG is formed of a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11. The gate electrode TG may also have a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11 and a vertical gate electrode extending in the depth direction of the semiconductor substrate 11.

The interlayer insulating layer 12 is laminated on the upper surface side of the first semiconductor substrate 11. The interlayer insulating layer 12 is made of an insulating material such as SiO ₂ (silicon oxide).

The polysilicon wiring layer 15 is a layer formed in the interlayer insulating layer 12. The polysilicon wiring layer 15 has an N-type polysilicon region 15N constituting the FD connection region 50, an N-type polysilicon region 15N constituting the FD boost region 60, a region consisting of the N-type polysilicon region 15N and an intrinsic polysilicon region (resistance region) 15I constituting the second wiring path 62, and a P-type polysilicon region 15P constituting the wiring path connecting the gate signal line (V _GT ) and the transfer gate TG.

The N-type polysilicon region 15N is a region made of N-type polysilicon. The P-type polysilicon region 15P is a region made of P-type polysilicon. The intrinsic semiconductor region (resistance region) 21I is a region made of intrinsic polysilicon. The intrinsic semiconductor region (resistance region) 21I is a region made of intrinsic polysilicon. However, the intrinsic polysilicon region (resistance region) 15I only needs to have a certain resistance, and may be doped with a small amount of impurity.

As shown in FIG. 14A, the N-type polysilicon region 15N that constitutes the FD connection region 50 has a band-like shape when viewed from the front. In other words, the FD connection region 50 has a band-like shape when viewed from the front. The FD connection region 50 is electrically connected to the floating diffusion FD by vertical wiring 46 that extends downward from near both ends of the band-like shape.

As shown in FIG. 14A, the N-type polysilicon region 15N that constitutes the FD boost region 60 has a hollow rectangular shape when viewed from the front, and surrounds the N-type polysilicon region 15N that constitutes the FD boost region 60. In other words, the N-type polysilicon region 15N that constitutes the FD boost region 60 has a band-like shape when viewed from the front, and surrounds the N-type polysilicon region 15N that constitutes the FD boost region 60 along a rectangular path.

In other words, when viewed from the front, the FD boost region 60 has a rectangular shape with a hollow center, which surrounds the FD boost region 60. Furthermore, the FD boost region 60 has a band-like shape, which can be said to surround the FD boost region 60 along a rectangular path.

As shown in FIG. 14A, the region consisting of the N-type polysilicon region 15N and the intrinsic polysilicon region (resistance region) 15I that constitutes the second wiring path 62 has a band-like shape when viewed from the front. One end of the band-like region consisting of the N-type polysilicon region 15N and the intrinsic polysilicon region (resistance region) 15I is connected to the center of the long rectangular side of the N-type polysilicon region 15N that constitutes the FD boost region 60. The other end is electrically connected to ground GND via vertical wiring 47.

The P-type polysilicon region 15P, which constitutes a wiring path connecting the gate signal line (V _GT ) and the transfer gate TG, has a strip-like shape in a front view. One end of the strip-like shape is electrically connected to the transfer gate TG via a vertical wiring 46. The other end is electrically connected to the gate signal line (V _GT ) via a vertical wiring 47.

The vertical wiring 46 is a wiring extending in the vertical direction connected to the lower surface of the N-type polysilicon region 15N constituting the FD connection region 50 and the P-type polysilicon region 15P constituting the wiring path connecting the gate signal line ( _V GT ) and the transfer gate TG. The vertical wiring 46 connected to the lower surface of the N-type polysilicon region 15N constituting the FD connection region 50 is made of N-type polysilicon and extends to the floating diffusion FD. The vertical wiring 46 connected to the lower surface of the P-type polysilicon region 15P constituting the wiring path connecting the gate signal line (V _GT ) and the transfer gate TG is made of P-type polysilicon and extends to the transfer gate TG.

The vertical wiring 47 is a wiring extending in the vertical direction connected to the upper surfaces of the N-type polysilicon region 15N that constitutes the FD connection region 50, the N-type polysilicon region 15N that constitutes the second wiring path 62, and the P-type polysilicon region 15P that constitutes the wiring path connecting the gate signal line (V _GT ) and the transfer gate TG. The vertical wiring 47 extends from the upper surfaces of these N-type polysilicon region 15N and P-type polysilicon region 15P to a wiring layer 29 of the second layer 20, which will be described later. The vertical wiring 47 is made of a metal material, such as copper or aluminum.

The second layer 20 includes a second semiconductor substrate 21, a P-type semiconductor region 21P and an N-type semiconductor region 21N that form the first wiring path 61, an interlayer insulating layer 22, an inner through-hole insulating layer 24, vertical wiring 47, 48, connection wiring 291, 292, and a wiring layer 29. The second layer 20 also includes transistors that form the readout circuit 124 and are formed on the second semiconductor substrate 21.

The second semiconductor substrate 21 is, for example, a single-crystal silicon substrate.

As shown in Figure 14B, the N-type semiconductor region 21N that constitutes the first wiring path 61 has a hollow rectangular shape in front view (hollow rectangle), with the central portion of the short side of the rectangle separated. In other words, the N-type semiconductor region 21N that constitutes the first wiring path 61 has a band-like shape in front view, extends along a rectangular path, and the central portion of the short side of the rectangle is separated. These separated portions are electrically connected to each other via the vertical wiring 48, connection wiring 292, and vertical wiring 48, as shown in Figures 14B, 14C, and 17.

14B , the P-type semiconductor region 21P constituting the first wiring path 61 has a strip-like shape in a front view. One end of the strip-like P-type semiconductor region 21P is electrically connected to the gate signal line (V _GT ) via the vertical wiring 48. The other end is connected to the long side of the rectangle of the N-type semiconductor region 21N constituting the first wiring path 61.

A PN junction is formed by the P-type semiconductor region 21P and the N-type semiconductor region 21N that form the first wiring path 61. This PN junction allows a current i to flow from the gate signal line (V _GT ) to the FD boost region 60, while preventing the current i from flowing from the FD boost region 60 to the gate signal line (V _GT ).

The interlayer insulating layer 22 is laminated on the upper surface side of the second semiconductor substrate 21. The interlayer insulating layer 22 is made of an insulating material such as SiO ₂ (silicon oxide).

The through-hole insulating layer 24 is an insulating layer provided inside the through-hole provided in the second semiconductor substrate 21 to allow the vertical wiring 47 to pass through. The through-hole insulating layer 24 is made of an insulating material such as SiN (silicon nitride) or SiO2 (silicon oxide).

The vertical wiring 47 is a wiring that extends vertically from the wiring layer 29 to the first layer 10. The vertical wiring 48 is a wiring that extends vertically from the wiring layer 29 to the second semiconductor substrate 21. The connection wirings 291 and 292 are wirings that connect the vertical wirings 47 and 48. The vertical wirings 47 and 48 and the connection wirings 291 and 292 are made of a metal material such as copper or aluminum.

The wiring layer 29 is a layer on which various wirings are formed. The wiring layer 29 is stacked on the upper surface of the interlayer insulating layer 22.

Furthermore, the reset transistor RST, amplification transistor AMP, selection transistor SEL, etc. that constitute the readout circuit 124 are formed on the second semiconductor substrate 21.

The image sensor 101 of the second embodiment has the above configuration.

In a conventional configuration in which FD boost wiring is provided, the need to lay FD boost wiring and wiring connecting the power supply and the FD boost wiring poses a problem of constricting the wiring layout of the CMOS image sensor. However, the image sensor 101 of the second embodiment described above forms the FD boost regions 60 and 15N in the semiconductor region and uses the ON voltage _VON of the transfer gate TG to boost the floating diffusion FD, thereby reducing the constraints on the wiring layout.

Furthermore, in the image sensor 101 of the second embodiment, the FD connection regions 50, 15N are surrounded by FD boost regions 60, 15N to which the ON voltage _{V_ON} or the GND voltage _{V_GND} of the transfer gate TG is applied. Therefore, the image sensor 101 of the second embodiment is less susceptible to the influence of signal crosstalk from the surrounding FD sharing units 150.

Note that the FD boost region 60 of the technology disclosed herein does not necessarily have to be arranged to surround the FD connection region 50. The FD boost region 60 only needs to be arranged in a manner that allows it to boost the FD connection region 50 and the floating diffusion FD. Therefore, the FD boost region 60 only needs to be arranged adjacent to the FD connection region 50.

However, from the perspective of reducing the influence of signal crosstalk from the surrounding FD sharing units 150 described above, it is preferable that the FD boost region 60 be arranged so as to surround the FD connection region 50 when viewed from the front.

In this way, with the technology disclosed herein, the semiconductor regions that make up the FD connection region 50 and FD boost region 60 can also be polysilicon regions. If the FD connection region 50 and FD boost region 60 are made of single crystal silicon regions, as in the first embodiment, three semiconductor substrates are required, whereas if the FD connection region 50 and FD boost region 60 are made of polysilicon regions, only two semiconductor substrates are required. Therefore, using polysilicon regions for the semiconductor regions that make up the FD connection region 50 and FD boost region 60 also has the advantage of saving semiconductor substrates.

(Method for manufacturing the image sensor 101 according to the second embodiment)
Next, an example of a method for manufacturing the image sensor 101 according to the second embodiment will be described.

Figures 19A to 19G are vertical cross-sectional views showing an example of a manufacturing method for the image sensor 101 of the second embodiment.

In manufacturing the image sensor 101 of the second embodiment, first, as shown in FIG. 19A, a photodiode PD, floating diffusion FD, transfer gate TG, and high-concentration P-type region 10a are formed on a first semiconductor substrate 21. The high-concentration P-type region 10a is an area that is electrically connected to ground GND.

The first semiconductor substrate 21 is, for example, a single-crystal silicon substrate. The photodiode PD is formed, for example, by providing a P-type well in the N-type semiconductor substrate 21 and providing a low-concentration N-type region within the P-type well. The floating diffusion FD is, for example, configured as a high-concentration N-type region provided within the P-type well.

Next, as shown in FIG. 9B, an interlayer insulating layer 12, a polysilicon wiring layer 15 that forms the FD connection region 50 and the FD boost region 60, etc., and vertical wiring 46 made of polysilicon are formed on the first semiconductor substrate 11.

The interlayer insulating layer 12 is formed by stacking insulating materials such as SiO ₂ (silicon oxide).

The polysilicon wiring layer 15 has an N-type polysilicon region 15N, a P-type polysilicon region 15P, and an intrinsic polysilicon region (resistance region) 15I. The N-type polysilicon region 15N is, for example, a region made of polysilicon doped with phosphorus. The P-type polysilicon region 15P is, for example, a region made of polysilicon doped with boron. The intrinsic polysilicon region (resistance region) 15I is, for example, a region made of polysilicon that has not been doped with impurities. However, the intrinsic polysilicon region (resistance region) 15I only needs to have a certain resistance, and may be doped with a small amount of impurities.

The vertical wiring 46 connected to the N-type polysilicon region 15N is made of N-type polysilicon. The vertical wiring 41 connected to the P-type polysilicon region 15P is made of P-type polysilicon.

In this way, the first layer 10 of the imaging element 101 is formed.

Next, as shown in FIG. 19C, a second semiconductor substrate 21 is laminated on the interlayer insulating layer 12 of the first layer 10. The second semiconductor substrate 21 is, for example, a single-crystal silicon substrate.

Next, as shown in 19D, the upper surface of the second semiconductor substrate 21 stacked on the interlayer insulating layer 12 of the first layer 10 is thinned. Thinning of the second semiconductor substrate 21 can be achieved by, for example, CMP.

Next, as shown in FIG. 19E, an N-type semiconductor region 21N and a P-type semiconductor region 21P that form the first wiring path 61 are formed near the top surface of the second semiconductor substrate 21.

Furthermore, through holes are formed in the second semiconductor substrate 21 for the vertical wiring 47, 48 to be formed later, and an in-through-hole insulating layer 24 is formed in the through holes. The in-through-hole insulating layer 24 is made of an insulating material such as SiN (silicon nitride) or SiO2 (silicon oxide).

Also, the reset transistor RST, amplification transistor AMP, selection transistor SEL, and other components that make up the readout circuit 124 are formed on the second semiconductor substrate 21.

19F, an interlayer insulating layer 22 is formed on the second semiconductor substrate 21. Thereafter, vertical wirings 47 and 48 are formed. The interlayer insulating layer 22 is formed by stacking insulating materials such as SiO ₂ (silicon oxide). The vertical wirings 47 and 48 are made of a metal material such as copper or aluminum.

Finally, as shown in Figure 19G, a wiring layer 29 is formed on the interlayer insulating layer 22. This forms the second layer 20 of the image sensor 101.

In this way, the image sensor 101 of the second embodiment can be manufactured.

To summarize the above, the image sensor 101 of the second embodiment has a photodiode PD (photoelectric conversion unit), multiple floating diffusions FD, multiple transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, multiple first wiring paths 61 electrically connecting the gate signal lines (V _GT ) of the multiple transfer gates TG to the FD boost region 60, and a second wiring path 62 electrically connecting the FD boost region 60 to ground GND via a resistor. The first wiring path 61 has a PN junction formed of a P-type semiconductor region and an N-type semiconductor region.

Furthermore, in the image sensor 101 of the second embodiment, the FD connection region 50 and FD boost region 60 are composed of N-type polysilicon regions 15N. The image sensor 101 has a first semiconductor substrate 21, an interlayer insulating layer 12, and a second semiconductor substrate 22, with the photodiode PD (photoelectric conversion unit) and floating diffusion PD formed in the first semiconductor substrate 21, the N-type polysilicon regions 15N of the FD connection region 50 and FD boost region 60 formed in the interlayer insulating layer 12, and the P-type semiconductor region 21P and N-type semiconductor region 21N of the PN junction formed in the second semiconductor substrate 21.

This type of image sensor 101 minimizes the burden on the wiring layout.

Furthermore, in the image sensor 101 of the second embodiment, the FD boosting region 60 is arranged to surround the FD connection region 50 when viewed from the front. In this type of image sensor 101, the effects of crosstalk are suppressed.

Furthermore, in the image sensor 101 of the second embodiment, at least one of the multiple transistors that make up the readout circuit 124 is formed on the second semiconductor substrate 21. This type of image sensor 101 conserves semiconductor substrate usage.

3. Third Embodiment
Next, an image sensor according to a third embodiment will be described.

FIG. 20 is a planar layout diagram showing the configuration of the image sensor 101 of the third embodiment.

The image sensor 101 of the third embodiment basically has the same configuration as the first embodiment. However, while the image sensor 101 of the first embodiment has the FD boost regions 60 and 21N electrically connected to ground GND via resistors, the image sensor 101 of the third embodiment has the FD boost regions 60 and 21N not electrically connected to ground GND, but instead electrically connected to the FD boost power supply 70.

The FD boost power supply 70 is a power supply that can supply the ON voltage _{V_ON} and the GND voltage _{V_GND} of the transfer gate TG. When the transfer gate TG is ON, the FD boost power supply 70 supplies the ON voltage _{V_ON} of the transfer gate TG to the FD boost regions 60 and 21N, and when the transfer gate TG is OFF, the FD boost power supply 70 supplies the GND voltage _{V_GND} to the FD boost regions 60 and 21N.

In the image sensor 101 of the third embodiment having this configuration, no current flows through the FD boost regions 60 and 21N even when the transfer gate TG is ON. Therefore, the image sensor 101 of the third embodiment has reduced power consumption.

It is possible to boost the floating diffusion FD by connecting only the FD boost power supply 70 without connecting the FD boost regions 60 and 21N to the transfer gate TG, but connecting the transfer gate TG and the FD boost regions 60 and 21N via a PN junction reduces the RC delay of the drive.

Furthermore, in the image sensor 101 of the third embodiment, the FD connection regions 50, 21N are surrounded by the FD boost regions 60, 21N to which the ON voltage _{V_ON} or the GND voltage _{V_GND} of the transfer gate TG is applied, and therefore are less susceptible to the influence of crosstalk of signals from the surrounding FD sharing units 150.

Furthermore, in the image sensor 101 of the third embodiment, the FD boost regions 60, 21N between adjacent FD sharing units 150 in one direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 21N of the FD supply units located at the outermost periphery of the pixel array section 111.

In other words, the FD sharing units 150 are arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD sharing units 150 adjacent in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD sharing unit 150 located on the outermost side of the multiple FD sharing units 150 arranged side by side in that direction.

In the example shown in Figure 20, the FD boost regions 60, 21N of adjacent FD shared units 150 in the left-right direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 21N of the FD shared unit 150 located at the outermost periphery of the pixel array section 111 on the right edge.

This configuration reduces the pressure on the wiring layout.

In the example shown in FIG. 20, the FD boost power supply 70 is directly connected to the FD boost regions 60 and 21N. However, the FD boost power supply 70 may also be connected to the FD boost regions 60 and 21N via, for example, the wiring layer 39 and the vertical wiring 43.

To summarize the above, the image sensor 101 of the third embodiment includes a plurality of photodiodes PD (photoelectric conversion units), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, a plurality of first wiring paths 61 having PN junctions formed of a P-type semiconductor region and an N-type semiconductor region, and an FD boost power supply 70. The FD boost power supply 70 supplies an ON voltage _{V_ON} to the FD boost region 60 when any of the plurality of transfer gates TG is ON, and supplies a ground voltage _{V_GND} to the FD boost region 60 when all of the plurality of transfer gates TG are OFF. The FD boost region 60 may be arranged to surround the FD connection region 50 in a front view.

Such an image sensor 101 reduces power consumption and drive RC delay.

Furthermore, in the image sensor 101 of the third embodiment, the FD boosting region 60 may be arranged to surround the FD connection region 50 when viewed from the front. In such an image sensor 101, the effects of crosstalk are reduced.

Furthermore, the image sensor 101 of the third embodiment has a plurality of FD shared units 150 arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD shared units 150 adjacent in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side of the plurality of FD shared units 150 arranged side by side in that direction. This image sensor 101 reduces the burden on the wiring layout.

4. Fourth Embodiment
Next, an image sensor according to a fourth embodiment will be described.

Figure 21 is a planar layout diagram showing the configuration of the image sensor 101 of the fourth embodiment.

The image sensor 101 of the fourth embodiment basically has the same configuration as the second embodiment. However, while the FD boost regions 60 and 15N of the image sensor 101 of the second embodiment are electrically connected to ground GND via resistors, the image sensor 101 of the fourth embodiment is not electrically connected to ground GND, but is instead electrically connected to the FD boost power supply 70.

The configuration of the FD boost power supply 70 is the same as that of the FD boost power supply 70 of the third embodiment described above. That is, the FD boost power supply 70 is a power supply that can supply the ON voltage _{V_ON} and the GND voltage _{V_GND} of the transfer gate TG. When any of the transfer gates TG is ON, the FD boost power supply 70 supplies the ON voltage _{V_ON} of the transfer gate TG to the FD boost regions 60 and 15N, and when all of the transfer gates TG are OFF, the FD boost power supply 70 supplies the GND voltage _{V_GND} to the FD boost regions 60 and 15N.

In the image sensor 101 of the fourth embodiment having this configuration, no current flows through the FD boost region 60, 15N even when the transfer gate TG is ON. Therefore, the image sensor 101 of the fourth embodiment has reduced power consumption.

It is possible to boost the floating diffusion FD by connecting only the FD boost power supply 70 without connecting the FD boost region 60, 15N to the transfer gate TG, but connecting the transfer gate TG and the FD boost region 60, 15N via a PN junction reduces the RC delay of the drive.

Furthermore, in the image sensor 101 of the fourth embodiment, the FD connection regions 50, 15N are surrounded by the FD boost regions 60, 15N to which the ON voltage _{V_ON} or the GND voltage _{V_GND} of the transfer gate TG is applied, and therefore are less susceptible to the influence of crosstalk of signals from the surrounding FD sharing units 150.

Furthermore, in the image sensor 101 of the fourth embodiment, the FD boost regions 60, 15N between FD sharing units 150 adjacent in one direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 15N of the FD supply units located at the outermost periphery of the pixel array section 111.

In other words, the FD sharing units 150 are arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD sharing units 150 adjacent in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD sharing unit 150 located on the outermost side of the multiple FD sharing units 150 arranged side by side in that direction.

In the example shown in FIG. 21, the FD boost regions 60, 15N of adjacent FD shared units 150 in the left-right direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 15N of the FD shared unit 150 located at the outermost periphery of the pixel array section 111 on the right edge.

This configuration reduces the pressure on the wiring layout.

In the example shown in FIG. 21, the FD boost power supply 70 is directly connected to the FD boost regions 60 and 15N. However, the FD boost power supply 70 may also be connected to the FD boost regions 60 and 15N via, for example, the wiring layer 29 and the vertical wiring 47.

To summarize the above, the image sensor 101 of the fourth embodiment includes a plurality of photodiodes PD (photoelectric conversion units), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, a plurality of first wiring paths 61 having PN junctions formed of a P-type semiconductor region and an N-type semiconductor region, and an FD boost power supply 70. The FD boost power supply 70 supplies an ON voltage _{V_ON} to the FD boost region 60 when any of the plurality of transfer gates TG is ON, and supplies a ground voltage _{V_GND} to the FD boost region 60 when all of the plurality of transfer gates TG are OFF.

Such an image sensor 101 reduces power consumption and drive RC delay.

Furthermore, in the image sensor 101 of the fourth embodiment, the FD boosting region 60 may be arranged to surround the FD connection region 50 when viewed from the front. In such an image sensor 101, the effects of crosstalk are reduced.

Furthermore, the image sensor 101 of the fourth embodiment has a plurality of FD shared units 150 arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD shared units 150 adjacent in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side of the plurality of FD shared units 150 arranged side by side in that direction. This image sensor 101 reduces the burden on the wiring layout.

<5. Fifth embodiment>
Next, the image sensor 101 according to the fifth embodiment will be described.

While the image sensor 101 of the first embodiment described above is a rolling shutter type image sensor, the image sensor 101 of the fifth embodiment is a global shutter type image sensor. The image sensor 101 of the fifth embodiment has the same configuration as the first embodiment, except for the configuration described below.

FIG. 22 is a diagram showing the circuit configuration of a pixel 121 of the image sensor 101 of the fifth embodiment. FIG. 23 is a planar layout diagram of a portion of the pixel area within the pixel array section 111 of the image sensor 101 of the fifth embodiment. FIG. 23 shows an area of 2 x 2, or four pixels.

In the image sensor 101 of the fifth embodiment, as in the first embodiment, four pixels 121 share one readout circuit 124. Figure 22 shows only one pixel 121. The configuration of the readout circuit 124 is the same as the readout circuit 124 of the first embodiment shown in Figure 2.

The pixel 121 has a photodiode PD, a charge storage unit MEM, three transfer transistors TRY, TRX, and TRG, a floating diffusion FD, and a discharge transistor OFG. In the illustrated example, two pixels 121 share one floating diffusion FD.

Furthermore, the readout circuit 124, like the first embodiment, has a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

The photodiode PD generates an electric charge according to the amount of light received through photoelectric conversion. The anode of the photodiode PD is connected to ground (GND). The cathode of the photodiode PD is connected to the source of the discharge transistor OFG and the drain of the transfer transistor TRY.

The charge holding unit MEM is an area that temporarily holds the charge generated and accumulated in the photodiode PD in order to realize the global shutter function. The charge holding unit MEM holds the charge transferred from the photodiode PD.

The transfer transistors TRY and TRX are arranged on the charge holding unit MEM, in that order from the photodiode PD side. The gates of the transfer transistors TRY and TRX are connected to the pixel drive line 122. The transfer transistors TRY and TRX control the potential of the charge holding unit MEM using a control signal applied to the gate electrode, and transfer the charge photoelectrically converted by the photodiode PD.

For example, when the transfer transistors TRY and TRX are turned on, the potential of the charge holding unit MEM becomes deeper, and when the transfer transistors TRY and TRX are turned off, the potential of the charge holding unit MEM becomes shallower. For example, when the transfer transistors TRY and TRX are turned on, the charge stored in the photodiode PD is transferred to the charge holding unit MEM via the transfer transistors TRY and TRX.

The transfer transistor TRG is arranged between the transfer transistor TRX and the floating diffusion FD. The source of the transfer transistor TRG is connected to the drain of the transfer transistor TRX, and the drain of the transfer transistor TRG is connected to the floating diffusion FD. The gate of the transfer transistor TRG is connected to the pixel drive line 122. The transfer transistor TRG transfers the charge held in the charge holding unit MEM to the floating diffusion FD in response to a control signal applied to the gate electrode.

For example, when the transfer transistor TRX is turned off and the transfer transistor TRG is turned on, the charge held in the charge holding unit MEM is transferred to the floating diffusion FD.

The floating diffusion FD is a floating diffusion region that temporarily holds the charge transferred from the photodiode PD via the transfer transistor TRG. The floating diffusion FD is connected to the drain of the transfer transistor TRG, the source of the reset transistor RST, and the gate of the amplification transistor AMP.

As mentioned above, in the illustrated example, two pixels 121 share one floating diffusion FD. Furthermore, the two floating diffusions FD, each shared by two pixels 121, are electrically connected by wiring. Therefore, it can be said that these two floating diffusions FD essentially constitute one floating diffusion. In other words, it can be said that the four pixels 121 essentially share one floating diffusion consisting of two floating diffusions FD and wiring.

The discharge transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to its gate electrode. The drain of the discharge transistor OFG is connected to the power supply line VDD. The source of the discharge transistor OFG is connected to the photodiode PD and the source of the transfer transistor TRY.

For example, when the drain transistor OFG is turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. In other words, the photodiode PD is initialized. In addition, the drain transistor OFG forms an overflow path between the photodiode PD and the power supply line VDD, and drains the charge that has overflowed from the photodiode PD to the power supply line VDD.

The reset transistor RST initializes (resets) each region from the charge storage unit MEM to the floating diffusion FD in response to a control signal applied to its gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD. The source of the reset transistor RST is connected to the floating diffusion FD.

For example, when the transfer transistor TRG and reset transistor RST are turned on, the potential of the charge holding unit MEM and floating diffusion FD is reset to the potential level of the power supply line VDD. In other words, turning on the reset transistor RST initializes the charge holding unit MEM and floating diffusion FD.

The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as the input of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD. In other words, the amplifier transistor AMP has a source connected to the vertical signal line VSL (123) via the selection transistor SEL, and thus forms a source follower circuit with the constant current source connected to one end of the vertical signal line VSL (123).

The source of the selection transistor SEL is connected to the vertical signal line VSL (123), and the drain is connected to the source of the amplification transistor AMP. A control signal is supplied to the gate electrode of the selection transistor SEL as a selection signal. When the control signal is turned on, the selection transistor SEL becomes conductive, and the pixel 121 connected to the selection transistor SEL becomes selected. When the pixel 121 becomes selected, the pixel signal output from the amplification transistor AMP is read out to the column signal processing unit 114 via the vertical signal line VSL (123).

Note that the planar layout of each transistor within pixel 121 is not limited to that shown in Figure 23. If the arrangement of each transistor within pixel 121 changes, the locations of the photodiode PD and charge storage unit MEM located below them will also change.

Except for the configuration described above, the specific configuration of the image sensor 101 in the fifth embodiment is basically the same as that in the first embodiment.

However, the "transfer transistor TRG" in the fifth embodiment corresponds to the "transfer transistor TR" in the first embodiment, and the "gate electrode of the transfer transistor TRG" in the fifth embodiment corresponds to the "transfer gate TG" in the first embodiment.

In this way, the technology disclosed herein can be applied not only to rolling shutter type image sensors, but also to global shutter type image sensors.

<6. Application examples to electronic devices>
FIG. 24 is a block diagram showing an example configuration of a camera 2000 as an electronic device to which the technology according to the present disclosure is applied.

Camera 2000 includes an optical unit 2001 consisting of a group of lenses and the like, an image sensor (image capture device) 2002 to which the image sensor 101 described above and the like are applied, and a DSP (Digital Signal Processor) circuit 2003, which is a camera signal processing circuit. Camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, operation unit 2007, and power supply unit 2008 are interconnected via bus line 2009.

The optical unit 2001 takes in incident light (image light) from the subject and forms an image on the imaging surface of the image sensor 2002. The image sensor 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal.

The display unit 2005 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the image sensor 2002. The recording unit 2006 records the moving images or still images captured by the image sensor 2002 on a recording medium such as a hard disk or semiconductor memory.

Operated by the user, the operation unit 2007 issues operation commands for the various functions of the camera 2000. The power supply unit 2008 appropriately supplies various types of power to the DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, and operation unit 2007 as operating power sources.

As mentioned above, by using the image sensor 101 or the like as the image sensor 2002, it is possible to expect to obtain good images.

<7. Application examples to mobile objects>
The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

Figure 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.

The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. In the example shown in FIG. 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (Interface) 12053.

The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a driveforce generating device such as an internal combustion engine or drive motor that generates vehicle driveforce, a driveforce transmission mechanism that transmits driveforce to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates vehicle braking force.

The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 accepts these radio waves or signal inputs and controls the vehicle's door lock device, power window device, lamps, etc.

The outside vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to an imaging unit 12031. The outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. Furthermore, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. Connected to the in-vehicle information detection unit 12040 is, for example, a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby enabling cooperative control aimed at autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

In addition, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

The audio/video output unit 12052 transmits at least one audio and/or video output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 25, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

Figure 26 shows an example of the installation position of the imaging unit 12031.

In FIG. 26, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly capture images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly capture images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly captures images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

Note that Figure 26 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 12101 to 12104, an overhead image of vehicle 12100 viewed from above can be obtained.

At least one of the image capturing units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera consisting of multiple image capturing elements, or an image capturing element having pixels for phase difference detection.

For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify and extract three-dimensional object data regarding three-dimensional objects into categories such as motorcycles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, it can provide driving assistance to avoid a collision by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drivetrain control unit 12010.

At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio/video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio/video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian in a desired position.

The foregoing describes an example of a vehicle control system to which the technology disclosed herein can be applied. Of the configurations described above, the technology disclosed herein can be applied to the imaging unit 12031. Specifically, the imaging element 101 shown in FIG. 1 and the like can be applied to the imaging unit 12031. By applying the technology disclosed herein to the imaging unit 12031, excellent operation of the vehicle control system can be expected.

8. Summary
Although an example of an embodiment of the present disclosure has been described above, the present disclosure can be implemented in various other forms. For example, various modifications, substitutions, omissions, or combinations thereof are possible without departing from the spirit of the present disclosure. Such modifications, substitutions, omissions, etc. are also included within the scope of the present disclosure, as well as within the scope of the inventions described in the claims and their equivalents.

Furthermore, the effects of the present disclosure described in this specification are merely examples, and other effects may also be present.

The present disclosure may also be configured as follows.
[Item 1]
a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion;
a plurality of floating diffusions that hold charges transferred from the photoelectric conversion unit;
a plurality of transfer gates that transfer the charges generated in the photoelectric conversion portion to the floating diffusion;
an FD connection region which is a wiring region connecting the plurality of floating diffusions;
an FD boosting region which is a wiring region for boosting the FD connection region;
a plurality of first wiring paths electrically connecting gate signal lines of the plurality of transfer gates and the FD boosting region;
a second wiring path electrically connecting the FD boosting region and ground via a resistor;
the FD connection region and the FD boosting region are formed by N-type semiconductor regions,
the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region;
Image sensor.
[Item 2]
Item 1, an imaging device according to item 1,
The FD boosting region is disposed so as to surround the FD connection region in a front view of the image sensor.
[Item 3]
Item 1 or 2, the imaging element
a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer;
the photoelectric conversion portion and the floating diffusion are formed in the first semiconductor substrate,
the N-type semiconductor regions of the FD connection region and the FD boosting region, and the P-type semiconductor region and the N-type semiconductor region of the PN junction are formed within the second semiconductor substrate.
[Item 4]
4. The imaging device according to any one of items 1 to 3,
the FD connection region and the FD boosting region are made of N-type single crystal silicon regions,
the PN junction of the first wiring path is formed by a P-type single crystal silicon region and an N-type single crystal silicon region.
[Item 5]
4. The imaging device according to any one of items 1 to 3,
The imaging element has the FD connection region and the FD boosting region formed of an N-type polysilicon region.
[Item 6]
Item 5. The imaging device according to item 5,
a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer;
the photoelectric conversion portion and the floating diffusion are formed in the first semiconductor substrate,
the N-type polysilicon regions of the FD connection region and the FD boosting region are formed in the interlayer insulating layer;
a P-type semiconductor region and an N-type semiconductor region of the PN junction are formed in the second semiconductor substrate.
[Item 7]
Item 6. The imaging device according to item 6,
An image sensor in which at least one of a plurality of transistors constituting a readout circuit is formed on the second semiconductor substrate.
[Item 8]
a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion;
a plurality of floating diffusions that hold charges transferred from the photoelectric conversion unit;
a plurality of transfer gates that transfer the charges generated in the photoelectric conversion portion to the floating diffusion;
an FD connection region which is a wiring region connecting the plurality of floating diffusions;
an FD boosting region which is a wiring region for boosting the FD connection region;
a plurality of first wiring paths electrically connecting gate signal lines of the plurality of transfer gates and the FD boosting region;
a FD boost power supply that is electrically connected to the FD boost region and is a power supply that can switch between a ground voltage and an ON voltage of the transfer gate,
the FD connection region and the FD boosting region are formed by N-type semiconductor regions,
the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region;
The FD boost power supply supplies the ON voltage to the FD boost region when any of the plurality of transfer gates is ON, and supplies the ground voltage to the FD boost region when all of the plurality of transfer gates are OFF.
[Item 9]
Item 8. The imaging device according to item 8,
The FD boosting region is disposed so as to surround the FD connection region in a front view of the image sensor.
[Item 10]
Item 8 or 9, the imaging element
a plurality of FD sharing units, which are structural units each including the plurality of photoelectric conversion units, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths;
The plurality of FD sharing units are arranged side by side in one direction when viewed from the front,
the FD boosting regions of the two FD sharing units adjacent in the one direction are connected to each other,
the FD boost power supply is connected to the FD boost region of the FD sharing unit located at the outermost position among the plurality of FD sharing units arranged side by side in the one direction.
[Item 11]
11. An electronic device comprising the imaging element according to any one of items 1 to 10.

101 Image sensor 111 Pixel array section 112 Vertical drive section 113 Ramp wave module 114 Column signal processing section 115 Clock module 116 Data storage section 117 Horizontal drive section 118 System control section 119 Signal processing section 121 Pixel 122 Pixel drive line 123 Vertical signal line 124 Readout circuit 150 FD sharing unit 10 First layer 11 First semiconductor substrate 11c Highly doped P-type region 12 Interlayer insulating layer 15 Polysilicon wiring layer 15N N-type polysilicon region 15P P-type polysilicon region 15I Intrinsic polysilicon region (resistance region)
20 Second layer 21 Second semiconductor substrate 21N N-type semiconductor region 21P P-type semiconductor region 21I Intrinsic semiconductor region (resistance region)
22, 23 Interlayer insulating layer 24 Insulating layer inside through hole 29 Wiring layer 291, 292 Connection wiring 30 Third layer 31 Third semiconductor substrate 32 Interlayer insulating layer 34 Insulating layer inside through hole 39 Wiring layer 41, 42, 43, 44, 45, 46, 47, 48 Vertical wiring 41a, 42a Pad electrode 50 FD connection region 60 FD boosting region 61 First wiring path 62 Second wiring path 70 FD boosting power supply PD Photodiode TR Transfer transistor TG Transfer gate FD Floating diffusion RST Reset transistor AMP Amplifying transistor SEL Select transistor VDD Power supply line VSL Vertical signal line

Claims (11)

a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion;
a plurality of floating diffusions that hold charges transferred from the photoelectric conversion unit;
a plurality of transfer gates that transfer the charges generated in the photoelectric conversion portion to the floating diffusion;
an FD connection region which is a wiring region connecting the plurality of floating diffusions;
an FD boosting region which is a wiring region for boosting the FD connection region;
a plurality of first wiring paths electrically connecting gate signal lines of the plurality of transfer gates and the FD boosting region;
a second wiring path electrically connecting the FD boosting region and ground via a resistor;
the FD connection region and the FD boosting region are formed by N-type semiconductor regions,
the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region;
Image sensor. 2. The imaging device according to claim 1,
The FD boosting region is disposed so as to surround the FD connection region in a front view of the image sensor. 2. The imaging device according to claim 1,
a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer;
the photoelectric conversion portion and the floating diffusion are formed in the first semiconductor substrate,
the N-type semiconductor regions of the FD connection region and the FD boosting region, and the P-type semiconductor region and the N-type semiconductor region of the PN junction are formed within the second semiconductor substrate. 2. The imaging device according to claim 1,
the FD connection region and the FD boosting region are made of N-type single crystal silicon regions,
the PN junction of the first wiring path is formed by a P-type single crystal silicon region and an N-type single crystal silicon region. 2. The imaging device according to claim 1,
The imaging element has the FD connection region and the FD boosting region formed of an N-type polysilicon region. 6. The imaging device according to claim 5,
a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer;
the photoelectric conversion portion and the floating diffusion are formed in the first semiconductor substrate,
the N-type polysilicon regions of the FD connection region and the FD boosting region are formed in the interlayer insulating layer;
a P-type semiconductor region and an N-type semiconductor region of the PN junction are formed in the second semiconductor substrate. The imaging device according to claim 6,
An image sensor in which at least one of a plurality of transistors constituting a readout circuit is formed on the second semiconductor substrate. a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion;
a plurality of floating diffusions that hold charges transferred from the photoelectric conversion unit;
a plurality of transfer gates that transfer the charges generated in the photoelectric conversion portion to the floating diffusion;
an FD connection region which is a wiring region connecting the plurality of floating diffusions;
an FD boosting region which is a wiring region for boosting the FD connection region;
a plurality of first wiring paths electrically connecting gate signal lines of the plurality of transfer gates and the FD boosting region;
a FD boost power supply that is electrically connected to the FD boost region and is a power supply that can switch between a ground voltage and an ON voltage of the transfer gate,
the FD connection region and the FD boosting region are formed by N-type semiconductor regions,
the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region;
The FD boost power supply supplies the ON voltage to the FD boost region when any of the plurality of transfer gates is ON, and supplies the ground voltage to the FD boost region when all of the plurality of transfer gates are OFF. The imaging device according to claim 8,
The FD boosting region is disposed so as to surround the FD connection region in a front view of the image sensor. The imaging device according to claim 8,
a plurality of FD sharing units, which are structural units each including the plurality of photoelectric conversion units, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths;
The plurality of FD sharing units are arranged side by side in one direction when viewed from the front,
the FD boosting regions of the two FD sharing units adjacent in the one direction are connected to each other,
the FD boost power supply is connected to the FD boost region of the FD sharing unit located at the outermost position among the plurality of FD sharing units arranged side by side in the one direction. An electronic device equipped with an imaging element,
The imaging element is
a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion;
a plurality of floating diffusions that hold charges transferred from the photoelectric conversion unit;
a plurality of transfer gates that transfer the charges generated in the photoelectric conversion portion to the floating diffusion;
an FD connection region which is a wiring region connecting the plurality of floating diffusions;
an FD boosting region which is a wiring region for boosting the FD connection region;
a plurality of first wiring paths electrically connecting gate signal lines of the plurality of transfer gates and the FD boosting region;
a second wiring path electrically connecting the FD boosting region and ground via a resistor;
the FD connection region and the FD boosting region are formed by N-type semiconductor regions,
the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region.