WO2025167343A1 - Chip, processing apparatus and electronic device - Google Patents

Abstract

The present application relates to the technical field of chips, relates to a chip, a processing apparatus and an electronic device, and provides a die division method in a chiplet. The chip comprises a first die and a second die, wherein the first die comprises a physical coding sublayer (PCS) circuit, and the second die comprises a physical medium attachment sublayer (PMA) circuit and a physical medium dependent sublayer (PMD) circuit; the PCS circuit of the first die is coupled with the PMA circuit of the second die; and the PMA circuit is coupled with the PMD circuit.

Description

Chip, processing device and electronic device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 6, 2024, with application number 2024101747792 and application name “A chip, processing device and electronic device”, the entire contents of which are incorporated by reference into this application.

Technical Field

The embodiments of the present application relate to the field of chip technology, and in particular to a chip, a processing device, and an electronic device.

Background Art

Chiplet technology splits a chip into multiple dies, then packages them together to form a single chip. Chiplet technology offers advantages such as flexible design, low cost, and a short R&D cycle. Chiplet development requires consideration of how to divide the dies.

Summary of the Invention

The present application provides a chip, a processing device, and an electronic device, and provides a method for dividing bare dies in a chiplet.

In a first aspect, a chip is provided, comprising a first die and a second die. The first die comprises a physical coding sublayer (PCS) circuit, and the second die comprises a physical medium attachment sublayer (PMA) circuit and a physical medium dependent sublayer (PMD) circuit. The PCS circuit of the first die is coupled to the PMA circuit of the second die, and the PMA circuit is coupled to the PMD circuit.

The above technical solution provides a die partitioning method within a chiplet, separating multiple circuits onto different dies. Different dies can utilize different process technologies. For example, the second die can utilize a mature process, resulting in lower hardware costs. Furthermore, a first die can be used with multiple second dies, and the number of first and second dies can be selected based on the scenario, providing greater design flexibility. Furthermore, the second die only includes PMA and PMD circuits, which are unrelated to functional logic. This allows for flexible reuse between different dies at a low cost. The PMA and PMD circuits are unrelated to functional logic and are used to couple with the link containing any of the multiple functions. The PCS circuit is related to functional logic and is used to couple with the link containing the function corresponding to the PCS circuit. Separating circuits related to functional logic and circuits unrelated to functional logic onto different dies, for example in a frame-type device scenario, eliminates crossover of single-board traces outside the chip and internal traces within the chip, reducing hardware costs and facilitating reuse of multiple second dies with the first die.

In one possible implementation of the first aspect, the PCS circuit includes a PCS transmit circuit and a PCS receive circuit, the PMA circuit includes a PMA transmit circuit and a PMA receive circuit, and the PMD circuit includes a PMD transmit circuit and a PMD receive circuit. The PCS transmit circuit is coupled to the PMA transmit circuit, which in turn is coupled to the PMD transmit circuit. The PCS receive circuit is coupled to the PMA receive circuit, which in turn is coupled to the PMD receive circuit. In the above possible implementation, the PCS circuit, the PMA circuit, and the PMD circuit each include a transmit side and a receive side, and the PMA transmit circuit, the PMA receive circuit, the PMD transmit circuit, and the PMD receive circuit are all located on different dies from the PCS transmit circuit and the PCS receive circuit. This reduces hardware cost, increases design flexibility, and facilitates multiplexing of multiple second dies with a first die.

In one possible implementation of the first aspect, the first die or the second die further includes a functional circuit. The PCS circuit is coupled to the PMA circuit via the functional circuit. In this possible implementation, other functional circuits may be included between the PCS circuit and the PMA circuit. These functional circuits may be configured based on application requirements, thereby enabling more flexible configuration of chip functions.

In one possible implementation of the first aspect, the functional circuit includes a forward error correction (FEC) circuit. Including the FEC circuit between the PCS circuit and the PMA circuit in this possible implementation can reduce the bit error rate. If the FEC circuit is located on a second die using a mature process, the chip cost can be further reduced. If the FEC circuit is located on a first die using an advanced process, the first die can also be manufactured using an advanced process, thereby improving chip performance.

In one possible implementation of the first aspect, the FEC circuit includes an FEC transmit circuit and an FEC receive circuit. The PCS transmit circuit is coupled to the PMA transmit circuit via the FEC transmit circuit. The PCS receive circuit is coupled to the PMA receive circuit via the FEC receive circuit. In this possible implementation, the FEC circuit includes a transmit side and a receive side, which can reduce bit error rates for both transmit and receive links in the chip. If the FEC transmit circuit and the FEC receive circuit are located on a second die, using a mature process for the second die, chip cost can be further reduced. If the FEC transmit circuit and the FEC receive circuit are located on a first die, using an advanced process for the first die, the FEC transmit circuit and the FEC receive circuit can also be manufactured using advanced processes, thereby improving chip performance.

In one possible implementation of the first aspect, the first die or the second die further includes a feedback circuit. The FEC receiving circuit is coupled to the feedback circuit, which is in turn coupled to the PMD receiving circuit. The FEC receiving circuit is configured to transmit bit error information to the PMD receiving circuit via the feedback circuit when the bit error rate (BER) obtained by forward error correction (FEC) is not zero. The feedback circuit is a serial interface. In this possible implementation, the bit error rate of the bit error information to be transmitted is relatively high. To avoid wasting bandwidth between dies, the feedback circuit for transmitting the bit error information is configured as a serial interface. The bit error information is transmitted in the form of serial data, thereby reducing the bandwidth for data transmission between dies.

In one possible implementation of the first aspect, the first die further includes a medium access control (MAC) circuit. The MAC circuit is coupled to the PCS circuit. In this possible implementation, if both the first die and the second die utilize mature processes, the MAC circuit can be decoupled from the advanced process die (advanced process dies offer better performance than mature process dies), further reducing costs and increasing design flexibility. If the first die utilizes an advanced process and the second die utilizes a mature process, placing as many circuits as possible, such as the MAC circuit, on the first die can improve chip performance and reduce package size.

In one possible implementation of the first aspect, the MAC circuit includes a MAC transmit circuit and a MAC receive circuit. The MAC transmit circuit is coupled to the PCS transmit circuit. The MAC receive circuit is coupled to the PCS receive circuit. In this possible implementation, the MAC circuit includes a transmit side and a receive side, and both the MAC transmit circuit and the MAC receive circuit are disposed in the first die. This reduces hardware cost and provides greater design flexibility. If the first die uses an advanced process, the MAC transmit circuit and the MAC receive circuit can also use the advanced process to improve chip performance.

In one possible implementation of the first aspect, the first die or the second die further includes a regulation circuit, and the PMA transmit circuit further includes a buffer. The MAC transmit circuit is coupled to the regulation circuit, which is in turn coupled to the PMA transmit circuit. The buffer is configured to store data while the MAC transmit circuit is transmitting data to the PMA transmit circuit via the PCS transmit circuit. The PMA transmit circuit is configured to control the MAC transmit circuit to reduce the bandwidth of transmitted data via the regulation circuit when the amount of data stored in the buffer exceeds a preset value. In this possible implementation, the regulation circuit is configured to adjust the transmit bandwidth of the first die when the amount of data stored in the PMA transmit circuit's buffer exceeds a first preset value, thereby alleviating the problem of excessive data traffic on the first die that the second die cannot process in time.

In one possible implementation of the first aspect, the first die further includes a first interface circuit, and the second die further includes a second interface circuit. The first interface circuit and the second interface circuit are coupled, and the first die is coupled to the second die via the first interface circuit and the second interface circuit. In this possible implementation, the first die is coupled to the second die via the first interface circuit and the second interface circuit, and the first die and the second die can communicate via the first interface circuit and the second interface circuit, establishing a basis for communication between the first die and the second die.

In a second aspect, a processing device is provided, which includes a printed circuit board and a chip provided by the first aspect or any possible implementation of the first aspect.

According to a third aspect, an electronic device is provided. The electronic device includes a housing and the processing device according to the second aspect.

It can be understood that any of the processing devices or electronic devices provided above can apply the corresponding chips provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding chips provided above, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a core particle technology provided in an embodiment of the present application;

FIG2 is a schematic diagram of an open system interconnection reference model provided in an embodiment of the present application;

FIG3 is a schematic diagram of the functions of a physical medium access sublayer circuit provided in an embodiment of the present application;

FIG4 is a schematic diagram of an electronic device provided in an embodiment of the present application;

FIG5 is a schematic diagram of a first chip provided in an embodiment of the present application;

FIG6 is a schematic diagram of a first interface die provided in an embodiment of the present application;

FIG7 is a schematic diagram of a second chip provided in an embodiment of the present application;

FIG8 is a first schematic diagram of a third chip provided in an embodiment of the present application;

FIG9 is a schematic diagram of a second bare die provided in an embodiment of the present application;

FIG10 is a second schematic diagram of a third chip provided in an embodiment of the present application;

FIG11 is a third schematic diagram of a third chip provided in an embodiment of the present application;

FIG12 is a fourth schematic diagram of a third chip provided in an embodiment of the present application;

FIG13 is a fifth schematic diagram of a third chip provided in an embodiment of the present application;

FIG14 is a sixth schematic diagram of a third chip provided in an embodiment of the present application;

FIG15 is a seventh schematic diagram of a third chip provided in an embodiment of the present application;

FIG16 is a schematic diagram eight of a third chip provided in an embodiment of the present application.

DETAILED DESCRIPTION

In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c can be single or multiple. The character "/" generally indicates that the previous and next associated objects are in an "or" relationship. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and execution order.

In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

In the embodiments of the present application, words such as "first" and "second" are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

In the embodiments of the present application, words such as "coupling" and "connection" should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

First, some basic concepts involved in the embodiments of this application are explained.

1. System-on-a-chip (SOC) technology and chiplet technology

SOC technology uses photolithography to fabricate multiple circuits with different functions onto the same die. As shown in Figure 1 (a), a first circuit 101, a second circuit 102, a third circuit 103, and a fourth circuit 104 constitute an SOC chip. The SOC chip may also include multiple input/output (I/O) interfaces. Each of the first circuit 101, the second circuit 102, the third circuit 103, and the fourth circuit 104 can be coupled to external devices using the four I/O interfaces in the SOC chip.

Chiplet technology, in contrast to SOC technology, splits a function-rich and large chip into multiple dies, which are then packaged together to form a single chip. As shown in Figure 1 (b), the chiplet technology chip is split into two dies: die 1 and die 2. The first circuit 101 and the second circuit 102 are fabricated on die 1, and the third circuit 103 and the fourth circuit 104 are fabricated on die 2. Die 1 and die 2 are coupled via an interconnect interface. Die 1 and die 2 may also each include multiple I/O interfaces. Each of the first circuit 101 and the second circuit 102 can be coupled to an external device based on the two I/O interfaces in die 1, and each of the third circuit 103 and the fourth circuit 104 can be coupled to an external device based on the two I/O interfaces in die 2.

SOC technology is highly dependent on process technology. For example, as chip manufacturing processes become increasingly advanced, chip technology has evolved from 28 nanometers to 10 nanometers, 7 nanometers, 5 nanometers, and even smaller. However, nanometer technology is approaching its physical limits, and improving chip technology requires new technological approaches. This is where the advantages of chiplet technology become apparent. First, during wafer processing, defective pixels are more likely to appear the further they are from the center of the wafer. Larger wafers increase the defect rate. Chiplet technology divides a single chip into multiple smaller dies, helping to improve yield and reduce manufacturing costs. Second, while the entire SOC chip must be manufactured using advanced process technology, chiplet technology allows different dies to be manufactured using different process technologies. For example, the die containing the logic circuitry can use an advanced process, while the interface die can use a mature process. Advanced processes are more expensive than mature processes, but offer better chip performance. Furthermore, as the nanometer process becomes smaller, the SOC chip design becomes more complex and costly. Chiplet technology offers greater design flexibility. Therefore, chiplet technology offers advantages such as design flexibility, low cost, and a shortened R&D cycle.

2. Open Systems Interconnection (OSI) Reference Model

The OSI reference model, commonly known as the OSI reference model or seven-layer model, is a standard system developed by the International Organization for Standardization for interconnecting computer or communication systems. It is an abstract model consisting of seven layers, encompassing not only a series of abstract terms or concepts but also specific protocols. As shown in Figure 2, the OSI reference model includes the application layer, presentation layer, session layer, transport layer, network layer, data link layer, and physical layer (PHY).

Among them, the application layer can be used to provide an interface between network services and users; the presentation layer can be used to be responsible for data representation, security and compression; the session layer can be used to establish, manage and terminate sessions; the transport layer can be used to define the protocol port number for transmitting data, as well as flow control and error checking; the network layer can be used to perform logical addressing and realize path selection between different networks; the data link layer can be used to perform functions such as establishing logical connections, performing hardware addressing, error checking, etc.; the physical layer can be used to establish, maintain and disconnect physical connections.

The Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard defines implementations from the data link layer to the physical layer (PHY). As shown in Figure 2, the data link layer may include the logical link control (LLC) layer and the medium access control (MAC) layer. For example, the upper half of the data link layer may include the LLC layer or other MAC client layer, and the lower half may include the MAC layer. MAC control may optionally be provided between the LLC and MAC layers. A physical layer signaling sublayer (PLS) may also be provided below the MAC layer (not shown in the figure). The PHY layer may include a reconciliation sublayer (RS), a medium-independent interface (MII), a physical coding sublayer (PCS), a physical medium attachment sublayer (PMA), a physical medium-dependent sublayer (PMD), a medium-dependent interface (MDI), etc. The PHY layer may be coupled with the medium layer.

The transmitting side of the MAC layer can be used to encapsulate data packets from the LLC layer into data frames and send the data frames to the RS layer. The receiving side of the MAC layer can be used to receive data frames from the RS layer and parse the data frames into upper-layer network data.

The RS layer can be used to provide a signal mapping mechanism between the MII and MAC layers (or between the MII and PLS layers). For example, the RS layer's transmitter can convert data from the MAC layer (or PLS layer) into a signal format that complies with the MII interface standard. For example, the first byte of the preamble is translated into the /S signature, data is transparently transmitted during normal transmission, and a /T signature is inserted after the frame check sequence (FCS) at the end of a frame transmission, and an /I signature is inserted after the /T signature. The RS layer's receiver can be used to perform framing on the PCS layer through the MII (e.g., the Gigabit Media Independent Interface (GMII)), search for frame headers, transparently transmit received data to the MAC layer for processing, translate the GMII interface's control signatures, and detect link error data indications provided by the PHY layer. The MII can be used to establish a connection from the MAC layer to the PCS layer, facilitate data transmission between the MAC and PCS layers, and perform link status control, such as detecting link errors.

The PCS layer can be used for functions such as frame header synchronization, encoding and decoding, scrambling and descrambling, and frame rate adjustment. For example, the transmit side of the PCS layer can be used to send data received from the GMII bus to other sublayers of the PHY layer after the above processing, and the receive side of the PCS layer can be used to send data from other sublayers of the PHY layer to the GMII bus after the above processing.

The PMA layer can be used for bit-level multiplexing, bit gearboxing, bit order reversal, and asynchronous clock and data processing. For example, the PMA layer's transmitter side can process data from upper layers (such as the PCS layer) and then send it to the PMD layer. The PMA layer's receiver side can asynchronously process data from the PMD layer and then send it to upper layers for subsequent operations. For example, as shown in Figure 3, the data in the PHY layer can be in the form of data streams. The upper layer of the PMA layer can include n data streams (e.g., 4 in the figure), and the PMA layer can include m data streams (e.g., 2 in the figure), where n is greater than m. During the process of processing the data in the upper layer and sending it to the PMA layer, the first data stream of the upper layer is: 0.6, 0.5, 0.4, 0.3; the second data stream is: 2.9, 2.8, 2.7, 2.6; the third data stream is: 1.6, 1.5, 1.4, 1.3; and the fourth data stream is: 3.8, 3.7, 3.6, 3.5. Bit-level multiplexing at the PMA layer can mean that the PMA layer converts data from four data streams of the upper layer into two data streams of the PMA layer for transmission. The first PMA data stream is: 0.6, 2.9, 0.5, 2.8, 0.4, 2.7, 0.3, 2.6, and the second data stream is: 1.6, 3.8, 1.5, 3.7, 1.4, 3.6, 1.3, 3.5. Bit width conversion at the PMA layer converts the data bit width from the upper layer's bit width (e.g., 80 bits) to the PMA layer's bit width (e.g., 64 bits). Bit order reversal at the PMA layer indicates the transmission order of multiple bits of data in the PMD layer.

The PMD layer can be used to convert parallel data to serial data and vice versa. The circuit used to perform the PMD layer function can also be called a serializer/deserializer (SerDes). For example, the transmitting side of the PMD layer can be used to convert parallel data to serial data, and the receiving side of the PMD can be used to convert serial data to parallel data.

After introducing the basic concepts of the embodiments of the present application, the specific contents of the embodiments of the present application are introduced.

An embodiment of the present application provides an electronic device, as shown in FIG4 , wherein the electronic device 1000 includes a housing (not shown in the figure) and a processing device, wherein the processing device includes a printed circuit board (PCB) (not shown in the figure) and a chip 2000. The chip 2000 includes a main circuit 200, a MAC circuit 300, and a PHY circuit 400. The main circuit 200 may include a circuit for performing a control function, a processing function, or a computing function, or may include a circuit for performing a function of sending and receiving data in a communication network, or may include other circuits, which are not limited in the embodiment of the present application. The MAC circuit 300 may be a circuit for performing MAC layer functions, and the PHY circuit 400 may be a circuit for performing PHY layer functions. Exemplarily, the chip 2000 is a chiplet technology chip.

In some possible implementations, the chip 2000 in FIG. 4 may separate the main circuit 200 into one die, and separate the MAC circuit 300 and the PHY circuit 400 into another die.

In some examples, chip 2000 may be the first chip 2000A as shown in FIG5 . The first chip 2000A includes a first main die 2100A and a first interface die 2200A. The first main die 2100A includes a first main circuit 200A, and the first interface die 2200A includes a first MAC circuit 300A and a first PHY circuit 400A. The first main circuit 200A is coupled to the first MAC circuit 300A, and the first MAC circuit 300A is coupled to the first PHY circuit 400A. The first main die 2100A uses an advanced process, while the first interface die 2200A uses a mature process, resulting in lower hardware costs. Furthermore, the first main die 2100A can be used in conjunction with multiple first interface die 2200A. The number of first main die 2100A and first interface die 2200A can be selected based on the scenario, providing greater design flexibility.

However, the first chip 2000A shown in FIG5 has the following problems:

First, the first PHY circuit 400A includes circuits related to functional logic (used to couple with a link where a function corresponding to the circuit is located), such as circuits for performing PCS layer functions. The first PHY circuit 400A also includes circuits unrelated to functional logic (used to couple with a link where any of the multiple functions is located), such as circuits for performing PMA layer functions and circuits for performing PMD layer functions. The first MAC circuit 300A is a circuit related to functional logic. Because circuits related to functional logic and circuits unrelated to functional logic are coupled to the first interface die 2200A (for example, a circuit with a bandwidth of 56 Gbps for performing PMD layer functions is coupled to the first MAC circuit 300A with a bandwidth of 400 Gbps), in a frame device scenario, there is a problem of cross-board wiring outside the first chip 2000A, or cross-wiring within the first chip 2000A, which increases hardware costs and is not conducive to the first main die 2100A multiplexing multiple first interface dies 2200A. Next, this problem will be illustrated using a frame switch scenario as an example.

As shown in Figure 6 (a), the first main circuit 200A in the first main die 2100A includes an optical module circuit and a switching network circuit. The optical module circuit refers to the message processing circuit on the optical module side, and the switching network circuit refers to the message processing circuit on the switching network side. The first interface die 2200A1 and the first interface die 2200A2 both include a first irrelevant circuit, a second irrelevant circuit, an optical module-related circuit, and a switching network-related circuit. The first irrelevant circuit and the second irrelevant circuit both refer to circuits unrelated to the functional logic of the optical module and the switching network (such as circuits for performing PMA layer functions and circuits for performing PMD layer functions). In other words, the first irrelevant circuit and the second irrelevant circuit can be used to couple with both the link where the optical module is located and the link where the switching network is located. The optical module-related circuit refers to circuits related to the functional logic of the optical module (such as circuits for performing PCS layer functions). In other words, the optical module-related circuit is used to couple with the link where the optical module is located. The switching network-related circuit refers to circuits related to the functional logic of the switching network. In other words, the switching network-related circuit is used to couple with the link where the switching network is located. The first unrelated circuits in the first interface die 2200A1 and the optical module circuits in the first master die 2100A are coupled to the optical module-related circuits in the first interface die 2200A1. Thus, the optical module circuits in the first master die 2100A can be coupled to an external optical module device via the optical module-related circuits and the first unrelated circuits in the first interface die 2200A1. The second unrelated circuits in the first interface die 2200A1 and the switching network circuits in the first master die 2100A are coupled to the switching network-related circuits in the first interface die 2200A1. Thus, the switching network circuits in the first master die 2100A can be coupled to an external switching network device via the switching network-related circuits and the second unrelated circuits in the first interface die 2200A1. The coupling relationships of the various circuits in the second interface die 2200A2 can be referenced to the coupling relationships of the various circuits in the first interface die 2200A1 (as shown in FIG. 6(a)). This embodiment of the present application will not be further described herein. Typically, the first interface die 2200 is manufactured with the same structure. Since the first interface die 2200A1 and the first interface die 2200A2 have the same structure, in actual use, the optical module-related circuits in the first interface die 2200A1 and the optical module-related circuits in the first interface die 2200A2 cannot both be located on the same side as the optical module circuits in the first main die 2100A. For example, in FIG6 (a), the optical module circuits are located on the right side, the optical module-related circuits of the first interface die 2200A2 are located on the right side, and the optical module-related circuits of the second interface die 2200A1 are located on the left side. Refer to the dotted circle in FIG6 (a). This will cause the routing between the first unrelated circuits of the first interface die 2200A1 and the optical module device to cross, and the routing between the second unrelated circuits of the first interface die 2200A1 and the switching network device to cross.

As shown in FIG6(b), unlike FIG6(a), for the first interface die 2200A1 and the first interface die 2200A2, the first and second irrelevant circuits can be coupled to the optical module-related circuits and the switching network-related circuits via a switch. In actual use, the switch is turned on as shown in FIG6(b), whereby the optical module-related circuits in the first interface die 2200A1 are coupled to the second irrelevant circuits, thereby allowing the optical module circuits in the first master die 2100A to be coupled to an external optical module device via the optical module-related circuits and the second irrelevant circuits in the first interface die 2200A1; and the switching network-related circuits in the first interface die 2200A1 are coupled to the first irrelevant circuits, thereby allowing the switching network circuits in the first master die to be coupled to an external switching network device via the switching network-related circuits and the first irrelevant circuits in the first interface die 2200A1. Although there is no single-board wiring crossing outside the first chip, please refer to the dotted circle shown in Figure 6 (b), this will cause the wiring inside the first interface bare chip 2200A1 to cross.

Second, the first interface die 2200A adopts a mature process, and too many circuits in the first chip 2000A are split onto the first interface die 2200A. These circuits cannot use the advanced process of the first main die 2100A (compared with the mature process, the advanced process has better chip performance), so this results in poor performance of the first chip 2000A.

In some other possible implementations, the chip 2000 in FIG. 4 may separate the main circuit 200 and the MAC circuit 300 into one die, and separate the PHY circuit 400 into another die.

In some examples, chip 2000 may be the second chip 2000B as shown in FIG7 . Second chip 2000B includes a second main die 2100B and a second interface die 2200B. Second main die 2100B includes a second main circuit 200B and a second MAC circuit 300B, and second interface die 2200B includes a second PHY circuit 400B. Second main circuit 200B is coupled to second MAC circuit 300B, and second MAC circuit 300B is coupled to second PHY circuit 400B. Second main die 2100B uses an advanced process, while second interface die 2200B uses a mature process, resulting in lower hardware costs. Furthermore, second main die 2100B can be used in conjunction with multiple second interface die 2200Bs, and the number of second main die 2100Bs and second interface die 2200Bs can be selected based on the scenario, providing greater design flexibility.

However, the second chip 2000B shown in FIG7 has the following problems:

First, the second PHY circuit 400B includes circuits related to functional logic (such as circuits for performing PCS layer functions) and circuits unrelated to functional logic (such as circuits for performing PMA layer functions and circuits for performing PMD layer functions). Since the circuits related to functional logic and the circuits unrelated to functional logic are coupled to the second interface bare chip 2200B, in the frame device scenario, there is a problem of crossover of the external single-board wiring of the second chip 2000B, or a problem of crossover of the internal wiring of the second chip 2000B, which increases the hardware cost and is not conducive to the second main bare chip 2100B multiplexing multiple second interface bare chips 2200B. This problem can be specifically referred to the problem corresponding to the first chip 2000A shown in Figure 5, and the embodiments of the present application will not be repeated here.

Second, the second interface die 2200B adopts a mature process, and too many circuits in the second chip 2000B are split onto the second interface die 2200B. These circuits cannot use the advanced process of the second main die 2100B (compared with the mature process, the advanced process has better chip performance), so this results in poor performance of the second chip 2000B.

In some other possible implementations, the chip 2000 in FIG4 may separate the PCS circuit in the PHY circuit 400 into one die, and separate the PMA circuit and PMD circuit in the PHY circuit 400 into another die. The PCS circuit is used to perform PCS layer functions, the PMA circuit is used to perform PMA layer functions, and the PMD circuit is used to perform PMD layer functions.

In some examples, the chip 2000 may be the third chip 2000C as shown in FIG8 . The third chip 2000C includes a first die 2210C and a second die 2220C. The first die 2210C includes a PCS circuit 410C, and the second die 2220C includes a PMA circuit 420C and a PMD circuit 430C. The PCS circuit 410C of the first die 2210C is coupled to the PMA circuit 420C of the second die 2220C, and the PMA circuit 420C is coupled to the PMD circuit 430C.

Exemplarily, the clock domains of the first die 2210C and the second die 2220C are different, and the second die 2220C can convert the clock domain through the PMA circuit 420C. For example, the PMA circuit 420C can be used to convert the clock domain of data between the clock domain of the PCS circuit 410C and the clock domain of the PMD circuit 430C. The clock domain of the PCS circuit 410C can be the clock domain of the first die 2210C, and the clock domain of the PMD circuit 430C can be the clock domain of the second die 2220C.

In the embodiment of the present application, the third chip 2000C shown in FIG8 has the following effects:

First, a die partitioning method in a chiplet is provided, where multiple circuits are split onto different dies. Different dies can be manufactured using different process technologies. For example, the second die 2220C can be manufactured using a mature process, resulting in lower hardware costs.

Second, the first die 2210C can be used in conjunction with multiple second die 2220Cs. The number of first die 2210C and the number of second die 2220C can be selected according to the scenario, which provides high design flexibility.

Third, the second die 2220C includes only the PMA circuit 420C and PMD circuit 430C, which are unrelated to the functional logic. This allows for flexible reuse between different dies at a low cost. For example, the PMA circuit 420C and PMD circuit 430C are unrelated to the functional logic and are used to couple with the link of any of the multiple functions. The PCS circuit 410C is related to the functional logic and is used to couple with the link of the function corresponding to the PCS circuit 410C. By separating the circuits related to the functional logic and the circuits unrelated to the functional logic onto different dies, in a modular device scenario, there is no crossover of single-board traces outside the third die 2000C, nor is there any crossover of traces inside the third die 2000C. This reduces hardware costs, facilitates the reuse of multiple second dies 2220C by the first die 2210C, and eliminates the design confusion caused by designing both circuits related to the functional logic and circuits unrelated to the functional logic on the same die. This is illustrated using a modular switch scenario. For example, as shown in FIG9 , the second die 2220C1 and the second die 2220C2 each include a first irrelevant circuit and a second irrelevant circuit. The first irrelevant circuit and the second irrelevant circuit can be used to couple with either the link where the optical module is located or the link where the switching network is located. The first irrelevant circuit includes a PMA circuit 420C and a PMD circuit 430C, and the second irrelevant circuit includes a PMA circuit 420C and a PMD circuit 430C. The first die 2210C includes a switching network circuit, a first switching network-related circuit, a second switching network-related circuit, an optical module circuit, a first optical module-related circuit, and a second optical module-related circuit. The first optical module-related circuit and the second optical module-related circuit are used to couple with the link where the optical module is located, and the first switching network-related circuit and the second switching network-related circuit are used to couple with the link where the switching network is located. The first switching network-related circuit, the second switching network-related circuit, the first optical module-related circuit, and the second optical module-related circuit all include a PCS circuit 410C. The switching network circuit is used to couple with an external switching network device via the first switching network-related circuit and the first unrelated circuit in the second die 2220C1. The switching network circuit is also used to couple with an external switching network device via the second switching network-related circuit and the second unrelated circuit in the second die 2220C2. The optical module circuit is used to couple with an external optical module device via the second optical module-related circuit and the second unrelated circuit in the second die 2220C1. The optical module circuit is also used to couple with an external optical module device via the first optical module-related circuit and the first unrelated circuit in the second die 2220C2. Because the first unrelated circuit and the second unrelated circuit can be coupled to any link containing any function, there is no problem of external or internal wiring crossing. When the first die 2210C is used in conjunction with multiple second dies 2220C, this can significantly reduce wiring crossings, significantly reducing hardware complexity.

In some possible implementations, the PCS circuit 410C, the PMA circuit 420C, and the PMD circuit 430C in FIG8 all include a transmitting side and a receiving side.

In some examples, as shown in FIG10 , PCS circuit 410C includes PCS transmit circuit 411C and PCS receive circuit 412C, PMA circuit 420C includes PMA transmit circuit 421C and PMA receive circuit 422C, and PMD circuit 430C includes PMD transmit circuit 431C and PMD receive circuit 432C. PCS transmit circuit 411C is coupled to PMA transmit circuit 421C, which in turn is coupled to PMD transmit circuit 431C. PCS receive circuit 412C is coupled to PMA receive circuit 422C, which in turn is coupled to PMD receive circuit 432C.

Exemplarily, PCS transmit circuit 411C processes the data (e.g., encodes it) and sends it to PMA transmit circuit 421C. PMA transmit circuit 421C processes the data (e.g., performs clock domain conversion) and sends it to PMD transmit circuit 431C. PMD transmit circuit 431C processes the data (e.g., converts parallel data into serial data) and sends it to a medium, including but not limited to PCB traces, copper cables, and optical fibers.

Exemplarily, the PMD receiving circuit 432C receives data from the medium, processes the data accordingly (e.g., converts serial data into parallel data), and sends the data to the PMA receiving circuit 422C. The PMA receiving circuit 422C processes the data accordingly (e.g., performs clock domain conversion) and sends the data to the PCS circuit 410C. The PCS circuit 410C processes the data accordingly (e.g., performs decoding).

Exemplarily, the PMA transmit circuit 421C includes multiple lanes, the PMD transmit circuit 431C includes multiple lanes, each lane in the PMA transmit circuit 421C is coupled to each lane in the PMD transmit circuit 431C in a one-to-one correspondence, each lane in the PMD transmit circuit 431C may include multiple parallel channels and one serial channel, and each lane in the PMD transmit circuit 431C is configured to convert data in the parallel channels into data in the serial channels. The PMA receive circuit 422C includes multiple lanes, the PMD receive circuit 432C includes multiple lanes, each lane in the PMA receive circuit 422C is coupled to each lane in the PMD receive circuit 432C in a one-to-one correspondence, each lane in the PMD receive circuit 432C may include multiple parallel channels and one serial channel, and each lane in the PMD receive circuit 432C is configured to convert data in the serial channels into data in the parallel channels.

In the embodiment of the present application, the PCS circuit 410C, the PMA circuit 420C and the PMD circuit 430C all include a transmitting side and a receiving side. The PMA transmitting circuit 421C, the PMA receiving circuit 422C, the PMD transmitting circuit 431C and the PMD receiving circuit 432C are all located on different bare chips from the PCS transmitting circuit 411C and the PCS receiving circuit 412C. This has low hardware cost, high design flexibility, and helps the first bare chip 2210C to multiplex multiple second bare chips 2220C.

In some possible implementations, the third chip 2000C in FIG8 may include a third main circuit and a third MAC circuit. Next, a method for separating the third main circuit and the third MAC circuit from the aforementioned first die 2210C and second die 2220C is introduced.

In some examples, as shown in FIG11( a ), the third chip 2000C further includes a third main die 2100C, in which the third main circuit 200C and the third MAC circuit 300C are disposed. The third main circuit 200C is coupled to the third MAC circuit 300C, and the third MAC circuit 300C is coupled to the PCS circuit 410C. In the embodiment of the present application, the third main die 2100C, where the third main circuit 200C is located, utilizes an advanced process to decouple as many circuits from the third main die 2100C as possible. The first die 2210C and the second die 2220C, where these circuits are located, utilize mature processes. This can reduce costs, increase design flexibility, and resolve issues such as external board wiring crossings and internal wiring crossings.

In other examples, as shown in FIG11( b ), the third chip 2000C further includes a third master die 2100C, the third master circuit 200C is disposed in the third master die 2100C, the third MAC circuit 300C is disposed in the first die 2210C, the third master circuit 200C is coupled to the third MAC circuit 300C, and the third MAC circuit 300C is coupled to the PCS circuit 410C. In this embodiment of the present application, the third MAC circuit 300C is further decoupled from the third master die 2100C, further reducing costs, improving design flexibility, and resolving issues such as crossover of external and internal board traces.

In yet other examples, as shown in FIG11( c ), the third master circuit 200C and the third MAC circuit 300C are both disposed in the first die 2210C, the third master circuit 200C being coupled to the third MAC circuit 300C, and the third MAC circuit 300C being coupled to the PCS circuit 410C. In the embodiment of the present application, the first die 2210C where the third master circuit 200C is located uses an advanced process, while the second die 2220C uses a mature process. Placing as many circuits as possible on the first die 2210C can improve the performance of the third chip 2000C and reduce the package size.

In some possible implementations, the third MAC circuit 300C shown in FIG. 11 (a), (b), or (c) includes a transmitting side and a receiving side.

In some examples, taking the third MAC circuit 300C as an example, which is provided on the first die 2210C, as shown in FIG12 , the third MAC circuit 300C includes a MAC transmit circuit 310C and a MAC receive circuit 320C. The MAC transmit circuit 310C is coupled to the PCS transmit circuit 411C, and the MAC receive circuit 320C is coupled to the PCS receive circuit 412C.

Exemplarily, the MAC transmitting circuit 310C processes the data accordingly and transmits the data to the PCS transmitting circuit 411C. Exemplarily, the MAC receiving circuit 320C receives the data from the PCS receiving circuit 412C and processes the data accordingly.

In the embodiment of the present application, the third MAC circuit 300C includes a transmitting side and a receiving side. The MAC transmitting circuit 310C and the MAC receiving circuit 320C are both arranged in the first bare die 2210C, which has low hardware cost and high design flexibility. If the first bare die 2210C adopts an advanced process, the MAC transmitting circuit 310C and the MAC receiving circuit 320C can also adopt the advanced process to improve the performance of the third chip 2000C.

In some possible implementations, since the clock domains of the first die 2210C and the second die 2220C are different and there is a bandwidth deviation, the first die 2210C may have a bandwidth acceleration ratio, and the bandwidth of the first die 2210C transmitting data is greater than the bandwidth of the second die 2220C transmitting data. Therefore, a buffer (buffer/cache) can be set in the PMA transmitting circuit 421C for buffering.

In one example, as shown in FIG13 , the first die 2210C or the second die 2220C further includes a regulation circuit 440C, and the PMA transmit circuit 421C further includes a buffer (not shown). The MAC transmit circuit 310C is coupled to the regulation circuit 440C, which in turn is coupled to the PMA transmit circuit 421C. The buffer is configured to store data while the MAC transmit circuit 310C is transmitting data to the PMA transmit circuit 421C via the PCS transmit circuit 411C. The PMA transmit circuit 421C is configured to control the MAC transmit circuit 310C, via the regulation circuit 440C, to reduce the bandwidth of the transmitted data when the amount of data stored in the buffer exceeds a first preset value.

Exemplarily, the buffer may be a first-in, first-out (FIFO) buffer. Exemplarily, the size of the buffer may be determined based on the amount of resources available to the second die 2220C. Alternatively, the size of the buffer may be determined based on the bit width of a parallel channel in a lane of the PMD transmit circuit 431C. For example, the size of the buffer may be 4 times, 8 times, 16 times, 32 times, 64 times, 128 times, or the like, the bit width of a parallel channel. Alternatively, the size of the buffer may be determined based on the length of the transmission path between the first die 2210C and the second die 2220C. For example, if the first die 2210C and the second die 2220C are packaged on a PCB, the size of the buffer may be determined based on the length of the transmission path between the PCS circuit 410C and the PMA transmit circuit 421C.

For example, the PMA transmitting circuit 421C controls the MAC transmitting circuit 310C to reduce bandwidth via the adjustment circuit 440C. When the amount of data stored in the buffer exceeds a first preset value, the PMA transmitting circuit 421C sends capacity information to the adjustment circuit 440C, indicating that the amount of data stored in the buffer exceeds the first preset value. The adjustment circuit 440C sends first indication information to the MAC transmitting circuit 310C based on the capacity information, and the MAC transmitting circuit 310C reduces the bandwidth of the transmitted data based on the first indication information. Alternatively, the PMA transmitting circuit 421C controls the MAC transmitting circuit 310C to reduce bandwidth via the adjustment circuit 440C. The PMA transmitting circuit 421C sends the amount of data stored in the buffer to the adjustment circuit 440C at preset intervals. When the amount of data stored in the buffer is not greater than the first preset value, the adjustment circuit 440C sends second indication information to the MAC transmitting circuit 310C, indicating that the MAC transmitting circuit 310C does not need to reduce the bandwidth of the transmitted data. When the data volume is greater than the first preset value, the adjustment circuit 440C stops sending the second indication information. If the MAC sending circuit 310C still does not receive the second indication information after a preset time interval, it reduces the bandwidth for sending data.

In the embodiment of the present application, by providing a regulation circuit 440C, when the amount of data stored in the buffer of the PMA transmitting circuit 421C is greater than a first preset value, the bandwidth of the transmitting side of the first bare chip 2210C is adjusted, thereby alleviating the problem that the data flow of the first bare chip 2210C is too large and the second bare chip 2220C cannot process it in time.

In some possible implementations, the third chip 2000C in FIG. 8 further includes a functional circuit, and the functional circuit can be divided on both the first die 2210C and the second die 2220C.

In some examples, as shown in (a) of FIG. 14 , the functional circuit 450C is disposed on the second die 2220C, and as shown in (b) of FIG. 14 , the functional circuit 450C is disposed on the first die 2210C, and the PCS circuit 410C is coupled to the PMA circuit 420C through the functional circuit 450C. The embodiments of the present application do not limit the number and specific functions of the functional circuit 450C.

In the embodiment of the present application, other functional circuits 450C may be included between the PCS circuit 410C and the PMA circuit 420C. The functional circuits 450C may be configured according to application requirements. In this way, the functions of the third chip 2000C may be configured more flexibly.

In some possible implementations, functional circuit 450C may include a pre-inverting circuit. For example, PCS transmit circuit 411C is coupled to the PMA transmit circuit via the pre-inverting circuit, and regulation circuit 440C is also coupled to the pre-inverting circuit. When the amount of data stored in the buffer exceeds a second preset value, PMA transmit circuit 421C instructs the pre-inverting circuit via regulation circuit 440C to reduce the bandwidth of data transmitted by PCS circuit 410C, where the second preset value is less than the first preset value. Optionally, a buffer circuit may be provided within the pre-inverting circuit.

In an embodiment of the present application, when the amount of data stored in the buffer exceeds a first preset value, the PMA transmit circuit 421C can control the MAC transmit circuit 310C to reduce the transmit bandwidth via the adjustment circuit 440C. However, it will take some time for the PCS circuit 410C to follow the MAC transmit circuit 310C in reducing the transmit bandwidth. If, during this period, the buffer is full of data while the PCS transmit circuit 411C is still sending data to the PMA transmit circuit 421C at a high bandwidth, the PMA transmit circuit 421C will not be able to process the data in time. When the amount of data stored in the buffer exceeds a second preset value, the adjustment circuit 440C and the pre-inverting circuit reduce the transmit bandwidth of the PCS transmit circuit 411C. Furthermore, when the amount of data stored in the buffer exceeds the first preset value, the adjustment circuit 440C reduces the transmit bandwidth of the MAC transmit circuit 310C. This alleviates the problem of the buffer being full while the PCS transmit circuit 411C is still sending data to the PMA transmit circuit 421C at a high bandwidth, causing the PMA transmit circuit 421C to be unable to process the data in time.

In some possible implementations, functional circuit 450C may include a forward error correction (FEC) circuit. Exemplarily, the FEC circuit is used to re-encode the data encoded by PCS circuit 410C, automatically correcting a certain amount of bit errors and reducing the bit error rate. Exemplarily, the FEC circuit may be a Reed-Solomon forward error correction (RSFEC) circuit, or an FEC circuit using other encoding methods, which is not limited in this embodiment of the present application.

In this embodiment of the present application, an FEC circuit is included between the PCS circuit 410C and the PMA circuit 420C to reduce the bit error rate. If the FEC circuit is located on the second die 2220C and the second die 2220C uses a mature process, the cost of the third chip 2000C can be further reduced. If the FEC circuit is located on the first die 2210C and the first die 2210C uses an advanced process, the FEC circuit can also be manufactured using an advanced process, thereby improving the performance of the third chip 2000C.

In some possible implementations, the FEC circuit in the functional circuit 450C includes a transmitting side and a receiving side.

In some examples, taking the FEC circuitry provided on the first die 2210C as an example, as shown in FIG15 , the FEC circuitry includes an FEC transmit circuit 451C and an FEC receive circuit 452C. The PCS transmit circuit 411C is coupled to the PMA transmit circuit 421C via the FEC transmit circuit 451C. The PCS receive circuit 412C is coupled to the PMA receive circuit 422C via the FEC receive circuit 452C.

Exemplarily, FEC transmission circuit 451C receives data from PCS transmission circuit 411C, performs forward error correction on the data, and sends the processed data to PMA transmission circuit 421C. Exemplarily, FEC reception circuit 452C receives data from PMA reception circuit 422C, performs forward error correction on the data, and sends the processed data to PCS reception circuit 412C.

In the embodiment of the present application, the FEC circuit includes a transmitting side and a receiving side, and can reduce the bit error rate for both the transmitting and receiving links in the third chip 2000C. If the FEC transmitting circuit 451C and the FEC receiving circuit 452C are provided on the second die 2220C, and the second die 2220C uses a mature process, the cost of the third chip 2000C can be further reduced. If the FEC transmitting circuit 451C and the FEC receiving circuit 452C are provided on the first die 2210C, the first die 2210C can use an advanced process, and the FEC transmitting circuit 451C and the FEC receiving circuit 452C can also use an advanced process, thereby improving the performance of the third chip 2000C.

In some possible implementations, the PMD receiving circuit 432C may adjust performance parameters according to the forward error correction result of the data by the FEC receiving circuit 452C.

For example, as shown in FIG16 , the first die 2210C or the second die 2220C further includes a feedback circuit 460C. The FEC receiving circuit 452C is coupled to the feedback circuit 460C, which is in turn coupled to the PMD receiving circuit 432C. The FEC receiving circuit 452C is configured to send error information to the PMD receiving circuit 432C via the feedback circuit 460C when the bit error rate (BER) obtained through forward error correction (FEC) is not zero. The feedback circuit 460C is a serial interface. The PMD receiving circuit 432C adjusts performance parameters to reduce the error rate of data transmission. The FEC receiving circuit 452C receives data from the PMD receiving circuit 432C, performs FEC on the data, and obtains error information. The error information indicates the bit error rate of the data. The PMD receiving circuit 432C can adjust the performance parameters of the PMD receiving circuit 432C based on the error information.

In an embodiment of the present application, the amount of error information data to be transmitted is large. To avoid wasting bandwidth between bare chips, the feedback circuit 460C for transmitting error information is set to a serial interface, and the error information is sent in the form of serial data, which can reduce the bandwidth of data transmission between bare chips.

In some possible implementations, as shown in FIG16 , the first die 2210C further includes a first interface circuit 471C, and the second die 2220C further includes a second interface circuit 472C. The first interface circuit 471C and the second interface circuit 472C are coupled, and the first die 2210C is coupled to the second die 2220C via the first interface circuit 471C and the second interface circuit 472C. Exemplarily, both the first interface circuit 471C and the second interface circuit 472C are low-latency interfaces, and the latency of both the first interface circuit 471C and the second interface circuit 472C is less than a preset threshold, for example, 20 nanoseconds.

In the embodiment of the present application, the first die 2210C is coupled to the second die 2220C via the first interface circuit 471C and the second interface circuit 472C. The first die 2210C and the second die 2220C can communicate via the first interface circuit 471C and the second interface circuit 472C, establishing a foundation for communication between the first die 2210C and the second die 2220C. Furthermore, selecting low-latency interfaces as the first interface circuit 471C and the second interface circuit 472C can reduce the communication latency between the first die 2210C and the second die 2210C, thereby improving the performance of the third chip 2000C.

In the several embodiments provided in this application, it should be understood that the disclosed electronic devices, chip systems, and chips can be implemented in other ways. For example, the embodiments described above are merely illustrative. For example, the division of the circuit is only a logical function division. In actual implementation, there may be other division methods, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, which may be electrical, mechanical or other forms.

The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims (12)

A chip, characterized in that the chip includes a first die and a second die; the first die includes a physical coding sublayer PCS circuit, and the second die includes a physical medium access sublayer PMA circuit and a physical medium dependent PMD circuit; The PCS circuit of the first die is coupled to the PMA circuit of the second die; the PMA circuit is coupled to the PMD circuit. The chip according to claim 1, wherein the PCS circuit includes a PCS transmitting circuit and a PCS receiving circuit, the PMA circuit includes a PMA transmitting circuit and a PMA receiving circuit, and the PMD circuit includes a PMD transmitting circuit and a PMD receiving circuit; The PCS transmitting circuit is coupled to the PMA transmitting circuit, and the PMA transmitting circuit is coupled to the PMD transmitting circuit; The PCS receiving circuit is coupled to the PMA receiving circuit, and the PMA receiving circuit is coupled to the PMD receiving circuit. The chip according to claim 2, wherein the first die or the second die further comprises a functional circuit; The PCS circuit is coupled to the PMA circuit through the functional circuit. The chip according to claim 3, wherein the functional circuit includes a forward error correction (FEC) circuit. The chip according to claim 4, wherein the FEC circuit comprises an FEC transmitting circuit and an FEC receiving circuit; The PCS transmitting circuit is coupled to the PMA transmitting circuit via the FEC transmitting circuit; The PCS receiving circuit is coupled to the PMA receiving circuit through the FEC receiving circuit. The chip according to claim 5, wherein the first die or the second die further comprises a feedback circuit; the FEC receiving circuit is coupled to the feedback circuit, and the feedback circuit is coupled to the PMD receiving circuit; The FEC receiving circuit is used to send error information to the PMD receiving circuit through the feedback circuit when the bit error rate obtained by forward error correction is not 0, and the feedback circuit is a serial interface. The chip according to any one of claims 2 to 6, wherein the first die further comprises a media access control (MAC) circuit; and the MAC circuit is coupled to the PCS circuit. The chip according to claim 7, wherein the MAC circuit comprises a MAC sending circuit and a MAC receiving circuit; The MAC transmitting circuit is coupled to the PCS transmitting circuit; and the MAC receiving circuit is coupled to the PCS receiving circuit. The chip according to claim 8, wherein the first die or the second die further comprises a regulating circuit, and the PMA transmitting circuit further comprises a buffer; the MAC transmitting circuit is coupled to the regulating circuit, and the regulating circuit is coupled to the PMA transmitting circuit; The buffer is used to store the data during the process in which the MAC transmitting circuit sends the data to the PMA transmitting circuit through the PCS transmitting circuit; The PMA sending circuit is configured to control the MAC sending circuit to reduce a bandwidth for sending data through the regulating circuit when the amount of the data stored in the buffer is greater than a preset value. The chip according to any one of claims 1 to 9, wherein the first die further comprises a first interface circuit, and the second die further comprises a second interface circuit; The first interface circuit and the second interface circuit are coupled, and the first die is coupled to the second die via the first interface circuit and the second interface circuit. A processing device, characterized in that the device comprises a printed circuit board and the chip according to any one of claims 1 to 10. An electronic device, characterized in that the electronic device comprises a housing and the processing device according to claim 11.