WO2025161061A1 - Multi-beam phased array architecture based on time division multiplexing, chip, and electronic device - Google Patents

Abstract

The present invention relates to the technical field of antennas, and provides a multi-beam phased array architecture based on time division multiplexing, a chip, and an electronic device. Two beam input interfaces are connected to four phase shift attenuation channels by means of power distribution networks; the four phase shift attenuation channels are connected to two antenna channels by means of power synthesis networks; and a control unit is connected to the four phase shift attenuation channels and is used for controlling on and off of the four phase shift attenuation channels, so that only a signal input by any beam input interface is processed at any moment. According to the present invention, a new overall architecture and a brand-new working mode of front-end channels are used, so that power distribution and synthesis from multiple beam signals to multiple antenna ports are realized. A control unit is added to each phase shift attenuation channel, and on and off of each channel signal is controlled by a clock signal with a certain frequency, so that it is ensured that back-off of the power of only one beam signal is required at any moment. The multi-beam phased array architecture has high symmetry, small layout area, and high efficiency.

Description

A time-division multiplexed multi-beam phased array architecture, chip, and electronic device

This application claims priority to the Chinese patent application filed with the China Patent Office on February 2, 2024, with application number 202410151663.7 and invention name “A time-division multiplexed multi-beam phased array architecture, chip and electronic device”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present invention relates to the field of antenna technology, and in particular to a time-division multiplexed multi-beam phased array architecture, chip, and electronic equipment.

Background Art

With the rapid development of communication technology in recent years, the demand for wireless transmission data rates has increased, and system capacity has become a major bottleneck. Currently, most major commercial communication systems operate below 6 GHz. Increasing the operating frequency is an effective way to address this bottleneck. Over the past decade, millimeter-wave communication technology has developed rapidly, especially phased array technology, which has attracted widespread attention due to its ability to increase equivalent isotropic radiated power (EIRP), reduce noise figure, and flexibly adjust beam direction.

Based on the traditional phased array, the multi-beam analog beamforming RF front-end array shares an antenna array and generates multiple independent communication beams at the same time. Without sacrificing beam accuracy, it can greatly improve the utilization efficiency of the channel and antenna array, thereby increasing the capacity of the communication system.

At present, there are still some key technical challenges to be overcome in multi-beam millimeter-wave beamforming RF front-end technology. Due to the complexity of multi-beamforming connections, the arrays reported so far are often small in scale and the single-channel chip area is large.

For antenna arrays, the spacing between adjacent antenna elements is typically half a wavelength to avoid grating lobes. Each antenna element occupies a fixed chip area. For an N-beam RF front end, each antenna must connect to N phase-shifting attenuation paths, significantly limiting the chip area available for each path.

Furthermore, the transmitter RF front end, due to the need to process multiple signals, has a higher peak-to-average ratio (PAR), meaning the output power needs to be backed off more deeply to ensure linear amplification of the output signal. However, for typical amplifiers, increasing the output power back-off often means a decrease in overall transmitter efficiency. A key challenge for millimeter-wave multi-beam phased arrays is how to mitigate the efficiency issues caused by power back-off due to the increase in beam signals.

Summary of the Invention

In view of the above problems, the present invention is proposed to provide a time-division multiplexed multi-beam phased array architecture, chip and electronic device that solve the above problems or partially solve the above problems.

A first aspect of an embodiment of the present invention provides a time-division multiplexed multi-beam phased array architecture, the multi-beam phased array architecture comprising: two beam input interfaces, four phase shift attenuation channels, two antenna channels, and a control unit;

The two beam input interfaces are connected to the four phase shift attenuation channels through a power distribution network;

The four phase-shift attenuation channels are connected to the two antenna channels via a power combining network;

The control unit is connected to the four phase-shift attenuation channels and is used to control the on and off of the four phase-shift attenuation channels so that at any time, each antenna channel only processes the signal input by one beam input interface.

Optionally, the two beam input interfaces are arranged on the left side of the chip layout;

The four phase-shift attenuation channels are arranged vertically on the chip layout;

The two antenna channels are arranged on the right side of the chip layout.

Optionally, the two beam input interfaces are connected to the four phase shift attenuation channels through two 1-to-2 power distribution networks;

The four phase-shift attenuation channels are connected to the two antenna channels through two 2-to-1 power combining networks.

Optionally, the control unit includes: two inverters and four switches;

The output end of each of the four phase-shift attenuation channels is connected to the power synthesis network through a switch;

Two inverters are used to invert the clock signal, so as to send the clock signal and the inverted signal of the clock signal to the target switch group;

The target switch group is: two phase-shift attenuation channels connected to the same beam input interface among the four phase-shift attenuation channels, and switches connected to their respective output ends.

Optionally, the output end of the first phase-shift attenuation channel connected to the first beam input interface is connected to the input end of the first switch;

The output end of the first switch is connected to the first branch in the power synthesis network;

An output end of the second phase-shift attenuation channel connected to the first beam input interface is connected to an input end of the second switch;

The output end of the second switch is connected to the second branch of the power combining network;

The output end of the third phase-shift attenuation channel connected to the second beam input interface is connected to the input end of the third switch;

The output end of the third switch is connected to the third branch of the power synthesis network;

an output end of the fourth phase-shift attenuation channel connected to the second beam input interface, and connected to an input end of the fourth switch;

The output end of the fourth switch is connected to the fourth branch of the power synthesis network;

The first switch and the fourth switch are controlled by an external clock signal and are closed or opened at the same time;

The second switch and the third switch are controlled by an inverted signal of the clock signal, are closed or opened at the same time, and are always in an opposite state to the first switch and the fourth switch;

In the power synthesis network, the end of the first branch is connected to the end of the third branch and then connected to the first antenna channel;

After the end of the second branch is connected to the end of the fourth branch, it is connected to the second antenna channel.

Optionally, a cross-layer is used at each routing intersection of the power distribution network or the power synthesis network.

Optionally, the four switches are all controlled by a clock signal of a preset frequency;

At any time, the target switch group has: one switch in a closed state and another switch in an open state.

A second aspect of an embodiment of the present invention provides a chip, comprising a time-division multiplexed multi-beam phased array architecture as described in any one of the first aspects.

A third aspect of an embodiment of the present invention provides an electronic device, comprising a time-division multiplexed multi-beam phased array architecture as described in any one of the first aspects.

The time-division multiplexed multi-beam phased array architecture provided by the present invention includes: two beam input interfaces, four phase-shift attenuation channels, two antenna channels and a control unit; the two beam input interfaces are connected to the four phase-shift attenuation channels through a power distribution network.

The four phase-shift attenuation channels are connected to the two antenna channels through a power synthesis network; the control unit is connected to the four phase-shift attenuation channels and is used to control the on and off of the four phase-shift attenuation channels so that at any time, only the signal input from any beam input interface is processed.

The time-division multiplexed multi-beam phased array architecture proposed in this invention is different from the traditional phased array architecture. It creatively adopts a new overall architecture and a new front-end channel working mode to achieve the power distribution and synthesis of 2-beam signals to 2 antenna ports. In each phase shift attenuation channel, a control The control unit uses a clock signal of a certain frequency to control the on and off of the channel signal, ensuring that only the power of one beam signal needs to be retracted at any time. In other words, it ensures the linear amplification of the signal and avoids the efficiency problem of power retraction caused by the increase of beam signals.

In addition, the phase-shift attenuation channels are arranged vertically in sequence, ensuring good consistency in the surrounding environment. The use of cross-jump layers at the intersection of the power distribution network and the power synthesis network can better ensure the consistency of length, making the multi-beam phased array architecture highly symmetrical.

A low-frequency clock signal is integrated within each phase-shift attenuation channel. As many circuit modules as possible are reused, especially amplifiers that take up more space and consume more current. The core modules of the phased array, the shifter and attenuator, are jointly designed and tightly laid out. Lumped models are used instead of transmission lines to save area, resulting in a small layout for the multi-beam phased array architecture.

A clock signal of a certain frequency controls the on-off switching of channel signals, ensuring that each antenna channel only processes signals from a specific beam interface at any given time. This allows the front end of each antenna channel to meet linear signal amplification requirements without requiring additional power backoff, improving overall transmitter efficiency and enhancing the efficiency of the multi-beam phased array architecture. Therefore, the time-division multiplexed multi-beam phased array architecture proposed in this invention is highly practical.

The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 schematically shows a circuit structure diagram of a time-division multiplexed multi-beam phased array architecture;

FIG2 schematically shows a modular schematic diagram of a chip;

FIG3 schematically shows a modular diagram of an electronic device.

Specific embodiments

To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the following The accompanying drawings in the embodiments clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

The present invention proposes a time-division multiplexed multi-beam phased array architecture, which includes: two beam input interfaces, four phase-shift attenuation channels, two antenna channels and a control unit; the two beam input interfaces are connected to the four phase-shift attenuation channels through a power distribution network.

The four phase-shift attenuation channels are connected to the two antenna channels through a power synthesis network; the control unit is connected to the four phase-shift attenuation channels and is used to control the on and off of the four phase-shift attenuation channels so that at any time, only the signal input from any beam input interface is processed.

To better explain and illustrate the time-division multiplexed multi-beam phased array architecture proposed in the present invention, reference is made to the circuit structure diagram of a time-division multiplexed multi-beam phased array architecture shown in FIG1 . FIG1 includes: two beam input interfaces BEAM1 and BEAM2, four phase shift and attenuation channels PSAC1, PSAC2, PSAC3, and PSAC4, two antenna channels T1 and T2, and a control unit. The two antenna channels T1 and T2 are respectively connected to the antenna output interfaces ANT1 and ANT2.

To more intuitively illustrate the circuit structure, Figure 1 illustrates a control unit consisting of switches S1, S2, S3, and S4, and inverters INV1 and INV2. It should be noted that Figure 1 illustrates exemplary connections and components, and does not imply that the time-division multiplexed multi-beam phased array architecture proposed in the present invention is limited to these connections and components. Any circuit structure or component that can achieve the corresponding function can be replaced based on the technical solution disclosed in the present invention, and no specific examples are given in the present embodiments.

In terms of layout, a better layout is: the two beam input interfaces BEAM1 and BEAM2 are arranged on the left side of the chip layout; the four phase-shift attenuation channels PSAC1, PSAC2, PSAC3, and PSAC4 are arranged vertically on the chip layout; and the two antenna channels T1 and T2 are arranged on the right side of the chip layout.

The two beam input interfaces BEAM1 and BEAM2 are connected to the four phase-shift attenuation channels PSAC1, PSAC2, PSAC3, and PSAC4 through two 1-to-2 power distribution networks; the four phase-shift attenuation channels PSAC1, PSAC2, PSAC3, and PSAC4 are connected to the two antenna channels T1 and T2 through two 2-to-1 power combining networks.

The control unit includes: four switches S1, S2, S3, S4, and two inverters INV1, INV2. Since the control switch needs to control the on and off of the phase shift attenuation channel, therefore:

The output end of each of the four phase-shift attenuation channels PSAC1, PSAC2, PSAC3, and PSAC4 needs to pass through a switch and then be connected to the power combining network. As shown in Figure 1, the output end of the phase-shift attenuation channel PSAC1 passes through switch S1 and then is connected to the power combining network; the output end of the phase-shift attenuation channel PSAC2 passes through switch S2 and then is connected to the power combining network; the output end of the phase-shift attenuation channel PSAC3 passes through switch S3 and then is connected to the power combining network; and the output end of the phase-shift attenuation channel PSAC4 passes through switch S4 and then is connected to the power combining network.

The four phase-shift attenuation channels (PSAC1, PSAC2, PSAC3, and PSAC4) are arranged vertically in sequence, ensuring good consistency in the surrounding environment. Low-frequency clock signals are integrated within each phase-shift attenuation channel, maximizing the reuse of circuit modules, particularly amplifiers, which consume a lot of area and current. The core modules of the phased array, the shifters and attenuators, are co-designed and tightly packed. Lumped transmission lines are used to save space, resulting in a compact layout for the multi-beam phased array architecture.

The two inverters are used to invert the clock signal CLK, thereby sending the clock signal CLK and its inverse to a target switch group. A target switch group refers to the switches connected to the outputs of two of the four phase-shift attenuation channels connected to the same beam input interface. Specifically, switches S1 and S2 form one target switch group, while switches S3 and S4 form another target switch group.

The output end of the first phase shift attenuation channel PSAC1 connected to the first beam input interface BEAM1 is connected to the input end of the first switch S1; the output end of the first switch S1 is connected to the first branch A1 in the power combining network.

The output end of the second phase shift attenuation channel PSAC2 connected to the first beam input interface BEAM1 is connected to the input end of the second switch S2; the output end of the second switch S2 is connected to the second branch A2 of the power combining network.

The output end of the third phase shift attenuation channel PSAC3 connected to the second beam input interface BEAM2 is connected to the input end of the third switch S3; the output end of the third switch S3 is connected to the third branch A3 of the power combining network.

The output end of the fourth phase shift attenuation channel PSAC4 connected to the second beam input interface BEAM2 is connected to the input end of the fourth switch S4; the output end of the fourth switch S4 is connected to the power synthesis network. The fourth branch is connected to S4.

The first and fourth switches S1 and S4 are controlled by an externally input clock signal CLK and are closed or opened simultaneously. The second and third switches S2 and S3 are controlled by the inverted version of the clock signal CLK and are closed or opened simultaneously, always in the opposite state to the first and fourth switches S1 and S4. Specifically, the four switches S1, S2, S3, and S4 are all controlled by a clock signal CLK of a preset frequency. The difference is that after the clock signal CLK is inverted by two inverters INV1 and INV2, two in-phase clock signals and two inverted clock signals are generated, respectively, to control the four switches.

Therefore, for any target switch group, at any given moment, one switch is closed and the other is open. Specifically, when the first switch S1 is closed, the second switch S2 is open; when the first switch S1 is open, the second switch S2 is closed. When the third switch S3 is closed, the fourth switch S4 is open; and when the third switch S3 is open, the fourth switch S4 is closed. Furthermore, the first and third switches S1 and S3 are closed or open simultaneously, while the second and fourth switches S2 and S4 are closed or open simultaneously.

Through this control method, a control unit is added to each phase-shift attenuation channel, and a clock signal of a certain frequency controls the on and off of the channel signal, ensuring that only the power of one beam signal needs to be backed off at any time. In other words, linear amplification of the signal is guaranteed. The front end of each antenna channel does not need to back off more power to meet the linear amplification of the signal, which is beneficial to improving the overall transmitter efficiency, avoiding the efficiency problem of power back-off caused by the increase of beam signals, and making the multi-beam phased array architecture highly efficient.

In the power combining network, a better connection method is: the end of the first branch A1 in the power combining network is connected to the end of the third branch A3 in the power combining network, and then connected to the first antenna channel T1; the end of the second branch A2 in the power combining network is connected to the end of the fourth branch A4 in the power combining network, and then connected to the second antenna channel T2.

Based on the above connection method, combined with Figure 1, it can be seen that crossover layers can be used at the intersection of the power distribution network or the power combining network. Using crossover layers at the intersection of the power distribution network and the power combining network can effectively ensure the consistency of the routing length, thereby achieving high symmetry in the multi-beam phased array architecture.

Based on the above time-division multiplexed multi-beam phased array architecture, simulation is performed in the millimeter wave Ka band. Tests have shown that the proposed time-division multiplexing (TDDM) multi-beam phased array antenna architecture can operate over a range of 25 GHz to 31 GHz. In the Ka band, this phased array chip layout achieves excellent TDDM performance within a compact footprint, significantly improving transmitter efficiency. This demonstrates the practicality of the proposed TDDM multi-beam phased array architecture.

Based on the above-mentioned time-division multiplexed multi-beam phased array architecture, referring to Figure 2, the present invention also proposes a chip, which includes any of the time-division multiplexed multi-beam phased array architectures described above, and the chip uses the time-division multiplexed multi-beam phased array architecture as a transmitter for communication.

Based on the above-mentioned time-division multiplexed multi-beam phased array architecture, referring to Figure 3, the present invention also proposes an electronic device, which includes any of the time-division multiplexed multi-beam phased array architectures described above, and the electronic device uses the time-division multiplexed multi-beam phased array architecture as a transmitter for communication.

Through the above examples, the time-division multiplexed multi-beam phased array architecture proposed in the present invention includes: two beam input interfaces, four phase-shift attenuation channels, two antenna channels and a control unit; the two beam input interfaces are connected to the four phase-shift attenuation channels through a power distribution network.

The four phase-shift attenuation channels are connected to the two antenna channels through a power synthesis network; the control unit is connected to the four phase-shift attenuation channels and is used to control the on and off of the four phase-shift attenuation channels so that at any time, only the signal input from any beam input interface is processed.

The time-division multiplexed multi-beam phased array architecture proposed in this invention differs from the traditional phased array architecture in that it creatively adopts a new overall architecture and a completely new front-end channel operating mode, realizing the power distribution and synthesis of two-beam signals to two antenna ports. A control unit is added to each phase-shift attenuation channel, and a clock signal of a certain frequency controls the on-off of the channel signal, ensuring that only the power of one beam signal needs to be backed off at any time. In other words, linear signal amplification is guaranteed, avoiding the efficiency problem of power back-off caused by the increase of beam signals.

In addition, the phase-shift attenuation channels are arranged vertically in sequence, ensuring good consistency in the surrounding environment. The use of cross-jump layers at the intersection of the power distribution network and the power synthesis network can better ensure the consistency of length, making the multi-beam phased array architecture highly symmetrical.

The low-frequency clock signal is integrated into each phase-shift attenuation channel, and as many circuit modules as possible are reused, especially amplifiers that occupy more area and consume more current. The core modules of the phased array: the shifter and attenuator are jointly designed and tightly laid out. The transmission line uses a lumped model to save area. The multi-beam phased array architecture has a small layout area.

A clock signal of a certain frequency controls the on-off switching of channel signals, ensuring that each antenna channel only processes signals from a specific beam interface at any given time. This allows the front end of each antenna channel to meet linear signal amplification requirements without requiring additional power backoff, improving overall transmitter efficiency and enhancing the efficiency of the multi-beam phased array architecture. Therefore, the multi-beam phased array architecture proposed in this invention is highly practical.

The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third etc. does not indicate any order. These words may be interpreted as names.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

A time-division multiplexed multi-beam phased array architecture, characterized in that the multi-beam phased array architecture comprises: two beam input interfaces, four phase shift attenuation channels, two antenna channels, and a control unit; The two beam input interfaces are connected to the four phase shift attenuation channels through a power distribution network; The four phase-shift attenuation channels are connected to the two antenna channels via a power combining network; The control unit is connected to the four phase-shift attenuation channels and is used to control the on and off of the four phase-shift attenuation channels so that at any time, each antenna channel only processes the signal input by one beam input interface. The multi-beam phased array architecture according to claim 1, wherein the two beam input interfaces are arranged on the left side of the chip layout; The four phase-shift attenuation channels are arranged vertically on the chip layout; The two antenna channels are arranged on the right side of the chip layout. The multi-beam phased array architecture according to claim 2, wherein the two beam input interfaces are connected to the four phase shift attenuation channels through two 1-to-2 power distribution networks; The four phase-shift attenuation channels are connected to the two antenna channels through two 2-to-1 power combining networks. The multi-beam phased array architecture according to claim 1, wherein the control unit comprises: two inverters and four switches; The output end of each of the four phase-shift attenuation channels is connected to the power synthesis network through a switch; Two inverters are used to invert the clock signal, so as to send the clock signal and the inverted signal of the clock signal to the target switch group; The target switch group is: two phase-shift attenuation channels connected to the same beam input interface among the four phase-shift attenuation channels, and switches connected to their respective output ends. The multi-beam phased array architecture according to claim 4, wherein the output end of the first phase shift attenuation channel connected to the first beam input interface is connected to the input end of the first switch; The output end of the first switch is connected to the first branch in the power synthesis network; An output end of the second phase-shift attenuation channel connected to the first beam input interface is connected to an input end of the second switch; The output end of the second switch is connected to the second branch of the power combining network; The output end of the third phase-shift attenuation channel connected to the second beam input interface is connected to the input end of the third switch; The output end of the third switch is connected to the third branch of the power synthesis network; an output end of the fourth phase-shift attenuation channel connected to the second beam input interface, and connected to an input end of the fourth switch; The output end of the fourth switch is connected to the fourth branch of the power synthesis network. The multi-beam phased array architecture according to claim 5, wherein the first switch and the fourth switch are controlled by an external clock signal and are closed or opened at the same time; The second switch and the third switch are controlled by an inverted signal of the clock signal, are closed or opened at the same time, and are always in an opposite state to the first switch and the fourth switch; In the power synthesis network, the end of the first branch is connected to the end of the third branch and then connected to the first antenna channel; After the end of the second branch is connected to the end of the fourth branch, it is connected to the second antenna channel. The multi-beam phased array architecture according to claim 1 is characterized in that a cross-layer is used at the intersection of the wiring of the power distribution network or the power synthesis network. The multi-beam phased array architecture according to claim 4, wherein the four switches are all controlled by a clock signal of a preset frequency; At any time, the target switch group has: one switch in a closed state and another switch in an open state. A chip, characterized in that the chip includes the time-division multiplexed multi-beam phased array architecture according to any one of claims 1-8. An electronic device, characterized in that the electronic device includes the time-division multiplexed multi-beam phased array architecture according to any one of claims 1-8.