WO2025160751A1 - Ultrasonic detection base plate and ultrasonic imaging apparatus - Google Patents

Abstract

The present application relates to the field of ultrasonic detection technology, and in particular, to an ultrasonic detection base plate and an ultrasonic imaging apparatus. The ultrasonic detection base plate comprises a substrate, and a detection region and a peripheral region arranged on one side of the substrate. The peripheral region is located on at least one side of the detection region. The detection region comprises: a plurality of array elements arranged in an array in a row direction and a column direction, and a plurality of signal lines arranged in the row direction and extending in the column direction. The signal lines are connected to the array elements. The plurality of signal lines comprise a plurality of partition signal lines divided into a plurality of signal line sets. Each signal line set comprises at least one partition signal line. The peripheral region comprises an adapter line extending in the row direction. The adapter line comprises a plurality of adapter line segments arranged in the row direction at intervals. The partition signal lines of a same signal line set are connected to a same adapter line segment, and the partition signal lines of different signal line sets are connected to different adapter line segments.

Description

Ultrasonic testing substrate and ultrasonic imaging device Technical Field

The present disclosure relates to the field of ultrasonic detection technology, and in particular to an ultrasonic detection substrate and an ultrasonic imaging device.

Background Art

Ultrasound imaging is an important non-destructive testing method in medicine. With technological advancements, ultrasound imaging is developing towards faster, clearer, and more three-dimensional imaging. High definition and high resolution are a constant pursuit, facilitating earlier disease detection and prompt treatment.

Overview

The present disclosure provides an ultrasonic detection substrate, comprising a base substrate, and a detection area and a peripheral area provided on one side of the base substrate, wherein the peripheral area is located on at least one side of the detection area;

The detection area includes: a plurality of array elements arranged in a row direction and a column direction, and a plurality of signal lines arranged in the row direction and extending in the column direction, the signal lines being connected to the array elements, the plurality of signal lines including a plurality of partition signal lines, the plurality of partition signal lines being divided into a plurality of signal line groups, the signal line groups including at least one of the partition signal lines;

The peripheral area includes a patch cord extending along a row direction, and the patch cord includes a plurality of patch cord segments arranged along the row direction and spaced apart;

Partition signal lines belonging to the same signal line group are connected to the same patch cord segment, and partition signal lines belonging to different signal line groups are connected to different patch cord segments.

In some embodiments, the peripheral area further comprises:

A fan-out line and a binding terminal, wherein the fan-out line is connected between the binding terminal and the patch line segment, and different patch line segments are connected to different binding terminals through different fan-out lines.

In some embodiments, a connection point between the patch line segment and the fan-out line is centered relative to the patch line segment in a row direction.

In some embodiments, the fan-out line and the patch line are provided on the same layer; or

The fan-out lines are arranged in different layers from the transfer lines and the partition signal lines.

In some embodiments, different patch cord segments belonging to the same patch cord are connected to the same number of partitioned signal lines; and/or

Different patch cord segments belonging to the same patch cord are connected to the same number of array elements; and/or

Different patch cord segments belonging to the same patch cord have the same width along the row direction.

In some embodiments, the plurality of signal lines further include a jumper signal line, the jumper signal line and the patch line segment are provided in different layers and their orthographic projections on the base substrate overlap, and there is no connection between the jumper signal line and the patch line segment;

In the orthographic projection on the base substrate, the number of the overlapping jumper signal lines is the same as that of the two patch cord segments belonging to the same patch cord.

In some embodiments, the plurality of signal lines further include a jumper signal line, wherein the jumper signal line and the adapter line segment are arranged in different layers and are not connected to each other;

A first hollow hole is provided on the adapter wire segment, and the first hollow hole overlaps with the orthographic projection of the jumper signal wire on the base substrate.

In some embodiments, the plurality of first hollow holes are spaced apart from each other and arranged along the column direction, and the orthographic projections of the first hollow holes on the base substrate cover the orthographic projections of the jumper signal lines on the base substrate in the row direction.

In some embodiments, the signal line and the adapter line are arranged in different layers;

The detection area includes two partition signal lines arranged in the same layer and separated from each other, the two partition signal lines are a first partition signal line and a second partition signal line, and the first partition signal line and the second partition signal line are used to provide different signals to the array element;

The peripheral area includes two adapter wires arranged in the same layer and separated from each other, the two adapter wires are a first adapter wire and a second adapter wire, the adapter wire segment in the first adapter wire is connected to the first partition signal line, and the adapter wire segment in the second adapter wire is connected to the second partition signal line, and the first adapter wire is located on the side of the second adapter wire close to the detection area.

In some embodiments, the number of the first partition signal lines is greater than or equal to the number of the second partition signal lines.

In some embodiments, the plurality of array elements are divided into a plurality of detection units, and the detection unit includes a plurality of array elements arranged along a row direction;

Different array elements belonging to the same detection unit are connected to different first partition signal lines, and different array elements belonging to the same detection unit are connected to the same second partition signal line.

In some embodiments, the first partition signal line is an enable signal line, and the second partition signal line is a reset control signal line; or

The first partition signal line is a reset control signal line, and the second partition signal line is an enable signal line;

The array element includes an ultrasonic sensor, the enable signal line is used to provide an enable signal to the array element, so that the array element responds to the enable signal and collects the induced voltage on the ultrasonic sensor, and the reset control signal line is used to provide a reset control signal to the array element, so that the array element responds to the reset control signal and writes a reset signal into the array element.

In some embodiments, the plurality of signal lines further include a power signal line, and the power signal line is used to provide a power signal to the array element;

The peripheral area further includes: a first transmission line extending in a row direction and connected to the plurality of power signal lines, wherein the first transmission lines located on the same side of the detection area are interconnected as an integrated structure; and

The first transmission line is located between the first patch line and the second patch line, or the first transmission line is located on a side of the second patch line away from the first patch line.

In some embodiments, two first transmission lines are arranged on opposite sides of the detection area along a column direction, and the peripheral area further includes:

The second transmission line extends along the column direction, is arranged in a different layer from the first transmission line and is connected to each other at the intersection position. Two second transmission lines are arranged opposite to each other on both sides of the detection area along the row direction.

In some embodiments, the peripheral area further comprises:

The first transfer pattern is located on a side of the first transfer line close to the detection area, is arranged on the same layer as the first transfer line, and is respectively connected to the first transfer line and the first partition signal line. The orthographic projections of the first partition signal line and the first transfer line on the base substrate do not overlap.

In some embodiments, the peripheral area further comprises:

a second transfer pattern, located on a side of the first transfer line close to the detection area, arranged on the same layer as the first transfer line and spaced apart from each other, wherein two adjacent second partition signal lines are connected to the same second transfer pattern through a via;

Of the two adjacent second partition signal lines, one crosses the first transfer line and is connected to the second transfer line through a via, and the other has no overlap with the orthographic projections of the first transfer line and the second transfer line on the base substrate.

In some embodiments, the partition signal line and the adapter line have overlapping orthographic projections on the base substrate, and the partition signal line and the adapter line are connected through a via.

In some embodiments, both opposite ends of the partition signal line along the column direction are connected to the adapter line, and the adapter line is arranged on two opposite sides of the detection area along the column direction.

The present disclosure provides an ultrasonic imaging device, comprising:

The ultrasonic detection substrate according to any one of the embodiments; and

A driving circuit is connected to the ultrasonic detection substrate and is used to provide a driving signal to the signal line.

The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

FIG1 exemplarily shows a schematic diagram of a planar structure of an ultrasonic detection substrate;

FIG2 exemplarily shows a schematic planar structural diagram of an ultrasonic detection substrate provided by the present disclosure;

FIG3 exemplarily shows a circuit layout diagram of a first peripheral area provided by the present disclosure;

FIG4 exemplarily shows a circuit layout diagram at the junction of the detection area and the peripheral area;

FIG5 exemplarily shows a connection diagram of a first patch line and a first fan-out line;

FIG6 exemplarily shows a connection diagram of a second patch line and a second fan-out line;

FIG7 exemplarily shows a circuit layout diagram of a second peripheral area provided by the present disclosure;

FIG8 exemplarily shows a circuit layout diagram on the opposite side of the first peripheral area provided by the present disclosure;

FIG9 exemplarily shows a circuit layout diagram at four corner positions in an ultrasonic detection substrate;

FIG10 exemplarily shows a circuit layout diagram of a third peripheral area provided by the present disclosure;

FIG11 exemplarily shows a circuit layout diagram of a fourth peripheral area provided by the present disclosure;

FIG12 exemplarily shows a circuit layout diagram of a fifth peripheral area provided by the present disclosure;

FIG13 exemplarily shows a schematic diagram of an equivalent circuit of an array element.

Detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

The present disclosure provides an ultrasonic testing substrate, as shown in FIG1 , comprising a base substrate 11, a detection area AA and a peripheral area NA disposed on one side of the base substrate 11, wherein the peripheral area NA is located on at least one side of the detection area AA. As shown in FIG1 , the peripheral area NA is located around the detection area AA.

As shown in Figures 1 and 2, the detection area AA includes: a plurality of array elements 12 arranged in an array along the row direction f1 and the column direction f2, and a plurality of signal lines 20 arranged along the row direction f1 and extending along the column direction f2. The signal lines 20 are connected to the array elements 12. The plurality of signal lines 20 include a plurality of partition signal lines 21. The plurality of partition signal lines 21 are divided into a plurality of signal line groups GP. The signal line group GP includes at least one partition signal line 21.

The array element 12 includes an ultrasonic sensor SS. In response to a signal provided by the signal line 20 , the array element 12 can generate and output a detection signal according to an induced voltage on the ultrasonic sensor SS.

As shown in FIG. 2 , the peripheral area NA includes a transfer line ZL extending along a row direction f1 . The transfer line ZL includes a plurality of transfer line segments LS arranged along the row direction f1 and spaced apart.

The partitioned signal lines 21 belonging to the same signal line group GP are connected to the same patch line segment LS, and the partitioned signal lines 21 belonging to different signal line groups GP are connected to different patch line segments LS.

In the ultrasonic detection substrate provided by the present invention, a patch cord segment LS corresponds to a partition signal line 21 in a signal line group GP, and the partition signal lines 21 in different signal line groups GP are provided with signals by different patch cord segments LS. The partition signal line 21 in each signal line group GP corresponds to a sub-area B1 in the detection area AA. This partition driving method can reduce the load C of the signal in the partition signal line 21. Since the delay time t=R*C, the delay time of the signal switching can be reduced, which is beneficial to improving the accuracy of the detection signal and improving the accuracy of ultrasonic imaging.

The technical solution provided by this disclosure facilitates large-area two-dimensional array ultrasonic testing of substrates. Using the acoustic imaging method, based on the spatial distribution characteristics of the wavefront, the large-area two-dimensional array element design can achieve improved resolution, with recognition resolution reaching 0.5mm to 1mm.

Exemplarily, as shown in FIG. 2 , a sub-area B1 in the detection area AA may include one or more columns of array elements 12 , and the partition signal lines 21 connected to the array elements 12 in one sub-area B1 constitute a signal line group GP.

Exemplarily, as shown in FIG3 , the detection area AA may include at least one partition signal line 21 (two types as shown in FIG3 ), and at least one partition signal line 21 includes a first partition signal line 211. Correspondingly, the peripheral area NA may include at least one adapter line ZL (two types as shown in FIG3 ), and at least one adapter line ZL includes a first adapter line ZL1. The adapter line segment LS in the first adapter line ZL1 is a first adapter line segment LS1. The first adapter line segment LS1 is connected to the first partition signal line 211, and the first partition signal lines 211 belonging to the same signal line group GP are connected to the same first adapter line segment LS1, and the first partition signal lines 211 belonging to different signal line groups GP are connected to different first adapter line segments LS1.

Exemplarily, as shown in Figure 3, at least one partition signal line 21 also includes a second partition signal line 212, at least one adapter line ZL also includes a second adapter line ZL2, the adapter line segment LS in the second adapter line ZL2 is the second adapter line segment LS2, the second adapter line segment LS2 is connected to the second partition signal line 212, and the second partition signal lines 212 belonging to the same signal line group GP are connected to the same second adapter line segment LS2, and the second partition signal lines 212 belonging to different signal line groups GP are connected to different second adapter line segments LS2.

The first partition signal line 211 and the second partition signal line 212 are used to provide different signals to the array element 12 , and the array element 12 is connected to both the first partition signal line 211 and the second partition signal line 212 .

In some embodiments, as shown in FIG. 4 , the adapter line ZL and the signal line 20 are disposed in different layers.

3 or 4 , the first partition signal line 211 is located in the third metal layer M3 , extends from the detection area AA to the peripheral area NA along the column direction f2 , and is connected to the first transfer line ZL1 located in the second metal layer M2 through a via.

For example, as shown in FIG3 , the second partition signal line 212 is located in the third metal layer M3 and extends from the detection area AA to the peripheral area NA along the column direction f2, crossing the first transfer line ZL1 (as shown in FIG7 ). The first transfer line ZL1 and the first transmission line 31 (as shown in FIG. 3 ) are connected to the second transfer line ZL2 located on the second metal layer M2 through a via.

3 or 7 , a plurality of partition signal lines 21 may be arranged on the same layer (e.g., all located on the third metal layer M3) and separated from each other, and a plurality of transfer lines ZL may be arranged on the same layer (e.g., all located on the second metal layer M2) and spaced apart along the column direction f2.

For example, the first patch cable ZL1 includes a first number of patch cable segments LS, and the second patch cable ZL2 includes a second number of patch cable segments LS. To simplify the design, the first number can be equal to the second number. Of course, the first number can also be greater than or less than the second number, and this disclosure is not limited to this. Both the first number and the second number are positive integers greater than 1.

Exemplarily, as shown in FIG. 3 or FIG. 7 , a plurality of switching line segments LS located in the same switching line ZL have the same position and height in the column direction f2 .

In some embodiments, as shown in FIG2 , the peripheral area NA further includes: a fan-out line 51 and a binding terminal PIN. The fan-out line 51 is connected between the binding terminal PIN and the patch line segment LS. Different patch line segments LS are connected to different binding terminals PIN via different fan-out lines 51. The binding terminal PIN is used to bind and connect to the driving circuit of the ultrasonic detection substrate, and the driving circuit is used to provide a driving signal to the signal line 20.

In some embodiments, the fan-out line 51 and the transfer line ZL are provided on the same layer, or the fan-out line 51 and the transfer line ZL and the partition signal line 21 are provided on different layers.

Exemplarily, as shown in Figure a in Figure 5, the fan-out line 51 connected to the first transfer line ZL1 is the first fan-out line 511. The first fan-out line 511 is arranged on different layers from the first transfer line ZL1 and the first partition signal line 211, respectively. The first fan-out line 511 is located, for example, in the first metal layer M1. The first fan-out line 511 is connected to the first transfer line segment LS1 located in the second metal layer M2 through a via (as shown in the dotted box X1 in Figure 5).

As shown in Figure a of Figure 5, a first transmission line 31, a second transfer line ZL2, and a ground line GND are sequentially arranged on the side of the first transfer line ZL1 away from the detection area AA, wherein the first transmission line 31 and the second transfer line ZL2 are arranged on the same layer as the first transfer line ZL1 and are located on the second metal layer M2, and the ground line GND is arranged on the same layer as the first partition signal line 211 and is located on the third metal layer M3. The first fan-out line 511 extends downward through the first transmission line 31, the second transfer line ZL2, and the ground line GND. By arranging the first fan-out line 511 on different layers from the first transfer line ZL1 and the first partition signal line 211, the first fan-out line 511 is connected to the first transmission line 31, the second transfer line ZL2, and the ground line GND. The ground line GND is arranged in different layers, thereby avoiding a short circuit between the first fan-out line 511 and the first transmission line 31, the second transfer line ZL2 and the ground line GND, and saving wiring space.

As shown in FIG. 5 b , different first adapter line segments LS1 are connected to different first fan-out lines 511 . For example, the first adapter line segments LS1 and the first fan-out lines 511 are connected in a one-to-one correspondence.

Exemplarily, as shown in Figure a in Figure 6, the fan-out line 51 connected to the second transfer line ZL2 is the second fan-out line 512, and the second fan-out line 512 is located, for example, in the second metal layer M2, that is, the second fan-out line 512 and the second transfer line ZL2 are arranged on the same layer, and the interconnected second fan-out line 512 and the second transfer line segment LS2 are an integrated structure.

As shown in Figure 6(a), a ground line GND is also provided on the side of the second transfer line ZL2 away from the detection area AA. The ground line GND is provided on the same layer as the second partition signal line 212 and is located on the third metal layer M3. The second fan-out line 512 passes through the ground line GND. By providing the second fan-out line 512 and the second transfer line ZL2 on the same layer, the ground line GND and the second fan-out line 512 are provided on different layers. This prevents short circuits between the second fan-out line 512 and the ground line GND, while saving wiring space.

As shown in FIG. 6 b , different second adapter line segments LS2 are connected to different second fan-out lines 512 . For example, the second adapter line segments LS2 and the second fan-out lines 512 are connected in a one-to-one correspondence.

In some embodiments, as shown in FIG. 2 , the connection point between the switch line segment LS and the fan-out line 51 is centered relative to the switch line segment LS in the row direction f1 .

As shown in FIG5(b), the connection point O1 between the first patch line segment LS1 and the first fan-out line 511 is centered relative to the first patch line segment LS1 in the row direction f1. As shown in FIG6(b), the connection point O2 between the second patch line segment LS2 and the second fan-out line 512 is centered relative to the second patch line segment LS2 in the row direction f1.

This embodiment can ensure that the signal input point of the fan-out line 51 is located in the middle position of the patch line segment LS along the row direction f1, thereby reducing the delay time difference between the far and near ends of the signal input point of the patch line segment LS and further improving the accuracy of ultrasonic imaging.

Exemplarily, the fan-out lines 51 (such as the first fan-out lines 511 shown in FIG. 5 and the second fan-out lines 512 shown in FIG. 6 ) at least partially extend along the column direction f2 .

In some embodiments, as shown in FIG2 , the two opposite ends of the partition signal line 21 along the column direction f2 (the upper end and the lower end as shown in FIG2 ) are both connected to the adapter line ZL, and the adapter line ZL is arranged on both sides of the detection area AA along the column direction f2. In this way, the partition signal line 21 can be driven on both sides. The delay time difference between the far and near ends of the signal input point of the partition signal line 21 is further reduced, and the accuracy of ultrasonic imaging is further improved.

3 and 4 show the circuit layout diagrams of the peripheral area NA located below the detection area AA, and FIG. 8 shows the circuit layout diagram of the peripheral area NA located above the detection area AA.

As shown in Figures 3, 4, and 8, the first partition signal line 211 extends upward and downward along the column direction f2, respectively, and connects to the first patch line ZL1 located above and below the detection area AA. The second partition signal line 212 extends upward and downward along the column direction f2, respectively, and connects to the second patch line ZL2 located above and below the detection area AA.

In some embodiments, different patch cord segments LS belonging to the same patch cord ZL are connected to the same number of partition signal lines 21. This can reduce the load differences between different patch cord segments LS, thereby reducing the delay time differences between different patch cord segments LS, and further improving the accuracy of ultrasonic imaging.

In the present disclosure, different adapter line segments LS belonging to the same adapter line ZL may be, for example, different first adapter line segments LS1 belonging to the same first adapter line ZL1 , or different second adapter line segments LS2 belonging to the same second adapter line ZL2 .

In some embodiments, different patch cord segments LS belonging to the same patch cord ZL connect to the same number of array elements 12. This can reduce the load differences between different patch cord segments LS, thereby reducing the delay time differences between different patch cord segments LS, and further improving the accuracy of ultrasonic imaging.

In some embodiments, different patch line segments LS belonging to the same patch line ZL have the same width along the row direction f1. This can reduce the load difference between different patch line segments LS, thereby reducing the delay time difference between different patch line segments LS, and further improving the accuracy of ultrasonic imaging.

In some embodiments, as shown in FIG4 , the plurality of signal lines 20 further include jumper signal lines 41. The jumper signal lines 41 are disposed on a different layer from the patch line segments LS and overlap in their orthographic projections on the base substrate 11. There is no connection between the jumper signal lines 41 and the patch line segments LS. In their orthographic projections on the base substrate 11, the number of jumper signal lines 41 that overlap with two patch line segments LS belonging to the same patch line ZL is the same.

Since the jumper signal line 41 and the transfer line segment LS are arranged in different layers and their orthographic projections on the base substrate 11 overlap, a coupling capacitor can be formed between the jumper signal line 41 and the transfer line segment LS. By setting the number of jumper signal lines 41 that overlap with the two transfer line segments LS belonging to the same transfer line ZL, The same can reduce the coupling capacitance difference between different adapter line segments LS, thereby reducing the delay time difference between different adapter line segments LS, and further improving the accuracy of ultrasonic imaging.

As shown in FIG4 , for the first patch cable ZL1, its jumper signal line 41 includes, for example, the second partition signal line 212, the power signal line 22, and the data signal line 23. As shown in FIG3 , for the second patch cable ZL2, its jumper signal line 41 includes, for example, the data signal line 23. As shown in FIG7 , for the second patch cable ZL2, its jumper signal line 41 includes, for example, the power signal line 22 and the data signal line 23.

To reduce coupling capacitance, in some embodiments, as shown in FIG4 , the plurality of signal lines 20 further include a jumper signal line 41. The jumper signal line 41 is disposed on a different layer from the patch line segment LS and is not connected to each other. The patch line segment LS is provided with a first hollow hole H1, which overlaps with the orthographic projection of the jumper signal line 41 on the base substrate 11.

By providing the first hollow hole H1 , the overlapping area between the jumper signal line 41 and the adapter line segment LS can be reduced, thereby reducing the coupling capacitance, thereby reducing the signal delay time, and improving the accuracy of ultrasonic imaging.

In some embodiments, as shown in FIG4 , a plurality of first hollow holes H1 are spaced apart from each other and arranged along the column direction f2 , and the orthographic projections of the first hollow holes H1 on the base substrate 11 cover the orthographic projections of the jumper signal lines 41 on the base substrate 11 in the row direction f1 .

Exemplarily, as shown in FIG. 4 , the width of the first hollow hole H1 along the row direction f1 is greater than the width of the jumper signal line 41 along the row direction f1 .

In some embodiments, as shown in Figure 3 or Figure 7, the first adapter line ZL1 is located on a side of the second adapter line ZL2 close to the detection area AA. Furthermore, the plurality of adapter lines ZL can be sequentially arranged along the column direction f2 in the peripheral area NA.

In some embodiments, as shown in FIG. 3 or FIG. 7 , the number of the first partition signal lines 211 is greater than or equal to the number of the second partition signal lines 212 .

When the number of first partition signal lines 211 is greater than the number of second partition signal lines 212, by setting the first adapter line ZL1 to be located on the side of the second adapter line ZL2 close to the detection area AA, the cross-over between the first partition signal line 211 and other lateral extension lines can be reduced, thereby reducing the coupling capacitance, reducing signal delay, and further improving the accuracy of ultrasonic imaging.

In some embodiments, as shown in FIG4 , a plurality of array elements 12 are divided into a plurality of detection units U. The detection unit U includes a plurality of array elements 12 arranged along the row direction f1. The same array element 12 is connected to different first partition signal lines 211 , and different array elements 12 belonging to the same detection unit U are connected to the same second partition signal line 212 .

Exemplarily, as shown in FIG. 4 , the detection unit U includes two array elements 12 arranged along the row direction f1 . The two array elements 12 are connected to different first partition signal lines 211 and to the same second partition signal line 212 .

Exemplarily, as shown in FIG4 , the first partition signal lines 211 connecting different array elements 12 in the same detection unit U are located in the same signal line group GP and connected to the same first patch line segment LS1 .

Exemplarily, as shown in Figure 2, a sub-area B1 includes n columns of detection units U, and the detection unit U includes two array elements 12 arranged along the row direction f1. The number of first partition signal lines 211 connecting the sub-area B1 is 2n, and the 2n first partition signal lines 211 are connected to the same first switching line segment LS1. The number of second partition signal lines 212 connecting the sub-area B1 is n, and the n second partition signal lines 212 are connected to the same second switching line segment LS2.

In some embodiments, the first partition signal line 211 is the enable signal line ENL, and the second partition signal line 212 is the reset control signal line RL; or the first partition signal line 211 is the reset control signal line RL, and the second partition signal line 212 is the enable signal line ENL.

An equivalent circuit diagram of an array element is shown in Figure 13. As shown in Figure 13, array element 12 includes an ultrasonic sensor SS. An enable signal line ENL is used to provide an enable signal to array element 12, so that array element 12 responds to the enable signal and collects the induced voltage on ultrasonic sensor SS. A reset control signal line RL is used to provide a reset control signal to array element 12, so that array element 12 responds to the reset control signal and writes a reset signal into array element 12.

In some embodiments, as shown in FIG3 or FIG7 , the plurality of signal lines 20 further include a power signal line 22, which is used to provide a power signal to the array element 12. The peripheral area NA further includes a first transmission line 31 extending along the row direction f1 and connected to the plurality of power signal lines 22. The first transmission lines 31 located on the same side of the detection area AA are interconnected and form an integrated structure.

As shown in FIG3 and FIG7 , the first transmission lines 31 located below the detection area AA are interconnected integral structures. As shown in FIG8 , the first transmission lines 31 located above the detection area AA are interconnected integral structures.

In some embodiments, the first transmission line 31 is located between the first patch line ZL1 and the second patch line ZL2 (as shown in FIG3 ), or the first transmission line 31 is located on a side of the second patch line ZL2 away from the first patch line ZL1 (as shown in FIG7 ).

In some embodiments, as shown in FIG9 , the two first transmission lines 31 are relatively arranged on both sides (e.g., the upper side and the lower side) of the detection area AA along the column direction f2, and the peripheral area NA further includes: a second transmission line 91, which extends along the column direction f2, is arranged in a different layer from the first transmission line 31 and is connected to each other at the intersection position, and the two second transmission lines 91 are relatively arranged on both sides (e.g., the left side and the right side) of the detection area AA along the row direction f1.

Exemplarily, the first transmission line 31 and the adapter line ZL are provided on the same layer, and the second transmission line 91 and the power signal line 22 are provided on the same layer.

In the present disclosure, the power signal is a DC signal.

Exemplarily, as shown in FIG9 , the power signal line 22 is located in the third metal layer M3, extends upward and downward from the detection area AA to the peripheral area NA along the column direction f2, and is connected to the first transmission line 31 located in the second metal layer M2 through a via, and the first transmission line 31 is connected to the second transmission line 91 located in the third metal layer M3 through a via.

As shown in FIG9 , the first transmission line 31 located on the upper and lower sides of the detection area AA is connected to the second transmission line 91 located on the left and right sides of the detection area AA through vias at the intersection, forming a closed route surrounding the detection area AA.

In order to further reduce the coupling capacitance, illustratively, as shown in Figure 3 or Figure 7, a second hollow hole H2 is provided on the first transmission line 31, and the second hollow hole H2 overlaps with the orthographic projection of the coupling signal line 24 on the base substrate 11, wherein the coupling signal line 24 refers to a signal line 20 that is arranged in a different layer from the first transmission line 31 and has an overlapping orthographic projection on the base substrate 11, and the coupling signal line 24 and the first transmission line 31 are not connected to each other.

As shown in FIG3 , the coupled signal line 24 of the first transmission line 31 includes the second partition signal line 212 and the data signal line 23. As shown in FIG7 , the coupled signal line 24 of the first transmission line 31 is the data signal line 23.

As shown in FIG3 or FIG7 , a plurality of second hollow holes H2 are spaced apart from each other and arranged along the column direction f2 , and the orthographic projections of the second hollow holes H2 on the base substrate 11 cover the orthographic projections of the coupling signal lines 24 on the base substrate 11 in the row direction f1 .

Exemplarily, as shown in FIG. 3 or FIG. 7 , the width of the second hollow hole H2 along the row direction f1 is greater than the width of the coupling signal line 24 along the row direction f1 .

In some embodiments, as shown in Figure 10 or Figure 11, the peripheral area NA also includes: a first transfer pattern 101, located on the side of the first transfer line ZL1 close to the detection area AA, and connected to the first transfer line ZL1 and the first partition signal line 211 respectively, and the first partition signal line 211 and the first transfer line ZL1 have no overlapping orthographic projections on the base substrate 11.

Exemplarily, the first switching pattern 101 and the first switching line ZL1 are provided on the same layer.

In some embodiments, as shown in FIG12 , the peripheral area NA further includes a second transfer pattern 121 located on a side of the first transfer line ZL1 near the detection area AA, arranged on the same layer as the first transfer line ZL1 and spaced apart from each other. Two adjacent second partitioned signal lines 212 are connected to the same second transfer pattern 121 via a via. Of the two adjacent second partitioned signal lines 212, one crosses the first transfer line ZL1 and is connected to the second transfer line ZL2 via a via, while the other does not overlap with either the first transfer line ZL1 or the second transfer line ZL2 in their orthographic projections on the base substrate 11.

In this embodiment, the overlapping area between the second partition signal line 212 and the first transfer line ZL1 can be reduced, thereby reducing the coupling capacitance and shortening the signal delay time.

In some embodiments, as shown in FIG. 3 or FIG. 7 , the orthographic projections of the partition signal line 21 and the adapter line ZL on the base substrate 11 overlap, and the partition signal line 21 and the adapter line ZL are connected through a via.

As shown in FIG. 3 or FIG. 7 , the first partition signal line 211 is connected to the first transfer line ZL1 through a via hole, and the second partition signal line 212 is connected to the second transfer line ZL2 through a via hole.

Exemplarily, as shown in FIG3 or FIG7 , the width of the portion of the partition signal line 21 connected to the adapter line ZL is increased, which can increase the contact area between the partition signal line 21 and the adapter line ZL and reduce the contact resistance.

As shown in FIG3 or FIG7 , the width of the portion of the first partition signal line 211 connected to the first transition line ZL1 is increased, and the width of the portion of the second partition signal line 212 connected to the second transition line ZL2 is increased.

Exemplarily, as shown in FIG. 3 or FIG. 7 , the vias connecting the partition signal lines 21 and the adapter lines ZL are arranged in an array along the row direction f1 and the column direction f2 .

In some embodiments, the ultrasonic sensor SS may be a vinylidene fluoride piezoelectric film sensor (ie, a PVDF sensor), a capacitive micromachined ultrasonic sensor SS (ie, a CMUT sensor), The piezoelectric micromachined ultrasonic transducer (ie, PMUT sensor) may also be other transducer sensors capable of realizing ultrasonic-voltage conversion.

As shown in FIG13 , the array element 12 includes an ultrasonic sensor SS and an array element circuit. The array element circuit adopts a 4T1C design, that is, it includes four transistors and one capacitor. The four transistors are a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, and the one capacitor is a first capacitor C1.

As shown in Figure 13, the gate of the first transistor T1 is connected to the reset control signal line RL, the first electrode is connected to the reset signal line BL, and the second electrode is connected to the first node N1, which is connected to the ultrasonic sensor SS. The gate of the second transistor T2 is connected to the enable signal line ENL, the first electrode is connected to the first node N1, and the second electrode is connected to the second node N2. The gate of the third transistor T3 is connected to the second node N2, the first electrode is connected to the power signal line 22, and the second electrode is connected to the first electrode of the fourth transistor T4. The gate of the fourth transistor T4 is connected to the scan signal line SCL, and the second electrode is connected to the data signal line 23. The first capacitor C1 is connected between the first electrode of the first transistor T1 and the second node N2.

Exemplarily, the scan signal line SCL and the reset signal line BL extend along the row direction f1. The reset control signal line RL, the enable signal line ENL, the power signal line 22, and the data signal line 23 extend along the column direction f2. Array elements 12 in the same row are connected to the same scan signal line SCL and reset signal line BL, while array elements 12 in the same column are connected to the same reset control signal line RL, the enable signal line ENL, the power signal line 22, and the data signal line 23.

The scan signal line SCL is used to provide a scan signal GT. The array element 12 can respond to the scan signal GT and generate a detection signal based on the induced voltage on the ultrasonic sensor SS. The detection signal is then loaded onto the data signal line 23. The data signal line 23 is used to output the detection signal. The power signal line 22 is used to provide a power signal to the array element 12. The enable signal line ENL is used to provide an enable signal to the array element 12, so that the array element 12 responds to the enable signal and collects the induced voltage on the ultrasonic sensor SS. The reset control signal line RL is used to provide a reset control signal to the array element 12, so that the array element 12 responds to the reset control signal and writes the reset signal input from the reset signal line BL to the first node N1.

For example, before collecting the induced voltage on the ultrasonic sensor SS, the first node N1 may be reset. For example, a reset control signal may be provided to the reset control signal line RL first, and then an enable signal may be provided to the enable signal line ENL. This may improve the accuracy of collection.

Exemplarily, since the detection signal generated by each array element 12 is independent, the data signal lines 23 are connected to the binding terminals in a one-to-one correspondence.

Exemplarily, different array elements 12 belonging to the same detection unit U are connected to different data signal lines 23, and different array elements 12 belonging to the same detection unit U are connected to the same power signal line 22. In the case where a sub-area B1 includes n columns of detection units U, the number of data signal lines 23 connected to the sub-area B1 is 2n, and the number of power signal lines 22 connected to the sub-area B1 is n.

The present disclosure provides an ultrasonic imaging device, comprising an ultrasonic detection substrate as provided in any embodiment, and a driving circuit connected to the ultrasonic detection substrate and configured to provide a driving signal to the signal line.

Those skilled in the art will appreciate that the ultrasonic imaging device provided by the present disclosure has the advantages of the above-mentioned ultrasonic detection substrate.

Exemplarily, the peripheral area of the ultrasonic detection substrate includes binding terminals, which are connected to signal lines. The binding terminals are, for example, bound and connected to one end of a flexible circuit board, and the other end of the flexible circuit board can be connected to a driving circuit (such as a printed circuit board).

Exemplarily, the ultrasonic imaging device provided by the present disclosure may also include an ultrasonic generator for emitting an ultrasonic signal. The ultrasonic sensor in the ultrasonic detection substrate receives the ultrasonic signal reflected back by the object to be detected and generates an induced voltage. The array element can generate a detection signal based on the induced voltage on the ultrasonic sensor.

The ultrasonic imaging device or ultrasonic detection substrate provided by the present disclosure can be used for medical ultrasonic imaging detection, and can also be applied to other fields that utilize ultrasonic imaging, such as ultrasonic flaw detection.

In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

In this disclosure, the terms "comprises,""includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus. "…" does not exclude the existence of other identical elements in the process, method, product or equipment that includes the elements.

References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the present disclosure.

“At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

“A and/or B” includes the following three combinations: A only, B only, and a combination of A and B.

As used in this disclosure, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

The use of "based on" or "according to" in this disclosure is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values may, in practice, be based on other conditions or values beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values may, in practice, be based on other conditions or values beyond the stated values.

As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

As used in this disclosure, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

The present disclosure describes exemplary embodiments with reference to cross-sectional and/or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims (19)

An ultrasonic detection substrate comprises a base substrate, and a detection area and a peripheral area arranged on one side of the base substrate, wherein the peripheral area is located on at least one side of the detection area; The detection area includes: a plurality of array elements arranged in a row direction and a column direction, and a plurality of signal lines arranged in the row direction and extending in the column direction, the signal lines being connected to the array elements, the plurality of signal lines including a plurality of partition signal lines, the plurality of partition signal lines being divided into a plurality of signal line groups, the signal line groups including at least one of the partition signal lines; The peripheral area includes a patch cord extending along a row direction, and the patch cord includes a plurality of patch cord segments arranged along the row direction and spaced apart; Partition signal lines belonging to the same signal line group are connected to the same patch cord segment, and partition signal lines belonging to different signal line groups are connected to different patch cord segments. The ultrasonic detection substrate according to claim 1, wherein the peripheral area further comprises: A fan-out line and a binding terminal, wherein the fan-out line is connected between the binding terminal and the patch line segment, and different patch line segments are connected to different binding terminals through different fan-out lines. The ultrasonic detection substrate according to claim 2, wherein the connection point between the patch line segment and the fan-out line is centered relative to the patch line segment in the row direction. The ultrasonic detection substrate according to claim 2, wherein the fan-out line and the adapter line are provided on the same layer; or The fan-out lines are arranged in different layers from the transfer lines and the partition signal lines. The ultrasonic detection substrate according to claim 1, wherein different adapter wire segments belonging to the same adapter wire are connected to the same number of partition signal lines; and/or Different patch cord segments belonging to the same patch cord are connected to the same number of array elements; and/or Different patch cord segments belonging to the same patch cord have the same width along the row direction. The ultrasonic detection substrate according to claim 1, wherein the plurality of signal lines further include a jumper signal line, the jumper signal line and the adapter line segment are arranged in different layers and their orthographic projections on the base substrate overlap, and there is no connection between the jumper signal line and the adapter line segment; In the orthographic projection on the substrate, the number of the overlapping jumper signal lines is the same as that of the two patch cord segments belonging to the same patch cord. The ultrasonic detection substrate according to claim 1, wherein the plurality of signal lines further include a jumper signal line, the jumper signal line and the adapter line segment are arranged in different layers and are not connected to each other; A first hollow hole is provided on the adapter wire segment, and the first hollow hole overlaps with the orthographic projection of the jumper signal wire on the base substrate. The ultrasonic detection substrate according to claim 7, wherein the plurality of first hollow holes are spaced apart from each other and arranged along the column direction, and the orthographic projection of the first hollow hole on the base substrate covers the orthographic projection of the jumper signal line on the base substrate in the row direction. The ultrasonic detection substrate according to claim 1, wherein the signal line and the adapter line are arranged in different layers; The detection area includes two partition signal lines arranged in the same layer and separated from each other, the two partition signal lines are a first partition signal line and a second partition signal line, and the first partition signal line and the second partition signal line are used to provide different signals to the array element; The peripheral area includes two adapter wires arranged in the same layer and separated from each other, the two adapter wires are a first adapter wire and a second adapter wire, the adapter wire segment in the first adapter wire is connected to the first partition signal line, and the adapter wire segment in the second adapter wire is connected to the second partition signal line, and the first adapter wire is located on the side of the second adapter wire close to the detection area. The ultrasonic detection substrate according to claim 9, wherein the number of the first partition signal lines is greater than or equal to the number of the second partition signal lines. The ultrasonic detection substrate according to claim 9, wherein the plurality of array elements are divided into a plurality of detection units, and the detection unit comprises a plurality of array elements arranged along a row direction; Different array elements belonging to the same detection unit are connected to different first partition signal lines, and different array elements belonging to the same detection unit are connected to the same second partition signal line. The ultrasonic detection substrate according to claim 9, wherein the first partition signal line is an enable signal line, and the second partition signal line is a reset control signal line; or The first partition signal line is a reset control signal line, and the second partition signal line is an enable signal line; The array element includes an ultrasonic sensor, the enable signal line is used to provide an enable signal to the array element, so that the array element responds to the enable signal and collects the induced voltage on the ultrasonic sensor, and the reset control signal line is used to provide a reset control signal to the array element, so that the array element responds to the reset control signal and writes a reset signal into the array element. The ultrasonic detection substrate according to claim 9, wherein the plurality of signal lines further comprise a power signal line, and the power signal line is used to provide a power signal to the array element; The peripheral area further includes: a first transmission line extending in a row direction and connected to the plurality of power signal lines, wherein the first transmission lines located on the same side of the detection area are interconnected as an integrated structure; and The first transmission line is located between the first patch line and the second patch line, or the first transmission line is located on a side of the second patch line away from the first patch line. The ultrasonic detection substrate according to claim 13, wherein the two first transmission lines are arranged on opposite sides of the detection area along a column direction, and the peripheral area further includes: The second transmission line extends along the column direction, is arranged in a different layer from the first transmission line and is connected to each other at the intersection position. Two second transmission lines are arranged opposite to each other on both sides of the detection area along the row direction. The ultrasonic detection substrate according to claim 9, wherein the peripheral area further comprises: The first transfer pattern is located on a side of the first transfer line close to the detection area, is arranged on the same layer as the first transfer line, and is respectively connected to the first transfer line and the first partition signal line. The orthographic projections of the first partition signal line and the first transfer line on the base substrate do not overlap. The ultrasonic detection substrate according to claim 9, wherein the peripheral area further comprises: a second transfer pattern, located on a side of the first transfer line close to the detection area, arranged on the same layer as the first transfer line and spaced apart from each other, wherein two adjacent second partition signal lines are connected to the same second transfer pattern through a via; Of the two adjacent second partition signal lines, one crosses the first transfer line and is connected to the second transfer line through a via, and the other has no overlap with the orthographic projections of the first transfer line and the second transfer line on the base substrate. The ultrasonic detection substrate according to claim 1, wherein the partition signal line and the adapter line have overlapping orthographic projections on the base substrate, and the partition signal line and the adapter line are connected through a via. The ultrasonic detection substrate according to claim 1, wherein both opposite ends of the partition signal line along the column direction are connected to the adapter line, and the adapter line is arranged on both sides of the detection area along the column direction. An ultrasonic imaging device, comprising: The ultrasonic detection substrate according to any one of claims 1 to 18; and A driving circuit is connected to the ultrasonic detection substrate and is used to provide a driving signal to the signal line.