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WO2025157018A1 - Cellule solaire et procédé de fabrication s'y rapportant, et module photovoltaïque - Google Patents

Cellule solaire et procédé de fabrication s'y rapportant, et module photovoltaïque

Info

Publication number
WO2025157018A1
WO2025157018A1 PCT/CN2025/071575 CN2025071575W WO2025157018A1 WO 2025157018 A1 WO2025157018 A1 WO 2025157018A1 CN 2025071575 W CN2025071575 W CN 2025071575W WO 2025157018 A1 WO2025157018 A1 WO 2025157018A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
solar cell
layer
along
cell according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/071575
Other languages
English (en)
Chinese (zh)
Inventor
于明哲
孙召清
黄志鹏
唐喜颜
邓小玉
邱浩然
吴华
曹玉甲
方亮
徐希翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longi Green Energy Technology Co Ltd
Original Assignee
Longi Green Energy Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202410092536.4A external-priority patent/CN117832302A/zh
Priority claimed from CN202410190935.4A external-priority patent/CN118116983A/zh
Priority claimed from CN202411231282.6A external-priority patent/CN120091661A/zh
Application filed by Longi Green Energy Technology Co Ltd filed Critical Longi Green Energy Technology Co Ltd
Publication of WO2025157018A1 publication Critical patent/WO2025157018A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes

Definitions

  • the present application relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module.
  • laser treatment is used to treat the semiconductor layer on the velvet surface.
  • Some semiconductor layers contain hydrogen. After absorbing light, the hydrogen-containing semiconductor layer heats up, allowing hydrogen in the semiconductor layer to escape, increasing the effective doping level.
  • Laser treatment can also reduce the contact resistance of the solar cell, thereby reducing energy loss during current collection and improving cell efficiency. However, if the laser treatment area is not properly selected, it can lead to a greater risk of leakage in certain areas of the solar cell, affecting cell efficiency.
  • the purpose of this application is to provide a solar cell and a method for manufacturing the same, as well as a photovoltaic module, so as to reduce contact resistance while reducing leakage risk and improving battery efficiency.
  • a solar cell comprising:
  • a semiconductor substrate having a first surface and a second surface opposite to each other;
  • the first semiconductor layer is arranged on the first surface, and the first semiconductor layer includes a first part and a second part adjacent to the first part along the second direction.
  • the degree of crystallization of the first part is greater than the degree of crystallization of the second part.
  • the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.
  • a crystallized structure is formed in the first part of the first semiconductor layer, so that the first part has a crystallized part and another part that is not crystallized.
  • the first part is not entirely a crystallized structure, but mostly an amorphous structure, with only a portion forming a crystallized structure, such as a nanocrystal.
  • the second part of the first semiconductor layer adjacent to the first part along the second direction is not crystallized, retaining the original amorphous structure (it should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon in the second part remains unchanged), so that the overall degree of crystallization of the first part of the first semiconductor layer is greater than the overall degree of crystallization of the second part. It can be understood that, under the same other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of the amorphous silicon material is presented.
  • the crystallized structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material.
  • the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, ensuring the passivation effect of the second part adjacent to the first part along the second direction, reducing the recombination of the edge of the first semiconductor layer, that is, for the back-contact solar cell, the second part of the first semiconductor layer is closer to the second semiconductor, and the degree of crystallization of the second part is smaller to ensure the passivation effect of the second part, preventing leakage between the second part and the second semiconductor layer.
  • the higher degree of crystallization of the first part is utilized to optimize the overall cell efficiency of the solar cell, thereby improving the cell efficiency, while the lower degree of crystallization of the second part is utilized to ensure the passivation effect of the second part and prevent leakage.
  • the solar cell further includes a second semiconductor layer disposed on the first surface.
  • the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction.
  • the first semiconductor layer and the second semiconductor layer have different conductivity types.
  • the second portion is closer to the second semiconductor layer than the first portion.
  • the second semiconductor layer has a side surface adjacent to the first semiconductor layer.
  • the second semiconductor layer includes a third portion and a fourth portion adjacent to the third portion along the second direction, the degree of crystallization of the third portion is greater than that of the fourth portion, and the second semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.
  • the second portion extends from the edge of the first portion along the second direction to near the adjacent side surface, but does not contact the adjacent side surface. This technical solution prevents the second portion from contacting the second semiconductor layer and allows for a greater distance between the second portion and the second semiconductor layer, further reducing the risk of electrical leakage between the second portion and the second semiconductor layer.
  • the second portion extends from the edge of the first portion to the adjacent side surface along the second direction and contacts the adjacent side surface.
  • the second portion overlaps at least a portion of the adjacent side surface of the second semiconductor layer.
  • the second portion has a lower degree of crystallization, allowing weaker current to be transmitted through the second portion and the adjacent side surface of the second semiconductor layer. When the solar cell is shaded, the current can form a leakage path through the second portion and the adjacent side surface of the second semiconductor layer, preventing the shaded cell from becoming a load and consuming energy generated by other illuminated cells, thereby reducing the risk of hot spots.
  • the distance between the edge of the first portion and the adjacent side surface is greater than or equal to 20 ⁇ m. This arrangement ensures that the first portion, which has a stronger transmission circuit capability, is farther away from the second semiconductor layer, reducing the risk of leakage between the first portion and the second semiconductor layer.
  • a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the second portion extends from an edge of the first portion to the overlapping portion along the second direction.
  • extending the second portion from the edge of the first portion to the overlapping portion can increase the ability to transmit current between the second portion and the second semiconductor layer.
  • current can form a leakage path through the second portion and the surface of the second semiconductor layer facing away from the semiconductor substrate. This leakage path has a stronger current transmission capability, further reducing the risk of hot spots.
  • the width of the second portion along the second direction is less than or equal to 500 ⁇ m and greater than or equal to 20 ⁇ m.
  • the solar cell further includes a first transparent conductive layer overlying the first semiconductor layer, wherein the projection of the first portion on the semiconductor substrate is completely within the projection of the first transparent conductive layer on the semiconductor substrate.
  • This configuration improves the carrier transport capability of the first semiconductor layer, enabling good ohmic contact with the electrode and enhancing electrical conductivity.
  • the first portion having a crystallized structure does not extend beyond the boundaries of the first transparent conductive layer, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer, improving electrical conductivity, and ultimately increasing cell efficiency.
  • the first transparent conductive layer extends to the adjacent side surface or to the second portion located above the second semiconductor layer. In this way, the first transparent conductive layer can cover a larger area of the first semiconductor layer, further improving the conductive performance.
  • the solar cell further includes a second transparent conductive layer, the second transparent conductive layer overlying the second semiconductor layer; a PN isolation region is defined between the second transparent conductive layer and the first transparent conductive layer, the PN isolation region being located on the second semiconductor layer.
  • the PN isolation region provides electrical insulation between the P region and the N region.
  • the projection of the first portion is located within the boundary of the first transparent conductive layer, and therefore, the first portion does not enter the boundary of the PN isolation region. Consequently, the laser irradiation range does not enter the PN isolation region. Because the PN isolation region lacks a crystalline structure or has a low degree of crystallization, the electrical insulation effect of the PN isolation region is maintained.
  • a portion of the second portion is disposed on the second semiconductor layer to form an overlapping portion, and the PN isolation region is disposed on the overlapping portion.
  • the solar cell further comprises a third semiconductor layer disposed on the second surface, wherein the material of the third semiconductor layer comprises at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, and the third semiconductor layer has a different conductivity type from the first semiconductor layer.
  • the third semiconductor layer comprises an amorphous silicon layer
  • both sides of the semiconductor substrate are provided with a full-surface amorphous silicon layer, and the amorphous silicon layers on both sides can form a heterojunction structure, thereby forming a double-sided heterojunction cell.
  • a polycrystalline silicon layer passivation structure can be formed on the second side, and an amorphous silicon layer or a nanocrystalline silicon layer passivation structure can be formed on the first side, thereby forming a double-sided hybrid cell.
  • the double-sided heterojunction cell and the double-sided hybrid cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle region is a crystalline structure in the present application to improve cell efficiency.
  • the first portion and the second portion both extend in a strip shape along a first direction, and the first direction and the second direction intersect.
  • the first portion and the second portion are arranged in a substantially parallel strip shape, so that they can gradually move along the first direction during laser irradiation, which facilitates the laser irradiation formation of the first portion.
  • the contact resistance of the first portion is lower than the contact resistance of the second portion. Because the first portion can have a crystalline structure and the second portion has an amorphous structure, the effective doping of the crystalline structure of the first portion is increased, which can reduce the contact resistance of the first portion relative to the second portion, thereby reducing energy loss during current collection in the first portion and improving battery efficiency.
  • the first portion extends along the first direction to the edge of the first surface, so that the area of the first portion can be maximized, the contact resistance can be reduced, and the current collection capability can be improved.
  • the second portion surrounds the first portion.
  • the second portion surrounding the first portion has a lower degree of crystallization, which can further reduce the risk of electrical leakage and ensure the photoelectric conversion efficiency of the solar cell.
  • the first portion is made of amorphous silicon and nanocrystalline silicon, while the second portion is made of amorphous silicon. This allows the second portion to have a better passivation effect. By properly arranging crystallized and amorphized regions on the first semiconductor layer, the overall efficiency of the solar cell is optimized, thereby improving the cell efficiency.
  • the semiconductor substrate includes a recessed portion on a first surface, the recessed portion being recessed relative to the remainder of the first surface toward the second surface, with the first portion located within the recessed portion.
  • the recessed portion is formed by etching into the surface of the semiconductor substrate and typically has a textured surface. Positioning the first portion comprising amorphous silicon, nanocrystalline silicon, and/or microcrystalline silicon within the recessed portion increases the contact area of the first portion, facilitating current collection.
  • the solar cell further includes a first gate line electrode, which is stacked above the first semiconductor layer, and a projection of the first gate line electrode on the semiconductor substrate overlaps with a projection of the first portion on the semiconductor substrate, and an area of the projection of the first gate line electrode on the semiconductor substrate is smaller than an area of the projection of the first portion on the semiconductor substrate.
  • a photovoltaic assembly includes a solar cell, wherein the solar cell is any one of the solar cells described above.
  • the photovoltaic module adopts the solar cell of the first aspect and any one of the above items, the photovoltaic module has the same beneficial effects as the first aspect, which will not be described in detail here.
  • the present application also provides a method for manufacturing a solar cell, comprising:
  • the semiconductor substrate having a first surface and a second surface opposite to each other;
  • the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;
  • a laser is used to irradiate a first portion of the first semiconductor layer, and a second portion of the first semiconductor layer is not irradiated, so that the degree of crystallization of the first portion is greater than the degree of crystallization of the second portion; the first region and the second region are adjacent to each other along the second direction.
  • the region corresponding to the first portion of the first semiconductor layer is crystallized by laser, so that the degree of crystallization is improved, while the region corresponding to the second portion of the first semiconductor layer adjacent to the first portion is not laser irradiated, retaining the amorphous structure (it should be noted that when the first semiconductor layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon of the second portion remains unchanged), so that the overall degree of crystallization of the first portion of the first semiconductor layer is greater than the overall degree of crystallization of the second portion.
  • the crystallized structure in the first part of the first semiconductor layer reduces the contact resistance, reduces the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), and thus helps to reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material.
  • the degree of crystallization of the second part of the first semiconductor layer is less than that of the first part, ensuring the passivation effect of the second part adjacent to the first part along the second direction, reducing the recombination of the edge of the first semiconductor layer, that is, for the back-contact solar cell, the second part of the first semiconductor layer is closer to the second semiconductor, and the degree of crystallization of the second part is smaller to ensure the passivation effect of the second part, preventing leakage between the second part and the second semiconductor layer.
  • the higher degree of crystallization of the first part is utilized to optimize the overall cell efficiency of the solar cell, thereby improving the cell efficiency, while the lower degree of crystallization of the second part is utilized to ensure the passivation effect of the second part and prevent leakage.
  • the first semiconductor layer is an amorphous silicon layer.
  • Laser irradiation of the first portion causes the amorphous silicon layer to partially crystallize into nanocrystals.
  • Using an amorphous silicon layer for the first semiconductor layer provides better passivation in the portion not irradiated by the laser, and provides enhanced insulation in the isolation region.
  • the method before irradiating the first portion with a laser, the method further includes forming a second semiconductor layer on the first surface, wherein the first semiconductor layer and the second semiconductor layer are arranged adjacent to each other along a second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the second semiconductor layer has an adjacent side surface proximal to the first semiconductor layer, and the second portion is closer to the second semiconductor layer than the first portion.
  • the second portion of the first semiconductor layer is closer to the second semiconductor layer, and the second portion has a lower degree of crystallization to ensure a passivation effect on the second portion, thereby preventing leakage between the second portion and the second semiconductor layer and reducing the photoelectric conversion efficiency of the solar cell.
  • the first portion extends along a first direction and is strip-shaped.
  • Irradiating the first portion with a laser includes: irradiating the first portion with the laser along the first direction, with the laser starting or ending at a first distance from the adjacent side surface along a second direction. An end of the second portion facing away from the first portion is spaced a certain distance from the adjacent side surface. The second portion does not contact the second semiconductor layer, and the distance between the second portion and the second semiconductor layer is relatively large, thereby further reducing the risk of leakage between the second portion and the second semiconductor layer.
  • the starting or ending position of the laser is a second distance from the boundary of the first semiconductor layer.
  • the second distance is the extension distance of the second portion along the first direction. The second distance prevents the laser from irradiating both ends of the first semiconductor layer along the first direction, preserving the amorphous structure. This ensures a passivation effect at the edge portion and reduces recombination at the edge portion.
  • the second distance is greater than the first distance.
  • the wavelength of the laser is 325nm to 532nm; and/or the energy density of the laser is 200mJ/ cm2 to 6000mJ/ cm2 .
  • the wavelength range it can be absorbed by the amorphous semiconductor layer, which is conducive to the crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high temperature range will be expanded, and the temperature at the top of the velvet structure will be too high, thereby affecting the passivation of the top area of the velvet structure. If the laser energy density is too low, the energy accumulation time is too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it is possible to achieve high temperature only at the top of the velvet structure, achieve morphological changes, and form a crystallized structure.
  • FIG2 is a schematic diagram of another solar cell provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a partial arrangement of a transparent conductive layer on a first surface of a solar cell provided in an embodiment of the present application;
  • FIG4 is a partial enlarged view of FIG3 provided in an embodiment of the present application.
  • FIG5 is a schematic cross-sectional view of the B-B section in FIG4 ;
  • FIG6 is a schematic cross-sectional view of the A-A section in FIG4 ;
  • FIG. 7 to 18 are schematic flow charts of the steps of a method for manufacturing a solar cell provided in an embodiment of the present application.
  • FIG19 is a schematic diagram comparing EL test images of a solar cell provided by an embodiment of the present application (B in the figure) and a solar cell with a conventional amorphous region (C in the figure);
  • FIG20 is a schematic diagram comparing the contact resistance of the P region of the solar cell provided by the embodiment of the present application and the conventional solar cell without a crystallization region;
  • FIG21 is a schematic diagram of the crystallization of the pyramid top provided in an embodiment of the present application.
  • FIG22 is a schematic diagram of another solar cell provided in an embodiment of the present application.
  • Reference numerals: 100 is the first semiconductor layer, 1 is the first strip portion, 11 is the first part, 12 is the second part, 13 is an intrinsic amorphous silicon layer, 14 is a p-type amorphous silicon layer, 15 is an overlapping portion, 2 is a second semiconductor layer, 201 is a third portion, 202 is a fourth portion, 21 is a tunneling oxide layer, 22 is an n-type doped polysilicon layer, 23 is an intrinsic polysilicon layer, 24 is a phosphosilicate glass layer, 25 is a silicon nitride mask layer, 3 is an edge isolation region, 4 is a first gate line electrode, 5 is a second gate line electrode, 6 is a semiconductor substrate, 7 is a transparent conductive layer, 71 is a first transparent conductive layer, 72 is a second transparent conductive layer, 73 is a third transparent conductive layer, 8 is a passivation layer, 9 is an anti-reflection layer, and 10 is a PN isolation region.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • “multiple” means two or more, unless otherwise clearly and specifically defined.
  • "Several” means one or more, unless otherwise clearly and specifically defined.
  • the terms “installed,” “connected,” and “connected” should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
  • an embodiment of the present application provides a solar cell comprising a semiconductor substrate 6 and a first semiconductor layer 100.
  • the semiconductor substrate 6 has a first surface and a second surface opposite each other.
  • the first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6.
  • the first semiconductor layer 100 comprises a first portion 11 and a second portion 12, wherein the first portion 11 and the second portion 12 are adjacent to each other along a second direction. That is, along the second direction, both sides of the first portion 11 are adjacent to the second portion 12, or one side of the first portion 11 is adjacent to the second portion 12.
  • the degree of crystallization of the first portion 11 is greater than that of the second portion 12.
  • the first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, that is, the first semiconductor layer 100 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first semiconductor layer 100 can be a combination of any two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.
  • the degree of crystallization of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon can be improved after laser crystallization. For example, when the first semiconductor layer 100 is an amorphous silicon layer, the laser crystallized portion will partially crystallize inside the amorphous silicon layer to form nanocrystalline grains.
  • Nanocrystalline silicon refers to a crystalline structure in which most of the grains are nanometer-sized, for example, the grain size is less than 200 nm.
  • the first semiconductor layer 100 includes a nanocrystalline silicon layer or a microcrystalline silicon layer, the crystallinity or degree of crystallization of the laser crystallized portion of the first semiconductor layer 100 will increase.
  • the present embodiment does not specifically limit the material and conductivity type of the semiconductor substrate 6.
  • the semiconductor substrate 6 may be a silicon substrate.
  • the semiconductor substrate 6 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate.
  • the conductivity type of the semiconductor substrate 6 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.
  • the semiconductor substrate 6 has a first surface and a second surface opposite to each other.
  • the first surface of the semiconductor substrate 6 can correspond to the light-facing surface of the solar cell, in which case the second surface of the semiconductor substrate 6 corresponds to the backlight surface of the solar cell; alternatively, the first surface of the semiconductor substrate 6 can correspond to the backlight surface of the solar cell, in which case the second surface of the semiconductor substrate 6 corresponds to the light-facing surface of the solar cell.
  • a crystallized structure is formed within the first portion 11 of the first semiconductor layer 100, resulting in a crystallized portion and a non-crystallized portion within the first portion 11.
  • the first portion 11 is not entirely crystallized, but rather mostly amorphous, with only a portion forming a crystallized structure, such as nanocrystals.
  • a second portion 12 of the first semiconductor layer 100, adjacent to the first portion 11 along the second direction, remains uncrystallized, retaining its original amorphous structure (it should be noted that when the first semiconductor layer 100 comprises nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon in the second portion 12 remains unchanged).
  • the overall degree of crystallization of the first portion 11 of the first semiconductor layer 100 being greater than the overall degree of crystallization of the second portion 12. It is understood that, with other factors being equal, the smaller the degree of crystallization of the semiconductor layer, the smaller the grains in the semiconductor layer, and the layer may even exhibit the disordered nature of amorphous silicon. Furthermore, the smaller the grains in the semiconductor layer, the more interfaces there are between the grains, resulting in a higher resistance at the grain interfaces. Therefore, the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces contact resistance, thereby reducing the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby helping to reduce transmission losses of carriers collected in the first semiconductor layer 100 to the conductive material.
  • the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring a passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second portion 12 is less, thereby ensuring a passivation effect of the second portion 12 and preventing leakage between the second portion 12 and the second semiconductor layer 2.
  • the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency.
  • the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.
  • the first semiconductor layer 100 is conformally disposed on the velvet surface.
  • the portion of the first semiconductor layer 100 covering at least a portion of the top of the pyramid-like structures has a greater degree of crystallization than the portion of the first semiconductor layer 100 covering the base of the pyramid-like structures.
  • the observed area should contain at least one pyramid-like structure.
  • the observed area should be greater than or equal to 5*5 ⁇ m 2 to prevent the degree of crystallization of the first semiconductor layer 100 from being inaccurately determined by observing only the base of the pyramid-like structures.
  • the contact resistance of the first portion 11 is lower than the contact resistance of the second portion 12. Because the first portion 11 has a crystalline structure or a higher degree of crystallization, and the second portion 12 has an amorphous structure or a lower degree of crystallization, the effective doping of the first portion 11 is increased, which can reduce the contact resistance of the first portion 11 relative to the second portion 12, thereby reducing energy loss during the current collection process of the first portion 11 and improving battery efficiency.
  • the overall contact resistance of a solar cell having the first semiconductor layer 100 with the first portion 11 is lower than the overall contact resistance of a solar cell having the first semiconductor layer 100 without the first portion 11.
  • the solar cell further includes a second semiconductor layer 2 disposed on the first surface.
  • the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction. That is, the solar cell is a back-contact solar cell.
  • the first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction.
  • the second semiconductor layer 2 has a side surface adjacent to the first semiconductor layer 100.
  • the second portion 12 is closer to the second semiconductor layer 2 than the first portion 11. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2.
  • the first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. To achieve the arrangement of P and N regions on the first surface, the first semiconductor layer 100 is one of a P region and an N region, and the second semiconductor layer 2 is the other of a P region and an N region.
  • the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.
  • the first semiconductor layer 100 may include a plurality of first strip portions 1 extending along the first direction
  • the second semiconductor layer 2 may include a plurality of second strip portions extending along the first direction.
  • the first strip portions 1 and the second strip portions are alternately arranged along the second direction, and the first direction and the second direction intersect.
  • the first strip portion 1 extends as a whole along the first direction, and the width direction of the first strip portion 1 is the same as the second direction; along the width direction of the first strip portion 1, the first strip portion 1 includes a first portion 11 and a second portion 12 that are adjacent to each other, that is, the first portion 11 and the second portion 12 are arranged adjacent to each other along the width direction of the first strip portion 1, and the second portion 12 is arranged closer to the second strip portion, and the second portion 12 is located between the first portion 11 and the second strip portion, thereby preventing leakage between the second portion 12 and the second strip portion.
  • the second portion 12 can be provided on both sides of the first portion 11 along the second direction, further reducing the risk of leakage.
  • both the first portion 11 and the second portion 12 are strip-shaped and extend along a first direction, intersecting the first and second directions.
  • the first portion 11 and the second portion 12 are arranged in a substantially parallel strip shape. This allows for gradual movement along the first direction during laser irradiation, facilitating the formation of the first portion 11 by laser irradiation.
  • the second portion 12 extends from the edge of the first portion 11 to a position close to the adjacent side surface, but does not contact the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to the region S3 in FIG5 , i.e., the end of the second portion 12 facing away from the first portion 11 is spaced a certain distance from the adjacent side surface. With this technical solution, the second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is larger, which helps further reduce the risk of leakage between the second portion 12 and the second semiconductor layer 2.
  • the second portion 12 extends from the edge of the first portion 11 to the adjacent side surface and contacts the adjacent side surface. Specifically, the second portion 12 extends from the edge of the first portion 11 to the S2 region in FIG5 , that is, the end of the second portion 12 facing away from the first portion 11 contacts the adjacent side surface, and the second portion 12 overlaps with at least part of the adjacent side surface.
  • the second portion 12 overlaps with at least part of the adjacent side surface of the second semiconductor layer 2, and the degree of crystallization of the second portion 12 is low. In this way, a weaker current can be transmitted through the adjacent side surfaces of the second portion 12 and the second semiconductor layer 2.
  • the current can form a leakage channel through the adjacent side surfaces of the second portion 12 and the second semiconductor layer 2, thereby preventing the blocked cell from becoming a load that consumes the energy generated by other illuminated cells, thereby reducing the risk of hot spots.
  • the distance between the edge of the first portion 11 and the adjacent side surface is greater than or equal to 20 ⁇ m.
  • This arrangement ensures that the first portion 11, which has a stronger transmission circuit capability, is spaced farther from the second semiconductor layer 2, reducing the potential for leakage between the first portion 11 and the second semiconductor layer 2.
  • the distance between the edge of the first portion 11 and the adjacent side surface is 20 ⁇ m, 22 ⁇ m, 24 ⁇ m, 25 ⁇ m, 50 ⁇ m, 70 ⁇ m, 100 ⁇ m, etc.
  • a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form an overlapping portion 15. That is, a portion of the second portion 12 extends to the upper side of the second semiconductor layer 2, and the portion of the second portion 12 located on the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is the overlapping portion 15.
  • the second portion 12 extends from the edge of the first portion 11 to the overlapping portion 15.
  • the second portion 12 extends from the edge of the first portion 11 to the region S1 in FIG5 , that is, the end of the second portion 12 facing away from the first portion 11 contacts the side of the second semiconductor layer 2 facing away from the semiconductor substrate 6.
  • the second part 12 Since the current transmission capability of the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6 is stronger than that of the adjacent side, in this technical solution, the second part 12 is extended from the edge of the first part 11 to the overlapping part 15, which can increase the current transmission capability between the second part 12 and the second semiconductor layer 2.
  • the current can form a leakage channel through the second part 12 and the surface of the second semiconductor layer 2 facing away from the semiconductor substrate 6.
  • the leakage channel has a stronger current transmission capability, further reducing the risk of hot spots.
  • the width of the second portion 12 along the second direction is less than or equal to 500 ⁇ m and greater than or equal to 20 ⁇ m. As shown in FIG5 , along the second direction, the extension distance of the second portion 12 is less than or equal to 500 ⁇ m and greater than or equal to 20 ⁇ m. In this configuration, if the width of the second portion 12 is set too large, for example, greater than 500 ⁇ m, it will block the second semiconductor layer 2 to a large extent, and effective current collection of the second semiconductor layer 2 cannot be formed. The leakage channel is too large, and the battery efficiency is greatly lost.
  • the width of the second portion 12 is set too small, for example, less than 20 microns, the laser crystallization process is difficult to control and may process other parts (such as the second semiconductor layer 2), causing damage to other parts.
  • the width of the second portion 12 along the second direction can be 100 ⁇ m, 90 ⁇ m, 80 ⁇ m, etc.
  • the width of the second portion 12 along the second direction is greater than or equal to 100 ⁇ m and less than or equal to 400 ⁇ m.
  • Such a design allows the second portion 12 to at least partially contact the second semiconductor layer 2 to form a leakage channel, while not overlapping the second semiconductor layer 2 too much to reduce the current collection area of the second semiconductor layer 2 .
  • the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, with the projection of the first portion 11 on the semiconductor substrate 6 completely located within the projection of the first transparent conductive layer 71 on the semiconductor substrate 6.
  • This configuration improves the carrier transport capability of the first semiconductor layer 100 by providing the first transparent conductive layer 71, enabling good ohmic contact with the electrode and enhancing conductivity.
  • the first portion 11 having a crystallized structure does not extend beyond the boundaries of the first transparent conductive layer 71, thereby reducing contact resistance within the effective conductive region of the first transparent conductive layer 71, improving conductivity, and increasing cell efficiency.
  • the first transparent conductive layer 71 extends to the adjacent side surface or extends to the second portion 12 located above the second semiconductor layer 2.
  • the first transparent conductive layer 71 can extend to the region S2 as shown in FIG5 , or the first transparent conductive layer 71 can extend to the region S1 as shown in FIG5 .
  • the first transparent conductive layer 71 can cover a larger area of the first semiconductor layer 100, further improving the conductive performance.
  • the solar cell further includes a second transparent conductive layer 72, which covers the second semiconductor layer 2; a PN isolation region 10 is provided between the second transparent conductive layer 72 and the first transparent conductive layer 71, and the PN isolation region 10 is located on the second semiconductor layer 2.
  • a PN isolation region 10 is provided between the second transparent conductive layer 72 and the first transparent conductive layer 71, and the PN isolation region 10 is located on the second semiconductor layer 2.
  • the solar cell may further include a third transparent conductive layer 73, which covers a portion of the second portion 12.
  • the first transparent conductive layer 71 covers the first portion 11, and an edge isolation region 3 is provided between the first transparent conductive layer 71 and the third transparent conductive layer 73.
  • the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 can further be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.
  • the transparent conductive layer can be a single-layer film or a laminated film.
  • a portion of the second portion 12 is disposed on the second semiconductor layer 2 to form an overlapping portion 15, and the PN isolation region 10 is disposed on the overlapping portion 15.
  • the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polysilicon layer 22
  • the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps the second semiconductor layer 2 to form an overlapping portion 15.
  • the PN isolation region 10 is located across the overlapping portion 15.
  • the width of the overlapping portion 15 needs to be reasonably set, for example, it can be in the range of 100-300 ⁇ m, so as to achieve the balance between the leakage channel and the current collection as described above.
  • the width of the second portion 12 directly affects the width of the overlapping portion 15 . Since the first portion 11 is at a certain distance from the adjacent side surface of the second semiconductor layer 2 , the width of the overlapping portion 15 should be preferably within the range of 100-300 ⁇ m.
  • the second semiconductor layer 2 when the first surface of a solar cell comprises a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 may comprise amorphous silicon, nanocrystalline silicon, and/or microcrystalline silicon.
  • the second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, except for a different conductivity type. That is, the second semiconductor layer 2 also has a first portion and a second portion adjacent to each other along the second direction, specifically referred to below as the third portion 201 and the fourth portion 202.
  • the third portion 201 of the second semiconductor layer 2 may or may not be entirely laser crystallized. For reference, see the above description of the first portion 11 of the first semiconductor layer 100, which will not be further elaborated here.
  • the first semiconductor layer 100 may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked together
  • the second semiconductor layer 2 may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked together, with both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer being disposed close to the semiconductor substrate 6.
  • the conductivity types of the first semiconductor layer 100 and the second semiconductor layer 2 may be interchangeable, which will not be described in detail.
  • the first semiconductor layer 100 and the second semiconductor layer 2 both of which have different conductivity types and are disposed on the first surface, can form a heterojunction structure, resulting in a heterojunction back-contact cell having both a P-region heterojunction structure and an N-region heterojunction structure on the back side.
  • This cell has the advantages of a heterojunction structure with good passivation, high conversion efficiency, long service life, and low energy consumption.
  • the heterojunction back-contact cell can also be applied to the cell structure described in this application with an amorphous structure at the edge and a crystalline structure in the middle region to improve cell efficiency.
  • the second semiconductor layer 2 when the first surface of the solar cell has a first semiconductor layer 100 and a second semiconductor layer 2, that is, when the solar cell is a back-contact cell, can be at least one of a polycrystalline silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer, and the first semiconductor layer 100 can be a heterojunction structure.
  • the second semiconductor layer 2 is a polycrystalline silicon layer, a tunneling passivation contact structure can be formed, and the second semiconductor layer 2 and the first semiconductor layer 100 have different conductivity types.
  • the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer stacked on the first surface, wherein the tunneling oxide layer 21 is disposed close to the semiconductor substrate 6.
  • the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22.
  • the first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 stacked on the first surface, wherein the intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6.
  • the doped polysilicon layer is a p-type doped polysilicon layer
  • the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.
  • a hybrid back contact cell having both a tunneling passivation contact structure and a heterojunction structure on the back is formed, wherein the first semiconductor layer 100 is a heterojunction structure.
  • the cell has the advantages of high conversion efficiency, good stability, and low Auger recombination of the tunneling passivation contact structure and good passivation effect, high conversion efficiency, long service life, and low energy consumption for preparation of the heterojunction structure.
  • the hybrid back contact cell can also be applied to the cell structure in which the edge is an amorphous structure and the middle area is a crystalline structure in the present application to improve the cell efficiency.
  • the second semiconductor layer 2 is other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed.
  • a back contact cell with different structures in the P region and N region can be formed.
  • the solar cell further includes a third semiconductor layer disposed on the second surface.
  • the material of the third semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, or microcrystalline silicon.
  • the third semiconductor layer has a different conductivity type from the first semiconductor layer 100. For example, if the entire second surface is covered with an amorphous silicon layer, the third semiconductor layer may also form a heterojunction structure.
  • the structure of the third semiconductor layer may be similar to that of the first semiconductor layer 100, similarly having a first portion 11 and a second portion 12, with the first portion 11 having a greater degree of crystallization than the second portion 12.
  • the conductivity type of the first semiconductor layer 100 is P-type and the conductivity type of the third semiconductor layer is N-type.
  • the first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate to the first surface.
  • the third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface, with the third intrinsic amorphous silicon layer disposed proximate to the second surface, thereby forming a bifacial heterojunction cell.
  • the conductivity type of the first semiconductor layer 100 can also be N-type
  • the conductivity type of the third semiconductor layer can be P-type, which will not be further described.
  • a polysilicon layer is disposed on the second surface, and the third semiconductor layer can form a tunneling passivation contact structure.
  • the first semiconductor layer 100 has a P-type conductivity type and the third semiconductor layer has an N-type conductivity type.
  • the first semiconductor layer 100 includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer disposed proximate the first surface.
  • the third semiconductor layer includes an N-type doped polysilicon layer disposed on the second surface, with a tunneling oxide layer disposed between the N-type doped polysilicon layer and the second surface.
  • the tunneling oxide layer and the N-type doped polysilicon layer form a tunneling passivation contact structure.
  • the third semiconductor layer can be disposed locally on the second surface, for example, in the form of multiple strips, forming a poly-finger structure. Doped field regions can be selectively formed on the substrate between the poly-finger structures. Alternatively, the third semiconductor layer can be formed entirely on the second surface, with only a thicker portion in the metallized contact area and a thinner portion in the non-metallized area.
  • the first semiconductor layer 100 may be a heterojunction structure, thus forming a double-sided hybrid solar cell.
  • the conductivity type of the first semiconductor layer 100 may also be N-type
  • the conductivity type of the third semiconductor layer may be P-type, which will not be described in detail.
  • bifacial heterojunction cells and bifacial hybrid solar cells can also be applied to the cell structure in which the degree of crystallization of the first part 11 is greater than that of the second part 12 in this application to improve cell efficiency.
  • the first portion 11 extends along the first direction to the edge of the first surface. That is, along the first direction, both ends of the first portion 11 extend to the edge of the first surface of the semiconductor substrate 6. This maximizes the area of the first portion 11, reduces contact resistance, and improves current collection capability. It should be noted that because the portion of the first semiconductor layer 100 near the edge of the semiconductor substrate 6 has large defects, poor passivation, high leakage current, and severe recombination, the portion of the first portion 11 near the edge of the first surface of the semiconductor substrate 6 may not serve as a current collection area.
  • the second portion 12 can surround the first portion 11. Specifically, the second portion 12 is disposed on both sides of the first portion 11, whether along the first direction or the second direction, completely surrounding the first portion 11. This arrangement allows the second portion 12 surrounding the first portion 11 to have a lower degree of crystallization, further reducing the risk of electrical leakage and ensuring the photovoltaic conversion efficiency of the solar cell.
  • the first portion 11 is rectangular and the second portion 12 is annular. That is, the first portion 11 located in the middle region corresponds to a rectangular shape, and the second portion 12 located in the edge region corresponds to a rectangular ring.
  • the first semiconductor layer 100 can form a continuous structure covering the entire first surface. In this case, the first semiconductor layer 100 can form one side of a bifacial solar cell, serving as either a P region or an N region. Because the first semiconductor layer 100 includes amorphous silicon and/or nanocrystalline silicon, the first semiconductor layer 100 can form a heterojunction structure.
  • the width of the second portion 12, extending from the first portion 11 to the second portion 12 and perpendicular to the side length of the semiconductor substrate 6, is 0.3 mm to 12 mm. This means that a 0.3 mm to 12 mm edge region around the first portion 11 is reserved and not subjected to laser crystallization. If the width of the second portion 12 is too wide, the area of the first portion 11 with the crystallized structure of the solar cell as a whole is smaller, resulting in less reduction in series resistance and greater current collection losses. If the width of the second portion 12 is too small, on the one hand, the edges of the first semiconductor layer 100 are thinner due to limitations of the coating process.
  • the width of the second portion 12 is selected to be 0.3 mm to 12 mm.
  • the width of the second portion 12 is 0.3 mm to 3 mm. This further increases the area of the first portion 11 of the first semiconductor layer 100, reduces contact resistance, and improves battery efficiency.
  • the width of the second portion 12 can be 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, etc.
  • the extension lengths of the second portions 12 at both end edges of the first strip-shaped portions 1 are 1 mm, 1.2 mm, 1.5 mm, etc.
  • the degree of crystallization of the two first strip-shaped portions 1 near the two side edges of the first surface is the same as the degree of crystallization of the second portions 12.
  • the material of the first portion 11 includes at least one of amorphous silicon and nanocrystalline silicon, that is, the first portion 11 can be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon, and the degree of crystallization can be improved after laser crystallization.
  • the first semiconductor layer 100 is an amorphous silicon layer
  • the laser crystallized portion will partially crystallize inside the amorphous silicon layer to form nanocrystalline grains.
  • the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystalline, the crystallinity or degree of crystallization of the first semiconductor layer 100 will be increased in the laser crystallized portion.
  • the material of the second portion 12 can be amorphous silicon, so that the second portion 12 has a better passivation effect.
  • the degree of crystallization of at least one first strip-shaped portion 1 near the edge of the first surface along the second direction is the same as the degree of crystallization of the second portion 12.
  • the plurality of first strip-shaped portions 1 are arranged along the second direction, and in the arrangement direction, the entire area of at least one first strip-shaped portion 1 near the edge of the first surface has the same degree of crystallization as the second portion 12.
  • At least one first strip-shaped portion 1 near the edge is not laser crystallized, while the remaining first strip-shaped portions 1 form amorphous second portions 12 only at both side edges in the second direction, thereby achieving an amorphous structure at both side edges of the first semiconductor layer 100.
  • the degree of crystallization of the entire area of the two strip-shaped portions respectively located on the two edges of the first surface is the same as the degree of crystallization of the second part 12, or two, three or more first strip-shaped portions 1 having the same degree of crystallization as the second part 12 are reserved near the edge of each first surface.
  • the semiconductor substrate 6 includes a recessed portion on the first surface, the recessed portion including sidewalls and a bottom wall.
  • the recessed portion is recessed relative to the remainder of the first surface toward the second surface, and the first portion 11 is located within the recessed portion.
  • the recessed portion is formed by etching into the surface of the semiconductor substrate 6 and typically has a textured surface. Positioning the first portion 11, which comprises amorphous silicon, nanocrystalline silicon, and/or microcrystalline silicon, within the recessed portion increases the contact area of the first portion 11, facilitating current collection.
  • the side of the semiconductor substrate 6 on which the amorphous semiconductor layer is provided has a velvet structure, and the amorphous semiconductor layer is conformal to the velvet structure.
  • the velvet structure has a light trapping effect, which increases the collection of light, and the velvet structure can achieve better contact with the electrode.
  • the crystallized structure reduces the contact resistance, but reduces the passivation effect, and the recombination may increase, which is not conducive to the photoelectric efficiency. Therefore, by forming a crystallized structure in a local area of a part of the velvet structure, the two factors of contact resistance and passivation effect can be balanced, so that the battery efficiency is optimized.
  • the EL (electroluminescent) test of a solar cell is a method for detecting internal defects in solar cells.
  • the brightness of the first portion 11, which has a relatively high degree of crystallization is greater than that of the second portion 12, which has a relatively low degree of crystallization.
  • the brightness of the first portion 11 in the EL test image is greater than that of the second portion 12, indicating that the contact resistance of the first portion 11 is lower than that of the second portion 12.
  • the electroluminescent brightness of the first portion 11, which has a lower contact resistance is higher, while the electroluminescent brightness of the second portion 12 is lower.
  • the image of solar cell B in Figure 19 shows that the brightness of the first portion 11 of solar cell B is greater than that of the second portion 12. Comparing it with the image of solar cell C shows that the brightness of solar cell C is consistent across the entire surface and is lower overall than that of solar cell B, indicating that the overall contact resistance of solar cell C is higher.
  • the solar cell further includes a first gateline electrode 4 extending along a first direction, and the first gateline electrode 4 is conductively disposed on the first portion 11 of the first semiconductor layer 100.
  • the first gateline electrode 4 extends in the same direction as the first strip-shaped portion 1, and is capable of collecting carriers from both the first portion 11 and a portion of the second portion 12 on the same first semiconductor layer 100.
  • the first gateline electrode 4 can improve its ability to collect carriers from the first semiconductor layer 100.
  • the solar cell further includes a second gate electrode 5 conductively disposed on the second semiconductor layer 2.
  • the second gate electrode 5 extends along a first direction, which is consistent with the extension direction of the second semiconductor layer 2.
  • the first gate electrode 4 is disposed on the first transparent conductive layer 71
  • the second gate electrode 5 is disposed on the second transparent conductive layer 72.
  • the ratio of the width of the first gate electrode 4 to the width of the first portion 11 is 10% to 120%, and specifically can be 10%, 30%, 50%, 80%, 100%, 120%, etc.
  • the ratio of the width of the first gate electrode 4 to the width of the middle portion is selected based on the material and carrier transport capability of the first semiconductor layer 100. If the carrier transport capability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be increased to increase the contact area between the first gate electrode 4 and the middle portion and reduce the contact resistance. Conversely, the ratio of the width of the first gate electrode 4 to the width of the middle portion can be reduced to save electrode material while still meeting current collection requirements.
  • the width of the first gateline electrode 4 can be 30 ⁇ m to 600 ⁇ m. Specifically, when the first gateline electrode 4 is fabricated using a screen printing process, the width of the first gateline electrode 4 is 30 ⁇ m to 80 ⁇ m. When the first gateline electrode 4 is fabricated using a deposition method such as electroplating, the width of the first gateline electrode 4 is 100 ⁇ m to 600 ⁇ m. The width of the middle portion is 200 ⁇ m to 700 ⁇ m. The appropriate width of the first gateline electrode 4 is selected based on the width of the middle portion and the electrode fabrication process.
  • the first gateline electrode 4 extends along the first direction and is disposed on the first transparent conductive layer 71.
  • the width of the first gateline electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle portion.
  • the width of the first transparent conductive layer 71 is 120 ⁇ m to 800 ⁇ m
  • the width of the first portion 11 is 200 ⁇ m to 700 ⁇ m
  • the ratio of the width of the first transparent conductive layer 71 to the width of the first portion 11 is 1.2 to 1.5.
  • the width of the first transparent conductive layer 71 is selected appropriately based on the width of the first portion 11.
  • the width of the first gateline electrode 4 is also selected appropriately based on the widths of the first portion 11, the first transparent conductive layer 71, and the electrode fabrication process. With this arrangement, the first gateline electrode 4 can be positioned directly opposite the first portion 11, with the width of the first transparent conductive layer 71 greater than the width of the middle portion, thereby improving current collection capability.
  • an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell described in any of the above embodiments.
  • the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the above solar cell, which will not be described in detail here.
  • the present application also provides a method for manufacturing a solar cell.
  • the method can be used to manufacture the solar cell described in Figures 1 to 6 and any of the above embodiments.
  • the method comprises the following steps:
  • a semiconductor substrate 6 is provided.
  • the semiconductor substrate 6 has a first surface and a second surface opposite to each other.
  • Step S200 forming a first semiconductor layer 100 on the first surface, wherein the first semiconductor layer 100 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon;
  • step S300 the first portion 11 of the first semiconductor layer 100 is irradiated with laser light, while the second portion 12 of the first semiconductor layer 100 is not irradiated, so that the degree of crystallization of the first portion 11 is greater than that of the second portion 12 ; the first portion 11 and the second portion 12 are adjacent to each other along the second direction.
  • a laser is used to perform crystallization treatment on the area corresponding to the first portion 11 of the first semiconductor layer 100, so that the degree of crystallization is improved, while the area corresponding to the second portion 12 of the first semiconductor layer 100 adjacent to the first portion 11 is not subjected to laser irradiation, and the amorphous structure is retained.
  • the first semiconductor layer 100 includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallization or crystallinity of the nanocrystalline silicon or microcrystalline silicon of the second portion 12 remains unchanged), so that the overall degree of crystallization of the first portion 11 of the first semiconductor layer 100 is greater than the overall degree of crystallization of the second portion 12.
  • the crystallized structure in the first portion 11 of the first semiconductor layer 100 reduces contact resistance, thereby reducing the contact resistance between the first portion 11 and the conductive material (transparent conductive layer or electrode), thereby helping to reduce transmission losses of carriers collected in the first semiconductor layer 100 to the conductive material.
  • the degree of crystallization of the second portion 12 of the first semiconductor layer 100 is less than that of the first portion 11, ensuring the passivation effect of the second portion 12 adjacent to the first portion 11 along the second direction, and reducing recombination at the edge of the first semiconductor layer 100. That is, for a back-contact solar cell, the second portion 12 of the first semiconductor layer 100 is closer to the second semiconductor, and the degree of crystallization of the second portion 12 is less, thereby ensuring the passivation effect of the second portion 12 and preventing leakage between the second portion 12 and the second semiconductor layer 2.
  • the higher degree of crystallization of the first part 11 is utilized to optimize the overall cell efficiency of the solar cell and improve the cell efficiency.
  • the lower degree of crystallization of the second part 12 is utilized to ensure the passivation effect of the second part 12 and prevent leakage.
  • a second semiconductor layer 2 is formed on the first surface.
  • the first semiconductor layer 100 and the second semiconductor layer 2 are arranged adjacent to each other along the second direction.
  • the first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types, and the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100. Compared with the first portion 11, the second portion 12 is closer to the second semiconductor layer 2.
  • the solar cell is a back-contact solar cell.
  • the first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface, and the first semiconductor layer 100 and the second semiconductor layer 2 are disposed adjacent to each other along the second direction.
  • the second semiconductor layer 2 has an adjacent side surface close to the first semiconductor layer 100.
  • the second portion 12 is closer to the second semiconductor layer 2. That is, along the second direction, the second portion 12 is located between the first portion 11 and the second semiconductor layer 2.
  • the first semiconductor layer 100 and the second semiconductor layer 2 have different conductivity types. To achieve the arrangement of P and N regions on the first surface, the first semiconductor layer 100 is one of the P and N regions, and the second semiconductor layer 2 is the other of the P and N regions.
  • the second part 12 of the first semiconductor layer 100 is closer to the second semiconductor layer 2, and the degree of crystallization of the second part 12 is relatively low to ensure the passivation effect of the second part 12, thereby preventing leakage between the second part 12 and the second semiconductor layer 2 and reducing the photoelectric conversion efficiency of the solar cell.
  • the first semiconductor layer 100 includes an amorphous silicon layer. After laser irradiation of a central portion, the amorphous silicon layer partially crystallizes to form nanocrystals. Using an amorphous silicon layer as the first semiconductor layer 100 provides a better passivation effect in the portion not irradiated by the laser, and provides a better insulation effect in the PN isolation region 10.
  • the first portion 11 extends along the first direction and is in a strip shape
  • the step S300 of irradiating the first portion 11 with laser light specifically includes the following steps:
  • step S301 a laser is irradiated on the first portion 11 along a first direction, and along a second direction, a starting position or an ending position of the laser is at a first distance from an adjacent side surface.
  • the second portion 12 extends from the edge of the first portion 11 to the region S3 in Figure 5.
  • the first distance is the width of the region S3 along the second direction, that is, there is a certain distance between the end of the second portion 12 facing away from the first portion 11 and the adjacent side surface.
  • the second portion 12 does not contact the second semiconductor layer 2, and the distance between the second portion 12 and the second semiconductor layer 2 is large, which helps further reduce the risk of leakage between the second portion 12 and the second semiconductor layer 2.
  • the starting or ending position of the laser is at a second distance from the boundary of the first semiconductor layer 100.
  • the second distance is the extension distance of the second portion 12 along the first direction. The second distance prevents the laser from irradiating both ends of the first semiconductor layer 100 along the first direction, thereby retaining the amorphous structure. Due to the non-uniformity of the laser's full width and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge portion of the first semiconductor layer 100, the laser damages the passivation of the edge portion, thereby increasing the recombination of the edge portion.
  • the present application does not form a crystallized structure at both ends of the first semiconductor layer 100 through laser, retaining the amorphous structure of the first semiconductor layer 100 at both ends, thereby ensuring the passivation effect at the edge portion and reducing the recombination of the edge portion.
  • the second distance is greater than the first distance, that is, the width of the second portion 12 along the first direction (the second portion immediately adjacent to the first portion along the second direction) is greater than the width of the second portion along the second direction.
  • the first distance is less than or equal to 500 ⁇ m
  • the second distance is 0.3-12 mm.
  • the wavelength of the laser is 325 nm to 532 nm.
  • the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and/or the energy density of the laser is 200 mJ/ cm2 to 6000 mJ/ cm2 .
  • the energy density of the laser can be 200 mJ/ cm2 , 500 mJ/cm2, 1000 mJ/ cm2 , 2000 mJ/ cm2 , 3000 mJ/ cm2 , 5000 mJ/ cm2 , 6000 mJ/ cm2 , etc.
  • the pulse width of the laser can be on the order of picoseconds to nanoseconds.
  • the laser can be absorbed by the first semiconductor layer 100, which is conducive to crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high temperature range will expand, and the temperature at the top of the suede structure will be too high, thereby affecting the passivation of the top region of the suede structure. If the laser energy density is too low, the energy accumulation time will be too long, affecting production efficiency, and the energy may not reach the energy required for crystallization. Therefore, choosing the laser energy density within this range can achieve high temperature only at the top of the textured structure, achieving morphological changes and forming a crystallized structure.
  • this embodiment provides a specific process for manufacturing a solar cell. Taking the preparation of a hybrid back-contact cell having a tunneling passivation contact structure and a heterojunction structure on the back as an example, the preparation process of the back-contact cell is as follows:
  • Step 1 As shown in FIG7 , the silicon wafer is polished and cleaned. Specifically, the silicon wafer is placed in a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer. The polishing morphology of both sides is regulated by controlling the temperature, time, and concentration of the chemical solution. The obtained silicon wafer is used as a semiconductor substrate 6, which can be an n-type, p-type, or intrinsic silicon substrate.
  • Step 2 As shown in FIG8 , a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 are sequentially formed on the backlight surface of the semiconductor substrate 6, wherein the tunneling oxide layer 21 is a SiOx layer.
  • the tunneling oxide layer 21 and the intrinsic polysilicon layer 23 are formed using one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition.
  • the tunneling oxide layer 21 can be formed by a high-temperature reaction of oxygen with the semiconductor substrate 6, or by a wet chemical method, such as a reaction of silicon with ozone, or an oxidation reaction of silicon with nitric acid.
  • the thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, and optionally, the thickness is 1.4 nm.
  • the thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, and optionally, the thickness is 120 nm.
  • Step 3 As shown in FIG9 , the intrinsic polysilicon layer 23 is doped by high-temperature diffusion to form an n-type doped polysilicon layer 22 , and a phosphorus-containing oxide layer, namely, a phosphosilicate glass layer 24 , is generated.
  • the doping concentration of the n-type doped polysilicon layer 22 is 1 ⁇ 10 19 cm -3 to 5 ⁇ 10 20 cm -3 .
  • Step 4 As shown in FIG10 , the phosphosilicate glass layer 24 formed after phosphorus diffusion is removed by using an HF solution.
  • Step 5 As shown in Figure 11, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22.
  • the silicon nitride mask layer 25 acts as a hydrogen source, providing hydrogen atoms at the interface between the crystalline silicon and the tunnel oxide layer 21 to passivate dangling bonds and also passivates some defects within the crystalline silicon. It also serves as a mask to protect the N-region film layer during subsequent P-region patterning.
  • Step 6 As shown in FIG12 , the P region is patterned using a laser process, and all P region film layers are laser ablated until the semiconductor substrate 6 .
  • the laser can be a 532 nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used.
  • Step 7 As shown in Figure 13, the exposed semiconductor substrate 6 in the P region is textured using a wet etching process to obtain a textured structure, such as a pyramid structure.
  • the silicon nitride mask layer 25 is then removed.
  • This wet etching process serves two purposes: firstly, to remove the damaged layer of the semiconductor substrate 6 in the P region after laser treatment, thus cleaning the interface; and secondly, to remove the silicon nitride mask layer 25 deposited in the N region.
  • Step 8 As shown in Figure 14, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the entire backlight surface of the semiconductor substrate 6 to form a P-region emitter.
  • the intrinsic amorphous silicon layer 13 has a thickness of 2nm to 20nm, and optionally, a thickness of 8nm;
  • the p-type amorphous silicon layer 14 has a thickness of 5nm to 50nm, and optionally, a thickness of 15nm.
  • a passivation layer 8 and an anti-reflection layer 9 are sequentially deposited on the front velvet surface of the semiconductor substrate 6.
  • the anti-reflection layer 9 can be any combination of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • the passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.
  • Step 9 As shown in Figure 15, the N region is patterned using a laser process to remove the intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polysilicon layer 22, exposing the n-type doped polysilicon layer 22.
  • An oxide layer will be generated on the n-type doped polysilicon layer 22, which will be removed by a wet etching process.
  • the laser can use a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser can be used.
  • the wet etching process can use a chain device, with the semi-finished product facing up and protected by a water film. The back is in contact with the HF solution to remove the oxide layer and the silicon nitride plated on the back.
  • Step 10 As shown in FIG15 , a laser process is used to irradiate the corresponding area of the first portion 11 of the p-type amorphous silicon layer 14 in the P region, so that the p-type amorphous silicon layer 14 forms a first portion having a crystallized structure, while the edge of the p-type amorphous silicon layer 14 along the second direction is not irradiated with laser, retaining the original amorphous structure to form a second portion 12.
  • the laser can be a 355nm or 532nm laser, and the pulse width can be a nanosecond or picosecond laser. Optionally, a 532 picosecond laser is used.
  • the pulsed laser spot moves and irradiates along the extension direction of the p-type amorphous silicon layer 14.
  • the laser processes in the ninth and tenth steps can be performed in the same step, and can be performed in no particular order.
  • the crystallization process is performed after the P region is patterned by laser.
  • a transparent conductive layer 7 is deposited on the backlight side of the semiconductor substrate 6.
  • the transparent conductive layer 7 can be one or more of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide, in a stacked or single layer.
  • a tin-doped indium oxide film layer can be used.
  • Step 12 As shown in FIG17 , the transparent conductive layer 7 on the N and P regions is disconnected to form a PN isolation region 10.
  • the transparent conductive layer 7 is formed into a first transparent conductive layer 71 located on the P region and a second transparent conductive layer 72 located on the N region, thereby achieving insulation between the P and N regions.
  • the transparent conductive layer 7 is disconnected near the edge of the semiconductor substrate 6 in the N and P regions, forming a third transparent conductive layer 73 located on the edge.
  • the PN isolation region 10 between the P and N regions spans the overlapping area between the N and P regions and part of the p region to achieve better insulation.
  • Step 13 As shown in FIG18 , a first gate line electrode 4 and a second gate line electrode 5 are deposited on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region, respectively.
  • the first gate line electrode 4 has two ends extending onto the second portions 12 on both sides as shown in FIG1 .
  • the first gate line electrode 4 and the second gate line electrode 5 can be made of silver, copper, aluminum, or a combination thereof.
  • the second semiconductor layer 2 of the solar cell of the embodiments of the present application includes a third portion 201 and a fourth portion 202 adjacent to the third portion 201 along the second direction, wherein the degree of crystallization of the third portion 201 is greater than the degree of crystallization of the fourth portion 202.
  • a portion of the second portion 12 of the first semiconductor layer 100 is disposed above the fourth portion 202 of the second semiconductor layer 2 to form an overlapping portion.
  • the solar cell includes a semiconductor substrate 6, a first semiconductor layer 100, and a second semiconductor layer 2.
  • the semiconductor substrate 6 has a first and second opposing surfaces.
  • the first semiconductor layer 100 and the second semiconductor layer 2 are both disposed on the first surface of the semiconductor substrate 6.
  • the first semiconductor layer 100 includes a first portion 11 and a second portion 12 adjacent to the first portion 11 along a second direction.
  • the first portion 11 has a higher degree of crystallization than the second portion 12.
  • the second semiconductor layer 2 includes a third portion 201 and a fourth portion 202 adjacent to the third portion 201 along the second direction.
  • the third portion 201 has a higher degree of crystallization than the fourth portion 202.
  • a portion of the second portion 12 of the first semiconductor layer 100 is disposed above the fourth portion 202 of the second semiconductor layer 2 to form an overlapping portion 15.
  • the second semiconductor layer 2 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.
  • the formation method and structure of the third portion 201 and the fourth portion 202 are similar to those of the first portion 11 and the second portion 12, and are not described in detail here.
  • the solar cell of this embodiment includes a semiconductor substrate 6 (e.g., a silicon substrate), with a first region, a second region, and a third region adjacent to each other on one side of the semiconductor substrate 6.
  • a semiconductor substrate 6 e.g., a silicon substrate
  • the first semiconductor layer 100 and a first electrode 4 are sequentially stacked on the semiconductor substrate 6.
  • the first semiconductor layer 100 is also referred to as a first doped layer.
  • a second semiconductor layer 2 and a second electrode 5 are sequentially stacked on the semiconductor substrate 6.
  • the second semiconductor layer 2 is also referred to as a second doped layer.
  • the first semiconductor layer 100 and the second semiconductor layer 2 have opposite conductivity.
  • the first semiconductor layer 100 and the second semiconductor layer 2 extend into the second region.
  • At least one of the first semiconductor layer 100 in the first region and the second semiconductor layer 2 in the third region has a crystallized region (a first portion 11 and a third portion 201).
  • a first portion 11 and a third portion 201 In the second region, at least a portion of the first semiconductor layer 100 is an amorphized region (a second portion 12), and at least a portion of the second semiconductor layer 2 is an amorphized region (a fourth portion 202).
  • the second portion 12 and the fourth portion 202 form an overlapping portion 15 in the second region.
  • the first doped layer in the first region has a textured surface
  • only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.
  • the first doped layer in the first region when the first doped layer in the first region has a smooth surface, the first doped layer in the laser irradiation region undergoes crystal transformation.
  • the second doped layer in the third region has a textured surface
  • only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.
  • the second doped layer in the third region when the second doped layer in the third region has a smooth surface, the second doped layer in the laser irradiation region undergoes crystal transformation.
  • a high-resistivity second region is provided between the first semiconductor layer 100 in the first region and the second semiconductor layer 2 in the third region for isolation. This reduces lateral carrier migration and leakage. Furthermore, the first semiconductor layer 100 in the first region has a first portion 11 with a higher degree of crystallization, and the second semiconductor layer 2 in the third region has a third portion 201 with a higher degree of crystallization. These crystallized regions have good conductivity and are conducive to carrier collection.
  • the second portion 12 of the first semiconductor layer 100 has a lower degree of crystallization or is even an amorphous region
  • the fourth portion 202 of the second semiconductor layer 2 has a lower degree of crystallization or is even an amorphous region.
  • Amorphous regions have lower carrier mobility and lower sheet resistance than crystalline regions, significantly reducing leakage current.
  • the solar cell further includes a first gateline electrode 4, which is stacked above the first semiconductor layer 100.
  • the projection of the first gateline electrode 4 on the semiconductor substrate 6 overlaps with the projection of the first portion 11 on the semiconductor substrate 6, and the projection area of the first gateline electrode 4 on the semiconductor substrate 6 is smaller than the projection area of the first portion 11 on the semiconductor substrate 6.
  • the projection of the first gateline electrode 4 on the semiconductor substrate 6 completely falls within the projection range of the first portion 11 on the semiconductor substrate 6, thereby ensuring that the first gateline electrode 4 is in contact with the first portion 11.
  • the solar cell further includes a second gateline electrode 5.
  • the first gateline electrode 5 is stacked above the second semiconductor layer 2, and the projection of the second gateline electrode 5 on the semiconductor substrate 6 overlaps with the projection of the third portion 201 on the semiconductor substrate 6. Furthermore, the projection area of the second gateline electrode 5 on the semiconductor substrate 6 is smaller than the projection area of the third portion 201 on the semiconductor substrate 6. Generally speaking, the projection of the second gateline electrode 5 on the semiconductor substrate 6 falls completely within the projection of the third portion 201 on the semiconductor substrate 6, thereby ensuring that the second gateline electrode 5 contacts the third portion 201.
  • the projection of the first gateline electrode 4 on the semiconductor substrate 6 overlaps with the projection of the first portion 11 on the semiconductor substrate 6, and the projection area of the first gateline electrode 4 on the semiconductor substrate 6 is smaller than the projection area of the first portion 11 on the semiconductor substrate 6.
  • the projection of the first gateline electrode 4 on the semiconductor substrate 6 e.g., a silicon substrate
  • the projection of the second gateline electrode 5 on the semiconductor substrate 6 overlaps with the projection of the third portion 201 on the semiconductor substrate 6, and the projection area of the second gateline electrode 5 on the semiconductor substrate 6 is smaller than the projection area of the third portion 201 on the semiconductor substrate 6.
  • the projection of the second gateline electrode 5 on the semiconductor substrate 6 (e.g., a silicon substrate) completely falls within the projection of the third portion 201 on the semiconductor substrate 6.
  • the current density here is the highest. Since the transmission efficiency of the first part 11 and the third part 201 is higher than that of the second part 12 and the fourth part 202, the larger the projected area of the first part 11 and the third part 201 on the semiconductor substrate 6, the higher the transmission efficiency and the smaller the contact resistance.
  • Step 1 Polish and clean the silicon wafer, and perform texturing on the light-incident surface.
  • Step 2 PECVD is used to deposit a 5nm intrinsic hydrogenated amorphous silicon passivation layer, a 30nm amorphous n layer, a 100nm SiNx layer (refractive index 2.5), and a 30nm laser absorption layer on the back of the battery.
  • Step 3 Use laser to remove the laser absorption layer in the first region, thereby forming a laser opening to expose the SiNx layer.
  • Step 4 Perform a wet process, use 10% concentration hydrofluoric acid to remove the SiNx layer in the laser opening to expose the amorphous n layer, and use 10% concentration potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer underneath, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.
  • Step 5 On the back of the cell, a 5nm intrinsic hydrogenated amorphous silicon passivation layer and a 30nm amorphous p-layer are sequentially deposited on the silicon wafer in the first area, the silicon nitride layer in the second area, and the silicon nitride layer in the third area using PECVD technology.
  • Step 6 Use laser (single spot energy density of laser is 200 mJ/cm 2 ) to remove the amorphous p layer and intrinsic hydrogenated amorphous silicon passivation layer in the third region to form an opening, thereby exposing the SiNx layer in the third region.
  • Step 7 Perform wet treatment and use 10% concentration hydrofluoric acid to remove the SiNx layer in the third area.
  • Step 8 Use PECVD to deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx anti-reflection film on the light-incident surface, with a refractive index of 2 and a thickness of 70nm.
  • Step 9 Perform laser crystallization treatment, using laser to crystallize the middle area of the amorphous p layer in the first region into a nanocrystalline p region, that is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist in the first region at the same time, the first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region, and the part of the amorphous n layer and the electrode layer stacked in the third region is crystallized into a nanocrystalline n region.
  • Step 10 sequentially depositing a TCO layer and an Ag electrode (first gate electrode) on the nanocrystalline p-layer; and sequentially depositing a TCO layer and an Ag electrode (second gate electrode) on the nanocrystalline n-layer.

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  • Photovoltaic Devices (AREA)

Abstract

La présente demande divulgue une cellule solaire et un procédé de fabrication s'y rapportant, et un module photovoltaïque. La cellule solaire comprend : un substrat semi-conducteur, qui a une première surface et une seconde surface opposées l'une à l'autre ; et une première couche semi-conductrice, qui est disposée sur la première surface, et comprend une première partie et une seconde partie qui est étroitement adjacente à la première partie dans une seconde direction, le degré de cristallisation de la première partie étant supérieur à celui de la seconde partie, et la première couche semi-conductrice étant constituée d'au moins l'un parmi le silicium amorphe, le silicium nanocristallin et le silicium microcristallin. En fournissant une zone cristallisée rationnelle et une zone non cristallisée rationnelle sur la première couche semi-conductrice, l'efficacité cellulaire globale de la cellule solaire est optimisée au moyen du degré supérieur de cristallisation de la première partie, ce qui permet d'améliorer l'efficacité de la cellule ; de plus, l'effet de passivation de la seconde partie est assuré au moyen du degré inférieur de cristallisation de la seconde partie, empêchant ainsi une fuite électrique.
PCT/CN2025/071575 2024-01-23 2025-01-09 Cellule solaire et procédé de fabrication s'y rapportant, et module photovoltaïque Pending WO2025157018A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
CN202410092536.4 2024-01-23
CN202410092536.4A CN117832302A (zh) 2024-01-23 2024-01-23 一种太阳能电池及其制备方法和电池组件
CN202410190935.4A CN118116983A (zh) 2024-02-20 2024-02-20 一种太阳能电池及其制备方法和电池组件
CN202410190935.4 2024-02-20
CN202411017051.5 2024-07-26
CN202411017051 2024-07-26
CN202411231282.6 2024-09-03
CN202411231282.6A CN120091661A (zh) 2024-07-26 2024-09-03 一种太阳能电池及其制作方法、光伏组件
CN202411231900.7A CN119421556B (zh) 2024-07-26 2024-09-03 一种太阳能电池及其制作方法、光伏组件
CN202411231900.7 2024-09-03

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CN118116983A (zh) * 2024-02-20 2024-05-31 隆基绿能科技股份有限公司 一种太阳能电池及其制备方法和电池组件

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