WO2025154570A1 - Semiconductor integrated circuit - Google Patents

Abstract

Provided is a semiconductor integrated circuit comprising a ground fault detection circuit that is operable even in a low voltage state in which an input voltage of a power supply line is reduced.　One end of a first resistor (R1) and one end of a second resistor (R2) are connected to a power supply line (202). A first switch (SW1) is connected between a second end of the first resistor (R1) and an output line (204) and is turned on when a high-side transistor (MH) is on. Transistors (Q1, Q2) are respectively connected to the first resistor (R1) and the second resistor (R2). A current source (242) is connected to the transistor (Q1). A current mirror group (244) includes a plurality of stages of current mirror circuits (CM1, CM2) and returns the current flowing through the transistor (Q2). A third resistor (R3) is connected to an output node of the current mirror group (244). A determination circuit (250) detects a ground fault abnormality on the basis of a voltage drop across the third resistor (R3).

Description

Semiconductor Integrated Circuit

This disclosure relates to semiconductor integrated circuits.

Semiconductor integrated circuits such as class D amplifiers, DC/DC converters, and motor drivers are equipped with a switching circuit (inverter) that includes a high-side transistor and a low-side transistor. If the output node of the switching circuit has a ground fault (short circuit to ground) and the high-side transistor is turned on, an overcurrent will flow through the high-side transistor. For this reason, semiconductor integrated circuits are sometimes equipped with a ground fault detection circuit.

JP 2017-195535 A

[overview]
The present disclosure has been made in light of such a situation, and an exemplary purpose of an embodiment of the present disclosure is to provide a semiconductor integrated circuit including a ground fault detection circuit that can operate even in a low-voltage state where the input voltage drops.

A semiconductor integrated circuit according to one embodiment of the present disclosure comprises a power supply line, an output line and a ground line, a constant voltage line generating a constant voltage lower than the input voltage of the power supply line, an output stage including a high-side transistor connected between the power supply line and the output line and a low-side transistor connected between the output line and the ground line, and a ground fault detection circuit that detects a ground fault in the output line. The ground fault detection circuit includes a first resistor having a first end connected to the power supply line, a second resistor having a first end connected to the power supply line, a first switch connected between the second end of the first resistor and the output line and turned on when the high-side transistor is on, a current source, a P-type first transistor having a first electrode connected to the second end of the first resistor and a control electrode and a second electrode connected to the current source, a P-type second transistor having a first electrode connected to the second end of the second resistor and a control electrode connected to the control electrode of the first transistor, a current mirror group including a multi-stage current mirror circuit that mirrors the current flowing through the second transistor and operates using a constant voltage as the power supply voltage, a third resistor connected to the output node of the current mirror group, and a determination circuit that generates a ground fault detection signal based on the result of comparing the voltage drop of the third resistor with a predetermined threshold voltage.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment. FIG. 2 is a circuit diagram of the ground fault detection circuit according to the embodiment. FIG. 3 is a circuit diagram for explaining the ground fault detection by the ground fault detection circuit. FIG. 4 is a circuit diagram of a ground fault detection circuit according to a comparative technique. FIG. 5 is a block diagram of an audio system. FIG. 6 is a block diagram of a step-down converter.

Detailed Description
(Overview of the embodiment)
A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

A semiconductor integrated circuit according to one embodiment comprises a power supply line, an output line and a ground line, a constant voltage line generating a constant voltage lower than the input voltage of the power supply line, an output stage including a high-side transistor connected between the power supply line and the output line and a low-side transistor connected between the output line and the ground line, and a ground fault detection circuit detecting a ground fault in the output line. The ground fault detection circuit includes a first resistor having a first end connected to the power supply line, a second resistor having a first end connected to the power supply line, a first switch connected between the second end of the first resistor and the output line and turned on when the high-side transistor is on, a current source, a P-type first transistor having a first electrode connected to the second end of the first resistor and a control electrode and a second electrode connected to the current source, a P-type second transistor having a first electrode connected to the second end of the second resistor and a control electrode connected to the control electrode of the first transistor, a current mirror group including a multi-stage current mirror circuit that mirrors the current flowing through the second transistor and operates using a constant voltage as the power supply voltage, a third resistor connected to the output node of the current mirror group, and a determination circuit that generates a ground fault detection signal based on the result of comparing the voltage drop of the third resistor with a predetermined threshold voltage.

With this configuration, by inserting a group of current mirrors, it becomes possible to detect ground faults even when the power supply voltage is low.

In one embodiment, the ground fault detection circuit may further include a second switch connected between the second end of the first resistor and the power supply line and turned on when the low-side transistor is on.

In one embodiment, the first transistor and the second transistor are bipolar transistors, and the high-side transistor, the low-side transistor, and the current mirror group may be MOS transistors. When using a semiconductor process in which bipolar transistors are faster than MOS transistors, constructing the first transistor and the second transistor from bipolar transistors enables high-speed ground fault detection.

In one embodiment, the first transistor, the second transistor, the high-side transistor, the low-side transistor, and the current mirror group may be MOS transistors.

In one embodiment, the semiconductor integrated circuit may be an audio class D amplifier.

In one embodiment, the semiconductor integrated circuit may be a switching regulator.

In one embodiment, the semiconductor integrated circuit may be for use in a vehicle.

In one embodiment, the minimum operating voltage of the semiconductor integrated circuit may be 4.5V or less.

(Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

In this specification, "a state in which component A is connected to component B" includes not only cases in which component A and component B are directly physically connected, but also cases in which component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

Similarly, "a state in which component C is connected (provided) between components A and B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

In addition, in this specification, the symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

1 is a circuit diagram of a semiconductor integrated circuit 200 according to an embodiment. The semiconductor integrated circuit 200 has a power supply terminal VCC, a switching terminal SW, a ground terminal GND, and a bootstrap terminal BS. A power supply voltage (input voltage) _VCC is supplied to the power supply terminal VCC, and the ground terminal GND is grounded. An inductive element such as a speaker coil, a motor coil, or an inductor is connected to the switching terminal SW. A bootstrap capacitor _CBS is connected between the bootstrap terminal BS and the switching terminal SW.

The semiconductor integrated circuit 200 generates, at the switching terminal SW, one of a high-level voltage V _CC , a low-level voltage of 0 V, or a high impedance state.

The semiconductor integrated circuit 200 includes a power supply line 202, an output line (also called a switching line) 204, a ground line 206, a bootstrap line 208, a rectifier element 209, a high-side driver 210, a low-side driver 220, a level shifter 230, and a ground fault detection circuit 240.

The power supply line 202 is connected to a power supply terminal VCC. The output line 204 is connected to a switching terminal SW. The ground line 206 is connected to a ground terminal GND. The bootstrap line 208 is connected to a bootstrap terminal BS. A constant voltage V _REG generated by a power supply circuit (not shown) is supplied to the bootstrap terminal BS via a rectifier element 209. The rectifier element 209 may be a diode whose cathode is connected to the bootstrap line 208 and whose anode receives the constant voltage V _REG . The rectifier element 209 may be a synchronous rectifier switch that switches in synchronization with the high-side transistor MH. The rectifier element 209 and an external bootstrap capacitor C _BS form a bootstrap circuit, which generates a bootstrap voltage V _BS in the bootstrap line 208, which is higher by V _REG -Vf than the switching voltage V _SW generated in the switching terminal SW (output line 204). Vf is the forward voltage of the rectifying element 209 .

The high-side transistor MH and the low-side transistor ML are N-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The high-side transistor MH is connected between the power supply line 202 and the output line 204, and the low-side transistor ML is connected between the output line 204 and the ground line 206.

The level shifter 230 level-shifts up the control signal HIN and passes it to the high-side driver 210. The high-side driver 210 drives the high-side transistor MH in response to the control signal HIN. The low-side driver 220 drives the low-side transistor ML in response to the control signal LIN.

When the high-side transistor MH is on and the low-side transistor ML is off, the switching voltage V _SW is a high-level voltage V _CC , and when the high-side transistor MH is off and the low-side transistor ML is on, the switching voltage V _SW is a low-level voltage 0 V. When both the high-side transistor MH and the low-side transistor ML are off, the switching terminal SW becomes high impedance.

The ground fault detection circuit 240 is enabled in a high output state in which the high-side transistor MH is on and the low-side transistor ML is off. In the enabled state, the ground fault detection circuit 240 can detect a ground fault abnormality in the switching terminal SW, and when a ground fault abnormality is detected, it asserts the ground fault detection signal GDET (for example, to a high level). The gate signal of the high-side transistor MH is supplied to the ground fault detection circuit 240 as an active high enable signal EN.

2 is a circuit diagram of a ground fault detection circuit 240 according to an embodiment. The ground fault detection circuit 240 includes a first switch SW1, a second switch SW2, a current source 242, a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a current mirror group 244, a level shifter 246, and a determination circuit 250.

A constant voltage _VREGD lower than the power supply voltage (input voltage) _VCC of the power supply line 202 is generated in the constant voltage line 203. For example, when the semiconductor integrated circuit 200 is an in-vehicle circuit, the power supply voltage _VCC may be 12V, and the constant voltage _VREGD may be 5V, 3.3V, or 1.5V.

The first end of the first resistor R1 is connected to the power supply line 202. The first end of the second resistor R2 is connected to the power supply line 202.

The first switch SW1 is connected between the second end of the first resistor R1 and the output line 204. The first switch SW1 is turned on when the high-side transistor MH is on. For example, the first switch SW1 is an NMOS transistor, and the gate of the first switch SW1 is supplied with the gate signal of the high-side transistor MH.

The second switch SW2 is connected between the power supply line 202 and the second end of the first resistor R1, and is turned on when the high-side transistor MH is turned off.

When the first switch SW1 is on and the second switch SW2 is off, the ground fault detection circuit 240 is enabled. When the first switch SW1 is off and the second switch SW2 is on, the ground fault detection circuit 240 is disabled.

The first transistor Q1 is a PNP bipolar transistor, and its first electrode (emitter) is connected to the second end of the first resistor R1. The second electrode (collector) and control electrode (base) of the first transistor Q1 are connected to the current source 242. The current source 242 includes, for example, a current source 243 and a current mirror circuit CM10, and sinks a constant current Ic.

The second transistor Q2 is a PNP bipolar transistor of the same type as the first transistor Q1, with a first electrode (emitter) connected to the second end of the second resistor R2 and a control electrode (base) connected to the control electrode (base) of the first transistor Q1.

The current mirror group 244 includes multiple stages of current mirror circuits and reflects the current Idet flowing through the second transistor Q2. In this example, the number of stages of the current mirror circuit is two, and includes two current mirror circuits CM1 and CM2. Note that the number of current mirror circuits may be an even number in order to reflect the current, and may be four, six, or eight stages. The current mirror group 244 is connected to the constant voltage line 203 and operates using the constant voltage _VREGD as a power supply voltage.

The third resistor R3 is connected between the output node 245 of the current mirror group 244 and the ground line 206. A voltage drop proportional to the output current Idet′ of the current mirror group 244 occurs across the third resistor R3.
Vdet=R3×Idet'

The determination circuit 250 generates the ground fault detection signal GDET based on the result of comparing the voltage drop (detection voltage) Vdet across the third resistor R3 with a predetermined threshold voltage Vth. Specifically, the determination circuit 250 asserts the ground fault detection signal GDET when Vdet>Vth.

In this embodiment, the judgment circuit 250 includes a comparator 252, a filter 254, a filter 256, and an AND gate 258. The comparator 252 compares the detection voltage Vdet with a predetermined threshold voltage Vth. The filter 254 is a low-pass filter that removes high-frequency components from the output signal COMP of the comparator 252. Noise components are removed by the filter 254. The level shifter 246 level-shifts down the gate signal of the high-side transistor MH, which is the enable signal EN. The filter 256 is a low-pass filter that removes high-frequency components from the output of the level shifter 246. The output of the filter 256 becomes a mask signal MSK that is at a high level when the ground fault detection circuit 240 is enabled. The AND gate 258 takes the logical product of the output of the filter 254 and the mask signal MSK, and outputs it as the ground fault detection signal GDET.

The above is the configuration of the ground fault detection circuit 240. Next, we will explain the operation of the ground fault detection circuit 240.

FIG. 3 is a circuit diagram explaining the ground fault detection of the ground fault detection circuit 240. The switching terminal SW is shorted to the ground (ground fault) via the ground fault path 2, and a short current flows via the high-side transistor MH. At this time, in the ground fault detection circuit 240, a short current Ishort flows via the first resistor R1, the first switch SW1, and the ground fault path 2.

Since the sum of the short-circuit current Ishort and the current Ic generated by the current source 242 flows through the first resistor R1, the emitter voltage Ve of the first transistor Q1 is expressed by equation (1).
Ve=Vcc-R1×(Ishort+Ic)...(1)

Since the base-emitter voltage of the first transistor Q1 and the base-emitter voltage of the second transistor Q2 are substantially equal, a voltage equal to the emitter voltage Ve of the first transistor Q1 is generated at the emitter of the second transistor Q2. At this time, a detection current Idet expressed by the equation (2) flows through the second resistor R2.
Idet=Ve/R2=R1×(Ishort+Ic)/R2…(2)

When R1=R2,
Idet=(Ishort+Ic)...(2')
It becomes.

This detection current Idet is reflected by the current mirror circuits CM1 and CM2, and the detection current Idet' is supplied to the third resistor R3. When the current amplification factor of the current mirror group 244 is α, the detection current Idet' is expressed by the following equation (3).
Idet'=Idet×α...(3)
The current amplification factor α is the product of the mirror ratios of the current mirror circuits CM1 and CM2. The current amplification factor α may be set to 1 or a value greater than 1.

A voltage drop occurring in the third resistor R3 due to the flow of the current Idet' is a detection voltage Vdet, which is expressed by equation (4).
Vdet=Idet'×R3=α×(Ishort+Ic)×R3...(4)

The threshold voltage Vth is set so that it is higher than the detection voltage Vdet when no ground fault occurs (Ishort = 0) and lower than the detection voltage Vdet when a ground fault occurs (Ishort > 0). When a ground fault occurs and a large short circuit current Ishort flows, Vdet > Vth, and the ground fault detection signal GDET is asserted.

In this way, according to the semiconductor integrated circuit 200 of the embodiment, a ground fault in the switching terminal SW can be detected by the ground fault detection circuit 240. Further advantages of the ground fault detection circuit 240 become clear when compared with comparative technologies.

FIG. 4 is a circuit diagram of a ground fault detection circuit 240R according to a comparative technique. The ground fault detection circuit 240R is the same as the ground fault detection circuit 240 in FIG. 2 except that the current mirror group 244 is omitted, and a third resistor R3 is directly connected to the collector of the second transistor Q2.

A voltage drop occurring across the third resistor R3 due to the flow of the current Idet is a detection voltage Vdet, which is expressed by equation (5).
Vdet=Idet×R3=(Ishort+Ic)×R3…(4)

The ground fault detection circuit 240R asserts the ground fault detection signal GDET when Vdet>Vth. We will explain the problem that occurs in the ground fault detection circuit 240R.

Consider the lower limit voltage of the power supply voltage V _CC of the ground fault detection circuit 240R. In a ground fault state, the following relational expression must be satisfied.
V _CC >(R2+R3)×Idet=R2×Idet+R3×Idet
In a ground short state, R3×Idet is higher than the threshold voltage Vth.
R3×Idet>Vth
For accurate voltage comparison in the determination circuit 250, it is desirable to set Vth to 1V or more, preferably to about 2 to 3V.
R3×Idet>Vth≧2V

In a ground fault state, if R2 × Idet ≈ 3.5 V,
V _CC >3.5V+2V=5.5V
Therefore, the minimum operating voltage V _{CC (MIN)} is 5.5 V. Therefore, it is difficult to use this device in applications that require operation at a power supply voltage V _CC of 5 V or less.

Returning to the ground fault detection circuit 240 in Fig. 2, in the ground fault detection circuit 240 in Fig. 2, a second resistor R2, a second transistor Q2, and a current mirror circuit CM1 are connected between the power supply line 202 and the ground line. Therefore, the lower limit voltage of the power supply voltage V _CC is expressed by the following equation.
V _CC >R2×Idet+Vds
Vds is the drain-source voltage of the NMOS transistor on the input side of the current mirror circuit CM1. The NMOS transistor of the current mirror circuit CM1 must operate in the saturation region, and the drain-source voltage Vds of the NMOS transistor must be greater than the pinch-off voltage Vp. This pinch-off voltage Vp is the overdrive voltage Vgs-Vth _(NMOS) of the NMOS transistor, and can be reduced to, for example, about 0.1 V. If R2×Idet≈3.5 V and Vds>0.1 V, then
V _CC >R2×Idet+Vds=3.6V
Therefore, the minimum operating voltage V _{CC (MIN)} is 3.6 V. This is significantly lower than 5.5 V of the comparative technology, and enables use in applications that require operation at a power supply voltage V _CC of 5 V or less.

For example, in-vehicle components include ICs (Integrated Circuits) that are required to operate in an emergency, and such ICs are required to operate at V _CC = 4.5 V. The semiconductor integrated circuit 200 including the ground fault detection circuit 240 according to the embodiment can meet such requirements.

A modified example of the ground fault detection circuit 240 is described.

The second switch SW2 may be configured with an NMOS transistor, similar to the high-side transistor MH. Alternatively, the second switch SW2 may be omitted.

The configuration of the determination circuit 250 is not limited to that shown in FIG. 2. Circuit elements other than a voltage comparator may be used for voltage comparison. For example, a MOS transistor may be used as the voltage comparison means.

The number of current mirror circuits in the current mirror group 244 may be an odd number. In this case, a third resistor R3 may be provided between the output node of the current mirror group 244 and the constant voltage line 203.

Next, we will explain the uses of switching circuits.

5 is a block diagram of an audio system 400. The audio system 400 includes an audio IC 200C, a speaker 402, a filter 404, a bootstrap capacitor C _BS , and a battery 410.

Audio IC 200C is a class D amplifier and includes a high-side transistor MH, a low-side transistor ML, a high-side driver 210, a low-side driver 220, level shifters 230 and 232, a ground fault detection circuit 240, and a pulse width modulator 310. The high-side transistor MH is connected between the power supply pin VCC and the switching pin SW, and the low-side transistor ML is connected between the switching pin SW and the ground pin GND.

The pulse width modulator 310 converts the audio signal _{V_AUD} into a PWM (pulse width modulated) signal and generates the control signals HIN and LIN.

The control signal HIN is level-shifted up by the level shifter 230 and supplied to the high-side driver 210.

The level shifter 232 is provided as a dummy to align the delay amount between the high side and the low side. The level shifter 232 may be omitted. The low-side driver 220 drives the low-side transistor ML according to the output of the level shifter 232.

The audio system 400 may be for use in a vehicle. In this case, a battery voltage V _BAT from an in-vehicle battery 410 is supplied to the power supply pin VCC as the power supply voltage V _CC . The voltage V _BAT of the in-vehicle battery is rated at 12 to 14 V, but even if the battery voltage V _BAT drops to 4.5 V or lower, the audio IC 200C is required to maintain operation.

According to the audio system 400 of FIG. 5, by using the ground fault detection circuit 240 including the current mirror group 244, it becomes possible to detect a ground fault even when the battery voltage V _BAT is low.

6 is a block diagram of a step-down converter 500. The step-down converter 500 includes a controller IC 200D and a step-down converter main circuit 510. The step-down converter 500 steps down a power supply voltage V _CC generated on an input line 502 to an output voltage V _OUT having a predetermined voltage level, and supplies the output voltage V OUT to a load (not shown) connected to an output line 504. The main circuit 510 includes a high-side transistor MH, a low-side transistor ML, an inductor L2, and an output capacitor C2.

The controller IC 200D includes a high-side transistor MH, a low-side transistor ML, a high-side driver 210, a low-side driver 220, a level shifter 230, a ground fault detection circuit 240, and a feedback circuit 320. Resistors R21 and R22 divide the output voltage _VOUT , and supply the divided feedback voltage _VFB to a feedback pin FB of the controller IC 200D.

The feedback circuit 320 generates a PWM signal whose duty cycle is adjusted so that the feedback voltage _VFB approaches a predetermined reference voltage _VREF . The feedback circuit 320 generates control signals HIN and LIN in response to the PWM signal. The level shifter 230 level-shifts the control signal HIN and supplies it to the high-side driver 210. The control signal LIN is also directly supplied to the low-side driver 220. A dummy level shifter may be inserted between the feedback circuit 320 and the low-side driver 220.

The step-down converter 500 may be a diode rectifier type, in which case a rectifier diode is connected instead of the low-side transistor ML, and the low-side driver 220 is omitted.

The step-down converter 500 may be for use in a vehicle. In this case, the power supply pin VCC is supplied with a battery voltage V _BAT as the power supply voltage VCC. The voltage V _BAT of the vehicle battery is rated at 12 to 14 V, but there are cases where the step-down converter 500 is required to continue operating even if the battery voltage V _BAT drops to 4.5 V or lower.

According to the step-down converter 500 of FIG. 6, by using the above-mentioned ground fault detection circuit 240, it becomes possible to detect a ground fault even in a state where the battery voltage V _BAT is low.

(Additional Note)
The present specification discloses the following techniques:

(Item 1)
A power supply line, an output line and a ground line;
a constant voltage line generating a constant voltage lower than the input voltage of the power supply line;
an output stage including a high-side transistor connected between the power supply line and an output line and a low-side transistor connected between the output line and the ground line;
a ground fault detection circuit for detecting a ground fault in the output line;
Equipped with
The ground fault detection circuit includes:
a first resistor having a first end connected to the power supply line;
a second resistor having a first end connected to the power supply line;
a first switch connected between the second end of the first resistor and the output line, the first switch being turned on when the high-side transistor is turned on;
A current source;
a first transistor of P type having a first electrode connected to the second end of the first resistor, and having a control electrode and a second electrode connected to the current source;
a second transistor of P type having a first electrode connected to the second end of the second resistor and having a control electrode connected to the control electrode of the first transistor;
a current mirror group including a multi-stage current mirror circuit that folds back a current flowing through the second transistor and operates using the constant voltage as a power supply voltage;
a third resistor connected between the output node of the current mirror group and the ground line;
a determination circuit that generates a ground fault detection signal based on a result of comparing a voltage drop across the third resistor with a predetermined threshold voltage;
A semiconductor integrated circuit comprising:

(Item 2)
2. The semiconductor integrated circuit according to item 1, wherein the ground fault detection circuit further includes a second switch connected between a second end of the first resistor and the power supply line and turned on when the low-side transistor is on.

(Item 3)
3. The semiconductor integrated circuit according to item 1, wherein the first transistor and the second transistor are bipolar transistors, and the high-side transistor, the low-side transistor, and the current mirror group are MOS transistors.

(Item 4)
3. The semiconductor integrated circuit according to claim 1, wherein the first transistor, the second transistor, the high-side transistor, the low-side transistor, and the current mirror group are MOS transistors.

(Item 5)
5. The semiconductor integrated circuit according to any one of items 1 to 4, which is an audio class D amplifier.

(Item 6)
5. The semiconductor integrated circuit according to any one of items 1 to 4, which is a switching regulator.

(Item 7)
7. The semiconductor integrated circuit according to any one of items 1 to 6, which is for in-vehicle use.

(Item 8)
8. The semiconductor integrated circuit according to item 7, wherein the minimum operating voltage is 4.5 V or less.

Although specific terms have been used to describe the embodiments of the present disclosure, this description is merely an example to aid understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, embodiments, examples, and modifications not described herein are also included within the scope of the present invention.

This disclosure relates to semiconductor integrated circuits.

200 Semiconductor integrated circuit 210 High-side driver 220 Low-side driver 230 Level shifter MH High-side transistor ML Low-side transistor VCC Power supply terminal SW Switching terminal GND Ground terminal BS Bootstrap terminal 202 Power supply line 203 Constant voltage line 204 Output line 206 Ground line 208 Bootstrap line 209 Rectifier element 240 Ground fault detection circuit SW1 First switch SW2 Second switch R1 First resistor R2 Second resistor R3 Third resistor Q1 First transistor Q2 Second transistor 242 Current source 244 Current mirror group 246 Level shifter 250 Judgment circuit 252 Comparator 254, 256 Filter 258 AND gate 200C Audio IC
200D Controller IC
400 Audio system 402 Speaker 404 Filter 410 Battery 500 Step-down converter 502 Input line 504 Output line 510 Main circuit

Claims (8)

A power supply line, an output line and a ground line;
a constant voltage line generating a constant voltage lower than the input voltage of the power supply line;
an output stage including a high-side transistor connected between the power supply line and an output line and a low-side transistor connected between the output line and the ground line;
a ground fault detection circuit for detecting a ground fault in the output line;
Equipped with
The ground fault detection circuit includes:
a first resistor having a first end connected to the power supply line;
a second resistor having a first end connected to the power supply line;
a first switch connected between the second end of the first resistor and the output line, the first switch being turned on when the high-side transistor is turned on;
A current source;
a first transistor of P type having a first electrode connected to the second end of the first resistor, and having a control electrode and a second electrode connected to the current source;
a second transistor of P type having a first electrode connected to the second end of the second resistor and having a control electrode connected to the control electrode of the first transistor;
a current mirror group including a multi-stage current mirror circuit that folds back a current flowing through the second transistor and operates using the constant voltage as a power supply voltage;
a third resistor connected to the output node of the current mirror group;
a determination circuit that generates a ground fault detection signal based on a result of comparing a voltage drop across the third resistor with a predetermined threshold voltage;
A semiconductor integrated circuit comprising: The semiconductor integrated circuit of claim 1, wherein the ground fault detection circuit further comprises a second switch connected between the second end of the first resistor and the power supply line and turned on when the low-side transistor is on. The semiconductor integrated circuit according to claim 1 or 2, wherein the first transistor and the second transistor are bipolar transistors, and the high-side transistor, the low-side transistor, and the current mirror group are MOS transistors. The semiconductor integrated circuit according to claim 1 or 2, wherein the first transistor, the second transistor, the high-side transistor, the low-side transistor, and the current mirror group are MOS transistors. The semiconductor integrated circuit according to claim 1 or 2, which is an audio class D amplifier. The semiconductor integrated circuit according to claim 1 or 2, which is a switching regulator. The semiconductor integrated circuit according to claim 1 or 2, which is for vehicle use. The semiconductor integrated circuit according to claim 7, wherein the minimum operating voltage is 4.5V or less.