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WO2025154346A1 - Dispositif à semi-conducteur et puce à semi-conducteur - Google Patents

Dispositif à semi-conducteur et puce à semi-conducteur

Info

Publication number
WO2025154346A1
WO2025154346A1 PCT/JP2024/036714 JP2024036714W WO2025154346A1 WO 2025154346 A1 WO2025154346 A1 WO 2025154346A1 JP 2024036714 W JP2024036714 W JP 2024036714W WO 2025154346 A1 WO2025154346 A1 WO 2025154346A1
Authority
WO
WIPO (PCT)
Prior art keywords
communication coil
communication
semiconductor device
semiconductor chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/036714
Other languages
English (en)
Japanese (ja)
Inventor
英嗣 入江
淳一郎 門本
修一 坂井
秀典 辻
周太 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Premo Inc
University of Tokyo NUC
Original Assignee
Premo Inc
University of Tokyo NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Premo Inc, University of Tokyo NUC filed Critical Premo Inc
Publication of WO2025154346A1 publication Critical patent/WO2025154346A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

Definitions

  • This disclosure relates to semiconductor devices and semiconductor chips.
  • One aspect of the present disclosure is a semiconductor device comprising a substrate and a semiconductor chip arranged vertically on the substrate, the semiconductor chip having a processor or memory, the communication coil performing magnetic field coupling communication with another communication coil arranged at a position away from the substrate and the semiconductor chip, the communication coil transmitting information input from the semiconductor chip or outputting received information to the semiconductor chip, the communication coil having a winding at least partially formed inside the substrate, and the central axis of the winding being in a direction different from the vertical direction.
  • a part of the communication coil 5 is formed inside the substrate 2.
  • the communication coil 5 has windings formed inside the semiconductor chip 1 and inside the substrate 2.
  • wiring 35 is provided for communication and power supply between the interposer 4 and the motherboard 90 etc. outside the semiconductor device 10.
  • wiring 45 is formed for communication and power supply between the semiconductor chip 1 and the motherboard 90 etc. outside the semiconductor device 10. It is preferable that wiring 35 and wiring 45 are not connected to the communication coil 5.
  • One or more of terminals 41 and 42 are connected to wiring 45.
  • One or more of terminals 31 are connected to wiring 35.
  • Base substrate vias 531V, 532V, 533V, and 534V are vias formed within base substrate 3.
  • the communication coil 5 is connected in the following order with the wiring and vias (1) to (5) mentioned above: wiring in chip 511H ⁇ via in chip 511V ⁇ via in interposer 541V ⁇ via in base substrate 531V ⁇ wiring in base substrate 1 (KB) ⁇ via in base substrate 533V ⁇ via in interposer 543V ⁇ via in chip 513V ⁇ wiring in chip 512H ⁇ via in chip 512V ⁇ via in interposer 542V ⁇ via in base substrate VH2 ⁇ wiring in base substrate 532H ⁇ via in base substrate 534V ⁇ via in interposer 544V ⁇ via in chip 514V ⁇ wiring in chip 513H.
  • the communication coil 5 has two or more windings, and passes from inside the semiconductor chip 1 through inside the substrate 2, then through inside the semiconductor chip 1, and then through inside the substrate.
  • the communication coil 5 has a central axis passing through the center 50 of the winding along the horizontal direction, but in order to meet various directivity requirements, the central axis may be approximately horizontal, and more specifically, may be within a range of less than 30 degrees from the horizontal direction. In addition, the central axis may be in a direction different from the vertical direction (Y direction).
  • the communication coil 5 is oriented in a direction different from the vertical direction (Y direction), so a semiconductor device 10 that meets various directivity requirements can be provided.
  • the communication coil 5 is configured with windings in parts formed inside the semiconductor chip 1 and inside the substrate 2, so a large winding can be configured, and the communication coil 5 can be formed in a position along the edge of the semiconductor device 10.
  • the difference between the central axes of communication coil 5a and communication coil 5b may be in the range of 30 degrees or more.
  • the communication axis directions of the two communication coils 5 are different from each other, so that a semiconductor device that meets various directivity requirements can be provided compared to the case where there is only one communication coil.
  • the central axis of communication coil 5a is aligned along the X direction, which is one of the horizontal directions.
  • the central axis of communication coil 5b is aligned along the X direction, which is one of the horizontal directions. It is desirable for communication coil 5a and communication coil 5b to be formed at positions separated from each other, and it is desirable for the center of substrate 2 to be located between communication coil 5a and communication coil 5b in the XZ plane.
  • the central axis of communication coil 5a and the central axis of communication coil 5b are in the same direction, taking into consideration manufacturing convenience, etc., it is sufficient that communication coil 5a and communication coil 5b are in approximately the same direction, and the difference in the direction of the central axis may be within a range of less than 30 degrees. According to embodiment 3, since the communication axis directions of the two communication coils 5 are in the same direction, it is possible to provide a semiconductor device that meets the requirement for directivity in a specific direction.
  • the center of the semiconductor device 10 and the center of the substrate 2 are located between communication coil 5a and communication coil 5b whose central axes point in the X direction, between communication coil 5c and communication coil 5d whose central axes point in the Z direction, and between communication coil 5e and communication coil 5f whose central axes point in the Y direction.
  • the semiconductor device 10 is provided with a communication coil whose central axis points in the Y direction, and therefore can also meet the demand for vertical directivity.
  • the central axes of the communication coils 5e and 5f may be approximately along the Y direction for manufacturing convenience. Therefore, the direction of the central axes of the communication coils 5e and 5f may differ from the Y direction by less than 30 degrees.
  • the communication coils 5a, 5b, 5c, and 5d may be in a direction different from the Y direction, and may differ from the Y direction by 30 degrees or more.
  • Fifth embodiment 14 is a side view showing a semiconductor device of embodiment 5.
  • the communication coil 5 does not pass through the semiconductor chip 1, and the entire winding is formed in a portion formed inside the substrate 2, and the central axis direction of the winding is the X-axis direction, but it may be in a direction different from the vertical direction.
  • a part of the winding of the communication coil 5 is formed on the base substrate 3, and the other part is formed on the interposer 4.
  • all of the winding of the communication coil 5 may be formed on the base substrate 3, in which case the interposer 4 may not be required. All of the winding of the communication coil 5 may be formed on the interposer 4.
  • all of the windings of the communication coil 5 are formed on the substrate 2, making it easier to manufacture than when all or part of the communication coil 5 is formed on the semiconductor chip 1.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Le problème décrit par la présente invention est de fournir un nouveau dispositif à semi-conducteur et similaire. La solution selon l'invention porte sur un dispositif à semi-conducteur qui comprend une carte et une puce à semi-conducteur disposée dans la direction verticale de la carte, la puce à semi-conducteur comprenant un processeur ou une mémoire, une bobine de communication effectuant une communication de couplage de champ magnétique avec une autre bobine de communication disposée à un emplacement éloigné de la carte et de la puce à semi-conducteur, la bobine de communication transmettant des informations entrées à partir de la puce à semi-conducteur ou délivrant les informations reçues à la puce à semi-conducteur, la bobine de communication comprenant un enroulement formé au moins en partie à l'intérieur de la carte, et la direction d'axe central de l'enroulement étant différente de la direction verticale. [Dessin sélectionné] FIG. 2
PCT/JP2024/036714 2024-01-19 2024-10-15 Dispositif à semi-conducteur et puce à semi-conducteur Pending WO2025154346A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2024006550 2024-01-19
JP2024-006550 2024-01-19

Publications (1)

Publication Number Publication Date
WO2025154346A1 true WO2025154346A1 (fr) 2025-07-24

Family

ID=96471339

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/036714 Pending WO2025154346A1 (fr) 2024-01-19 2024-10-15 Dispositif à semi-conducteur et puce à semi-conducteur

Country Status (1)

Country Link
WO (1) WO2025154346A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347286A (ja) * 2002-05-29 2005-12-15 Ajinomoto Co Inc コイル内蔵多層基板、半導体チップ、及びそれらの製造方法
JP2006286816A (ja) * 2005-03-31 2006-10-19 Sanyo Electric Co Ltd 半導体装置
WO2009113372A1 (fr) * 2008-03-13 2009-09-17 日本電気株式会社 Dispositif à semi-conducteur
WO2010032534A1 (fr) * 2008-09-18 2010-03-25 株式会社ルネサステクノロジ Dispositif à semi-conducteurs
JP2011146615A (ja) * 2010-01-18 2011-07-28 Sumitomo Bakelite Co Ltd 電子回路装置、その電子回路基板
JP2012054535A (ja) * 2010-08-06 2012-03-15 Renesas Electronics Corp 半導体装置、電子装置、及び半導体装置の製造方法
JP2024002506A (ja) * 2022-06-24 2024-01-11 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347286A (ja) * 2002-05-29 2005-12-15 Ajinomoto Co Inc コイル内蔵多層基板、半導体チップ、及びそれらの製造方法
JP2006286816A (ja) * 2005-03-31 2006-10-19 Sanyo Electric Co Ltd 半導体装置
WO2009113372A1 (fr) * 2008-03-13 2009-09-17 日本電気株式会社 Dispositif à semi-conducteur
WO2010032534A1 (fr) * 2008-09-18 2010-03-25 株式会社ルネサステクノロジ Dispositif à semi-conducteurs
JP2011146615A (ja) * 2010-01-18 2011-07-28 Sumitomo Bakelite Co Ltd 電子回路装置、その電子回路基板
JP2012054535A (ja) * 2010-08-06 2012-03-15 Renesas Electronics Corp 半導体装置、電子装置、及び半導体装置の製造方法
JP2024002506A (ja) * 2022-06-24 2024-01-11 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法

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