WO2025151835A1

WO2025151835A1 - Precision analog to digital circuit tuned voltage and current mode dc-dc converter

Info

Publication number: WO2025151835A1
Application number: PCT/US2025/011276
Authority: WO
Inventors: Gregory Szczeszynski
Original assignee: PSemi Corp
Current assignee: PSemi Corp
Priority date: 2024-01-12
Filing date: 2025-01-10
Publication date: 2025-07-17
Anticipated expiration: 2026-07-12

Abstract

Circuits and methods are provided that generate a reference signal in a digital loop for controlling a controller in an analog loop. An analog loop circuit receives a reference signal, determines a first error based the reference signal and a sensing signal in multiple sensing signals, and regulates regulate a system output signal of the system based on the first error. A digital loop circuit converts the system output signal into a digital system output signal, determines a second error between the digital system output signal and a digital reference signal received from a device coupled to the system, determines a control signal using the second error, and converts the control signal into the reference signal.

Description

PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of and priority to in their entirety the following United States Provisional Patent Applications filed on January 12, 2024, which are all incorporated by reference in their entirety:

[0002] Application No. 63/620,507 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0003] Application No. 63/620,623 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0004] Application No. 63/620,613 entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER;”

[0005] Application No. 63/620,465 entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS;”

[0006] Application No. 63/620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT;”

[0007] Application No. 63/620,450 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0008] Application No. 63/620,469 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0009] Application No. 63/620,678 entitled “RECONFIGURABLE MULTI-LEVEL POWER CONVERTER TO CHARGE PUMP MODE AND FRACTIONAL CHARGE PUMP MODE;”

[0010] Application No. 63/620,417 entitled “INPUT CURRENT SLEW FOR A MULTILEVEL CONVERTER;”

[0011] Application No. 63/620,726 entitled “ADJUSTING OVERVOLTAGE PROTECTION BASED ON MODE OF OPERATION SYSTEMS AND METHODS;” [0012] Application No. 63/620,737 entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL;”

[0013] Application No. 63/620,741 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS;”

[0014] Application No. 63/620,527 entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS;”

[0015] Application No. 63/620,488 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0016] Application No. 63/620,553 entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS;”

[0017] Application No. 63/620,638 entitled “GENERAL STARTUP FOR MULTILEVEL POWER CONVERTER CIRCUITS;”

[0018] Application No. 63/620,733 entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER;”

[0019] Application No. 63/620,738 entitled “PREDICTIVE CONTROL LOOP PRECHARGING DURING A MULTI-LEVEL ZONE CHANGE;”

[0020] Application No. 63/620,764 entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROL

LOOP CIRCUIT;”

[0021] Application No. 63/620,607 entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS;”

[0022] Application No. 63/620,575 entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS;”

[0023] Application No. 63/620,582 entitled “PARALLEL OPERATION OF MULTILEVEL POWER CONVERTERS;” and

[0024] Application No. 63/620,763 entitled “AVERAGE AND PEAK CURRENT

SENSE SYSTEMS AND METHODS.” BACKGROUND

[0025] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0026] Many electronic products, including mobile computing and/or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0027] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0028] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. When a fly capacitor is used (z.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it.

[0029] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits. SUMMARY

[0030] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits.

[0031] The embodiments are directed to a system comprising an analog loop circuit configured to receive a reference signal, determine a first error based the reference signal and a sensing signal in a plurality of sensing signals, and regulate a system output signal of the system based on the first error, and a digital loop circuit configured to convert the system output signal into a digital system output signal, determine a second error between the digital system output signal and a digital reference signal received from a device coupled to the system, determine a control signal based the second error, and convert the control signal into the reference signal

[0032] The embodiments are directed to a system comprising an analog loop circuit configured to receive a reference signal, determine a first error between the reference signal and a sense signal received from a sensor of a multi-level converter, and regulate an output signal of the multi-level converter based on the first error, and a digital loop circuit configured to, generate a control signal by adjusting a digital reference signal with a digital trim circuit, and convert, using a digital-to-analog converter, the control signal into the reference signal for processing by the analog loop circuit during a subsequent iteration.

[0033] The embodiments are directed to a method comprising receiving an analog reference signal, determining a first error between the analog reference signal and at least one of a plurality of sense signals generated by at least one sensor of a system, regulating, using a controller, an analog system output of the system using the first error, converting, using an analog-to-digital converter, the analog system output into a digital system output, determining a second error between a digital reference signal and the digital system output, wherein the digital reference signal is associated with a device that uses the analog system out, and converting, using a digital-to-analog circuit, the second error into the analog reference signal for regulating the analog system output during a subsequent iteration.

[0034] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits. [0035] The embodiments are directed to a system comprising a power converter configured to operate in a plurality of zones, each zone corresponding to a pair of voltage levels in a plurality of voltage levels, a controller configured to store information corresponding to a first zone in the plurality of zones, and a control circuit configured to receive a control signal indicating a zone change from the first zone to a second zone in the plurality of zones, and set the information to correspond to the second zone, wherein setting the information regulates fluctuation of a current in the power converter during the zone change.

[0036] The embodiments are directed to a method comprising storing, at a controller, information corresponding to a first zone in a plurality of zones associated with a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels, receiving, at a control circuit of the controller, a control signal indicating a zone change from the first zone to a second zone in the plurality of zones, and setting, at the controller, the information known to correspond to the second zone.

[0037] The embodiments are directed to a system comprising a current control loop configured to receive a first current signal and a second current signal, generate an output signal representing an output current, and store information corresponding to a first zone of operation of a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels, and a control circuit in the current control loop configured to set the information to correspond to a second zone of operation of the power converter, wherein the second zone corresponds to a second pair of voltage levels in the plurality of voltage levels, and wherein setting the information to correspond to the second zone reduces a spike in the output current during a zone change from the first zone to the second zone.

[0038] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly. DESCRIPTION OF THE DRAWINGS

[0039] FIG. 1 A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. IB is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0045] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0049] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure. [0050] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0051] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0052] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0053] FIG. 10 is a block diagram of an example embodiment of control circuitry for an -level converter cell, in accordance with one or more embodiments of the present disclosure.

[0054] FIG. 11 is a block diagram of a controller, in accordance with one or more embodiments of the disclosure.

[0055] FIGs. 12-13 are block diagrams of a controller connected to a feedback loop, according to some embodiments.

[0056] FIGs. 14-15 is an example method for generating a reference signal at a digital loop for controlling a controller in an analog loop, in accordance with one or more embodiments of the disclosure.

[0057] FIG. 16 is a block diagram of a controller, according to one or more embodiments of the disclosure.

[0058] FIG. 17A is a graph illustrating voltage levels and a duty cycles during in zones of an example four-level converter circuit, according to one or more embodiments of the disclosure.

[0059] FIG. 17B is a graph illustrating voltage levels with dead zones and an output voltage, according to one or more embodiments of the disclosure.

[0060] FIG. 17C is a graph illustrating effects on output current during a zone change with and without predictive control, according to one or more embodiments of the disclosure.

[0061] FIG. 18 is a flow chart illustrating predictive control of a control loop during a zone change, according to one or more embodiments of the disclosure. [0062] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

[0063] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multilevel converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0064] FIGs. 1-6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li- polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure. The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.

[0065] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0066] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs. 1 A-B), dual-integrated circuits (see, e.g., Figs. 2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig. 3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architecture having a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs. 1-3 A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs. 4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9A charging current) in a low-profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via interintegrated circuit (EC) technology; and/or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and output over current protection (OCP), and IC over-temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and/or paralleled operation.

[0067] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0068] In a step-down regulation mode, the power converter operates as a multi-level stepdown regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection. [0069] During a constant-voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT REG first, then CV is regulated to VOUT REG. If the VBATTP sensed voltage reaches VBATT REG first, then CV is regulated to VB ATT REG. This provides a fast battery top off while preventing voltage above safety limit.

[0070] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide- by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the power converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for I0UT MAX, VOUT REG and VBATT REG). In this mode, the power converter monitors an IIN MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when UN current exceeds IIN MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5 A in single IC operation.

[0071] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0072] In some embodiments, to enable the IC, both an EN pin and an IC EN bit are set to logic high (1). When either the EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC is enabled, the POR status bit sets to 1 to indicate the IC has a fresh power up. [0073] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1 -bit registers V EXTG, EXTG EN and EXTGX). The V EXTG bit sets the gate drive voltage and can be set to 9V or 5 V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0074] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0075] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0076] To enable the IC, both the EN pin and IC EN bit are set to logic high (1). When either EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V EXTG, EXTG EN and EXTGX. The V EXTG bit sets the gate drive voltage and can be set to 9V or 5V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled.

[0077] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.

[0078] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC EN bit= 1 at lOOus(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT MAX register is set to the target maximum charger current in CC operation, and the IIN MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting. [0079] The MODE register and other related registers are set for step -down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0080] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0081] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as an example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC EN bit=l at 100us(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN MAX register is set to a value below the adapter current limit. VOUT REG, VBATT REG and I0UT MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0082] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0083] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0084] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC EN bit is set to 1 at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage at VIN. Next, the IIN MAX register is set to the target current limit. VBATT REG and I0UT MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0085] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC. [0086] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC STATUS1 and IC STATUS2 would report the fault event.

[0087] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a power converter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0088] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740, which may include one or more logic devices 742, memories 744, communications components 746, input/output (I/O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and/or external device 760, as applicable.

[0089] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be implemented as a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic device 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as random- access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile randomaccess memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0090] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8A is a schematic diagram of a 3 -level DC-to-DC buck converter circuit 800 that may be used as the converter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor Cl is coupled in series with switches S3 and S4, and in parallel with switches SI and S2. An inductor LI is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and the voltage across the output capacitor COUT is VOUT.

[0091] In the illustrated example, the presence of the single fly capacitor Cl in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and SI and S3 are open, effectively bypassing Cl and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and SI and S3 are closed, effectively bypassing Cl and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state SI and S4 are open and S2 and S3 are closed, connecting Cl from VIN to LX, and thus charging Cl with inductor LI current flowing into a load. The voltage across Cl will be about VIN/2 and the voltage level at Lx will also equal about VIN/2. In a fourth switch state, SI and S4 are closed and S2 and S3 are open, connecting Cl from Lx to GND and thus discharging Cl with inductor LI current flowing to a load. The voltage across Cl will be about VIN/2 and the voltage level at Lx will also equal about VIN/2 (e.g., this may assume that Cl was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN/2 at the Lx node.

[0092] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor Cl), the inductor LI sees small jumps in the voltage level at Lx, going from GND to only VIN/2 and back to GND, which results in reduced voltage ripple across the inductor LI and less filtering to smooth VOUT than a converter circuit with only SI and S2 switches.

[0093] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VEST and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG. 8B) includes 6 series- coupled switches S1-S6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, ’AVIN, and %VIN) at node LX from 8 switch states (3 switch states result in the ’AVIN level at Lx, and 3 other switch states result in the %VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may never use GND. For example, in a 4-level converter circuit, an output VOUT set to 0.5*VIN can be achieved by alternating the Lx node between % VIN and ’A V.

[0094] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a ’A charge-pump with the additional benefit that any input voltage that is a sum of ’A ratios can be created, including VIN and GND.

[0095] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0096] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3 -level converter circuit will now be described. For example, in a 3- level converter circuit, one way to generate the Level-1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors Cl for these Lx voltage levels. However, for the Level 2 (VIN/2) voltage level at Lx, two separate switch states can be used: one switch state charges the capacitor (S3 and S2 closed, SI and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, SI and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VIN/2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN/2, then the controller would select discharge (the fourth switch state).

[0097] Referring to FIGs. 8B, a 4-level converter circuit 830 (X = 2) illustrates the chargebalance difficulty when more capacitors are present. A Level-1 voltage level (GND) and a Level-4 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’A VIN) and Level-3 voltage level (% VIN) at Lx each can be achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5-level converter circuit (X= 3). A Level-1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’AVIN) and Level-4 voltage level (³A VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2/4 VIN) at Lx can be achieved by any of six different switch states.

[0098] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real- world environment, where all system variables tend to be dynamic.

[0099] In a 2-Level example, the converter circuit switches between two switch states: SI closed and S2 open (voltage level at Lx = VIN), or SI open and S2 closed (voltage level at Lx = GND). A PWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at Lx (noting that, the average Lx voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the Lx average voltage is higher and/or lower (for negative currents) than the VOUT average). As can be appreciated, the inductor L sees large jumps in the voltage level at Lx, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0100] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. AS noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M=X+ 2 voltage levels at node Lx from 2^(y+1) switch states.

[0101] FIG. 8C is schematic diagram of a generalized A7-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG. 9. A set of switches, Sl-S[2*( f- 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: SI & S2, S3 & S4, ... S[2*( f- 2)+l] & S[2*( f- 1)]. A set ofM- 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in between those switches. In terms of switch pairs, there are M~ 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and again the voltage across the output capacitor COUT is VOUT. The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0102] In various embodiments, each fly capacitor Cx has a first terminal coupled between an outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x-1], where “high- side” refers to the VIN side of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M= 3 multi-level converter cell, a first terminal of the single (X= 1) fly capacitor Cl would be coupled between outer high-side switch S3 and inner high-side switch SI, and a second terminal of the capacitor Cl would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx. [0103] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an A-f-level converter and capacitor Cx, where x = 1, 2, ... [M~ 2], its target voltage is:

Vtarget

[0104] The voltage detector may be configured to output a HIGH/LOW status signal, CT.v _H/L, indicating with the voltage across the corresponding fly capacitor Cx is greater than VREF or less than VREF. The CFX_H/L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cx.

[0105] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CT._V H/LX status signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0106] In a switch state in which the outer high-side and inner low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would again be bypassed. [0107] While each fly capacitor Cx can control both of its own pairs of high-side and low- side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG. 8B, in “outer-switch” methods, fly capacitor Cl will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor Cl will control its inner switches SI and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary - that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer-switches, then no fly capacitor controls the left-over innermost switches SI and S2. If instead each fly capacitor Cx controls its inner- switches, then no fly capacitor controls the left-over outermost switches S[2*(A/-1)] and S[2*(A/-2)+l], Switch states for the left-over switches are also complementary.

[0108] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controller 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1 A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0109] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input/output signals VO that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, such as low voltage FETs/MOSFETs) to cause the converter circuit 920 to boost or buck VEST to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input/output signals VO, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.

[0110] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an -level converter cell 1000 such as the generalized version depicted in FIG. 8B. The M- level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor COUT (conceptually, the inductor L also may be considered as being included within the A/-level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the A/-level converter cell 1020 and to switch control inputs of the A/-level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and/or current) of the AT-level converter cell 1020 and dynamically generate a set of switch control inputs to the AV-level converter cell 1020 that attempt to stabilize the output voltage and/or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, the advanced control circuitry 1000 may be configured to monitor the input of the AAlevel converter cell 1020 (e.g., voltage and/or current) and/or an internal node of the A-/- level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and/or current of a node (e.g., input terminal, internal node, or output terminal) of the A-/- level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the A/-level converter cell 1020.

[OHl] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON- time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the A/-level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M- level converter cell 1020 and/or an internal node of the A/-level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cell 1020 to maintain desired values for VOUT: charge, discharge, or tri-state (z.e., open, with no current flow).

[0112] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT (or an attenuated version of VOUT) to a reference voltage which represents a desired VOUT target voltage (which may be dynamic) and outputs a control signal to indicate whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0113] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and/or RC circuits.

[0114] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUT and the reference voltage (thus indicating that some levels of the A-f-level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUT is greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0115] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a chargebalance state on the fly capacitors within the A-f-level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past. [0116] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUT and/or VIN, and, in some embodiments, to the HIGH/LOW status signals, C .- _H/L, from the voltage detectors coupled to corresponding fly capacitors Cx within the A/-level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VIN to determine which Target Level should charge or discharge the output of the AT-level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1/5VIN), Level-3 (2/5VIN), Level-4 (3/5VIN), Level-5 (4/5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0117] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3 V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1/3 VIN voltage level at Lx (i.e. , 4V). The PWM control signal sets a duty cycle between that Target Level and another Target Level (e.g., GND) so that the average voltage level at Lx will be about 3 V.

[0118] In general, for steady-state operations, the Target Level voltage closest to VOUT that either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and/or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.

[0119] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CT.v _H/L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated by the Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0120] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the /W-level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the A-f-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the A-f-level Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the AT-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CFX H/L status signal(s) to cause the A-f-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the Al- level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0121] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0122] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLK may be applied to the A7-level Switch State Selector 1014. The A7-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VIN changes or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0123] In some embodiments, the A7-level Switch State Selector 1014 may take into account the current II flowing through the inductor L by way of an optional currentmeasurement input 1016, which may be implemented in conventional fashion.

[0124] In an A7-level multi-level converter circuit, the configuration of switches that achieves Level-1 (e.g., GND) or Level -M (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration of switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations - that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle - to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0125] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT):

(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and

(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods). [0126] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly:

(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner-switch control methods); and

(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0127] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x) to actually charge or discharge, the next inward (if one exists) fly capacitor C(x 7) (for outerswitch control methods) or the previous outward (if one exists) fly capacitor C(x+7) (for inner- switch control methods) must be set to the opposite state (z.e., discharge or charge) so that a bypass situation does not occur.

[0128] For any multi-level converter circuit of order M that can create M voltage levels - z.e., Level-1 (e.g., GND) through Level -M (e.g., VIN) - then the following switch count rules apply for any Level -m:

(1) - zzz low-side switches must be set to be closed (ON);

(2) m - 1 high-side switches must be set to be closed (ON); and

(3) switches that are not required to be ON must be set to be OFF (open).

[0129] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014:

Step 1) Select a fly capacitor that has not previously been selected;

Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (z.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g., for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (z.e., as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”; Step 3) Loop to Step 1 until all fly capacitors have been selected;

Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0130] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No. 20230148059, which is incorporated by reference herein in its entirety.

[0131] FIG. 11 is a block diagram 1100 of a controller, according to some embodiments. An exemplary controller may be controller 1002. Controller 1002 may regulate and control different system variables, including output voltage (VOUT), average current (IAVE), and peak current (IPEAK). An output voltage (VOUT) may be an output voltage of the multi-level converter. An average current (IAVE) may be a current measured across one or more switches of the multilevel converter over a predetermined amount of time. Peak current (IPEAK) may be a current measured across one or more switches of the multi-level converter at certain time. Multiple peak current (IPEAK) measurements may be used to determine the average current (IAVE) over a predetermined amount of time. In particular, controller 1002 may regulate and control different system variables of the multi-level power converter during different stages of the battery charging application.

[0132] Controller 1002 illustrated in FIG. 11 may include multiple amplifiers, such as a first amplifier and a second amplifier. The first amplifier may be a voltage error amplifier 1102 and a second amplifier may be an average current error amplifier 1104. Voltage error amplifier 1102 and average current error amplifier 1104 may be operational transconductance amplifiers. Voltage error amplifier 1102 may determine an error between voltage inputs, such as output voltage (VOUT) that may be an output voltage of the multi-level converter and a reference voltage that may be sensed using a sensor or a load. Average current error amplifier 1104 may be a type of current error amplifier that determines an error between two inputs representing currents. In case of average current error amplifier 1104, the inputs may represent an average current (IAVE) that passes through the multi-level converter and may be regulated and a reference average current that may be sensed using one of the sensors. Additionally, controller 1002 may include a comparator, such as pulse width modulated (PWM) comparator 1106. A comparator may compare two inputs and generate an output indicating which input is greater. The PWM comparator 1106 may be a comparator that compares the two inputs and generates a PWM signal that may be used to set a duty cycle. In case of PWM comparator 1106 the inputs may represent the peak current (IPEAK) that may be regulated and the sensed peak current (IPEAK) that may be sensed using one or more sensors. The voltage error amplifier 1102, the average current error amplifier 1104, and the PWM comparator 1106 may be arranged in sequence, such that an output signal of the voltage error amplifier 1102 may be an input signal into the average current error amplifier 1104, and an output signal of the average current error amplifier 1104 may be an input signal into PWM comparator 1106.

[0133] In some embodiments, voltage error amplifier 1102, average current error amplifier 1104, and PWM comparator 1106 may receive a signal representing a system variable to be regulated and a signal representing a reference value for the system variable that may be sensed using one or more sensors. For example, voltage error amplifier 1102 may receive a system variable that may be an output voltage (VOUT) 1108 and a reference voltage (VREF) 1110 and determine an error between output voltage (VOUT) 1108 and a reference voltage (VREF) 1110. Output voltage (VOUT) may be an output voltage to be regulated by the multi-level converter. The reference voltage (VREF) 1110 may be a reference voltage that is a voltage across a load, e.g., a battery. The voltage error amplifier 1102 may use output voltage (VOUT) 1108 and reference voltage (VREF) 1110 to generate an output signal. The output signal may correspond to an error between output voltage (VOUT) 1108 and reference voltage (VREF) 1110 and represent an average current (IAVG) and may be referred to as a Vamp lavg 1112 signal. The Vamp lavg signal 1112 may represent a minimum of the output voltage (VOUT) 1108 and reference voltage (VREF) 1110 or an error between output voltage (VOUT) 1108 and reference voltage (VREF) 1110, and may correspond to an average current (IAVG) to be regulated by the multi-level converter. The value corresponding to the Vamp lavg signal 1112 may be measured at the comparison node or comp node 1115. When comp node 1115 represents an average current, the error between output voltage (VOUT) 1108 and reference voltage (VREF) 1110 may be an indication to controller 1002 to increase the average current (IAVG).

[0134] In some embodiments, voltage error amplifier 1102 may be included in a circuit referred to as a voltage control loop 1124. Voltage control loop 1124 may control the output voltage (VOUT) generated by the multi-level converter. Typically, voltage control loop 1124 may be a more precise but a slow loop when compared to other loops in controller 1002.

[0135] As discussed above, Vamp lavg signal 1112 that is an output of voltage error amplifier 1102 may be an input to average current error amplifier 1104. For example, average current error amplifier 1104 may receive the Vamp lavg signal 1112 that may correspond to an average current (IAVG) to be regulated and an average sensed current (ISENSE AVG) signal 1114 and determine an error between average current (IAVG) and average sensed current (ISENSE AVG). The average sensed current (ISENSE AVG) may be sensed using a sensor that senses an average current across switches of the multi-level converter. For example, switches S3 and S4 of the 3-level converter discussed in FIG. 8A and switches S5 and S6 of the 4-level converter discussed in FIG. 8B may be sensed to determine the average sensed current (ISENSE AVG).

[0136] The average current error amplifier 1104 may use Vamp lavg signal 1112 and average sensed current (ISENSE AVG) signal 1114 to generate an output signal that corresponds to an error between average current (IAVG) and average sensed current (ISENSE AVG). The output signal may be a Vamp lpeak signal 1116 representing a peak current (IPEAK). The peak current (IPEAK) may be a peak current to be regulated by the multi-level converter. The Vamp lpeak signal 1116 may be a minimum of or an error between the average current (IAVG) corresponding to the Vamp lavg signal 1112 and an average sensed current (ISENSE AVG) corresponding to average sensed current (ISENSE AVG) signal 1114. The value corresponding to the Vamp lpeak signal 1116 may be measured at the comparison node or comp node 1118. The error between the average current (IAVG) and the sensed average current (ISENSE AVG) may be an indication to controller 1002 to increase the peak current (IPEAK).

[0137] In some embodiments, average current error amplifier 1104 may be included in a circuit referred to as a current control loop 1126. The current control loop 1126 may regulate the average current (IAVG) used by a system, such as the multi-level converter. Typically, current control loop 1126 may be a less precise but a faster loop when compared to other loops in controller 1002, such as voltage control loop 1124.

[0138] As discussed above, Vamp lpeak signal 1116 that is an output of average current error amplifier 1104 may be an input to PWM comparator 1106. For example, PWM comparator 1106 may receive Vamp lpeak signal 1116 that may correspond to the peak current (IPEAK) to be regulated and a sensed peak current (ISENSE PEAK) signal 1120. PWM comparator 1106 may compare the peak current (IPEAK) to the sensed peak current (ISENSE PEAK) and generate a PWM signal based on the comparison. The pulse width modulation signal may set the duty cycle. The sensed peak current (ISENSE PEAK) may be sensed using sensors that senses current across switches of multi-level converters discussed in FIGs. 8A and 8B. For example, switches S3 and S4 of the 3-level converter discussed in FIG. 8A and switches S5 and S6 of the 4-level converter discussed in FIG. 8B may be sensed to determine the average sensed current (ISENSE PEAK). In some instances the sensed peak current (ISENSE PEAK) may also be mixed with a slope compensation waveform. The slope compensation waveform may be a triangular or sawtooth waveform, ramp voltage waveform, or a portion of the ramp voltage waveform and may mixed with the sensed peak current (ISENSE PEAK) to make the sensed peak current (ISENSE PEAK) more stable.

[0139] The PWM comparator 1106 may use Vamp lpeak signal 1116 and sensed peak current (ISENSE PEAK) signal 1120 to generate a PWM signal 1122. The PWM signal 1122 may be a pulse width modulation signal that indicates whether the peak current (IPEAK) corresponding to Vamp lpeak signal 1116 or sensed peak current (ISENSE PEAK) corresponding to the sensed peak current (ISENSE PEAK) signal 1120 is greater. PWM signal 1122 may be a digital signal that may set a duty cycle as discussed in FIG. 10. For example, PWM signal 1122 may set a duty cycle when the multi-level converter circuit changes zones, such as from a first zone to a second zone, from the second zone to a third zone, from the third zone to a fourth zone, or vice versa.

[0140] In some embodiments, PWM comparator 1106 may be included in a circuit referred to as a peak current control loop 1128. The peak current control loop 1128 may regulate the peak current (IPEAK) used by a system, such as the multi-level converter.

[0141] As discussed above, controller 1002 receives reference signals, such as reference voltage (VREF) 1110, sensed average current (ISENSE AVG) signal 1114, and sensed peak current (ISENSE PEAK) signal 1120. The voltage error amplifier 1102 in voltage control loop 1124 then determines an error between output voltage (VOUT) 1108 and reference voltage (VREF) 1110 which represented in Vamp lavg signal 1112. Vamp lavg signal 1112 indicates an amount of compensation needed to output voltage (VOUT) 1108 to reduce the error. Similarly, the average current error amplifier 1114 in current control loop 1126 determines an error between Vamp lavg signal 1112 which represents the average current (IAVG) and sensed average current (ISENSE AVG). The error is represented in Vamp lpeak signal 1116, which indicates the compensation needed to the average current (IAVG) to reduce the error. The comparator 1106 in peak current control loop 1128 may determine PWM signal that sets the duty cycle based on the peak current (IPEAK) represented in the Vamp lpeak signal 1116 and the sensed peak current (ISENSE PEAK) represented in sensed peak current (ISENSE PEAK) 1120. The duty cycle then regulates the system variables, such as output voltage (VOUT) 1108, the input current (IIN), and output current (IOUT). Thus, the combination of voltage loop 1124, current control loop 1126, and peak current control loop 1128 regulate the output voltage (VOUT) 1108, the input current (IIN), and output current (IOUT). The reference voltage (VREF) 1110, the sensed average current (ISENSE AVG) in sensed average current (ISENSE AVG) signal 1114, and the sensed peak current (ISENSE PEAK) in sensed peak current (ISENSE PEAK) signal 1120 are then sensed for the corresponding output voltage (VOUT) 1108, the input current (IIN), and output current (IOUT), and are fed back into controller 1002. In this scheme, the output voltage (VOUT) 1108, average current (IAVG), and peak current (IPEAK) gradually approach reference voltage (VREF) 1110, sensed average current (ISENSE AVG), and sensed peak current (ISENSE PEAK).

[0142] In some instances, the sensors that generate reference voltage (VREF) 1110, sensed average current (ISENSE AVG), and sensed peak current (ISENSE PEAK) may have errors, and have accuracy that may vary over time, with increases and decreases in temperature, etc. To further increase accuracy of the reference variables, a multi-level power converter may include or be coupled to a feedback loop. The feedback loop may be a digital loop that also generates a reference signal. Controller 1002 may receive the reference signal from the digital loop and regulate the system variables together with reference voltage (VREF) 1110, sensed average current (ISENSE AVG) signal 1114, and sensed peak current (ISENSE PEAK) 1120 received from the sensors.

[0143] FIG. 12 is a block diagram 1200 of a controller connected to a feedback loop, according to some embodiments. FIG. 12 illustrates a feedback loop 1202 connected to controller 1002. Feedback loop 1202 may be a digital loop. Controller 1002 may be included in an analog error amplifier circuit 1204 that is part of an analog loop. The output of controller 1002 may set a duty cycle for a multi-level converter, which may be included in system 1206. The output of system 1206 may include an output system signal 1208 and may represent system variables, such as output voltage (VOUT) 1108, input current (IIN), and/or output current (IOUT). The system variables in output system signal 1208 may be passed to sensors 1210 that may regulate controller 1002, and may sense reference voltage (VREF) 1108, sensed average current (ISENSE AVG), and peak current (ISENSE PEAK). In some embodiments, the sensors 1210 may also be finetuned using a reference signal 1212, which is an output of feedback loop 1202 and is discussed in further detail below. The controller 1002, system 1206, and sensors 1210 may form a circuit referred to as an analog loop that regulates system variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT) in system 1206. [0144] As discussed above, feedback loop 1202 may be a digital loop that may generate a reference signal 1212. The reference signal 1212 is fed into controller 1002 to also regulate the system variables such as (VOUT) 1108, input current (IIN), and output current (IOUT). Feedback loop 1202 may receive a digital reference signal 1218 from a device. The device may be used by a user, such as a battery, and may be connected to system 1206 and receive the output system variables in output system signal 1208 (not shown). The digital reference signal 1218 may include digital measurements determined at the device using a telemetry function, sensors, or other circuits that may measure voltage, current, etc., at the user device. The digital measurements may be the system output 1208 as measured at the device. In some embodiments, the measurements may be made using a high precision analog-to-digital converter (ADC) connected to the device, and converted to digital measurements. For example, a high precision ADC may measure a voltage across the battery and convert the measurements into a digital voltage (not shown). The digital voltage across a battery may correspond to digital values for reference voltage (VREF) 1110. Notably, the battery voltage is an example, and the ADC may also measure current, including input current (IIN), and output current (IOUT), and determine digital measurements that correspond to input current (IIN), and output current (IOUT).

[0145] Feedback loop 1202 may include a register 1220 and a digital trim circuit 1222. Register 1220 may store digital measurements received using digital reference signal 1218. Digital trim circuit 1222 may adjust the digital measurements, including voltage or current measurements, by some small amount. The amount may be a predefined amount and may be ten percent or less in some embodiments. The adjusted digital measurements may be represented in a control signal 1224.

[0146] The feedback loop 1202 may also include a digital-to-analog converter (DAC) 1226. DAC 1226 may receive the control signal 1224 and convert the control signal 1224 into reference signal 1212, which is an analog signal. Reference signal 1212 may be an analog counterpart to control signal 1224. Reference signal 1212 may be fed into controller 1002. Alternatively, analog error amplifier circuit 1204 may determine an error from reference signal 1212 and feed the error into controller 1002 together with reference voltage (VREF) 1110, sensed average current (ISENSE AVG) signal 1114, and sensed peak current (ISENSE PEAK) signal 1120. The reference signal 1212 or the error that corresponds to the reference signal 1212 may be processed using voltage control loop 1124, current control loop 1126, or peak current control loop 1128 during subsequent clock cycles to further drive the output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). The process may then repeat as discussed above.

[0147] The feedback loop 1202 may be a digital loop that generates reference signal 1212 to regulates system variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). The digital loop may be slower and more precise than the analog loop discussed above. The analog loop, on the other hand is a less precise and a faster loop. For example, the analog loop may have a cross-over frequency of one mega-hertz, while the digital loop frequency may be slower by several factors. In this way, analog loop may quickly regulate the system variables, while the feedback loop 1202 adds another slow and precise regulation layer.

[0148] FIG. 13 is a block diagram 1300 of a controller connected to another feedback loop, according to some embodiments. FIG. 13 illustrates a feedback loop 1302 connected to controller 1002. Controller 1002 may be included in an analog error amplifier circuit 1304. The output of controller 1002 may set a duty cycle for as multi-level converter, which may be included in system 1306. The output of system 1306 may include an output system signal 1308 corresponding to system variables, such as output voltage (VOUT) 1108, input current (IIN), and/or output current (IOUT). The system variables in output system signal 1308 may be passed to sensors 1310 that may regulate controller 1002, and may sense reference voltage (VREF) 1108, sensed average current (ISENSE AVG), and peak current (ISENSE PEAK). In some embodiments, the sensors 1310 may also be finetuned using an analog reference signal 1312, which is an output of feedback loop 1302 and is discussed in further detail below. The controller 1002, system 1306, and sensors 1310 may form a circuit referred to as an analog loop that regulates system variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT) in system 1306.

[0149] In some embodiments, system output signal 1308 of system 1306, which may be an analog output, may be measured using a high precision analog-to-digital converter (ADC) 1314 connected to system 1306. The ADC 1314 may receive system output signal 1308 which may include output voltage (VOUT) 1108, input current (IIN), and output current (IOUT) and convert system output signal 1308 into digital measurements. The ADC 1314 may transmit the digital measurements to feedback loop 1302 using digital system output signal 1316. [0150] Feedback loop 1302 may be a digital loop that may generate a reference signal 1312. The reference signal 1312 is fed into controller 1002 to also regulate the system variables such as (VOUT) 1108, input current (IIN), and output current (IOUT). Feedback loop 1302 may receive the digital measurements in the digital system output signal 1316. Feedback loop 1302 also receives digital reference signal 1318 that includes digital measurements determined at a device that is connected to system 1306, and may used by a user. For example, digital measurements may be determined at a device, such as a battery, using a telemetry function, sensors, or other circuits that may measure voltage, current, etc., at the user device. In some embodiments, the measurements may also be determined using a high precision analog-to-digital converter (ADC) connected to the user device, and converted to digital measurements. For example, a high precision ADC may measure a voltage across the battery and convert the measurements into a digital voltage (not shown). The digital voltage across a battery may correspond to digital values for reference voltage (VREF) 1110. Notably, the battery voltage is an example, and the ADC may also measure current, including input current (IIN), and output current (IOUT), and determine digital measurements that correspond to input current (IIN), and output current (IOUT).

[0151] Feedback loop 1302 may include a register 1320 and a controller 1322. Register 1320 may receive and store the digital measurements received using digital reference signal 1318. Controller 1322 may be a proportional-integral-derivative (PID) controller, proportional controller, exponential controller, linear controller, non-liner controller or another controller that determines an error between the digital measurements provided using signals 1316 and 1318. In particular, controller 1322 may receive the digital measurements received in digital reference signal 1318 from a device and stored in register 1320 and the digital measurements received in digital system output signal 1316 from system 1306. Based on the digital measurements from digital reference signal 1318 and digital measurements from digital system output signal 1316, controller 1322 may determine an error and generate a control signal 1324 based on the error. For example, controller 1322 may determine the control signal 1324 based on a proportion of the error between the digital measurements from digital reference signal 1318 and digital measurements from digital system output signal 1316. In another example, controller 1322 may determine the control signal 1324 based on an error that has a non-linear relationship between the digital measurements from digital reference signal 1318 and digital measurements from digital system output signal 1316. In another example, controller 1322 may determine the control signal 1324 based on an error that has an exponential relationship between the digital measurements from digital reference signal 1318 and digital measurements from digital system output signal 1316.

[0152] The feedback loop 1302 may also include a digital-to-analog converter (DAC) 1326. DAC 1326 may receive the control signal 1324 and convert the control signal 1324 into reference signal 1312, which is an analog signal. Reference signal 1312 may be an analog counterpart to control signal 1324. Reference signal 1312 may be fed into controller 1002. Alternatively, analog error amplifier circuit 1304 may determine an error from reference signal 1312 and feed the error into controller 1002 together with reference voltage (VREF) 1110, sensed average current (ISENSE AVG) signal 1114, and sensed peak current (ISENSE PEAK) signal 1120. The reference signal 1312 or the error that corresponds to the reference signal 1212 may be processed using voltage control loop 1124, current control loop 1126, or peak current control loop 1128 during subsequent clock cycles to further drive the output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). The process may then repeat as discussed above.

[0153] The controller 1002, system 1306, high precision ADC 1314 and feedback loop 1302 may form a digital loop circuit that regulates system variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). The digital loop may be slower and more precise than the analog loop discussed above. The analog loop, on the other hand is a less precise and a faster loop. For example, the analog loop may have a cross-over frequency of one mega-hertz, while the digital loop frequency may be slower by several factors. In this way, analog loop may quickly regulate the system variables, while the feedback loop 1202 adds another slow and precise regulation layer.

[0154] FIG. 14 is an example method 1400 for generating a reference signal at a digital loop for controlling a controller in an analog loop, in accordance with one or more embodiments. Method 1400 may be implemented using components and circuits discussed in FIGs. 1-13.

[0155] In operation 1402, a reference signal is received at an analog loop. For example, analog loop that includes controller 1002 receives analog reference signal 1312 generated by the digital loop.

[0156] At operation 1404, an error based on the reference signal and a sensing signal is determined at the analog loop. For example, analog error amplifier circuit 1304 may determine an error based on the reference signal 1312. Alternatively, one or more voltage control loop 1124, current control loop 1126, or peak current control loop 1128 may determine an error between the reference signal 1312 and other signals, including sensing signals, that are fed into the respective control loops 1124, 1126, or 1128 of controller 1002.

[0157] At operation 1406, a system output signal is regulated based on the error at the analog loop. For example, controller 1002 may set a duty cycle based on the signals, including reference signal 1312 that is passed to voltage control loop 1124, current control loop 1126, and/or peak current control loop 1128. Using the duty cycle, system 1306, which may be the power converter, may regulate systems variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). One or more system variables may be included or represented in system output signal 1308.

[0158] At operation 1408, a system output signal is converted into a digital system output signal at a digital loop. For example, ADC 1314 of a digital loop may receive the system output signal 1308 and convert the system variables included or represented in system output signal 1308 into digital measurements. The digital measurements may be transmitted to feedback loop 1302 using digital system output signal 1316.

[0159] At operation 1410, a second error is determined based on the digital system output signal and a digital reference signal. For example, feedback loop 1302 may receive a digital reference signal 1318, which may represent digital measurements measured at a device, such as a battery, that receives system variables generated by system 1306. Controller 1322 may determine an error between the digital measurements represented in digital reference signal 1318 and the digital measurements represented using digital system output signal 1316.

[0160] At operation 1412, a control signal is determined based on the second error. Controller 1322 may also generate control signal 1324 based on the error. To generate control signal 1324, controller 1322 may use one or more control schemes, such as proportional, exponential, PID, non-linear, and the like. Control signal 1324 may be a digital representation of the reference signal 1312.

[0161] At operation 1414, a control signal is converted into a reference signal using a digital -to-analog converter in the digital loop. For example, DAC 1326 converts control signal 1324 into an analog reference signal 1312, which is then fed into controller 1002 at a subsequent iteration. [0162] FIG. 15 is an example method 1500 for generating a reference signal at a digital loop for controlling a controller in an analog loop, in accordance with one or more embodiments. Method 1500 may be implemented using components and circuits discussed in FIGs. 1-13.

[0163] In operation 1502, a reference signal is received at an analog loop. For example, analog loop that includes controller 1002 receives an analog reference signal 1212 generated by the digital loop.

[0164] At operation 1504, an error based on the reference signal and one of the sensing signals is determined at the analog loop. For example, analog error amplifier circuit 1204 may determine an error based on the reference signal 1212. Alternatively, one or more voltage control loop 1124, current control loop 1126, or peak current control loop 1128 may determine an error between the reference signal 1212 and other signals, including sensing signals, that are fed into the respective control loops 1124, 1126, or 1128 of controller 1002.

[0165] At operation 1506, a system output signal is regulated based on the error at the analog loop. For example, controller 1002 may set a duty cycle based on the signals, including reference signal 1212 that is passed to voltage control loop 1124, current control loop 1126, and/or peak current control loop 1128. Using the duty cycle, system 1206, which may be the power converter, may regulate systems variables, such as output voltage (VOUT) 1108, input current (IIN), and output current (IOUT). One or more system variables may be included or represented in system output signal 1208.

[0166] At operation 1508, a digital reference signal is adjusted. For example, feedback loop 1202 may receive a digital reference signal 1218, which may represent digital measurements made a device, such as a battery that receives system variables generated by system 1206. The digital measurements in the digital reference signal 1218 may be adjusted using digital trim circuit 1222.

[0167] At operation 1510, a control signal is determined using the adjusted digital reference signal 1218. Feedback loop 1202 may generate control signal 1224 based on the adjusted digital measurements.

[0168] At operation 1512, a control signal is converted into a reference signal using a digital-to-analog converter in the digital loop. For example, DAC 1226 converts control signal 1224 into an analog reference signal 1212, which is then fed into controller 1002 at a subsequent iteration.

[0169] FIG. 16 is another block diagram 1600 of a system that includes a controller, according to some embodiments. Some components in FIG. 16 are discussed in FIG. 11, and are also discussed below. An exemplary controller may be controller 1002. Controller 1002 may regulate and control different system variables, including output voltage (VOUT), average current (IAVE), and peak current (IPEAK). In particular, controller 1002 may regulate and control different system variables of the multi-level power converter during different stages of the battery charging application.

[0170] Controller 1002 illustrated in FIG. 16 may include multiple amplifiers, such as a first amplifier and a second amplifier. The first amplifier may be a voltage error amplifier 1102 and a second amplifier may be an average current error amplifier 1104. Voltage error amplifier 1102 and average current error amplifier 1104 may be operational transconductance amplifiers. Additionally, controller 1002 may include a comparator, such as PWM comparator 1106. The voltage error amplifier 1102, the average current error amplifier 1104, and the PWM comparator 1106 may be arranged in sequence, such that an output signal of the voltage error amplifier 1102 may be an input signal into the average current error amplifier 1104, and an output signal of the average current error amplifier 1104 may be an input signal into PWM comparator 1106.

[0171] In some embodiments, voltage error amplifier 1102, average current error amplifier 1104, and PWM comparator 1106 may receive a signal representing a system variable to be regulated and a signal representing a reference value for the system variable that may be sensed using one or more sensors. For example, voltage error amplifier 1102 may receive a system variable that may be an output voltage (VOUT) 1108 and a reference voltage (VREF) 1110. Output voltage (VOUT) may be an output voltage to be regulated by the multi-level converter. The reference voltage (VREF) 1310 may be a reference voltage that is a voltage across a load, e.g., a battery. The voltage error amplifier 1102 may use output voltage (VOUT) 1108 and reference voltage (VREF) 1110 to generate an output signal. The output signal may represent an average current (IAVG) and may be referred to as a Vamp lavg 1112 signal. The Vamp lavg signal 1112 may represent a minimum of the output voltage (VOUT) 1108 and reference voltage (VREF) 1110 or an error between output voltage (VOUT) 1108 and reference voltage (VREF) 1110, and may correspond to an average current (IAVG) to be regulated by the multi-level converter. [0172] In some embodiments, voltage error amplifier 1102 may be included in a circuit referred to as a voltage control loop 1124. Voltage control loop 1124 may control the output voltage (VOUT) generated by the multi-level converter. Typically, voltage control loop 1124 may be a more precise but a slow loop when compared to other loops in controller 1002.

[0173] As discussed above, Vamp lavg signal 1112 that is an output of voltage error amplifier 1102 may be an input to average current error amplifier 1104. For example, average current error amplifier 1104 may receive the Vamp lavg signal 1112 that may correspond to an average current (IAVG) to be regulated and an average sensed current (ISENSE AVG) signal 1114. The average sensed current (ISENSE AVG) may be sensed using a sensor that senses an average current across switches of the multi-level converter. For example, switches S3 and S4 of the 3-level converter discussed in FIG. 8A and switches S5 and S6 of the 4-level converter discussed in FIG. 8B may be sensed to determine the average sensed current (ISENSE AVG).

[0174] The average current error amplifier 1104 may use Vamp lavg signal 1112 and average sensed current (ISENSE AVG) signal 1114 to generate an output signal. The output signal may be a Vamp lpeak signal 1116 representing a peak current (IPEAK). The peak current (IPEAK) may be a peak current to be regulated by the multi-level converter. The Vamp lpeak signal 1116 may be a minimum of or an error between the average current (IAVG) corresponding to the Vamp lavg signal 1112 and an average sensed current (ISENSE AVG) corresponding to average sensed current (ISENSE AVG) signal 1114. The error between the average current (IAVG) and the sensed average current (ISENSE AVG) may be an indication to controller 1002 to increase the peak current (IPEAK).

[0175] In some embodiments, average current error amplifier 1104 may be included in a circuit referred to as a current control loop 1126. The current control loop 1126 may regulate the average current (IAVG) used by a system, such as the multi-level converter. Typically, current control loop 1126 may be a less precise but a faster loop when compared to other loops in controller 1002, such as voltage control loop 1124.

[0176] As discussed above, Vamp lpeak signal 1116 that is an output of average current error amplifier 1104 may be an input to PWM comparator 1106. For example, PWM comparator 1106 may receive Vamp lpeak signal 1116 that may correspond to the peak current (IPEAK) to be regulated and a sensed peak current (ISENSE PEAK) signal 1120. The sensed peak current (ISENSE PEAK) signal 1120 may be sensed using sensors that senses current across switches of multi-level converters discussed in FIGs. 8 A and 8B. For example, switches S3 and S4 of the 3-level converter discussed in FIG. 8A and switches S5 and S6 of the 4-level converter discussed in FIG. 8B may be sensed to determine the sensed peak current (ISENSE PEAK). In some instances the sensed peak current (ISENSE PEAK) may also be mixed with a slope compensation waveform. The slope compensation waveform may be a triangular or sawtooth waveform, ramp voltage waveform, or a portion of the voltage wave form and may mixed with the sensed peak current (ISENSE PEAK) to make the sensed peak current (ISENSE PEAK) more stable.

[0177] The PWM comparator 1106 may use Vamp lpeak signal 1116 and sensed peak current (ISENSE PEAK) signal 1120 to generate a PWM signal 1122. The PWM signal 1122 may be a minimum of or an error between the peak current (IPEAK) corresponding to Vamp lpeak signal 1116 and sensed peak current (ISENSE PEAK) corresponding to the peak current (ISENSE PEAK) signal 1320. PWM signal 1122 may be used to set a duty cycle as discussed in FIG. 10. For example, PWM signal 1122 may set a duty cycle when the multi-level converter circuit changes zones, such as from a first zone to a second zone, from the second zone to a third zone, from the third zone to a fourth zone, or vice versa.

[0178] In some embodiments, PWM comparator 1106 may be included in a circuit referred to as a peak current control loop 1128. The peak current control loop 1128 may regulate the peak current (IPEAK) used by a system, such as the multi-level converter.

[0179] As discussed above, the power converter may operate in different modes, including a buck mode, a boost mode, a buck-to-boost mode, a three-level converter, a four-level converter, another M-lev el converter, etc. In each mode, the power converter may also operate using multiple voltage levels, such as a voltage levels VIN, GND, ’AVIN, and %VIN for a 4- level converter discussed in FIG. 8B or voltage levels VIN, VIN/2, and GND for a 3-level converter discussed in FIG. 8 A. FIG. 17A is a diagram 1700A of a graph illustrating voltage levels and duty cycles of a 4-level power converter, according to some embodiments. Notably, the graph of a 4-level converter is for illustrative purposes only, and similar embodiments may be applied to the power converter operating using a different number of levels and modes. As shown in diagram 1700A, graph 1702 illustrates a relationship between input voltage and time. Further, input voltage is divided into four voltage levels, VIN, %VIN, ’AVIN, and GND. The regions between pairs of voltage levels may be referred to as zones. For example, a region between voltage levels GND and ’AVIN may be referred to as a zone 1704A, a region between voltage levels AVIN and AVIN may be referred to as a zone 1704B, and a region between voltage levels AVIN and VEST may be referred to as a zone 1704C. Further, each zone in zones 1704A-C may be associated with a corresponding duty cycle. For example, zone 1704A may be associated with a duty cycle 1706A, zone 1704B may be associated with a duty cycle 1706B, and zone 1704C maybe associated with a duty cycle 1706C.

[0180] In some embodiments, the regions above and below the voltage levels may be referred to as dead zones. FIG. 17B is a diagram 1700B of a graph illustrating voltage levels of a 4-level power converter with dead zones, according to some embodiments. Notably, the graph of a 4-level converter is for illustrative purposes only, and similar embodiments may be applied to the power converter operating using a different number of levels and modes. For example, in graph 1702, the region above and below voltage level ’AVIN may be referred to as a dead zone 1708 A, and the region above and below voltage level AVIN may be referred to as a dead zone 1708B. Although not shown, there may be a dead zone around each voltage level. Dead zones 1708 A and 1708B may be regions where power converter may have difficultly generating output voltage VOUT because power converter may not have control over current in the inductor between node Lx and voltage VOUT shown in FIG. 8B. This is because the power converter may not ramp up or ramp down the current as required to generate output voltage VOUT. Typically, dead zones 1708A and 1708B may be predefined or be configured within the power converter.

[0181] The output voltage VOUT, shown as an output voltage 1710, may be generated within one of zones 1704A-C. When output voltage 1710 is within one of zones 1704A-C, such as zone 1704A, the duty cycle 1706A remains the same. As output voltage 1710 enters a dead zone, such as dead zone 1708 A, output voltage 1710 may become difficult to regulate and the duty cycle 1706A may change to, for example, duty cycle 1706B. The change in the duty cycle may also cause a spike in output current IOUT. The output current IOUT may be the regulated peak current IPEAK in some embodiments. FIG. 17C is a graph illustrating an output current during a zone change, according to some embodiments. In particular, when output voltage 1710 operates within zone 1704A, output current IOUT may be at a predefined number of amperes (or an approximate predefined number of amperes). The level of output current IOUT when the power converter operates in zone 1704A is shown at a level of output current 1724 in graph 1712 prior to time t. When output voltage 1710 enters dead zone 1708A at or around time t, the duty cycle changes (e.g., from duty cycle 1706A to 1706B shown in FIG. 17A). In conventional systems, a change in the duty cycle may cause a current spike 1726 in output current IOUT for a time period 1728 beginning at time t. Although not shown, the current spike 1726 may be 30% to 100% of the level of output current 1724. Time period 1728 may last until current control loop 1126 regulates the output current IOUT back to the level of output current 1724. In another example, instead of current spike 1726, output current IOUT may also decrease in value to below the level of output current 1724 for time period 1728 (not shown), until current control loop 1126 may regulate output current IOUT back to the level of output current 1724.

[0182] In conventional systems, current spike 1726 above the level of output current 1724 may negatively affect power converter and stress the components within the power converter. For example, the power converter may be configured to operate below a maximum allowable current of the power converter, and current spike 1726 of the output current (IOUT) may exceed the maximum current. This may result in an inductor shown in FIGs. 8A and 8B being oversaturated, a battery being prevented from being charged further, a fuse that may be blown, among other adverse impacts to the power controller and the system where the power controller operates.

[0183] Going back to FIG. 10, when the power converter enters or exits one of dead zones, the load currents change briefly. Further, the state variables in the circuit are reset because the steady state conditions are different for new voltage levels. This in turn may cause the output current (IOUT) to go high and exceeding the current limit, which in turn causes the multi-level controller 1010 to reduce the current limit, and again exit or enter the dead zone. Accordingly, once power converter enters or exits one of dead zones, voltage level selector 1012 within multi-level controller 1010 may create a stabilization period (e.g., a predetermined time period) to let the power converter stabilize and reach desired voltage level and output current (IOUT).

[0184] Going back to FIG. 16, in order to reduce the likelihood of the current spike 1726 occurring in output current IOUT during the zone change, controller 1002 may include a control circuit 1130. Control circuit 1130 may be included in current control loop 1126. For example, control circuit 1130 may be incorporated in current control loop 1126 between a capacitor 1132 storing charge corresponding to the output signal, such as Vamp lpeak 1116 and a resistor 1134. In this case, control circuit 1130 may regulate the peak current (IPEAK). In other examples, control circuit 1130 may be connected to other components in controller 1002. [0185] Control circuit 1130 may predictively regulate output current IOUT to reduce the likelihood of current spike 1726 occurring during the zone change. Control circuit 1130 may receive a control signal 1136 that indicates that the power converter is changing zones, e.g., from a current zone 1704A to a new zone 1704B (or between other zones 1704A-C). In some embodiments, control signal 1136 may be issued using Multi-Level Switch State Selector 1014 discussed in FIG. 10 at or around time t.

[0186] In response to receiving control signal 1136, control circuit 1130 may generate a signal 1138 that may predictively regulate the output current IOUT at or around time t. For example, signal 1138 may set the information in controller 1002 from information associated with the current zone, e.g. 1704A, to information known to be associated with the new zone, e.g., 1704B. The information may be stored in control circuit 1130, elsewhere in controller 1002, or be included in control signal 1136. Signal 1138 may be a pulse.

[0187] In some embodiments, signal 1138 may change the information by charging or discharging capacitor 1132 from the voltage associated with zone 1704A to the voltage associated with zone 1704B. With reference to graph 1712 in FIG. 17C, predictively charging or discharging capacitor 1132 to the voltage known to be associated with zone 1704B, when or just prior to the power converter changing zones, may lower output current IOUT to a level shown as output current 1730, which is below output current 1724. This may avoid or reduce current spike 1726. For example, the value of output current 1730 may be a predefined number of amperes lower than output current 1724 and may be below output current 1724 by a predefined threshold. Since charging or discharging the capacitor 1132 may only approximately change the level of output current 1724 to output current 1730, current control loop 1126 may then regulate output current IOUT to bring the level of output current IOUT back to the level of output current 1724. In another example, control circuit 1130 may predict a voltage value of capacitor 1132 that may maintain the level of output current IOUT close to output current 1724, shown as output current 1732. The control circuit 1130 may generate signal 1338 that may charge or discharge the capacitor to the predicted voltage value that corresponds to the level of output current 1732. The current control loop 1126 may then regulate output current IOUT to bring the output current IOUT from the level of output current 1732 to the level of output current 1724. In this way, when the power converter transitions from zone 1704A to 1704B (or between other zones), the impact on output current IOUT is minimized, and output current IOUT is regulated at or around the level of output current 1724. With the embodiments discussed above, the current spike 1726 may disappear, be below the level of output current 1724, such as at levels corresponding to output current 1730 or 1732, or be 5-10% of current spike 1726 (not shown).

[0188] In dead zones, it may be difficult to guarantee positive or uniform current into a capacitor (COUT) when the capacitor (COUT) is being balanced. One way to identify that the capacitor (COUT) is not being balanced is detecting when the capacitor does not continuously switch between charging and discharging. When the capacitor (COUT) is not switching between charging and discharging, the capacitor (COUT) may be overcharging. In this case, a current source may be turned on until the capacitor (COUT) becomes balanced and begins to switch between charging and discharging.

[0189] In some embodiments, output current (IOUT) should be net positive to maintain charge on the capacitor (COUT). If the output current (IOUT) is heavily negative (e.g., below a negative current threshold), the polarity of when capacitor (COUT) is charged or discharged. If the output current (IOUT) is close to zero (e.g., the output current (IOUT) being slightly positive and/or slightly negative for each cycle), the power converter’s ability to balance capacitor (COUT) may be distorted. When a power converter is operating in a continuous conduction mode (CCM), a discontinuous conduction mode (DCM) may be implemented at zero current to prevent the output current (IOUT) from becoming negative. However, switching to the DCM mode may cause a minimum load at peak frequency. The minimum load may be high for a small inductor, particularly in the dead zone. Further, the small inductor may have a large ripple current. Accordingly, to minimize the load, the DCM mode may be activated when the output current (IOUT) is below zero. This is because the ripple current from the small inductor is positive and may cause the net current (output current (IOUT) plus ripple current) to be net positive. The value of the negative output current (IOUT) at which DCM mode may be activated may depend on the value of the ripple current. That is, the value of the negative output current (IOUT) at which DCM mode is activated may vary as long as the ripple current from the small inductor is sufficient to cause a positive net current.

[0190] As discussed in FIG. 8A, power converter may be a 3-level converter circuit. The 3 -level converter circuit may operate in a boost mode. In a dead zone, DCM mode may not be implemented. However, because the DCM mode is not implemented in the dead zone, there is no guarantee of a net positive current or a net negative current in the dead zone in a single cycle. An inductor may be charged to supply current and discharged to ground. However, when the inductor is parked in the dead zone, that inductor current may be net negative or net positive, even though the entire output current (IOUT) may be positive. In the boost mode, to keep the capacitor balanced, the 3 -level converter circuit may avoid the dead zone by skipping a level. For example, the 3-level power converter may skip the second level and jump from the first level to the third level. Similarly, in an M-level converter circuit, the level where the inductor L is parked in a dead zone with no guarantee of a net positive or net negative current may be skipped. For example, in a six-level converter circuit where level four is near the dead zone, the six-level converter circuit may jump from level three to level five and avoid level four to keep the capacitor balanced. In this way, by avoiding the dead zone, the ripple current is maintained, the output current (IOUT) is kept positive by the DCM mode, the inductor L is being charged and discharged, and the capacitor (COUT) is kept balanced.

[0191] In some embodiments, there may be various operating modes within dead zones. The operating modes may be based on the input and output current (IOUT). For example, dead zone may introduce a high minimum output current (I OUT), particularly when the DCM mode is being implemented. For example, parking the inductor in the dead zone may result in a high minimum output current (I OUT) that may not occur in the CCM mode or when the power converter is not operating in the dead zones. In some instances, different operating modes for the power converter may correspond to different ranges for input and output current (IOUT). For example, a less efficient mode (e.g., mode that consumes more power) may be used when the power converter is operating in the dead zone with a low input or output current (I OUT), and a more efficient mode (e.g., mode that consumes less power) may be set when the power converter is operating in the dead zone with a high input or output current (I OUT). The number of operating modes, ranges for the input and output current (IOUT) and corresponding modes may be configured or preconfigured in the power converter.

[0192] FIG. 18 is an example flow chart illustrating predictive control of a control loop during a zone change, in accordance with one or more embodiments. The operations 1804- 1806 in flow chart 1800 may be performed using circuits discussed in FIGs. 1-10, 16-17A-C.

[0193] In operation 1802, a control signal is received. For example, control circuit 1130 in the controller 1002 of the power converter receives control signal 1136 indicating a zone change that changes the duty cycle, such as a zone change from a current zone 1704A to a new zone 1704B. [0194] At operation 1804, information corresponding to the new zone is set. For example, control circuit 1130 may issue signal 1138 that may set information stored in controller 1002 from information corresponding to the current zone 1704A to information corresponding to the new zone 1704B. Signal 1138 may set the information during the zone change, such as at time t, just prior to the zone change, or as soon as technologically possible after receiving control signal 1136 indicating the zone change. In one embodiment, signal 1138 may charge or discharge capacitor 1132 to a voltage known to correspond to zone 1704B. Setting the voltage of capacitor 1132 may prevent or reduce the magnitude of current spike 1726 of output current IOUT from the level of output current 1724 to the levels of output current 1730 or 1732. Once the information is set, current control loop 1126 may regulate the output current IOUT from the level of output current 1730 or 1732 to return to the level of output current 1724. As discussed above, reducing current spike 1726 may prevent the output current IOUT from exceeding the maximum allowable current in the power converter as well as reducing or preventing the likelihood of damage to the components of the power converter.

[0195] Further aspects of the present disclosure include the following:

[0196] Aspect 1 includes a system comprising: an analog loop circuit configured to: receive a reference signal; determine a first error based the reference signal and a sensing signal in a plurality of sensing signals; and regulate a system output signal of the system based on the first error; and a digital loop circuit configured to: convert the system output signal into a digital system output signal; determine a second error between the digital system output signal and a digital reference signal received from a device coupled to the system; determine a control signal based the second error; and convert the control signal into the reference signal.

[0197] Aspect 2 includes the system of aspect 1, wherein the digital loop circuit further comprises a proportional-integral-derivative (PID) controller configured to determine the control signal using the second error.

[0198] Aspect 3 includes the system of any of aspects 1-2, wherein the digital loop circuit further comprises a controller configured to determine the control signal based on a proportion of the second error between the digital system output signal and the digital reference signal.

[0199] Aspect 4 includes the system of any of aspects 1-3, wherein the digital loop circuit further comprises a controller configured to determine the control signal based on the second error that has a non-linear relationship between the digital system output signal and the digital reference signal.

[0200] Aspect 5 includes the system of any of aspects 1-4, wherein the digital loop circuit further comprises a controller that is configured to determine the control signal based on the second error that has an exponential relationship between the digital system output signal to the digital reference signal.

[0201] Aspect 6 includes the system of any of aspects 1-5, wherein the digital loop circuit further comprises a register that stores the digital reference signal.

[0202] Aspect 7 includes the system of any of aspects 1-6, wherein the digital loop circuit further comprises a digital-to-analog converter configured to convert the control signal into the reference signal.

[0203] Aspect 8 includes the system of any of aspects 1-7, wherein the system output signal is a battery voltage signal and the digital loop circuit further comprises an analog-to-digi- tal converter configured to convert the battery voltage signal into the digital system output signal.

[0204] Aspect 9 includes the system of any of aspects 1-8, wherein the analog loop circuit further comprises a controller configured to regulate the system output signal of the system.

[0205] Aspect 10 includes the system of any of aspects 1-9, wherein the controller includes a voltage control loop circuit, an average current control loop circuit, and a peak current control loop circuit and configured to regulate the system output signal corresponding to one of the voltage control loop circuit, the average current control loop circuit, or the peak current control loop circuit.

[0206] Aspect 11 includes the system of any of aspects 1-10, wherein the plurality of sensing signals comprises a reference voltage signal, a sensed average current signal, or a peak current signal.

[0207] Aspect 12 includes the system of any of aspects 1-11, wherein the analog loop circuit is further configured to operate at a first frequency, and the digital loop circuit is further configured to operate at a second frequency, the first frequency faster than the second frequency.

[0208] Aspect 13 includes a system comprising: an analog loop circuit configured to: receive a reference signal; determine a first error between the reference signal and a sense signal received from a sensor of a multi-level converter; and regulate an output signal of the multi-level converter based on the first error; and a digital loop circuit configured to: generate a control signal by adjusting a digital reference signal with a digital trim circuit; and convert, using a digital -to-analog converter, the control signal into the reference signal for processing by the analog loop circuit during a subsequent iteration.

[0209] Aspect 14 includes the system of aspect 13, wherein the digital loop circuit comprises a register configured to store the digital reference signal.

[0210] Aspect 15 includes the system of any of aspects 13-14, wherein the analog loop circuit further comprises a controller configured to regulate the output signal of the multilevel converter using the at least one of the plurality of the control loops.

[0211] Aspect 16 includes the system of any of aspects 13-15, wherein the controller includes an average current loop and the reference signal is associated with an average current.

[0212] Aspect 17 includes the system of any of aspects 13-16, wherein the controller includes a voltage loop and the reference signal is associated with an output voltage.

[0213] Aspect 18 includes the system of any of aspects 13-17, wherein the output signal of the multi-level converter is associated with a battery voltage.

[0214] Aspect 19 includes a method comprising: receiving an analog reference signal; determining a first error between the analog reference signal and at least one of a plurality of sense signals generated by at least one sensor of a system; regulating, using a controller, an analog system output of the system using the first error; converting, using an analog-to-digital converter, the analog system output into a digital system output; determining a second error between a digital reference signal and the digital system output, wherein the digital reference signal is associated with a device that uses the analog system out; and converting, using a digital-to-analog circuit, the second error into the analog reference signal for regulating the analog system output during a subsequent iteration. [0215] Aspect 20 includes the method of aspect 19, wherein the regulating the controller using the first error occurs at a first frequency, and determining the second error occurs at a second frequency, the first frequency faster than the second frequency.

[0216] Aspect 21 includes a system comprising: a power converter configured to operate in a plurality of zones, each zone corresponding to a pair of voltage levels in a plurality of voltage levels; a controller configured to store information corresponding to a first zone in the plurality of zones; and a control circuit configured to: receive a control signal indicating a zone change from the first zone to a second zone in the plurality of zones; and set the information to correspond to the second zone, wherein setting the information regulates fluctuation of a current in the power converter during the zone change.

[0217] Aspect 22 includes the system of aspect 21, wherein the controller comprises a capacitor that stores the information as a first voltage and to set the information to correspond to the second zone, the control circuit is further configured to charge or discharge the capacitor to a second voltage known to correspond to the second zone.

[0218] Aspect 23 includes the system of any of aspects 21-22, wherein the capacitor is within a current control loop of the controller and the charging or discharging the capacitor regulates an output current of the current control loop to a level below a predefined threshold during the zone change.

[0219] Aspect 24 includes the system of any of aspects 21-23, wherein the current control loop further regulates the output current subsequent to charging or discharging the capacitor.

[0220] Aspect 25 includes the system of any of aspects 21-24, wherein the control circuit is further configured to set the information when a voltage output enters a dead zone associated with the zone change from the first zone associated with a first pair of voltage levels to the second zone associated with a second pair of voltage levels.

[0221] Aspect 26 includes the system of any of aspects 21-25, wherein the controller further comprises: a voltage loop configured to receive an output voltage and a reference voltage and generate a first signal representing an average current to be regulated by the power converter; and a current control loop configured to receive the first signal representing the average current and a second signal representing sensed average current and generate an output signal representing a peak current, wherein the peak current is the current regulated by the control circuit setting the information.

[0222] Aspect 27 includes the system of any of aspects 21-26, wherein setting the information reduces a spike in the peak current to below a predefined threshold during the zone change.

[0223] Aspect 28 includes the system of any of aspects 21-27, wherein the peak current is mixed with a slope compensation waveform, wherein the slope compensation waveform is one of a sawtooth waveform or a ramp voltage waveform.

[0224] Aspect 29 includes the system of any of aspects 21-28, wherein the control signal includes the information corresponding to the second zone.

[0225] Aspect 30 includes a method comprising: storing, at a controller, information corresponding to a first zone in a plurality of zones associated with a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels; receiving, at a control circuit of the controller, a control signal indicating a zone change from the first zone to a second zone in the plurality of zones; and setting, at the controller, the information known to correspond to the second zone.

[0226] Aspect 31 includes the method of aspect 30, wherein a capacitor of the controller stores the information associated with a first voltage corresponding to the first zone, and the setting the information further comprises charging or discharging the capacitor to a second voltage known to correspond to the second zone.

[0227] Aspect 32 includes the method of any of aspects 30-31, wherein the capacitor is within a current control loop of the controller and charging or discharging the capacitor regulates an output current of the current control loop to a level below a predefined threshold.

[0228] Aspect 33 includes the method of any of aspects 30-32, wherein setting the information occurs when a voltage output enters a dead zone associated with the power converter changing from the first zone associated with the first pair of voltage levels to the second zone associated with a second pair of voltage levels.

[0229] Aspect 34 includes the method of any of aspects 30-33, further comprising: generating, at a voltage control loop of the controller, a first signal representing a regulated average current from an output voltage and a reference voltage; receiving, at a current control loop of the controller, the first signal representing the regulated average current and a second signal representing an average current sensed at a sensor of the power converter; generating, at the current control loop, an output signal representing a regulated peak current from the first signal and the second signal; and controlling the regulated peak current by setting the information to correspond to the second zone during the zone change.

[0230] Aspect 35 includes the method of any of aspects 30-34, wherein controlling the regulated peak current reduces a spike in the regulated peak current to below a predefined threshold.

[0231] Aspect 36 includes the method of any of aspects 30-35, wherein the control signal includes the information known to correspond to the second zone.

[0232] Aspect 37 includes a system comprising: a current control loop configured to: receive a first current signal and a second current signal; generate an output signal representing an output current; and store information corresponding to a first zone of operation of a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels; and a control circuit in the current control loop configured to set the information to correspond to a second zone of operation of the power converter, wherein the second zone corresponds to a second pair of voltage levels in the plurality of voltage levels, and wherein setting the information to correspond to the second zone reduces a spike in the output current during a zone change from the first zone to the second zone.

[0233] Aspect 38 includes the system of aspect 37, wherein the power converter is a multilevel power converter.

[0234] Aspect 39 includes the system of any of aspects 37-38, wherein the control circuit receives a signal indicating the zone change from the first zone to the second zone.

[0235] Aspect 40 includes the system of any of aspects 37-39, wherein the current control loop comprises a capacitor configured to: store the information as a first voltage; and to set the information, charge or discharge to a second voltage known to correspond to the second zone; and wherein the control circuit is further configured to generate a signal to charge or discharge the capacitor to the second voltage. [0236] General Benefits and Advantages of Multi-Level Power Converters

[0237] Embodiments of the current invention improve the power density and/or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and/or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0238] More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:

[0239] - adaptability to applications in which input and/or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);

[0240] - efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0241] - efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;

[0242] - enabling design optimizations for power efficiency, power density, and formfactor of the power converter - for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and/or to lower an overall bill of materials;

[0243] - the ability to take advantage of the performance of smaller, low voltage transistors;

[0244] - adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g, USB, USB-C, power-over Ethernet, etc.); [0245] - adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g., LCDs and LEDs of all types);

[0246] - the ability to be implemented in a number of IC technologies e.g, MOSFETs,

GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0247] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters include portable and mobile computing and/or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z- Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery -backup systems and/or power conversion for processing systems and/or electronic/op- tical networking systems), internet-of-things (IOT) devices (e.g., smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC/DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and/or infotainment systems), and other devices and systems that utilize portable electricity generating sources and/or require power conversion.

[0248] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.1 la, b, g, ac, ax), as well as other radio communication standards and protocols.

[0249] Programmable Embodiments

[0250] Some or all aspects of the invention, particularly the Multi-Level Switch State Selector 1014 of FIG. 10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (z.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client/server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and/or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code may be applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.

[0251] Each such computer program may be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.

[0252] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or permanently), the storage media or device being readable by a general or special purpose programmable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a specific or predefined manner to perform the functions described in this disclosure.

[0253] Fabrication Technologies & Options

[0254] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multi-level power converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC -based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiCE), hafnium dioxide (HFO2), or aluminum oxide AI2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and/or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0255] Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0256] The controlled s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and/or combinatorial logic.

[0257] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transis- tor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0258] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0259] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0260] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design. [0261] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0262] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0263] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

[0264] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A system comprising: an analog loop circuit configured to: receive a reference signal; determine a first error based the reference signal and a sensing signal in a plurality of sensing signals; and regulate a system output signal of the system based on the first error; and a digital loop circuit configured to: convert the system output signal into a digital system output signal; determine a second error between the digital system output signal and a digital reference signal received from a device coupled to the system; determine a control signal based the second error; and convert the control signal into the reference signal.

2. The system of claim 1, wherein the digital loop circuit further comprises a proportional- integral-derivative (PID) controller configured to determine the control signal using the second error.

3. The system of claim 1, wherein the digital loop circuit further comprises a controller configured to determine the control signal based on a proportion of the second error between the digital system output signal and the digital reference signal.

4. The system of claim 1, wherein the digital loop circuit further comprises a controller configured to determine the control signal based on the second error that has a non-linear relationship between the digital system output signal and the digital reference signal.

5. The system of claim 1, wherein the digital loop circuit further comprises a controller that is configured to determine the control signal based on the second error that has an exponential relationship between the digital system output signal to the digital reference signal.

6. The system of claim 1, wherein the digital loop circuit further comprises a register that stores the digital reference signal.

7. The system of claim 1, wherein the digital loop circuit further comprises a digital -to-analog converter configured to convert the control signal into the reference signal.

8. The system of claim 1, wherein the system output signal is a battery voltage signal and the digital loop circuit further comprises an analog-to-digital converter configured to convert the battery voltage signal into the digital system output signal.

9. The system of claim 1, wherein the analog loop circuit further comprises a controller configured to regulate the system output signal of the system.

10. The system of claim 9, wherein the controller includes a voltage control loop circuit, an average current control loop circuit, and a peak current control loop circuit and configured to regulate the system output signal corresponding to one of the voltage control loop circuit, the average current control loop circuit, or the peak current control loop circuit.

11. The system of claim 9, wherein the plurality of sensing signals comprises a reference voltage signal, a sensed average current signal, or a peak current signal.

12. The system of claim 1, wherein the analog loop circuit is further configured to operate at a first frequency, and the digital loop circuit is further configured to operate at a second frequency, the first frequency faster than the second frequency.

13. A system comprising: an analog loop circuit configured to: receive a reference signal; determine a first error between the reference signal and a sense signal received from a sensor of a multi-level converter; and regulate an output signal of the multi-level converter based on the first error; and a digital loop circuit configured to: generate a control signal by adjusting a digital reference signal with a digital trim circuit; and convert, using a digital-to-analog converter, the control signal into the reference signal for processing by the analog loop circuit during a subsequent iteration.

14. The system of claim 13, wherein the digital loop circuit comprises a register configured to store the digital reference signal.

15. The system of claim 13, wherein the analog loop circuit further comprises a controller configured to regulate the output signal of the multi-level converter using the at least one of the plurality of the control loops.

16. The system of claim 15, wherein the controller includes an average current loop and the reference signal is associated with an average current.

17. The system of claim 15, wherein the controller includes a voltage loop and the reference signal is associated with an output voltage.

18. The system of claim 17, wherein the output signal of the multi-level converter is associated with a battery voltage.

19. A method comprising: receiving an analog reference signal; determining a first error between the analog reference signal and at least one of a plurality of sense signals generated by at least one sensor of a system; regulating, using a controller, an analog system output of the system using the first error; converting, using an analog-to-digital converter, the analog system output into a digital system output; determining a second error between a digital reference signal and the digital system output, wherein the digital reference signal is associated with a device that uses the analog system out; and converting, using a digital-to-analog circuit, the second error into the analog reference signal for regulating the analog system output during a subsequent iteration.

20. The method of claim 19, wherein the regulating the controller using the first error occurs at a first frequency, and determining the second error occurs at a second frequency, the first frequency faster than the second frequency.

21. A system comprising: a power converter configured to operate in a plurality of zones, each zone corresponding to a pair of voltage levels in a plurality of voltage levels; a controller configured to store information corresponding to a first zone in the plurality of zones; and a control circuit configured to: receive a control signal indicating a zone change from the first zone to a second zone in the plurality of zones; and set the information to correspond to the second zone, wherein setting the information regulates fluctuation of a current in the power converter during the zone change.

22. The system of claim 21, wherein the controller comprises a capacitor that stores the information as a first voltage and to set the information to correspond to the second zone, the control circuit is further configured to charge or discharge the capacitor to a second voltage known to correspond to the second zone.

23. The system of claim 22, wherein the capacitor is within a current control loop of the controller and the charging or discharging the capacitor regulates an output current of the current control loop to a level below a predefined threshold during the zone change.

24. The system of claim 23, wherein the current control loop further regulates the output current subsequent to charging or discharging the capacitor.

25. The system of claim 21, wherein the control circuit is further configured to set the information when a voltage output enters a dead zone associated with the zone change from the first zone associated with a first pair of voltage levels to the second zone associated with a second pair of voltage levels.

26. The system of claim 21, wherein the controller further comprises: a voltage loop configured to receive an output voltage and a reference voltage and generate a first signal representing an average current to be regulated by the power converter; and a current control loop configured to receive the first signal representing the average current and a second signal representing sensed average current and generate an output signal representing a peak current, wherein the peak current is the current regulated by the control circuit setting the information.

27. The system of claim 26, wherein setting the information reduces a spike in the peak current to below a predefined threshold during the zone change.

28. The system of claim 26, wherein the peak current is mixed with a slope compensation waveform, wherein the slope compensation waveform is one of a sawtooth waveform or a ramp voltage waveform.

29. The system of claim 21, wherein the control signal includes the information corresponding to the second zone.

30. A method comprising: storing, at a controller, information corresponding to a first zone in a plurality of zones associated with a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels; receiving, at a control circuit of the controller, a control signal indicating a zone change from the first zone to a second zone in the plurality of zones; and setting, at the controller, the information known to correspond to the second zone.

31. The method of claim 30, wherein a capacitor of the controller stores the information associated with a first voltage corresponding to the first zone, and the setting the information further comprises charging or discharging the capacitor to a second voltage known to correspond to the second zone.

32. The method of claim 31, wherein the capacitor is within a current control loop of the controller and charging or discharging the capacitor regulates an output current of the current control loop to a level below a predefined threshold.

33. The method of claim 30, wherein setting the information occurs when a voltage output enters a dead zone associated with the power converter changing from the first zone associated with the first pair of voltage levels to the second zone associated with a second pair of voltage levels.

34. The method of claim 30, further comprising: generating, at a voltage control loop of the controller, a first signal representing a regulated average current from an output voltage and a reference voltage; receiving, at a current control loop of the controller, the first signal representing the regulated average current and a second signal representing an average current sensed at a sensor of the power converter; generating, at the current control loop, an output signal representing a regulated peak current from the first signal and the second signal; and controlling the regulated peak current by setting the information to correspond to the second zone during the zone change.

35. The method of claim 34, wherein controlling the regulated peak current reduces a spike in the regulated peak current to below a predefined threshold.

36. The method of claim 30, wherein the control signal includes the information known to correspond to the second zone.

37. A system comprising: a current control loop configured to: receive a first current signal and a second current signal; generate an output signal representing an output current; and store information corresponding to a first zone of operation of a power converter, wherein the first zone corresponds to a first pair of voltage levels in a plurality of voltage levels; and a control circuit in the current control loop configured to set the information to correspond to a second zone of operation of the power converter, wherein the second zone corresponds to a second pair of voltage levels in the plurality of voltage levels, and wherein setting the information to correspond to the second zone reduces a spike in the output current during a zone change from the first zone to the second zone.

38. The system of claim 37, wherein the power converter is a multi-level power converter.

39. The system of claim 37, wherein the control circuit receives a signal indicating the zone change from the first zone to the second zone.

40. The system of claim 37, wherein the current control loop comprises a capacitor configured to: store the information as a first voltage; and to set the information, charge or discharge to a second voltage known to correspond to the second zone; and wherein the control circuit is further configured to generate a signal to charge or discharge the capacitor to the second voltage.