WO2025148789A1 - Encoding method and apparatus, and decoding method and apparatus - Google Patents

Abstract

The present application relates to an encoding method and apparatus, and a decoding method and apparatus. In the encoding method, a first device may determine a second bit sequence and a third bit sequence on the basis of a first bit sequence, wherein the third bit sequence comprises a bit sequence, which is in a base graph corresponding to the first bit sequence and has a weight higher than a first threshold, that is, a weight corresponding to the second bit sequence is lower than a weight corresponding to the third bit sequence; further, the first device can perform polar code encoding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence having a lower weight by means of polar code encoding, so as to improve error correction performance; and the third bit sequence having a higher weight can be subjected to LDPC encoding together with the result (i.e., a fourth bit sequence obtained by performing polar code encoding on the second bit sequence) of polar code encoding. The error floor of LDPC decoding is reduced and the error correction performance of an LDPC code is improved.

Description

A coding method, a decoding method and a device

This application claims the priority of the Chinese patent application with application number 202410035730.9 filed with the State Intellectual Property Office of China on January 9, 2024, and the priority of the Chinese patent application with the invention name "A coding method, a decoding method and a device", all of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method and a device.

Background Art

Low density parity check (LDPC) code is a channel coding scheme very close to the Shannon line, with the characteristics of good performance and low complexity. It has been identified by the 3rd generation partnership project (3GPP) as the data channel coding scheme for the fifth generation (5G) communication technology.

However, when the signal-to-noise ratio (SNR) is relatively high, LDPC codes may have an error floor due to the influence of trap sets, and their bit error rate (BLER) will no longer decrease as the signal-to-noise ratio increases. A trap set is a set of bit numbers that cannot be correctly decoded and output after a large fixed number of iterations. The error floor is mainly determined by the size and distribution of the trap set. Therefore, how to reduce the error floor of LDPC codes has become an urgent problem to be solved at the current stage.

Summary of the invention

The present application provides an encoding method, a decoding method and a device, which can reduce the error floor and bit error rate of LDPC codes, thereby improving the error correction performance.

In a first aspect, a coding method is provided, which can be executed by a first device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the first device, or by a logical node, a logical module, or software that can implement all or part of the functions of the first device. In the coding method, a second bit sequence and a third bit sequence can be determined based on a first bit sequence, and the third bit sequence includes a bit sequence whose weight in a base graph corresponding to the first bit sequence is higher than a first threshold. The second bit sequence can also be polarization coded to obtain a fourth bit sequence. Thus, the third bit sequence and the fourth bit sequence can be low-density parity check LDPC coded to obtain a fifth bit sequence.

It can be seen that in the above embodiment, the first device can determine the second bit sequence and the third bit sequence based on the first bit sequence, and the third bit sequence includes a bit sequence in the base map corresponding to the first bit sequence whose weight is higher than the first threshold. That is to say, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the first device can perform polarization code encoding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with a lower weight by using polarization code encoding to improve the error correction performance. For the third bit sequence with a higher weight, LDPC encoding can be performed together with the result of polarization code encoding (i.e., the fourth bit sequence obtained by performing polarization code encoding on the second bit sequence). In this way, the error floor of LDPC decoding can be reduced, thereby improving the error correction performance of LDPC code. At the same time, the LDPC coding load caused by Polar outer code encoding can also be reduced, thereby reducing the code rate of LDPC code and improving waterfall performance.

In a possible implementation, determining the second bit sequence and the third bit sequence based on the first bit sequence includes: determining a first numerical value based on the first column number in the base graph whose weight is higher than a first threshold; determining the third bit sequence from the first bit sequence based on the first numerical value and a lifting factor corresponding to the first bit sequence; and determining the second bit sequence based on the third bit sequence and the first bit sequence.

It can be seen that in the above embodiment, the first device can determine the first value based on the first number of columns in the base graph whose weight is higher than the first threshold, and thus can determine the third bit sequence from the first bit sequence based on the first value and the lifting factor corresponding to the first bit sequence. In this way, the bit sequence with a larger column weight in the first bit sequence can be determined more accurately, and then the bit sequence with a smaller column weight, that is, the second bit sequence, can be determined more accurately.

In a possible implementation manner, the first column number is an integer greater than or equal to 1. For example, the first column number may be 2 or 3.

In a possible implementation, determining a first numerical value based on a first column number in a base graph with a weight higher than a first threshold includes: determining a second column number with the highest reliability from other columns in the base graph except for columns with a weight higher than the first threshold; and determining the first numerical value based on the first column number and the second column number.

It can be seen that in the above embodiment, the first device can also determine the first value based on the first column number and the second column number, and the first value can be used to determine the third bit sequence from the first bit sequence, which is equivalent to increasing the number of bits that are not polar code encoded. Therefore, this can reduce the LDPC coding load caused by Polar outer code encoding, thereby reducing the code rate of the LDPC code and improving the waterfall area performance.

In a possible implementation, performing polarization code encoding on the second bit sequence to obtain a fourth bit sequence includes: performing check code encoding on the second bit sequence to obtain a sixth bit sequence; and performing polarization code encoding on the sixth bit sequence to obtain the fourth bit sequence. The check code encoding may be parity check (PC) encoding and/or cyclic redundancy check (CRC) encoding.

It can be seen that in the above embodiment, the first device can first perform check code encoding on the second bit sequence, and then perform polar code encoding. This is equivalent to the check code only checking the bits of the non-large column heavy part, because the large column heavy bits are almost never wrong. If an error occurs, then the non-large column heavy bits are also very likely to be wrong. The check code can be used to correct the non-large column heavy bits. In addition, the check code can be used for error correction, so that when SCL decoding is used, the performance of the polar code under SCL decoding can be improved.

In a possible implementation, the method further includes: performing check code encoding on the seventh bit sequence to obtain the first bit sequence.

It can be seen that in the above embodiment, the first device can perform check code encoding on the seventh bit sequence to obtain the first bit sequence. The seventh bit sequence contains bits with large column weights. In other words, bits with large column weights can also be checked by the check code, so that a lower false alarm rate (FAR) can be obtained.

In a possible implementation, the method further includes: segmenting the initial bit sequence based on a first segment length to obtain X bit sequences, where the X bit sequences include the first bit sequence or the seventh bit sequence, and X is an integer greater than 1; wherein the first segment length is determined based on the first numerical value and the lifting factor.

It can be seen that in the above embodiment, the first device can segment the initial bit sequence based on the first segment length, and the first segment length is determined based on the first value and the lifting factor. In other words, this provides a segmentation method adapted to the present solution, reducing the coding error problem caused by segmentation errors.

In a possible implementation, the first segment length is determined based on the first value and the lifting factor, including: the first segment length is determined based on the first value, the lifting factor and the second value; wherein the second value is determined based on the total number of columns of the base graph and the first value.

In a possible implementation manner, the first segment length satisfies the following conditions: Among them, a is the first value, b is the second value, R is the third value, and Z is the boost factor.

In a possible implementation, determining the second bit sequence based on the third bit sequence and the first bit sequence includes: segmenting other bit sequences in the first bit sequence except the third bit sequence based on a second segment length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; wherein the second segment length is determined based on a maximum length supported by polar code encoding and a third value.

It can be seen that in the above embodiment, the first device may segment the other bit sequences in the first bit sequence except the third bit sequence based on the second segment length (determined based on the maximum length supported by polar code encoding and the third value) to obtain Y bit sequences, and the Y bit sequences may include the second bit sequence. This can prevent errors when polar code encoding is performed on the second bit sequence, and better compatibility with the current polar code mode.

In a possible implementation manner, the second segment length satisfies the following conditions: Wherein, Nm is the maximum length supported by the polar code encoding, and R is the third value.

In a possible implementation, the method further includes: sending a symbol sequence based on a third bit sequence.

In a second aspect, a decoding method is provided, which can be executed by a second device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the second device, or by a logical node, a logical module, or software that can implement all or part of the functions of the second device. In the decoding method, a symbol sequence can be obtained, so that a fifth bit sequence can be determined based on the symbol sequence, and then the fifth bit sequence is LDPC decoded to obtain a third bit sequence and a fourth bit sequence. In this way, the fourth bit sequence can be polarized and decoded to obtain a second bit sequence, and the first bit sequence can be determined based on the third bit sequence and the second bit sequence.

It can be seen that in the above embodiment, the second device can first determine the fifth bit sequence based on the symbol sequence, and then perform LDPC decoding on the fifth bit sequence to obtain the third bit sequence and the fourth bit sequence, so that the fourth bit sequence can be polarization code decoded to obtain the second bit sequence. In this way, the first bit sequence can be determined based on the third bit sequence and the second bit sequence. This can be used to reduce the error floor of LDPC decoding, thereby improving the error correction performance of LDPC code. At the same time, the LDPC coding load caused by Polar outer code encoding can also be reduced, thereby reducing the code rate of LDPC code and improving waterfall area performance. In addition, the second device performs polarization code decoding on some bit sequences (such as the fourth bit sequence) in the LDPC decoding result, which reduces the decoding delay and improves the decoding efficiency.

In a third aspect, a communication device is provided, comprising a unit or module for implementing any of the methods described in any of the first to second aspects. The communication device may be a first device or a second device, or a module of the first device or the second device (e.g., a processor, a chip, or a chip system), or a logical node, a logical module, or software that can implement all or part of the functions of the first device or the second device.

In a fourth aspect, a communication device is provided, the communication device comprising at least one processor; wherein the at least one processor is used to execute any of the methods described in any of the first aspect to the second aspect. The communication device may be a first device or a second device, or a module of the first device or the second device (such as a processor, a chip, or a chip system, etc.), or a logical node, a logical module, or software that can implement all or part of the functions of the first device or the second device. At least one processor may execute a computer program or instruction in a memory so that the above method is executed. The memory may be included in the communication device or may be located outside the communication device. In addition, the communication device may further include an interface.

In a fifth aspect, a communication system is provided, the communication system comprising a first device and a second device; the first device is used to execute the method as described in any one of the first aspects; the second device is used to execute the method as described in any one of the second aspects.

In a sixth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed, the computer executes any of the methods described in any of the first to second aspects.

In a seventh aspect, a computer program product is provided, the computer program product comprising: a computer program code, and when the computer program code is executed by a computer, the computer executes any one of the methods described in any one of the first aspect to the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a basic architecture of a communication system provided in an embodiment of the present application;

FIG2 is a schematic diagram of a communication process between communication devices;

FIG3 is a schematic diagram of polar code encoding;

FIG4 is a schematic diagram of a check matrix;

FIG5 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

FIG6 is a schematic diagram of a flow chart of a decoding method provided in an embodiment of the present application;

FIG7 is a schematic diagram of a flow chart of another encoding method provided in an embodiment of the present application;

FIG8 is a schematic diagram of a flow chart of another decoding method provided in an embodiment of the present application;

FIG9 is an example of encoding and decoding provided in an embodiment of the present application;

FIG10 is a comparison diagram of beneficial effects provided by an embodiment of the present application;

FIG11 is another example of encoding and decoding provided in an embodiment of the present application;

FIG12 is a comparison diagram of another beneficial effect provided by an embodiment of the present application;

FIG13 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application;

FIG14 is a schematic diagram of the structure of another communication device provided in an embodiment of the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Among them, the terms "system" and "network" in the embodiments of the present application can be used interchangeably. Unless otherwise specified, "/" indicates that the objects associated before and after are in an "or" relationship. For example, A/B can represent A or B; "and/or" in this application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. These three situations, where A and B can be singular or plural. And, in the description of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be one or more. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between network elements and identical or similar items with substantially the same functions. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

References to "one embodiment" or "some embodiments" etc. described in the embodiments of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

The following specific implementation methods further describe in detail the objectives, technical solutions and beneficial effects of the present application. It should be understood that the following are only specific implementation methods of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the scope of protection of the present application.

In the various embodiments of the present application, unless otherwise specified or provided for in any logical conflict, the terms and/or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

It should be understood that the technical solutions of the embodiments of the present application can be applied to the long term evolution (LTE) architecture, the fifth generation mobile communication technology (5G), wireless local area network (WLAN) system, vehicle to everything (V2X) communication system, LTE-vehicle (LTE-V), vehicle to vehicle (V2V), vehicle networking, machine type communications (MTC), etc. The technical solutions of the embodiments of the present application can also be applied to other future communication systems, such as 6G communication systems, etc. In future communication systems, the functions may remain the same, but the names may change.

The following describes the infrastructure of the communication system provided by the embodiment of the present application. The communication system provided by the present application may include one or more network devices, and one or more terminal devices. The following is an exemplary explanation of the system architecture shown in Figure 1. As shown in Figure 1, the communication system includes a network device 10 and one or more terminal devices (such as the terminal device 20 in Figure 1) that communicate with the network device 10.

It should be noted that the number of network devices and terminal devices in Figure 1 is only for illustration and should not be regarded as a specific limitation of the present application. The following is a detailed description of each device involved in the system architecture.

1. Terminal equipment

Terminal equipment is an entity on the user side that is used to receive signals, or send signals, or both receive and send signals. Terminal equipment is used to provide one or more of voice services and data connectivity services to users. Terminal equipment can be a device that includes wireless transceiver functions and can cooperate with network equipment to provide communication services to users. Specifically, terminal equipment can refer to user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, terminal, wireless communication equipment, user agent, user device or road side unit (RSU). The terminal device can also be a drone, an Internet of Things (IoT) device, a station (ST) in a wireless local area network (WLAN), a cellular phone, a smart phone, a cordless phone, a wireless data card, a tablet computer, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a laptop computer, a machine type communication (MTC) device, or a wireless communication device. ication, MTC) terminal, handheld device with wireless communication function, computing device or other processing device connected to wireless modem, vehicle-mounted device, wearable device (also called wearable smart device), virtual reality (VR) terminal, augmented reality (AR) terminal, wireless terminal in remote medical, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. The terminal device can also be a terminal in 5G system or a terminal in next generation communication system, which is not limited in the embodiments of the present application.

The embodiments of the present application do not limit the device form of the terminal device. The device for realizing the function of the terminal device can be the terminal device; it can also be a device that can support the terminal device to realize the function, such as a chip system. The device can be installed in the terminal device or used in combination with the terminal device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

2. Network equipment

A network device is an entity on the network side that is used to send signals, receive signals, or both send and receive signals. A network device can be a device deployed in a radio access network (RAN) to provide wireless communication functions for terminal devices.

In a possible scenario, the network equipment may be equipment with base station functions, such as evolved NodeB (eNodeB), transmission and receiving point (TRP), transmission point (TP), next generation NodeB (gNB), next generation base station in 6G mobile communication system, integrated access and backhaul (IAB) node, non-ground network equipment in NTN, i.e. equipment that can be deployed on high altitude platforms or satellites, etc. The network equipment may be a transmission reception point (TRP), a base station, or various forms of control nodes. For example, a network controller, a wireless controller, etc. Specifically, the network equipment may be various forms of macro base stations, micro base stations (also called small stations) in heterogeneous network (HetNet) scenarios, relay stations, access points (AP), radio network controllers (RNC), node B (NB), base station controllers (BSC), base transceiver stations (BTS), home base stations (e.g., home evolved node B, or home node B, HNB), baseband units (BBU) and remote radio units (RRU) in distributed base station scenarios, transmission points (TRP), transmitting points (TP), mobile switching centers, etc., and may also be antenna panels of base stations. The control node may connect to multiple base stations and configure resources for multiple terminals covered by multiple base stations. In systems using different wireless access technologies, the names of devices with base station functions may be different. For example, it can be a gNB in 5G, or a network-side device in a network after 5G, or a network device in a future public land mobile network (PLMN) network, or a device that performs base station functions in device-to-device (D2D) communication, machine-to-machine (M2M) communication, or vehicle networking communication, etc. This application does not limit the specific name of the network device. The network device can also be a baseband pool (BBU pool) and RRU under an open access network (open RAN, O-RAN or ORAN), a cloud radio access network (cloud radio access network, CRAN), etc.

All or part of the functions of the network device in this application can also be implemented by software functions running on hardware, or by virtualization functions instantiated on a platform (such as a cloud platform). The network device in this application can also be a logical node, logical module or software that can implement all or part of the network device functions.

In another possible scenario, multiple network devices collaborate to assist the terminal device in achieving wireless access, and different network devices respectively implement part of the functions of the base station. For example, the network device may include a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU may be set separately, or may be included in the same network element, such as a baseband unit (BBU). The RU may be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). It is understood that the network device may be a CU node, a DU node, or a device including a CU node and a DU node. In addition, the CU may be divided into a network device in the access network RAN, or the CU may be divided into a network device in the core network CN, without limitation here.

In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, CU may also be called O-CU (open CU), DU may also be called O-DU, CU-CP may also be called O-CU-CP, CU-UP may also be called O-CU-UP, and RU may also be called O-RU. For the convenience of description, CU, CU-CP, CU-UP, DU and RU are described as examples in this application. Any unit of CU (or CU-CP, CU-UP), DU and RU in this application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

In the embodiments of the present application, the form of the network device is not limited. The device for realizing the function of the network device can be the network device; or it can be a device that can support the network device to realize the function, such as a chip system. The device can be installed in the network device or used in combination with the network device.

In order to facilitate the understanding of the content of this solution, some of the terms involved in the embodiments of the present application are explained below to facilitate understanding by those skilled in the art. This part is only for ease of understanding and cannot be regarded as a specific limitation of the present application.

1. Communication process between communication devices

For example, in FIG2 , the first device may perform source coding, channel coding, rate matching, and modulation on the bit stream generated by the source, and then transmit the information to the second device through the channel. Correspondingly, after receiving the information, the second device sequentially performs demodulation, rate matching, channel decoding, and source decoding on the information to obtain the destination, that is, restore the bit stream generated by the source. The channel may be an additive white Gaussian noise (AWGN) channel. Among them, at least one of the first device and the second device may be a terminal device or a network device in FIG1 .

2. Polar Code

Polar code is a known channel coding scheme that can be strictly proven to "reach" the channel capacity. It has the characteristics of high performance and low complexity. It has been identified by 3GPP as the control channel coding scheme for 5G control channel enhanced mobile broadband (eMBB) scenarios (uplink/downlink).

Polar code is a linear block code, and its encoding process can be x _N = u _N G _N , where u _N = {u ₀ , u ₁ , ..., u _N-1 } is a binary row vector of length N, is the encoding matrix, The Kronecker power represented by For example, n = 2, and the polar code encoding matrix with a code length of N = 4 can be obtained.

In the encoding process of polar code, u _N can be divided into two parts. One part of the bits carries information, which is called information bits. The index set of these bits can be recorded as A. The other part of the bits is a fixed value, called fixed bits, which are usually set to 0. When the fixed bits are set to 0, the encoding process of polar code can be simplified to x _A = u _A GN(A), where u _A is the information bit set in u _N , and its length can be recorded as K; GN(A) is a submatrix in GN composed of rows corresponding to the indices in set A, and GN(A) is a K×N matrix. Among them, the selection of set A will affect the performance of polar code.

FIG3 shows a schematic diagram of polar code encoding. As shown in FIG3 , u ₈ ={u ₀ ,u ₀ ,...,u ₇ } is a binary row vector of length 8, which may include fixed bits and information bits. The fixed bits and information bits may be adjacent or interlaced. For example, u ₀ , u ₁ , u ₂ and u ₄ are fixed bits and may all be 0. u ₃ , u ₅ , u ₆ and u ₇ are information bits. The circle plus symbol shown in FIG3 represents an exclusive-or operation. u ₀ , u ₁ , u ₂ and u ₄ are four bits with the lowest reliability, and u ₃ , u ₅ , u ₆ and u ₇ are four bits with the highest reliability. Among them, the intermediate result in the encoding process shown in FIG3 is only an example, and the embodiment of the present application does not limit this. In the present application, polar code encoding and polar code outer code encoding can replace each other.

In the present application, the polar code may include at least one of the following: Arikan Polar code, parity check polar code (PC-Polar) code, cyclic redundancy check polar code (CA-Polar) code, or parity check-cyclic redundancy check polar code-polar code (PC-CA-Polar) code. Arikan Polar refers to the original polar code, which is not concatenated with other codes, including information bits and/or frozen bits. PC-Polar is a polar code concatenated with a PC code. CA-Polar is a polar code concatenated with a CRC code. PC-CA-Polar code is a polar code concatenated with both a PC code and a CRC code.

Among them, CRC code, as a commonly used error detection code, is the most common outer code cascaded with polar code. In the present application, the length of the CRC code can be R bits, and R can be a positive integer, such as 4, 6, 8, 11, 16 or 24, and the present application does not limit its length. It should be understood that the CRC code can be obtained based on a generating polynomial, and the power of the generating polynomial of the R-bit CRC code can be R. The polynomials used by CRC codes of different lengths are different. For example, taking the length of the CRC code as 24 bits, the polynomial used can be CRC24. The present application does not limit the specific polynomial used by the CRC code.

There are many possible implementations of polar code decoding, such as successive cancellation decoding (SC) decoding, successive cancellation list decoding (SCL), successive cancellation stack (SCS) decoding, CRC-aided successive cancellation list (CA-SCL) decoding, belief propagation (BP) decoding and soft cancellation (SCAN) decoding. The present application does not limit the decoding method of polar code. For example, the polar code is Arikan Polar code, and SC decoding, SCL decoding, SCS decoding, BP decoding or SCAN decoding can be used. The polar code is PC-Polar code, CA-Polar code or PC-CA-Polar code, and CA-SCL decoding can be used.

3. LDPC Code

LDPC code is a type of linear block code with a sparse check matrix, that is, the density of non-zero elements in the check matrix (also called parity check matrix or LDPC matrix) is relatively low, that is, the number of zero elements in the check matrix is far greater than the number of non-zero elements. LDPC code can be represented by a check matrix or a Tanner graph, and this application does not limit the specific form of expression of LDPC code. For ease of understanding, the following is an introduction using the representation of LDPC code by a check matrix as an example, which should not be regarded as a limitation of this application.

The check matrix of the LDPC code can be seen in Figure 4. In Figure 4, the check matrix includes a high rate region, an incremental redundancy region, and an extended check region. The area selected by the dotted line represents the code rate. The main characteristic of the check matrix is nestedness, that is, the low code rate region can contain the high code rate region, and the high code rate region can be used as a submatrix of the low code rate region. In one possible implementation, different matrix regions can be selected according to the code rate as the check matrix. For example, from the upper left area to the lower right area of the matrix, such as the 0th row to the _M0th row and the 0th column to the _N0th column. _M0 and _N0 can be integers greater than 0.

Optionally, the check matrix of the LDPC code can be obtained by a basegraph (BG) and a shifting value. The basegraph can be determined based on the length of the information bit and the code rate. The code rate refers to the proportion of bits before encoding (i.e., information bits) in the bits after encoding. Among them, the basegraph can be divided into BG1 and BG2. Exemplarily, the code length of the information bit applicable to BG1 is 308 bits to 8448 bits, and the code rate is 0.25 to 0.95. The code length of the information bit applicable to BG2 is 40 bits to 3840 bits, and the code rate is 0.20 to 0.95.

It should be noted that in this application, the row and column numbers of the base graph can be numbered starting from 0, and the row and column numbers of the matrix can be numbered starting from 0. This application does not limit the specific value from which the row and column numbers start numbering.

Generally, the base graph may include m×n matrix elements (entries), which may be represented by a matrix with m rows and n columns. The values of the matrix elements may be 0 or 1, where the elements with a value of 0 may be called zero elements, indicating that the elements may be replaced by a Z*Z all-zero matrix (zeromatrix). The elements with a value of 1 may be called non-zero elements, indicating that the elements may be replaced by a Z*Z circulant permutation matrix (circulantpermutationmatrix). In other words, each matrix element represents an all-zero matrix or a circulant permutation matrix.

Wherein, Z can be a positive integer, which can be called a lifting factor, a lifting size, or a lifting factor, etc., and can be determined, for example, according to the length of the information bit. For example, Z can be a _j ∈ {2, 3, 5, 7, 9, 11, 13, 15}, max(k _j ) ∈ {7, 7, 6, 5, 5, 5, 4, 4}. j is an integer greater than or equal to 0. For example, Z can be k _j ∈{0,1,2,3,4,5,6,7}. For example, Z can be k _j ∈{0,1,2,3,4,5,6,7}. For example, Z can be k _j ∈{0,1,2,3,4,5,6}. For example, Z can be k _j ∈{0,1,2,3,4,5}. For example, Z can be k _j ∈{0,1,2,3,4,5}. The rest are similar and are not listed here one by one.

Optionally, Z is associated with the translation value. For example, a set of multiple Zs (which may be referred to as a lifting factor set (set of lifting sizes), which is described below using the lifting factor set as an example) may correspond to the translation value, such as the row number of the lifting factor set corresponding to the column number of the translation value. Optionally, the column number of the translation value may be described as a set index (set index). Specifically, in Table 1, the lifting factor set may correspond to a set index. For example, {2, 4, 8, 16, 32, 64, 128, 256} corresponds to 0, and the rest are similar and will not be described here.

Table 1 LDPC lifting factor set (setofLDPCliftingsizeZ)

The following describes the process of replacing the elements in the base graph with the Z*Z matrix in conjunction with specific examples. Specifically: Assume that the value of the element in the i-th row and j-th column of the base graph is 1, and its translation value is Pi _,j , where Pi _,j is an integer greater than or equal to 0. The element in the i-th row and j-th column of the base graph with a value of 1 can be replaced by the Z*Z circulant permutation matrix corresponding to _Pi ,j, which can be obtained by cyclically shifting the Z*Z unit matrix to the right Pi _,j times. It can be seen that by replacing each element with a value of 0 in the base graph with a Z*Z all-zero matrix, and replacing each element with a value of 1 with a Z*Z circulant permutation matrix corresponding to its translation value, the check matrix of the LDPC code can be obtained. The base graph can be used to indicate the position of the offset value, and the non-zero elements in the base graph correspond to the offset value. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z). For example, assuming Z = 4, each zero element is replaced by a 4*4 matrix of all zeros, assuming P _2,3 = 2, then the non-zero element in the 2nd row and 3rd column is replaced by a 4*4 circulant permutation matrix, which is obtained by 2 right circulant shifts of the 4*4 identity matrix. It should be noted that this is only an example and is not intended to be limiting.

Among them, there are many possible implementation methods of LDPC codes, such as minimum sum algorithm (Min-Sum, MS) decoding or BP decoding. This application does not limit the decoding method of LDPC codes. Optionally, MS decoding can be divided into offset minimum sum algorithm (Offset-MS) decoding and normalized minimum sum algorithm (Normalized-MS) decoding. Offset minimum sum algorithm decoding can be, for example, layered offset minimum sum algorithm (layered offset min-sum, LOMS) decoding.

The following is a detailed description of the embodiment of the present application in conjunction with Figure 5. It should be noted that the execution subject of the method provided in the present application may be the first device and the second device in Figure 2. The following is an introduction taking the first device as a terminal device and the second device as a network device as an example, which should not be regarded as a limitation of the present application. Among them, the processing performed by the single execution subject (terminal device or network device) shown in the embodiment of the present application can also be divided into execution by multiple execution subjects, and these execution subjects can be logically and/or physically separated. For example, the processing performed by the network device can be divided into execution by at least one of CU, DU and RU. In addition, the various embodiments of the present application are only illustrated by taking the execution of all the steps included therein as an example, and should not be regarded as a specific limitation of the present application. That is to say, the steps included in the embodiments of the present application (such as any one of the embodiments in Figures 5 to 8) can be partially or fully executed in the absence of logical conflicts.

As shown in FIG5 , an encoding method is provided in an embodiment of the present application, and the method includes but is not limited to the following steps:

501. A terminal device performs polarization code encoding on a first bit sequence to obtain a second bit sequence.

The first bit sequence may include at least one of the following: an information bit sequence, a frozen bit sequence, or a check bit sequence. The information bit sequence is a sequence composed of information bits, and the frozen bit sequence is a sequence composed of frozen bits. The check bit sequence may include a PC code and/or a CRC code. The first bit sequence is divided into two cases for introduction below, which should not be regarded as a limitation of the present application. Specifically:

In the first case, the first bit sequence includes an information bit sequence.

In the second case, the first bit sequence includes an information bit sequence and a check bit sequence.

The second bit sequence may be a polar code. For example, for the first case, the second bit sequence may be an Arikan Polar code. For the second case, the second bit sequence may be a PC-Polar code, a CA-Polar code, or a PC-CA-Polar code.

In a possible implementation, the length Npolar of the second bit sequence may be determined according to the length T of the first bit sequence and the code rate R corresponding to the second bit sequence. For example, the length of the second bit sequence satisfies the following conditions:

Among them, the application This is just an example of rounding up, which should not be considered as a limitation of the present application. For example, rounding up in the present application can be replaced by rounding down.

R may be a code rate corresponding to the second bit sequence. R may be a predefined or preconfigured value greater than 0, or R may be indicated by a network device to a terminal device. For example, R may be 0.9517, or R may be (Nm×0.9517)/Nm, such as 975/1024. Nm is the maximum length supported by the polar code encoding. Optionally, Nm may be an integer greater than 0, such as Nm is 1024.

In a possible implementation, the information bit sequence in the first bit sequence may be a partial or complete bit sequence of the initial bit sequence. The initial bit sequence in the present application may be referred to as a mother code. The initial bit sequence may include an information bit sequence. Optionally, the initial bit sequence may also include a frozen bit sequence or may not include a frozen bit sequence. The following takes the initial bit sequence not including the frozen bit sequence as an example to introduce the relationship between the first bit sequence and the initial bit sequence, which should not be regarded as a limitation of the present application, specifically:

1. The information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. For example, when the length of the initial bit sequence is less than the maximum length Kcb supported by LDPC coding, the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. In other words, the information bit sequence in the first bit sequence is the entire bit sequence of the initial bit sequence, that is, the first bit sequence of the unconcatenated check bit sequence is the same as the initial bit sequence.

Kcb can be determined based on a base graph. For example, if the base graph is BG1, Kcb is 8448. If the base graph is BG2, Kcb is 3840. The base graph is determined based on the length and code rate of the information bits in the initial bit sequence.

2. The terminal device may segment the initial bit sequence based on the first segment length to obtain L bit sequences, where L is an integer greater than 1. For example, when the length of the initial bit sequence is greater than Kcb, the terminal device may segment the initial bit sequence based on the first segment length to obtain L bit sequences. That is, the information bit sequence in the first bit sequence is a partial bit sequence of the initial bit sequence, that is, the first bit sequence of the unconcatenated check bit sequence is a partial bit sequence of the initial bit sequence.

Among them, the L bit sequences may include a fourth bit sequence. For example, for the first case above, the fourth bit sequence may be used as the first bit sequence. For the second case above, the terminal device may perform check code encoding on the fourth bit sequence to obtain a first bit sequence. The check code encoding may be PC encoding and/or CRC encoding. For example, taking CRC encoding on the fourth bit sequence as an example, the terminal device may cascade a 24-bit CRC code at the end of the fourth bit sequence to obtain the first bit sequence.

It should be pointed out that the length of the initial bit sequence equal to Kcb can be used as a condition for "the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence", or as a condition for "the terminal device segments the initial bit sequence based on the first segment length to obtain L bit sequences", which is not limited here.

In a possible implementation, the first segment length may be determined based on the first value R and Kcb. For example, the first segment length satisfies the following conditions: For example, assuming R is 0.9517, Kcb is 3840, K1 can be

In a possible implementation, the lengths of the L bit sequences may be partially the same, completely the same, or completely different. It should be understood that the process of encoding each bit sequence in the L bit sequences is similar, for example, refer to FIG. 5 , which is not described in detail here.

In a possible implementation, the length of the information bit sequence in the first bit sequence may be greater than, equal to, or less than Nm. For example, when the length of the information bit sequence in the first bit sequence is greater than or equal to Nm, the terminal device may further segment the first bit sequence based on the second segment length to obtain P bit sequences, where P is an integer greater than 1. In this case, step 501 may include: the terminal device performs polarization code encoding on the P bit sequences respectively to cascade into a second bit sequence. The present application does not limit the process of cascading polarization coded bit sequences.

Optionally, the second segment length may be determined based on Nm and R, for example, by satisfying the following conditions: For example, assuming R is 0.9517 and Nm is 1024, K2 can be

In a possible implementation, the lengths of the P bit sequences may be partially the same, completely the same, or completely different. For example, the first bit sequence includes 2924 bits, the second segment length is 975, and the terminal device may divide the first bit sequence into three bit sequences based on the second segment length, with lengths of 975, 975, and 974, respectively. That is, the lengths of two of the three bit sequences are the same.

502. The terminal device performs LDPC encoding on the second bit sequence to obtain a third bit sequence.

The third bit sequence is an LDPC code, which can also be called an LDPC codeword sequence.

Optionally, after step 502, step 503 may be further included.

503. The terminal device sends a symbol sequence based on the third bit sequence.

Correspondingly, the network device receives the symbol sequence. For example, the network device receives the symbol sequence from the terminal device. Correspondingly, the terminal device sends the symbol sequence to the network device based on the third bit sequence.

Optionally, step 503 may include: the terminal device modulates the third bit sequence based on the modulation mode to obtain a symbol sequence. The modulation mode in the present application may be quadrature phase shift keying (QPSK), binary phase shift keying (BPSK), 16-quadrature amplitude modulation (QAM), 64-QAM, 256-QAM, 1024-QAM or 4096-QAM, etc. This application does not limit this.

It can be seen that in the above embodiment, the terminal device can first perform polar code encoding on the first bit sequence to obtain a second bit sequence, and then perform LDPC encoding on the second bit sequence to obtain a third bit sequence, that is, an LDPC code. In this way, the error floor of LDPC decoding can be reduced without losing the code rate of the LDPC code, thereby improving the error correction performance of the LDPC code.

As shown in FIG6 , a decoding method is provided in an embodiment of the present application. It should be noted that the embodiment shown in FIG5 or the embodiment shown in FIG6 can be performed separately, or the embodiment shown in FIG5 and the embodiment shown in FIG6 can be combined, for example, the embodiment shown in FIG5 is performed before step 601 of FIG6 . The embodiment shown in FIG6 is described in detail below. Specifically, the method includes but is not limited to the following steps:

601. A network device obtains a symbol sequence.

For example, a network device receives a sequence of symbols from a terminal device.

602. The network device determines a third bit sequence based on the symbol sequence.

Optionally, the network device may demodulate the symbol sequence based on the modulation mode to obtain a third bit sequence, wherein the third bit sequence is an LDPC code, which may also be referred to as an LDPC codeword sequence.

603. The network device performs LDPC decoding on the third bit sequence to obtain a second bit sequence.

The manner in which the network device performs LDPC decoding on the third bit sequence can refer to the above related description, which is not described in detail here. The second bit sequence is similar to the second bit sequence in step 501 of FIG. 5, which is not described in detail here.

604. The network device performs polarization code decoding on the second bit sequence to obtain a first bit sequence.

The first bit sequence is similar to the first bit sequence in step 501 of FIG5 , and is not described in detail here. The manner in which the network device performs polar code decoding on the second bit sequence can refer to the above related description, and is not described in detail here.

It can be seen that in the above embodiment, the network device can first determine the third bit sequence based on the symbol sequence, so that the third bit sequence can be LDPC decoded to obtain the second bit sequence, and then the second bit sequence can be polar code decoded to obtain the first bit sequence. This can be used to reduce the error floor of LDPC decoding, and then improve the error correction performance of LDPC code.

As shown in FIG. 7 , another encoding method provided by the present application includes but is not limited to the following steps:

701. A terminal device determines a second bit sequence and a third bit sequence based on a first bit sequence, where the third bit sequence includes a bit sequence in a base graph corresponding to the first bit sequence and having a weight higher than a first threshold.

The first bit sequence may include at least one of the following: an information bit sequence, a frozen bit sequence, or a check bit sequence. The information bit sequence is a sequence composed of information bits, and the frozen bit sequence is a sequence composed of frozen bits. The check bit sequence may include a PC code and/or a CRC code. The first bit sequence is divided into two cases for introduction below, which should not be regarded as a limitation of the present application. Specifically:

The first type, the first bit sequence includes an information bit sequence.

The second type is that the first bit sequence includes an information bit sequence and a check bit sequence. In this case, the terminal device can perform check code encoding on the seventh bit sequence to obtain the first bit sequence. The check code encoding can be PC encoding and/or CRC encoding. For example, taking CRC encoding on the seventh bit sequence as an example, the terminal device can cascade a 24-bit CRC code at the end of the seventh bit sequence to obtain the first bit sequence.

Optionally, step 701 may include: the terminal device determines a first numerical value based on the first number of columns in the base graph whose weights are higher than a first threshold, thereby determining a third bit sequence from the first bit sequence based on the first numerical value and a lifting factor corresponding to the first bit sequence, and further determining a second bit sequence based on the third bit sequence and the first bit sequence.

The terminal device determines the first value based on the number of first columns in the base graph whose weights are higher than the first threshold value. There are several implementation methods, specifically:

1. The first value is the first column number. The first column number is an integer greater than or equal to 1, such as 2 or 3. Generally, the weights of the first T columns in the base graph are higher than the first threshold, and T is the first column number. Exemplarily, assuming that the first column number is 2, that is, the weights of the 0th to 1st columns in the base graph are higher than the first threshold. Or, assuming that the first column number is 3, that is, the weights of the 0th to 2nd columns in the base graph are higher than the first threshold. The first threshold may be a predefined or preconfigured value greater than 0.

2. The terminal device determines the second column number with the highest reliability (i.e., the lowest bit error) from the base graph except for the other columns whose weights are higher than the first threshold, and determines the first value based on the first column number and the second column number. For example, the terminal device sorts the reliabilities of the other columns in the order of reliability from high to low or from low to high, and counts the number of columns with the highest reliability to obtain the second column number. Among them, reliability from high to low can be understood as bit error rate from low to high. And vice versa.

In a possible implementation, the first value may be the sum of the first column number and the second column number. Exemplarily, assuming that the base graph includes 10 columns, the first column number is 2, that is, the weights of the 0th column to the 1st column in the base graph are higher than the first threshold. The terminal device may sort the reliabilities of the 2nd column to the 9th column in order of reliability from high to low or from low to high, so as to count the number of columns with the highest reliability and obtain the second column number. For example, the second column number may be an integer greater than or equal to 1.

3. The terminal device determines the third number of columns whose reliability is higher than the second threshold from the base graph except for the other columns whose weight is higher than the first threshold, and determines the first value based on the first number of columns and the third number of columns. For example, the first value is the sum of the first number of columns and the third number of columns. The third threshold may be a predefined or preconfigured value greater than 0.

Among them, the weight in the base graph can be understood as: the weight of the column in the base graph. Here, only the column weight is introduced as an example, which should not be regarded as a limitation of the present application. It should be pointed out that in the present application, the weight of the base graph is determined by the number of non-zero elements. For example, the weight of a row refers to the number of non-zero elements included in a row, and the weight of a column refers to the number of non-zero elements included in a column. The weight of a row and the weight of a column can be referred to as row weight and column weight, respectively.

In a possible implementation, the base graph may be determined based on the length and code rate of the information bits in the initial bit sequence. The lifting factor corresponding to the first bit sequence may be determined based on the length of the information bits in the initial bit sequence. Among them, the information bit sequence in the first bit sequence may be a partial or complete bit sequence of the initial bit sequence. The initial bit sequence may include an information bit sequence. Optionally, the initial bit sequence may also include a frozen bit sequence or may not include a frozen bit sequence. The following takes the initial bit sequence not including a frozen bit sequence as an example to introduce the relationship between the first bit sequence and the initial bit sequence, which should not be regarded as a limitation of the present application, specifically:

1. The information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. For example, when the length of the initial bit sequence is less than the maximum length Kcb supported by LDPC coding, the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. In other words, the information bit sequence in the first bit sequence is the entire bit sequence of the initial bit sequence, that is, the first bit sequence of the unconcatenated check bit sequence is the same as the initial bit sequence.

Kcb can be determined based on a base graph. For example, if the base graph is BG1, Kcb is 8448. If the base graph is BG2, Kcb is 3840. The base graph is determined based on the length and code rate of the information bits in the initial bit sequence.

2. The terminal device may segment the initial bit sequence based on the first segment length to obtain X bit sequences, where X is an integer greater than 1. For example, when the length of the initial bit sequence is greater than Kcb, the terminal device may segment the initial bit sequence based on the first segment length to obtain X bit sequences. Among them, the X bit sequences may include the first bit sequence or the seventh bit sequence. For example, for the first case above, the X bit sequences include the first bit sequence. That is, the information bit sequence in the first bit sequence is a partial bit sequence of the initial bit sequence. For the second case above, the X bit sequences include the seventh bit sequence. That is, the seventh bit sequence is a partial bit sequence of the initial bit sequence.

It should be pointed out that the length of the initial bit sequence being equal to Kcb can be used as a condition for "the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence", or as a condition for "the terminal device segments the initial bit sequence based on the first segment length to obtain X bit sequences", which is not limited here.

Optionally, the first segment length may be determined based on the first value and the lifting factor. For example, the first segment length may be determined based on the first value, the lifting factor, and the second value. The second value is determined based on the total number of columns of the base graph and the first value, such as the second value is the difference between the total number of columns of the base graph and the first value.

Optionally, the first segment length can also be determined based on a third value. The third value is the code rate corresponding to the second bit sequence. The third value may be a predefined or preconfigured value greater than 0, or the third value may be indicated by the network device to the terminal device. For example, the third value may be 0.9517, or the third value may be (Nm×0.9517)/Nm, such as 975/1024. Nm is the maximum length supported by the polar code encoding. Nm may be an integer greater than 0, such as Nm is 1024.

In a possible implementation, the first segment length may satisfy the following conditions: Wherein, a is the first value, b is the second value, R is the third value, and Z is the boost factor. For example, assuming that Z is 384, a is 2, b is 8, and R is 0.9517, Among them, a×Z＝M1, Therefore, K1=M1+M2.

The terminal device determines the third bit sequence from the first bit sequence based on the first value and the lifting factor corresponding to the first bit sequence, for example, may include: the terminal device selects the first Q bits from the first bit sequence as the third bit sequence based on the product Q of the first value and the lifting factor. For example, if the first value is 2 and the lifting factor is 104, Q may be 208.

The terminal device determines the second bit sequence based on the third bit sequence and the first bit sequence, which can be implemented in the following ways, specifically:

1. The second bit sequence is other bit sequences in the first bit sequence except the third bit sequence. For example, when the length of the other bit sequence is less than Nm, the second bit sequence is the other bit sequence.

2. The terminal device segments the other bit sequences based on the second segment length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence. For example, when the length of the other bit sequences is greater than Nm, the terminal device segments the other bit sequences based on the second segment length to obtain Y bit sequences. Where Y is an integer greater than 1. The second segment length can be determined based on Nm and the third value. For example, the second segment length satisfies the following conditions:

It should be pointed out that the length of other bit sequences equal to Nm can be used as a condition for "the second bit sequence is other bit sequences", or as a condition for "the terminal device segments other bit sequences based on the second segment length to obtain Y bit sequences", which is not limited here.

702. The terminal device performs polarization code encoding on the second bit sequence to obtain a fourth bit sequence.

For example, for the first case above, step 702 can be understood as: the terminal device performs check code encoding on the second bit sequence to obtain a sixth bit sequence, and then performs polar code encoding on the sixth bit sequence to obtain a fourth bit sequence. The fourth bit sequence can be a polar code, such as a PC-Polar code, a CA-Polar code, or a PC-CA-Polar code.

In a possible implementation manner, the length Npolar of the fourth bit sequence may be determined according to the lengths T and R of the second bit sequence.

For example, the length of the fourth bit sequence satisfies the following conditions:

703. The terminal device performs LDPC encoding on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence.

The fifth bit sequence is an LDPC code. It can also be called an LDPC codeword sequence. In a possible implementation, step 703 may include: the terminal device performs LDPC encoding on a bit sequence obtained by concatenating the third bit sequence with the fourth bit sequence to obtain a fifth bit sequence. For example, the fourth bit sequence is concatenated at the end of the third bit sequence.

Optionally, after step 703 , step 704 may be further included.

704. The terminal device sends a symbol sequence based on the fifth bit sequence.

Correspondingly, the network device receives the symbol sequence. For example, the network device receives the symbol sequence from the terminal device. Correspondingly, the terminal device sends the symbol sequence to the network device based on the fifth bit sequence.

Optionally, step 704 may include: the terminal device modulates the fifth bit sequence based on a modulation method to obtain a symbol sequence.

It can be seen that in the above embodiment, the terminal device can determine the second bit sequence and the third bit sequence based on the first bit sequence, and the third bit sequence includes a bit sequence in the base map corresponding to the first bit sequence whose weight is higher than the first threshold. That is to say, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the terminal device can perform polarization code encoding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with a lower weight by using polarization code encoding to improve the error correction performance. For the third bit sequence with a higher weight, LDPC encoding can be performed together with the result of polarization code encoding (that is, the fourth bit sequence obtained by performing polarization code encoding on the second bit sequence). In this way, the error floor of LDPC decoding can be reduced, thereby improving the error correction performance of LDPC code. At the same time, the LDPC coding load caused by Polar outer code encoding can also be reduced, thereby reducing the code rate of LDPC code and improving waterfall performance.

As shown in FIG8, another decoding method is provided in an embodiment of the present application. It should be noted that the embodiment shown in FIG7 or the embodiment shown in FIG8 can be performed separately, or the embodiment shown in FIG7 and the embodiment shown in FIG8 can be combined, for example, the embodiment shown in FIG7 is performed before step 801 of FIG8. The embodiment shown in FIG8 is described in detail below. Specifically, the method includes but is not limited to the following steps:

801. A network device obtains a symbol sequence.

For example, a network device receives a sequence of symbols from a terminal device.

802. The network device determines a fifth bit sequence based on the symbol sequence.

Optionally, the network device may demodulate the symbol sequence based on the modulation mode to obtain a fifth bit sequence, wherein the fifth bit sequence is an LDPC code, which may also be referred to as an LDPC codeword sequence.

803. The network device performs LDPC decoding on the fifth bit sequence to obtain a third bit sequence and a fourth bit sequence.

For example, the network device performs LDPC decoding on the fifth bit sequence to obtain a bit sequence that is a concatenation of the third bit sequence and the fourth bit sequence. The manner in which the network device performs LDPC decoding on the fifth bit sequence can refer to the above-mentioned related description, which is not described in detail here. The third bit sequence and the fourth bit sequence are similar to the third bit sequence and the fourth bit sequence in step 701 of FIG. 7, respectively, and are not described in detail here. The length of the fourth bit sequence satisfies the following conditions: For example, the last Npolar bits in the "bit sequence after the third bit sequence and the fourth bit sequence are cascaded" can be used as the fourth bit sequence, and the remaining bits can be used as the third bit sequence. That is, the difference between the length of the bit sequence after the third bit sequence and the fourth bit sequence are cascaded and Npolar is the length of the third bit sequence.

804. The network device performs polarization code decoding on the fourth bit sequence to obtain a second bit sequence.

The second bit sequence is similar to the second bit sequence in step 701 of FIG7 , and is not described in detail here. The manner in which the network device performs polar code decoding on the fourth bit sequence can refer to the above related description, and is not described in detail here.

805. The network device determines a first bit sequence based on the third bit sequence and the second bit sequence.

For example, the first bit sequence includes a third bit sequence and a second bit sequence. For example, a bit sequence in which the second bit sequence is cascaded at the end of the third bit sequence is the first bit sequence. The first bit sequence is similar to the first bit sequence in step 701 of FIG. 7 and is not described in detail here. Optionally, in the case where the first bit sequence includes a check bit sequence, the network device may further check the first bit sequence. For example, PC check and/or CRC check, etc.

It can be seen that in the above embodiment, the network device can first determine the fifth bit sequence based on the symbol sequence, and then perform LDPC decoding on the fifth bit sequence to obtain the third bit sequence and the fourth bit sequence, so that the fourth bit sequence can be polarized and decoded to obtain the second bit sequence. In this way, the first bit sequence can be determined based on the third bit sequence and the second bit sequence. Because the network device performs polarization code decoding on part of the bit sequence (such as the fourth bit sequence) in the LDPC decoding result, the decoding delay is reduced and the decoding efficiency is improved. At the same time, it can also be used to reduce the error floor of LDPC decoding, thereby improving the error correction performance of the LDPC code.

The beneficial effects of the embodiments described in FIGS. 5 to 8 are described in detail below with reference to specific examples, specifically:

1. Examples of the encoding method shown in FIG. 5 and the decoding method shown in FIG. 6

Assuming that the length of the information bit U is 1000 bits, the process of combining the encoding method shown in FIG5 and the decoding method shown in FIG6 can refer to the Polar-LDPC encoding and decoding process of FIG9. For example, the terminal device sequentially performs CRC24 encoding, polar code encoding, LDPC encoding, and QPSK modulation on the information bit, and then sends the information to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device sequentially demodulates, LOMS decodes, and polar code decodes the information to obtain The information bit U is encoded by CRC24 and polar code in turn, which is equivalent to adding polar redundancy check bits to the CRC codeword. The length of the bit sequence after the information bit is encoded by CRC24 is 1024 bits, that is, K_Ca-polar = 1024 bits in Figure 9. The length of the bit sequence after the 1024 bits are encoded by polar code is N_polar N_polar=K_ldpc. Further, after 1076 bits are LDPC-coded, the length of the bit sequence is N_ldpc, such as 3000 bits.

The LDPC encoding and decoding process of Figure 9 is as follows: the terminal device sequentially performs CRC24 encoding, LDPC encoding, and QPSK modulation on the information bits, and then sends the information to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device sequentially demodulates and LOMS decodes the information to obtain In addition, in FIG9 , the number of iterations of the LOMS decoding may be 15 or 25, the polar code decoding may be SC decoding or SCL decoding, and the path width L may be 8. The length is 1000 bits.

The following is based on the example shown in Figure 9 and combined with Figure 10 to illustrate the beneficial effects of the encoding method shown in Figure 5 and the decoding method shown in Figure 6. Specifically, in Figure 10, the abscissa represents SNR, that is, Es/N0, and the ordinate represents BLER.

Among them, in 10-1 of Figure 10, the number of iterations of LOMS decoding is 15. The curve of Polar-LDPC represents the BLER performance corresponding to the Polar-LDPC encoding and decoding process in Figure 9. The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in Figure 9. It can be seen that when the BLER is less than or equal to 6× ^10-6 , the error correction performance corresponding to the Polar-LDPC encoding and decoding can still decrease exponentially with the increase of SNR, and there is no error flattening.

In 10-2 of FIG10, the number of iterations of LOMS decoding is 25. The curve of Polar-LDPC represents the BLER performance corresponding to the Polar-LDPC encoding and decoding process in FIG9. The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in FIG9. It can be seen that when the BLER is less than or equal to 6× ^10-6 , the error correction performance corresponding to the Polar-LDPC encoding and decoding can still decrease exponentially with the increase of SNR, and there is no error flattening.

2. Examples of the encoding method shown in FIG. 7 and the decoding method shown in FIG. 8

Assuming that the length of the information bit U is 1000 bits (bits), the process of combining the encoding method shown in FIG. 7 and the decoding method shown in FIG. 8 can refer to the Polar-LDPC encoding and decoding 1 or Polar-LDPC encoding and decoding 2 process of FIG. 11. For example, the terminal device determines the lifting factor Z based on the length of the information bit U. For example, if the length of the information bit is 1000 bits, and the length N_ldpc after LDPC encoding is 3000 bits, BG2 can be selected, the total number of columns is 10, and Z=104. Because the column weight of the first T columns of BG2 is large, the corresponding information bits are relatively reliable and not prone to errors, so there is no need for additional protection through polar code encoding. That is, the bits that cause LDPC to generate error flattening are mainly distributed in the positions corresponding to non-large column weights. For example, T is 2, the column weights of columns 0 to 1 of BG2 are large, and the bits corresponding to columns 2 to 9 (non-large column weights) are prone to errors. The number of bits with large column weights (K_B) is Z×2=208.

The Polar-LDPC encoding and decoding 1 process of Figure 11 is as follows: the terminal device performs CRC24 encoding and polarization code encoding on 792 bits in sequence. After CRC24 encoding of 792 bits, the length of the bit sequence K_S_CRC is 816 bits. After polarization code encoding of 816 bits, the length of the bit sequence N_polar is 858 bits. Furthermore, 208 bits and 858 bits are cascaded (their length K_ldpc is 1066 bits), LDPC encoding and QPSK modulation are performed in sequence, and the information is sent to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device demodulates and LOMS decodes the information in sequence to obtain the bits that need to be polarization code decoded, whose length is K_ldpc-K_B=858 bits. A large column of heavy bits with a length of 208 bits can also be obtained. In this way, we can get

The Polar-LDPC encoding and decoding 2 process of Figure 11 is as follows: the terminal device performs CRC24 encoding on the information bits to obtain a bit length K_CRC of 1024 bits. Among them, the length of the bit sequence K_polar that needs to be encoded with polarization code is 816 bits, and the length of the bit sequence K_B that does not need to be encoded with polarization code is 208 bits. Further, the 816 bits are polarization-coded to obtain a bit sequence length N_polar of 858 bits. In this way, 208 bits and 858 bits can be cascaded (whose length K_ldpc is 1066 bits), LDPC encoded and QPSK modulated in sequence, and the information is sent to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device demodulates and LOMS decodes the information in sequence to obtain bits that need to be decoded with polarization code, whose length is K_ldpc-K_B=858 bits. A large column of bits with a length of 208 bits can also be obtained. In this way, we can get In FIG. 11 , the number of iterations of the LOMS decoding may be 15 or 25, the polar code decoding may be SC decoding or SCL decoding, and the path width L may be 8. The length of is 1000 bits. In addition, the LDPC encoding and decoding process of FIG11 is similar to the LDPC encoding and decoding process of FIG9 , and will not be described in detail here.

The following is based on the example shown in Figure 11 and combined with Figure 12 to illustrate the beneficial effects of the encoding method shown in Figure 7 and the decoding method shown in Figure 8. Specifically, in Figure 12, the abscissa represents SNR, that is, Es/N0, and the ordinate represents BLER.

In 12-1 of Figure 12, the number of iterations of LOMS decoding is 15, and the largest columns are the first 2 columns of BG2. The curve of Polar-LDPC shown in Figure 9 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding process in Figure 9. The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in Figure 11. The curve of Polar-LDPC shown in Figure 11 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in Figure 11. It can be seen that when the BLER is less than or equal to 8× ^10-6 , the Polar-LDPC encoding and decoding shown in Figure 9, the Polar-LDPC encoding and decoding 1 in Figure 11 and the corresponding error correction performance can still decrease exponentially with the increase of SNR, and there is no error flattening.

In 12-2 of FIG12, the number of iterations of LOMS decoding is 25, and the largest columns are the first two columns of BG2. The curve of Polar-LDPC shown in FIG9 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding process in FIG9. The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in FIG11. The curve of Polar-LDPC shown in FIG11 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in FIG11. It can be seen that when the BLER is less than or equal to ^10-5 , the Polar-LDPC encoding and decoding shown in FIG9, the Polar-LDPC encoding and decoding 1 in FIG11 and the corresponding error correction performance can still decrease exponentially with the increase of SNR, and there is no error flattening.

In 12-3 of FIG12, the number of iterations of LOMS decoding is 15, and the largest columns are the first 3 columns of BG2. The LDPC curve represents the BLER performance corresponding to the LDPC encoding and decoding process in FIG11. The Polar-LDPC curve shown in FIG11 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in FIG11. It can be seen that when the BLER is less than or equal to ^10-5 , the Polar-LDPC encoding and decoding shown in FIG9, the Polar-LDPC encoding and decoding 1 in FIG11, and the corresponding error correction performance can still decrease exponentially with the increase of SNR, and there is no error flattening.

In 12-4 of FIG. 12, the number of iterations of LOMS decoding is 25, and the largest columns are the first 3 columns of BG2. The LDPC curve represents the BLER performance corresponding to the LDPC encoding and decoding process in FIG. 11. The Polar-LDPC curve shown in FIG. 11 represents the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in FIG. 11. It can be seen that when the BLER is less than or equal to ^10-5 , the Polar-LDPC encoding and decoding shown in FIG. 9, the Polar-LDPC encoding and decoding 1 in FIG. 11, and the corresponding error correction performance can still decrease exponentially with the increase of SNR, and there is no error flattening.

In addition, comparing 12-1 of FIG. 12 with 12-3 of FIG. 12, or comparing 12-2 of FIG. 12 with 12-4 of FIG. 12, in 12-3 of FIG. 12 and 12-4 of FIG. 12, polar code encoding is not performed on the information bits corresponding to the large column weights of the first three columns, which further reduces the redundant bits added by the polar code outer code, and the performance loss in the waterfall area is reduced from 0.2 dB to about 0.1xdB, thereby improving the performance in the waterfall area.

It is understandable that, in order to realize the above functions, the above-mentioned device includes hardware structures and/or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

The embodiment of the present application can divide the terminal device or network device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

Referring to Figure 13, Figure 13 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. The communication device 1300 can be applied to the method shown in any of the embodiments shown in Figures 5 to 8 above. As shown in Figure 13, the communication device 1300 includes: a processing module 1301 and a transceiver module 1302. The processing module 1301 can be one or more processors, and the transceiver module 1302 can be a transceiver or a communication interface. The communication device can be used to implement the terminal device or network device involved in any of the above method embodiments, or to implement the functions of the network element involved in any of the above method embodiments. The network element or network function can be a network element in a hardware device, a software function running on dedicated hardware, or a virtualization function instantiated on a platform (e.g., a cloud platform). Optionally, the communication device 1300 can also include a storage module 1303 for storing program code and data of the communication device 1300.

In one example, when the communication device is used as a terminal device or a chip used in a terminal device, and performs the steps performed by the terminal device in the above method embodiment. The transceiver module 1302 is used to specifically perform the sending and/or receiving actions performed by the terminal device in any embodiment of Figures 5 to 8, such as supporting the terminal device to perform other processes of the technology described herein. The processing module 1301 can be used to support the communication device 1300 to perform the processing actions in the above method embodiment, for example, supporting the terminal device to perform other processes of the technology described herein.

Exemplarily, the processing module 1301 is used to: determine a second bit sequence and a third bit sequence based on the first bit sequence, where the third bit sequence includes a bit sequence whose weight is higher than a first threshold in a base graph corresponding to the first bit sequence; perform polar code encoding on the second bit sequence to obtain a fourth bit sequence; and perform low-density parity check LDPC encoding on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence.

In a possible implementation, when determining the second bit sequence and the third bit sequence based on the first bit sequence, the processing module 1301 is used to: determine a first numerical value based on the first number of columns in the base graph whose weights are higher than a first threshold; determine the third bit sequence from the first bit sequence based on the first numerical value and the lifting factor corresponding to the first bit sequence; and determine the second bit sequence based on the third bit sequence and the first bit sequence.

In a possible implementation, when determining a first numerical value based on the first number of columns in the base graph whose weights are higher than a first threshold, the processing module 1301 is used to: determine a second number of columns with the highest reliability from other columns in the base graph except for columns whose weights are higher than the first threshold; and determine the first numerical value based on the first number of columns and the second number of columns.

In a possible implementation, when polarization code encoding is performed on the second bit sequence to obtain a fourth bit sequence, the processing module 1301 is configured to: perform check code encoding on the second bit sequence to obtain a sixth bit sequence; and perform polarization code encoding on the sixth bit sequence to obtain a fourth bit sequence.

In a possible implementation, the processing module 1301 is further configured to perform check code encoding on the sixth bit sequence to obtain the first bit sequence.

In a possible implementation, the processing module 1301 is further used to segment the initial bit sequence based on the first segment length to obtain X bit sequences, where the X bit sequences include the first bit sequence or the seventh bit sequence, and X is an integer greater than 1; wherein the first segment length is determined based on the first value and the lifting factor.

In a possible implementation, when the second bit sequence is determined based on the third bit sequence and the first bit sequence, the processing module 1301 is configured to segment other bit sequences in the first bit sequence except the third bit sequence based on a second segment length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; wherein the second segment length is determined based on a maximum length supported by polar code encoding and a third value.

In a possible implementation manner, the transceiver module 1302 is further configured to send a symbol sequence based on a third bit sequence.

In one example, when the communication device is used as a network device or a chip used in a network device, and performs the steps performed by the network device in the above method embodiment. The transceiver module 1302 is used to specifically perform the sending and/or receiving actions performed by the network device in any embodiment of Figures 5 to 8, such as supporting the network device to perform other processes of the technology described herein. The processing module 1301 can be used to support the communication device 1300 to perform the processing actions in the above method embodiment, for example, supporting the network device to perform other processes of the technology described herein.

Exemplarily, the processing module 1301 is used to: obtain a symbol sequence; determine a fifth bit sequence based on the symbol sequence; perform LDPC decoding on the fifth bit sequence to obtain a third bit sequence and a fourth bit sequence; perform polar code decoding on the fourth bit sequence to obtain a second bit sequence; and determine a first bit sequence based on the third bit sequence and the second bit sequence.

In a possible implementation, when the terminal device or network device is a chip, the transceiver module 1302 may be a communication interface, a pin or a circuit, etc. The communication interface may be used to input data to be processed to the processor, and may output the processing result of the processor to the outside. In a specific implementation, the communication interface may be a general purpose input output (GPIO) interface, which may be connected to multiple peripheral devices (such as a display (LCD), a camera (camera), a radio frequency (RF) module, an antenna, etc.). The communication interface is connected to the processor via a bus.

The processing module 1301 may be a processor, which may execute the computer execution instructions stored in the storage module so that the chip executes the method involved in any of the embodiments shown in FIG. 5 to FIG. 8. Further, the processor may include a controller, an operator and a register. Exemplarily, the controller is mainly responsible for instruction decoding and sends a control signal for the operation corresponding to the instruction. The operator is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logical operations, etc., and may also perform address operations and conversions. The register is mainly responsible for saving register operands and intermediate operation results temporarily stored during the execution of instructions. In a specific implementation, the hardware architecture of the processor may be an ASIC architecture, a microprocessor without interlocked piped stages architecture (microprocessor without interlocked piped stages architecture, MIPS) architecture, an advanced reduced instruction set machine (advanced RISC machines, ARM) architecture, or a second processor (network processor, NP) architecture, etc. The processor may be single-core or multi-core. The storage module may be a storage module in the chip, such as a register, a cache, etc. The storage module may also be a storage module located outside the chip, such as a ROM or other types of static storage devices that can store static information and instructions, RAM, etc.

It should be noted that the functions corresponding to the processor and the interface can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

FIG14 is a schematic diagram of the structure of another communication device provided in an embodiment of the present application. It is understandable that the communication device 1410 includes necessary means such as modules, units, elements, circuits, or interfaces, which are appropriately configured together to implement the present solution. The communication device 1410 may be the above-mentioned terminal device or network device, or a component (such as a chip) in these devices, to implement the method described in the above-mentioned method embodiment. The communication device 1410 includes one or more processors 1411. The processor 1411 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processing unit may be used to control the communication device (such as a terminal device, a network device, or a chip, etc.), execute software programs, and process data of software programs.

Optionally, in one design, the processor 1411 may include a program 1413 (sometimes also referred to as code or instruction), and the program 1413 may be run on the processor 1411, so that the communication device 1410 performs the method described in the above embodiment. In another possible design, the communication device 1410 includes a circuit (not shown in FIG. 14), and the circuit is used to implement the functions of the terminal device, network device, etc. in the above embodiment. Optionally, the communication device 1410 may include one or more memories 1412, on which a program 1414 (sometimes also referred to as code or instruction) is stored, and the program 1414 may be run on the processor 1411, so that the communication device 1410 performs the method described in the above method embodiment. Optionally, data may also be stored in the processor 1411 and/or the memory 1412. The processor and the memory may be provided separately or integrated together.

Optionally, the communication device 1410 may further include a transceiver 1415 and/or an antenna 1416. The processor 1411 may also be sometimes referred to as a processing unit, which controls the communication device (e.g., a terminal device or a network device). The transceiver 1415 may also be sometimes referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which is used to implement the transceiver function of the communication device through the antenna 1416.

An embodiment of the present application further provides a communication device, which includes at least one processor; wherein the at least one processor is configured to execute any method described in any one of the embodiments in Figures 5 to 8.

An embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed, the computer executes any method as described in any one of the embodiments in Figures 5 to 8.

An embodiment of the present application further provides a computer program product, which includes: a computer program code, and when the computer program code is executed by a computer, the computer executes any of the methods described in any of the embodiments shown in Figures 5 to 8.

An embodiment of the present application also provides a chip, which includes at least one processor and an interface, wherein the processor is used to read and execute instructions stored in a memory, and when the instructions are executed, the chip executes any method as described in any of the embodiments in Figures 5 to 8.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application. In addition, each network element unit in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software network element units.

If the above-mentioned integrated unit is implemented in the form of a software network element unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the part that essentially contributes to the technical solution of the present application, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a terminal device, a cloud server, or a network device, etc.) to perform all or part of the steps of the above-mentioned methods in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes. The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims (16)

A coding method, characterized by comprising: Determine a second bit sequence and a third bit sequence based on the first bit sequence, wherein the third bit sequence includes a bit sequence in a base graph corresponding to the first bit sequence and having a weight higher than a first threshold; Performing polar code encoding on the second bit sequence to obtain a fourth bit sequence; Low-density parity check (LDPC) encoding is performed on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence. The method according to claim 1, characterized in that the determining the second bit sequence and the third bit sequence based on the first bit sequence comprises: determining a first value based on a first number of columns in the base graph whose weights are higher than the first threshold; determining the third bit sequence from the first bit sequence based on the first value and a lifting factor corresponding to the first bit sequence; The second bit sequence is determined based on the third bit sequence and the first bit sequence. The method according to claim 1 or 2, characterized in that the first column number is an integer greater than or equal to 1. The method according to any one of claims 1 to 3, characterized in that determining the first value based on the first number of columns in the base graph whose weights are higher than the first threshold value comprises: Determine a second column number with the highest reliability from the base graph except for other columns whose weights are higher than the first threshold; The first value is determined based on the first column number and the second column number. The method according to any one of claims 1 to 4, characterized in that the step of performing polar code encoding on the second bit sequence to obtain a fourth bit sequence comprises: Performing check code encoding on the second bit sequence to obtain a sixth bit sequence; Polar code encoding is performed on the sixth bit sequence to obtain the fourth bit sequence. The method according to any one of claims 1 to 4, characterized in that the method further comprises: Perform check code encoding on the seventh bit sequence to obtain the first bit sequence. The method according to any one of claims 1 to 6, characterized in that the method further comprises: Segmenting the initial bit sequence based on a first segment length to obtain X bit sequences, where the X bit sequences include the first bit sequence or the seventh bit sequence, and X is an integer greater than 1; The first segment length is determined based on the first value and the boost factor. The method according to claim 7, characterized in that the first segment length is determined based on the first value and the boost factor, comprising: The first segment length is determined based on the first value, the lifting factor and a second value; wherein the second value is determined based on the total number of columns of the base graph and the first value. The method according to claim 7 or 8, characterized in that The first segment length meets the following conditions: Wherein, a is the first value, b is the second value, R is the third value, and Z is the boost factor. The method according to any one of claims 1 to 9, characterized in that determining the second bit sequence based on the third bit sequence and the first bit sequence comprises: Segmenting the other bit sequences in the first bit sequence except the third bit sequence based on the second segment length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; The second segment length is determined based on a maximum length supported by polar code encoding and a third value. The method according to claim 10, characterized in that The second segment length meets the following conditions: The Nm is a maximum length supported by polar code encoding, and the R is the third value. A communication device, characterized by comprising a unit or module for implementing the method as claimed in any one of claims 1 to 11. A communication device, characterized in that the communication device comprises at least one processor; wherein the at least one processor is configured to execute the method according to any one of claims 1 to 11. A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and when the computer instructions are executed, the computer is caused to execute the method as described in any one of claims 1 to 11. A computer program product, characterized in that the computer program product comprises: a computer program code, and when the computer program code is executed by a computer, the computer executes the method as claimed in any one of claims 1 to 11. A chip, characterized in that the chip includes at least one processor and an interface, the processor is used to read and execute instructions stored in a memory, and when the instructions are executed, the chip executes the method according to any one of claims 1 to 11.