WO2025141588A1

WO2025141588A1 - Printed circuit ultra-thin capacitor for high breakdown voltage

Info

Publication number: WO2025141588A1
Application number: PCT/IL2024/051239
Authority: WO
Inventors: Yaad ELIYA; Eran Lipp; Raymond BLANGA; Adva BRAYMOK LAUFER; Tzagay MEVRAT
Original assignee: PCB Technologies Ltd
Current assignee: PCB Technologies Ltd
Priority date: 2023-12-31
Filing date: 2024-12-30
Publication date: 2025-07-03
Anticipated expiration: 2026-06-30
Also published as: TW202529494A

Abstract

Provided herein is a printed circuit ultra-thin capacitor for high breakdown voltage, the capacitor comprising: a multilayered structure comprising a plurality of capacitor layers, the plurality of capacitor layers comprising: a first and a second conductive layer having a thickness of no more than about 3 um; and a dielectric layer having a thickness of about 8 um to about 15 um positioned therebetween; and an adhesive resin applied between each of the plurality of capacitor layers having a substantially equal potential, the adhesive resin is configured fill gaps in the conductive pattern having the substantially equal potential, such that to breakdown voltage dependency on adhesive resin properties is avoided; wherein a total thickness of a printed circuit board and of the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating under an applied voltage of up to 2,500V.

Description

PRINTED CIRCUIT ULTRA-THIN CAPACITOR FOR HIGH BREAKDOWN VOLTAGE

TECHNICAL FIELD

The present disclosure, according to some embodiments thereof, relates generally to capacitors, and more particularly, to a printed circuit ultra-thin capacitor and a method of manufacturing thereof.

BACKGROUND

Capacitors are devices that accumulate electric charges and store electrical energy. They are widely used in various types of electrical and electronic devices. The basic capacitor structure includes two parallel conductive plates separated by a dielectric material. An increase in the conductive plates area, results in increased capacitance. Furthermore, connecting several capacitors in parallel increases the total capacitance and the stored energy therein, since the equivalent capacitance of capacitors connected in parallel is the sum of each individual capacitance thereof. The required large area thereof, however, may increase the probability of defects presence (e.g., defects in the dielectric material), thereby increasing the leakage current and may also lead to a premature breakdown of the capacitor. The increased leakage current results in shorter retention time. Put differently, the increased leakage current leads to energy dissipation from the capacitor, such that the charge/energy stored in the capacitor is reduced. Hence, in order to compensate for the reduced capacitance, the capacitors are typically stacked or connected in parallel, however, in such scenarios, the total area of the capacitor is increased. An alternative approach to increase the capacitance may include using high-k materials.

Hence, there is a need in the art for thin capacitors having a high breakdown voltage. SUMMARY

Aspects of the disclosure, according to some embodiments thereof, relate to electric devices or discrete devices, and more particularly, to a printed circuit ultra-thin capacitor and a method of manufacturing thereof.

According to some embodiments, there is provided a printed circuit ultra-thin capacitor for high breakdown voltage, the capacitor including: a multilayered structure comprising a plurality of capacitor layers, each of the plurality of capacitor layers including: a first and a second conductive layer including copper, each of the first and the second conductive layers having a thickness of no more than about 3 um; and a dielectric layer positioned between the first and the second conductive layers, the dielectric layer having a thickness of about 8 um to about 15 um; wherein each of the first and the second conductive layers includes a conductive pattern; wherein the multilayered structure includes an adhesive resin applied between each of the plurality of capacitor layers having a substantially equal potential, the adhesive resin is configured fill gaps in the conductive pattern having a substantially even potential, such that to breakdown voltage dependency on adhesive resin properties is avoided; wherein a thickness of the adhesive resin is at least about a sum of the thicknesses the first and the second conductive layers; wherein a total thickness of a printed circuit board and of the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating under an applied voltage of up to about 2,500V.

According to some embodiments, the adhesive resin may be configured to fill gaps in the conductive pattern between each of the plurality of capacitor layers having a positive and a negative potential, thereby increasing a capacitance thereof.

According to some embodiments, a capacitance per unit area thereof and per capacitor layer is about 0.5 nF/cm² to about 1 nF/cm².

According to some embodiments, the first and the second conductive layers are made of or include copper.

According to some embodiments, the thickness of each of the first and the second conductive layers may be in a range of about 0.5 um to about 1.5 um. According to some embodiments, a thickness of the adhesive resin may be in a range of about 12 um to about 50 um.

According to some embodiments, the adhesive resin may be made of or include an acrylic resin, an epoxy resin, or polyimide.

According to some embodiments, the dielectric layer may be made of or include an acrylic resin, an epoxy resin, or polyimide.

According to some embodiments, the dielectric layer may include one or more of high permittivity additives: AI2O3, TiCh, BaTiOs or a combination thereof.

According to some embodiments, the plurality of capacitor layers may include at least about 5 capacitor layers.

According to some embodiments, the plurality of capacitor layers may include about 20 capacitor layers, and wherein the total thickness of the printed circuit board and of the capacitor may be about 0.8 mm.

According to some embodiments, a capacitance of the printed circuit ultra-thin capacitor may be about 40 nF, and wherein a total area of the plurality of capacitor layers may be about 5 cm².

According to some embodiments, the capacitor may be flexible.

According to some embodiments, each of the plurality of capacitor layers may be capable of bending to a radius of about 10 cm to about 20 cm.

According to some embodiments, a top and a bottom of a first portion of the multilayered structure may be coated with an insulating protective layer, the insulating protective layer may be configured to provide electrical insulation, thereby avoiding a surface breakdown of the capacitor.

According to some embodiments, contact pads may be formed on a top and a bottom of a second portion of the multilayered structure, wherein the contact pads comprise copper, and wherein the contact pads may be coated with finish layer, the finish layer comprising one or more of: nickel, gold, silver, tin. According to some embodiments, a thickness of the finish layer may be between about 0.1 um to about 20 um.

According to some embodiments, there is provided a method for manufacturing a printed circuit ultra-thin capacitor, the method including: obtaining a plurality of capacitor layers, each of the plurality of capacitor layers includes a first and a second conductive copper layer, and a dielectric layer positioned between the first and the second conductive copper layers; performing a first surface treatment, the first surface treatment including a pre-patterning surface treatment and a first micro-etching of the first and the second conductive copper layers, the first micro-etching is configured to adjust a surface roughness of the first and the second conductive copper layers; forming a pattern on each of the first and the second conductive copper layers; performing a second surface treatment, the second surface treatment comprising a post-patterning surface treatment and a second micro-etching; stacking the plurality of capacitor layers one above the other, the stacking includes applying an adhesive resin configured to attach the plurality of capacitor layers to one another and laminating thereof, thereby forming a multilayered structure; drilling to form through-holes configured to electrically connect first and second conductive copper layer having positive and negative potential; electroplating the through-holes; forming an external pattern to obtain contact pads; applying an isolating coating layer on at least a portion of the multilayered structure; performing a fourth surface treatment, the fourth surface treatment comprising surface cleaning and a fourth micro-etching, the fourth surface cleaning is configured to remove copper oxide from the contact pads; and performing surface finish of the multilayered structure.

According to some embodiments, the first micro-etching and/or the second microetching and/or the third micro-etching and/or the fourth micro-etching may include a wet etching process.

According to some embodiments, the first micro-etching and/or the second microetching and/or the third micro-etching and/or the fourth micro-etching may be configured to remove about 0.5 um or less.

According to some embodiments, the first micro-etching, the second microetching and the third micro-etching and/or the fourth micro-etching remove not more than about 2 um. According to some embodiments, a thickness of the adhesive resin may be a sum of an approximate thickness of the first and the second conductive copper layers and an approximate depth of the gaps in the copper pattern.

According to some embodiments, forming the pattern may include performing a resist lamination; laser direct imaging to expose the resist, wherein the resist is solid; developing the resist; and removing material from the first and the second conductive copper layers.

Certain embodiments of the present disclosure may include some, all, or none of the above advantages. One or more other technical advantages may be readily apparent to those skilled in the art from the figures, descriptions, and claims included herein. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of conflict, the patent specification, including definitions, governs. As used herein, the indefinite articles “a” and “an” mean “at least one” or “one or more” unless the context clearly dictates otherwise.

BRIEF DESCRIPTION OF THE FIGURES

Some embodiments of the disclosure are described herein with reference to the accompanying figures. The description, together with the figures, makes apparent to a person having ordinary skill in the art how some embodiments may be practiced. The figures are for the purpose of illustrative description and no attempt is made to show structural details of an embodiment in more detail than is necessary for a fundamental understanding of the disclosure. For the sake of clarity, some objects depicted in the figures are not drawn to scale. Moreover, two different objects in the same figure may be drawn to different scales. In particular, the scale of some objects may be greatly exaggerated as compared to other objects in the same figure.

In block diagrams and flowcharts, optional elements/components and optional stages may be included within dashed boxes. In the figures:

FIG. 1 shows a schematic illustration of a cross-sectional side view of a printed circuit capacitor for high breakdown voltage, according to some embodiments;

FIGs. 2A-2B show a schematic illustration of a cross-sectional side view of a printed circuit capacitor for high breakdown voltage having a first and a second configuration, according to some embodiments;

FIG. 3 shows a schematic illustration of a flow chart of a method for manufacturing a printed circuit capacitor for high breakdown voltage, according to some embodiments; and

FIGs. 4A-4E show a schematic illustration of a cross-sectional side view of some of the steps of the method of FIG. 3 for manufacturing a printed circuit capacitor for high breakdown voltage of FIG. 3, according to some embodiments.

DETAILED DESCRIPTION

The principles, uses and implementations of the teachings herein may be better understood with reference to the accompanying description and figures. Upon perusal of the description and figures present herein, one skilled in the art will be able to implement the teachings herein without undue effort or experimentation.

In the following description, various aspects of the invention will be described. For the purpose of explanation, specific details are set forth in order to provide a thorough understanding of the invention. However, it will also be apparent to one skilled in the art that the invention may be practiced without specific details being presented herein. Furthermore, well-known features may be omitted or simplified in order not to obscure the invention.

As used herein, the term “about” may be used to specify a value of a quantity or parameter (e.g. the length of an element) to within a continuous range of values in the neighborhood of (and including) a given (stated) value. According to some embodiments, “about” may specify the value of a parameter to be between 80 % and 120 % of the given value. For example, the statement “the length of the element is equal to about 1 m” is equivalent to the statement “the length of the element is between 0.8 m and 1.2 m”. According to some embodiments, “about” may specify the value of a parameter to be between 90 % and 110 % of the given value. According to some embodiments, “about” may specify the value of a parameter to be between 95 % and 105 % of the given value.

As used herein, according to some embodiments, the terms “substantially” and “about” may be interchangeable.

As used herein, according to some embodiments, the terms “isolating” and “insulating” may be interchangeable.

As used herein, according to some embodiments, the term “ultra-thin” may refer to a thickness of a printed circuit capacitor. According to some embodiments, the term “ultra-thin” may refer to the thickness of a printed circuit board and a printed circuit capacitor thereof. According to some embodiments, the term “ultra-thin” may refer to the thickness of about 2 mm or less. According to some embodiments, the term “ultra-thin” may refer to the thickness of about 1 mm or less, about 0.8 mm or less, about 0.5 mm or less, about 0.4 mm or less, about 0.3 mm or less. Each possibility is a separate embodiment.

According to some embodiments, the term “ultra-thin” may refer to the thickness of about 0.5 mm to about 1.5 mm of a printed circuit board having a printed circuit capacitor. According to some embodiments, the term “ultra-thin” may refer to the thickness of about 0.3 mm to about 1mm. According to some embodiments, the term “ultra-thin” may refer to the thickness of about 0.5 mm to about 1 mm. Each possibility is a separate embodiment.

It may be understood by the skilled in the art that the ultra-thin thickness of the printed circuit board with the printed circuit capacitor may depend, among others, on the number of layers therein and on the manufacturing technology thereof. According to some embodiments, the term “ultra-thin” may refer to the thickness of a printed circuit board made of a plurality of capacitor layers (i.e. a plurality of capacitor units). According to some embodiments, the term “ultra-thin” may refer to a printed circuit board having a thickness of about 0.5 mm, wherein the printed circuit board includes 10 or more capacitor layers therein. According to some embodiments, the term “ultra-thin” may refer to a printed circuit board having a thickness in a range between about 0.3 mm to about 1.5 mm, wherein the printed circuit board includes 10 or more layers therein. According to some embodiments, the term “ultra-thin” may refer to a printed circuit board having a thickness in a range between about 0.3 mm to about 1 mm, wherein the printed circuit board includes at least 10 or more layers therein.

As used herein, according to some embodiments, the term “ultra-thin” may refer to a thickness of a capacitor layer (i.e. a capacitor unit), e.g., in a printed circuit board. According to some embodiments, the capacitor may have a thickness of about 2 mm or less, about 1 mm or less, of about 0.8 mm or less, of about 0.5 mm or less, of about 0.4 mm or less, and about 0.3 mm or less. Each possibility is a separate embodiment. According to some embodiments, the capacitor may have a thickness in a range of about 0.1 mm to about 1 mm, about 0.1 mm to about 0.5 mm, about 0.3 mm to about 0.5 mm, about 0. 1 mm to about 0.8 mm. Each possibility is a separate embodiment.

As used herein, according to some embodiments, the term “high breakdown voltage” may refer to a breakdown voltage of a printed circuit capacitor, as disclosed herein, wherein the high breakdown voltage is of about 500V or higher, about 700V or higher, about 800V or higher, about 1000V or higher, about 1200V or higher, about 1500V or higher, about 1700V or higher, about 1800V or higher, about 2000V or higher, about 2200V or higher, about 2500V or higher, and the like. Each possibility is a separate embodiment.

According to some embodiments, the term “high breakdown voltage” may refer to any breakdown voltage in a range of about 500V-1000V, about 500V- 1500V, about 500V-2000V, about 500V-2500V, about 500V-3000V, about 800V-3000V, about 1000V-1500V, about 1000V-2000V, about 1000V-2500V, about 1500V to about 2500V, about 1000V-3000V, about 2000V-2500V, about 2000V-3000V, and the like, or any combination thereof. Each possibility is a separate embodiment.

According to some embodiments, the term “high breakdown voltage” may refer to a breakdown voltage of about up to 2500V, about up to 2700V, about up to 3000V. Each possibility is a separate embodiment. According to some embodiments, there is provided herein a printed-circuit capacitor having a multilayered structure, the multilayered structure including a plurality of capacitor layers, the plurality of capacitor layers including: a first and a second conductive layer, each of the first and the second conductive layers having a thickness of no more than about 3 um, and a dielectric layer positioned between the first and the second conductive layers, the dielectric layer having a thickness of about 2 um to about 25 um; wherein each of the first and the second conductive layers includes a conductive pattern; wherein the multilayered structure comprises an adhesive resin applied between each of the plurality of capacitor layers having a substantially equal potential, the adhesive resin is configured fill gaps in the conductive pattern having a substantially even potential, such that to breakdown voltage dependency on adhesive resin properties is avoided;; wherein a thickness of the adhesive resin is at least about a sum of the thicknesses the first and the second conductive layers; wherein a total thickness of a printed circuit board and of the capacitor is about 1 mm or less; and wherein the capacitor is capable of operating under an applied voltage of up to about 3000V.

Advantageously, according to some embodiments, the printed-circuit capacitor disclosed herein has a capacitance per unit area per single capacitor layer in a range of about 0.5 nF/cm2 to about 1 nF/cm², while having a total thickness of a printed circuit board and of the capacitor of about 1 mm or less.

Advantageously, according to some embodiments, the printed-circuit capacitor is capable of operating under a high operating voltage (e.g., about 500V or more, about 1000V or more, up to about 2500V, up to about 3000V, and the like), while having a total thickness of the printed circuit board and of the capacitor of about 1 mm or less.

Advantageously, according to some embodiments, the printed-circuit capacitor enables minimizing the dimension of devices while achieving a high capacitance per unit area, and hence may be utilized for a wide variety of applications, such as but not limited to, energy storage devices, fast discharge applications, medical devices, electric devices, discrete devices, and the like, or any combination thereof.

According to some embodiments, there is disclosed a method for manufacturing a printed-circuit capacitor. Advantageously, in some embodiments, the disclosed method is a facile and cost-effective method. Advantageously, in some embodiments, the disclosed method may be implemented as a mass production method, as elaborated in greater detail elsewhere herein. Advantageously, the disclosed method may facilitate manufacturing lightweight and/or ultra-thin devices, such as but not limited to, electric and discrete devices.

Reference is made to Fig. 1, which shows a schematic illustration of a cross- sectional side view of a capacitor 100, according to some embodiments.

According to some embodiments, capacitor 100 is a printed circuit board capacitor. According to some embodiments, capacitor 100 may be an ultra-thin capacitor. According to some embodiments, a thickness of the printed circuit board including capacitor 100 may be about 2 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be about 1 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be about 0.8 mm or less. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be about 0.5 mm or less. Each possibility is a separate embodiment. As a non-limiting example, the thickness of the printed circuit board including capacitor 100 may be less than about the thickness of a standard credit card (i.e., standard credit cards have a thickness of about 0.5 mm to about 0.7 mm)

According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.4 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.4 mm to about 0.7 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.4 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.4 mm to about 1 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.4 mm to about 2 mm. Each possibility is a separate embodiment.

According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0. 1 mm to about 2 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.2 mm to about 2 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.1 mm to about 1 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0.1 mm to about 0.8 mm. According to some embodiments, the thickness of the printed circuit board including capacitor 100 may be in a range of about 0. 1 mm to about 0.5 mm. Each possibility is a separate embodiment. It may be understood by the skilled in the art that the thickness of the printed circuit board including capacitor 100 may depend, among others, on manufacturing technology thereof and on the number of capacitor layers (e.g., capacitor units) therein.

According to some embodiments, capacitor 100 may be a flexible capacitor. According to some embodiments, capacitor 100 may be bendable. According to some embodiments, one capacitor layer (e.g., a capacitor layer 110a as depicted in Fig. 1) of capacitor 100 may be bended to a radius of about 20 cm without damaging thereof (i.e., without causing plastic deformation thereto). According to some embodiments, one capacitor layer may be bended to a radius of about 15 cm to about 20 cm without damaging thereof (i.e., without causing plastic deformation thereto). According to some embodiments, one capacitor layer may be bended to a radius of about 5 cm to about 20 cm without damaging thereof (i.e., without causing plastic deformation thereto). According to some embodiments, one capacitor layer may be bended to a radius of about 2 cm to about 10 cm without damaging thereof (i.e., without causing plastic deformation thereto). Each possibility is a separate embodiment. Alternatively, in some embodiments, capacitor 100 may be a substantially rigid capacitor, i.e., substantially devoid of the bending capability.

According to some embodiments, capacitor 100 may have a parallel-plate capacitor configuration, as schematically depicted in Fig. 1. It may be understood by skilled in the art that the configuration of capacitor 100 is not limited thereto. In some embodiments, the configuration of capacitor 100 may include, among others, a radial configuration (not shown).

According to some embodiments, capacitor 100 may have a multilayered structure

101. According to some embodiments, multilayered structure 101 may include one or more capacitor layers/sheets llOa-c (also referred to as “plurality of capacitor layers/sheets 110”). According to some embodiments, and as depicted in Fig. 1, plurality of capacitor layers/sheets 110 of the multilayered structure 101 may include three capacitor layers/sheets llOa-c.

According to some embodiments, each of plurality of capacitor layers/sheets 110 includes a first conductive layer/sheet, a second conductive layer/sheet and a dielectric layer therebetween. Put differently, in some embodiments, each of plurality of capacitor layers/sheets 110 includes a capacitor unit. According to some embodiments, and as depicted in Fig. 1, a first capacitor layer/sheet 110a includes a first conductive layer/sheet 112a, a second conductive layer 116a and a dielectric layer 114a therebetween. Similarly, a second capacitor layer 110b includes a first conductive layer/sheet 112b, a second conductive layer/sheet 116b and a dielectric layer 114b therebetween; and a third capacitor layer 110c includes a first conductive layer/sheet 112c, a second conductive layer/sheet 116c and a dielectric layer 114c therebetween.

According to some embodiments, plurality of capacitor layers/sheets 110 may include 2, 3, 4, 5, 6, 7, 8, 9, 10 or more capacitor layers/sheets. According to some embodiments, plurality of capacitor layers/sheets 110 may include at least about 10 capacitor layers or more. According to some embodiments, plurality of capacitor layers/sheets 110 may include about 20 capacitor layers or more. According to some embodiments, plurality of capacitor layers/sheets 110 may include about 5 capacitor layers to about 40 capacitor layers. According to some embodiments, plurality of capacitor layers/sheets 110 may include about 20 to about 40 capacitor layers 110. As another non-limiting example, plurality of capacitor layers/sheets 110 may include about 11 capacitor layers 110.

According to some embodiments, plurality of capacitor layers/sheets 110 may include about 20 capacitor layers, such that the thickness thereof is about 0.8 mm. According to some embodiments, plurality of capacitor layers/sheets 110 may include about 30 capacitor layers, such that the thickness thereof is about 1.2 mm. According to some embodiments, plurality of capacitor layers/sheets 110 may include about 40 capacitor layers, such that the thickness thereof is about 1.6 mm. Each possibility is a separate embodiment. Each possibility is a separate embodiment. According to some embodiments, capacitor 100 may include a single capacitor layer/sheet (e.g., a capacitor layer 110a).

According to some embodiments, a total number of capacitor layers/sheets 110 include an odd number or an even number, as elaborated in greater detail on Figs. 2A- 2B

According to some embodiments, each of first and second conductive layers/sheets 112a-c and 116a-c may be in the form of a conductive sheet, a coating, a layer, a foil, a surface, and the like. Each possibility is a separate embodiment.

According to some embodiments, first conductive layer 112a-c and second conductive layer 116a-c may be identical or similar in terms of thickness and/or composition. According to some embodiments, first conductive layer 112a-c and second conductive layer 116a-c may be made of or include one or more metals, such as but not limited to, metal alloys, compounds, mixtures, and the like.

According to some embodiments, first conductive layer 112a-c and second conductive layer 116a-c may be made of or include copper. According to some embodiments, each of first conductive layer 112a-c and second conductive layer 116a-c may include a copper sheet. According to some embodiments, each of first conductive layer 112a-c and second conductive layer 116a-c may include a copper foil. According to some embodiments, each of first conductive layer 112a-c and second conductive layer 116a-c may include a copper coating. According to some embodiments, each of first conductive layer 112a-c and second conductive layer 116a-c may include a copper layer.

According to some embodiments, the thickness of each of first conductive layer 112a-c and each of second conductive layer 116a-c of capacitor 100 may be of about 3 um or less. According to some embodiments, the thickness of each of first conductive layer 112a-c and each of second conductive layer 116a-c of capacitor 100 may be in a range of about 0.5 um to about 3 um, about 0.5 um to about 1.5 um, about 1 um to about 2.5 um. About 1.5 um to about 3 um, and the like. Each possibility is a separate embodiment. According to some embodiments, the thickness of each of first conductive layer 112a-c and each of second conductive layer 116a-c of capacitor 100 may be in a range of about 0.4 um to about 1.5 um, about 0.5 um to about 1 um, about 1 um to about 1.5 um, about 1 um to about 1.2 um, about 1.2 um to about 1.5 um, about 0.7 um to about 1.5 um, and the like. Each possibility is a separate embodiment. According to some embodiments, the thickness of each of first conductive layer 112a-c and each of second conductive layer 116a-c of capacitor 100 may be about 0.4 mm, about 0.5 um, about 0.8 um, about 1 um, about 1.2 um. Each possibility is a separate embodiment.

Alternatively, in some embodiments, the thickness of each of first conductive layer 112a-c and each of second conductive layer 116a-c of capacitor 100 may be about 3 um or higher.

According to some embodiments, each of dielectric layer 114a-c may be made of or include one or more insulating materials. According to some embodiments, the one or more insulating materials may include one or more polymers. According to some embodiments, each of dielectric layer 114a-c may be made of or include polyimide, epoxy, an acrylic resin, and the like, or a combination thereof. According to some embodiments, the acrylic resin may include high permittivity additives. According to some embodiments, the high permittivity additives may include, among others, AI2O3, TiCh, perovskite materials, and the like, or any combination thereof. As a non-limiting example, the perovskite materials may include, among others, barium titanate.

According to some embodiments, a thickness of each of dielectric layer 114a-c may be in a range of about 2 um to about 25 um. According to some embodiments, the thickness of each of dielectric layer 114a-c may be in a range of about 8 um to about 15 um. According to some embodiments, the thickness of each of dielectric layer 114a-c may be in a range of about 10 um to about 15 um, about 2 um to about 15 um, about 2 um to about 10 um, about 10 um to about 15 um, about 10 um to about 12 um, and the like. Each possibility is a separate embodiment.

According to some embodiments, each of first layer 112a-c and each of third layer 116a-c may include or be in the form of a pattern. According to some embodiments, each of first layer 112a-c and each of third layer 114a-c may be, among others, etched to form the pattern. As a non-limiting example, the pattern of each of first layer 112a-c and each of third layer 116a-c may include a plurality of conductive islands/regions. According to some embodiments, each of first layer 112a-c and each of third layer 114a-c may have a different pattern. According to some embodiments, each of first layer 112a-c and each of third layer 116a-c may have a partially similar and a partially different pattern. According to some embodiments, each of first layer 112a-c and each of third layer 116a-c may have a substantially identical or similar pattern. Each possibility is a separate embodiment.

According to some embodiments, drilling may be performed to electrically connect each of first layer 112a-c and each of third layer 116a-c having a positive potential each of first layer 112a-c and each of third layer 116a-c having a negative potential.

According to some embodiments, and as schematically depicted in Fig. 1, a portion of the pattern may include a first contact pad 120a formed on a first surface/side 102 (also referred to as “top surface/side 102”) and a second contact pad 120c formed on a second surface/side 104 (also referred to as “bottom surface/side 104”) of capacitor 100. According to some embodiments, first and second contact pads 120a/120c may be configured to connect capacitor 100 to external devices, an electrical circuit, and the like (not shown). According to some embodiments, first and second contact pads 120a/120c may be made of or include copper, or any other suitable conductive material.

According to some embodiments, wherein each of first layer 112a-c and each of third layer 116a-c are made of or include copper, an environmentally stable oxide layer/coating 118a-c may be at least partially present thereon, as elaborated in greater detail elsewhere herein. According to some embodiments, the stable oxide may include an environmentally stable copper oxide. According to some embodiments, oxide layer/coating 118a-c may be made of or include CuO, CuCh, or a combination thereof. According to some embodiments, oxide layer/coating 118a-c may be configured to increase surface roughness of first and second conductive layers 112a-c and 116a-c. According to some embodiments, oxide layer/coating 118a-c may be configured to facilitate adhesion of and second conductive layers 112a-c and 116a-c to an adhesive resin 122 during lamination.

According to some embodiments, contact pads 120a/120c are substantially devoid of oxide coating 118a-c. According to some embodiments, contact pads 120a/120c may be coated with a surface finish layer (not shown). According to some embodiments, the finish layer may be configured to protect contact pads 120a/120c from oxidation and, optionally and/or additionally, to facilitate connecting capacitor 100 to other devices, e.g., by facilitating wire bonding, facilitating the solderability of contact pads 120a/120c, and the like. According to some embodiments, the finish layer may include one or more metals. According to some embodiments, the one or more metals of the finish layer may include, among others, nickel, gold, silver, tin, and the like, or any combination thereof. According to some embodiments, the finish layer may be applied by, among others, an electroless nickel immersion gold process, or any variations thereof.

According to some embodiments, and as schematically depicted in Fig. 1, each of plurality of capacitor layers/sheets 110 may be attached/stacked one above the other by an adhesive polymer resin 122 applied therebetween. According to some embodiments, adhesive polymer resin 122 is configured to attach and fill gaps in the pattern of each of first conductive layer 112a-c and each of second conductive layer 116a-c. According to some embodiments, adhesive polymer resin 122 is configured to electrically isolate each of each of first conductive layer 112a-c and each of second conductive layer 116a-c. As a non-limiting example, and as depicted in Fig. 1, adhesive polymer resin 122 is configured to electrically isolate second conductive layer 116a of first capacitor layer 110a from the adjacent first conductive layer 112b of second capacitor layer 110b, thereby preventing short-circuiting therebetween.

According to some embodiments, adhesive polymer resin 122 may be made of or include a dielectric paste. According to some embodiments, adhesive polymer resin 122 may be made of or include an acrylic resin, an epoxy resin, polyimide, and the like, or any combination thereof. Each possibility is a separate embodiment.

According to some embodiments, the thickness of adhesive polymer resin 122 applied between first and second conductive layers 112a-c and 116a-c may be at least about twice the thickness thereof. Put differently, as a non-limiting example, the thickness of adhesive polymer resin 122 applied between first conductive layer 112b of second capacitor layer 110b and between second conductive layer 116a of first capacitor layer 110a may be at least about a sum of the thicknesses of first conductive layer 112b and of second conductive layer 116a. According to some embodiments, and as schematically depicted in Fig. 1, the thickness of adhesive polymer resin 122 may vary, due to the pattern (gaps of the pattern) of first and second conductive layers 112a-c and 116a-c.

According to some embodiments, the thickness of adhesive polymer resin 122 may be in a range of about 12 um to about 50 um, about 25 um to about 50 um, about 12 um to about 30 um, and the like. Each possibility is a separate embodiment.

According to some embodiments, and as schematically depicted in Fig. 1, top surface 102 of capacitor 100 is partially coated with an insulating coating layer 106. Similarly, bottom (opposing) surface 104 of capacitor 100 is partially coated with an insulating coating layer 108. In some embodiments, coating layer 106 may be identical or similar to coating layer 108 in terms of composition and/or thickness thereof. According to some embodiments, coating layer 106/108 may be made of or include a protective polymer coating, a layer, and the like. According to some embodiments, coating layer 106/108 may include a solder mask layer/cover. According to some embodiments, coating layer 106/108 may be made of or include coverlay including polyimide and an adhesive such as acrylic resin.

According to some embodiments, coating layer 106/108 may be made of or include one or more polymers configured to protect the conductive pattern of first and second conductive layers 112a and 116c from the environment. According to some embodiments, coating layer 106/108 may be configured to provide sufficient insulation, such that surface breakdown is avoided.

According to some embodiments, a capacitance per unit area per single capacitor layer of capacitor 100 may be in a range of about 0.5 nF/cm²to about 1 nF/cm², of about 0.8 nF/cm² to about 1 nF/cm², and the like.

According to some embodiments, the capacitance of multilayered capacitor 100 having an area of about 5 cm² may be about 40 nF, wherein capacitor 100 is made of 10 laminated capacitor units. Put differently, in some embodiments, the capacitance of capacitor 100 may be about 7 nF/cm² or more. As a non-limiting example, the capacitance of multilayered capacitor 100 may be about 7 nF/cm² or more, wherein each capacitor unit may include a first and a second conductive layer having a thickness of about 3 um, and a dielectric layer having a thickness of about 8 um therebetween, and wherein an adhesive polymer resin having a thickness of about 25 um is implemented thereon for laminating each of the capacitor units.

Reference is made to Fig. 2A-B, which show a schematic illustration of a cross- sectional side view of a printed circuit capacitor for high breakdown voltage having a first and a second configuration, respectively, according to some embodiments.

According to some embodiments, the following components depicted in Fig. 2A 206, 208, 210a-d, 212a-d, 214a-d, 216a-d, 220 and 222 correspond to and may have substantially the same or similar structure and configuration as the previously described components 106, 108, llOa-c, 112a-c, 114a-c, 116a-c, 120 and 122, respectively, of Fig. 1. Similarly, according to some embodiments, the following components depicted in Fig. 2B 206', 208', 210a-d', 212a-d', 214a-d', 216a-d', 220' and 222' correspond to and may have substantially the same or similar structure and configuration as the previously described components 106, 108, llOa-c, 112a-c, 114a-c, 116a-c, 120 and 122, respectively, of Fig. 1.

According to some embodiments, and as depicted in Fig. 2A, a capacitor 200 having a multilayered structure 201 may have a first configuration. According to some embodiments, the first configuration includes an adhesive resin 222 applied between conductive layers having an alternating potential. Put differently, adhesive resin 222 applied between each of a plurality of capacitor layers 210a-d wherein first and second conductive layers/sheets 212a-d and 216a-d having an alternating positive and negative potential. According to some embodiments, and as depicted in Fig. 2A, adhesive resin 222 is applied to laminate a second conductive layer/sheet 216a having a first potential (e.g., a positive potential) to a first conductive layer/sheet 216b having a second opposite potential (e.g., a negative potential). Consequently, in some embodiments, forming a capacitor therebetween, such that adhesive resin 222 may be configured to serve as the dielectric layer thereof, which, in turn, may increase the capacitance of capacitor 200.

According to some embodiments, and as depicted in Fig. 2A, capacitor 200 may further include a plurality of vias 230/232 configured to electrically connect each of first and second conductive layers 212a-d and 214a-d. According to some embodiments, and as depicted in Fig. 2B, a capacitor 200' having a multilayered structure 201' may have a second configuration. According to some embodiments, the second configuration includes an adhesive resin 222' applied between conductive layers having substantially the same potential/polarity. Put differently, adhesive resin 222' applied between each of a plurality of capacitor layers 210a-d' wherein first and second conductive layers/sheets 212a-d' and 216a-d' having substantially even/equal potential. According to some embodiments, and as depicted in Fig. 2B, adhesive resin 222' is applied to laminate a second conductive layer/sheet 216a' having a first potential (e.g., a positive potential) to a first conductive layer/sheet 216b' having a same polarity (e.g., a positive potential). Consequently, in some embodiments, adhesive resin 222' may be devoid of a potential drop thereon. Put differently, in some embodiments, in the second configuration, the breakdown voltage of capacitor 200' may be substantially devoid of adhesive resin 222' properties.

Reference is made to Fig. 3, which shows a flowchart 300 of a method for forming/manufacturing a printed circuit capacitor (such as but not limited to, capacitor 100 of Fig. 1), and to Figs. 4A-E, which schematically and partially illustrate steps thereof, according to some embodiments.

According to some embodiments, the following components depicted in Figs. 4A-E 401, 402, 404, 406, 408, 410a, 410b, 410c, 412a, 412b, 412c, 414a, 414b, 414c, 416a, 416b, 416c, 418a, 418b, 418c, 420 and 422 correspond to and may have substantially the same or similar structure and configuration as the previously described components 101, 102, 104, 106, 108, 110a, 110b, 110c, 112a, 112b, 112c, 114a, 114b, 114c, 116a, 116b, 116c, 118a, 118b, 118c, 120 and 122, respectively, of Fig. 1.

According to some embodiments, at step 302, the method may include obtaining a plurality of capacitor layers/sheets 410a-c. According to some embodiments, and as schematically depicted in Fig. 4A, which shows a cross-sectional side view of plurality of capacitor layers/sheets 410a-c, the plurality of capacitor layer/sheets include 3 capacitor layers/sheets. According to some embodiments, the number of capacitor layers/sheets 410a-c may include, among others, about 5 or more, about 10 or more, about 15 or more, about 20 or more, about 30 or more, about 40 or more, or any other number of capacitor layers/sheets. Each possibility is a separate embodiment. According to some embodiments, and as depicted in Fig. 3A, each of capacitor layers 410a-c includes a first conductive layer 412a-c, a second conductive layer 416a-c, and a dielectric layer 314a-c. According to some embodiments, each of dielectric layer 414a-c is positioned between each of first conductive layer 412a-c and second conductive layer 316a-c. According to some embodiments, first conductive layer 412a-c may be made of or include copper. According to some embodiments, second conductive layer 316a-c may be made of or include copper. According to some embodiments, first conductive layer 412a-c may be similar or identical to second conductive layer 316a-c in terms of thickness and/or composition.

According to some embodiments, each of plurality of capacitor layers/sheets 410a-c may be in a form of a laminate, i.e. a first and a second conductive layers are attached to the dielectric layer positioned therebetween. According to some embodiments, obtaining plurality of capacitor layers/sheets 410a-c may optionally include obtaining a plurality of laminates, such as, but not limited to, Farad Flex™ by Oak-Mitsui.

According to some embodiments, obtaining the plurality of laminates may optionally include stripping off the first and the second conductive layers thereof, and forming a first and a second conductive layers having a desired thickness and/or composition, such that the first and the second conductive layers having the desired properties are attached to the dielectric layer of each of the plurality of laminates.

According to some embodiments, dielectric layer 414a-c may be made of or include one or more polymers. According to some embodiments, dielectric layer 414a-c may be made of or include a polymer resin and material/particles having high dielectric constant (i.e., high permittivity additives). According to some embodiments, the polymer resin of dielectric layer 414a-c may be made of or include epoxy and/or polyimide. According to some embodiments, dielectric layer 414a-c may high permittivity additives such as but not limited to, AI2O3, TiCh, BaTiOs and the like, or any combination thereof. As a non-limiting example, dielectric layer 414a-c may be in a form of a layered structure including a first and a second polymer and a high dielectric constant layer positioned therebetween. According to some embodiments, an initial thickness (i.e., thickness at step 302) of each of first and second conductive layers 412a-c and 416a-c may be in a range of about 1.5 um to about 5 um. According to some embodiments, an initial thickness (i.e., thickness at step 302) of each of first and second conductive layers 412a-c and 416a-c may be in a range of about 3 um to about 5 um. According to some embodiments, the thickness of each of first and second conductive layers 412a-c and 316a-c may about 3 um or less, about 4 um or less, about 4.5 um or less, about 5 um or less. Each possibility is a separate embodiment.

According to some embodiments, the initial thickness of each of first and second conductive layer 412a-c and 416a-c (i.e., in some embodiments, the initial thickness of the copper layer/sheet) advantageously allows achieving an ultra-thin printed circuit capacitor, as described in greater detail elsewhere herein. It may be understood by the skilled in the art that decreasing the initial thickness of the first and the second conductive layers 412a-c and 316a-c (i.e., in some embodiments, decreasing the copper layer/sheet thickness) leads to, among others, decrease in the final thickness of a printed circuit capacitor. According to some embodiments, the thickness of the first and the second conductive layers may affect the thickness of the resin applied between each of the capacitor layers/sheets to attach the capacitor layers to one another, as described in greater detail elsewhere herein.

According to some embodiments, at step 304, the method may include performing a first surface treatment of each of the plurality of capacitor layers 410a-c. According to some embodiments, the first surface treatment may include cleaning plurality of capacitor layers 410a-c.

According to some embodiments, the first surface treatment may include performing a first micro-etching of each of the first and the second conductive layers 412a-c and 416a-c, as schematically depicted in Fig. 4A. In some embodiments, the first micro-etching is configured to enhance adhesion of a photoresist, as elaborated elsewhere herein, by tailoring a surface roughness of first and second conductive layer 412a-c and 416a-c. According to some embodiments, the first micro-etching is advantageously configured to etch/remove about 0.5 um or less, about 0.4 um or less, about 0.3 um or less, about 0.2 um or less, from the surface of each of first and second conductive layer 412a-c and 416a-c. Each possibility is a separate embodiment. As a non-limiting example, the first micro-etching is configured to etch/remove about 0.2 to about 0.5 um of copper from each of first and second conductive layer 412a-c and 416a-c. Advantageously, in some embodiments, removing about 0.5 um or less may decrease a variation in the thickness of a remainder portion of first and second conductive layer 412a-c and 416a-c (e.g., a remainder portion of copper sheet/layer), which, in turn, facilitates achieving substantially uniform etching. Consequently, in some embodiments, facilitating image/pattem formation. In some embodiments, obtaining a substantially uniform thickness of first and second conductive layer 412a-c and 416a-c (e.g., of copper layers) while minimizing the thickness variation thereof, may result in maintaining the integrity and minimizing the probability of defects formation in first and second conductive layers 412a-c and 416a-c.

According to some embodiments, the first micro-etching may include, among others, a wet etching process.

According to some embodiments, at step 306, the method may include forming a pattern on each of first and second conductive layers 412a-c and 416a-c of each of plurality of capacitor layers/sheets 410a-c. According to some embodiments, the pattern formed on each of first and second conductive layer 412a-c and 416a-c may be similar or identical, as schematically depicted in Fig.4. According to some embodiments, the pattern formed on each of first and second conductive layers 412a-c and 416a-c may be different. According to some embodiments, a first portion of the pattern formed on the first conductive layer 412a-c and/or second conductive layer 416a-c may be similar or identical, while a second portion (i.e., a remainder portion) of the pattern may be different. Each possibility is a separate embodiment.

According to some embodiments, the pattern may be formed by any suitable process, such as, but not limited to, etching (e.g., wet/chemical etching), lithography, and the like.

According to some embodiments, forming the pattern may include applying a photoresist layer on the surface of first and second conductive layers 412a-c and 416a-c. According to some embodiments, the photoresist may be applied, among others, by spin coating, dipping or dry film lamination.

According to some embodiments, forming the pattern may include exposure of the photoresist, e.g., by applying an adequate wavelength and dose thereto. According to some embodiments, exposure of the photoresist may be performed by using a blocking mask. According to some embodiments, exposure of the photoresist may be performed by implementing a mask-less process, such as direct imagining, laser imaging, and the like. According to some embodiments, the exposure of the photoresist may be configured to change the chemical properties of exposed regions thereof, thereby allowing selective resist removal in a subsequent resist development stage.

According to some embodiments, forming the pattern may include development of the resist.

According to some embodiments, forming the pattern may include removing material from the first and the second conductive layers 412a-c and 416a-c. According to some embodiments, removing material may include removing the resist, by any suitable process, after the pattern is formed, e.g., by etching, stripping, laser ablation, and the like, or any combination thereof.

According to some embodiments, at step 308, the method may include performing a second surface treatment of each of the plurality of capacitor layers 410a-c. According to some embodiments, the second surface treatment may include performing a postpatterning surface treatment. According to some embodiments, the post-patterning surface treatment may include cleaning plurality of capacitor layers 410a-c by any suitable cleaning procedure.

According to some embodiments, the post-patterning surface treatment may include performing a second micro-etching of each of the first and the second conductive layers 412a-c and 416a-c. According to some embodiments, the second micro-etching may include etching a portion of copper from first and second conductive layer 412a-c and 416a-c, thereby forming an environmentally stable copper oxide compound, as elaborated elsewhere herein.

According to some embodiments, the second micro-etching may be configured to tailor/adjustthe surface roughness of first and second conductive layers 412a-c and 416a- c and to provide an environmental protection for the stacking step/process. According to some embodiments, the second micro-etching may be advantageously configured to etch/remove about 0.5 um or less, about 0.4 um or less, about 0.3 um or less, about 0.2 um or less, from the surface of each of first and second conductive layer 412a-c and 416a- c. Each possibility is a separate embodiment. As a non-limiting example, the second micro-etching may be configured to etch/remove about 0.2 to about 0.5 um of a copper from each of first and second conductive (copper) layer 412a-c and 416a-c. Advantageously, in some embodiments, removing about 0.5 um or less may decrease the variation in the thickness of a remainder portion of first and second conductive layer 412a-c and 416a-c (e.g., a remainder portion of copper sheet/layer), which, in turn, reduces the final thickness of a printed circuit capacitor, while maintaining and/or ensuring process reliability.

According to some embodiments, and as depicted in Fig. 4C, the second surface preparation may include forming a substantially stable surface oxide 418a-c on each of first and second conductive layers 412a-c and 416a-c. According to some embodiments, the surface oxide may be spontaneously formed thereon. According to some embodiments, wherein each of the first and the second conductive layers 412a-c and 416a-c are made of copper, the surface oxide may be made of or include an environmentally stable copper oxide, such as CuO (also known as “black oxide”) and a mixture of CuO and C112O oxides (also known as “brown oxide”).

According to some embodiments, at step 310, the method may include stacking the plurality of capacitor layers/sheets 410a-c one above the other to manufacture a multilayered structure (such as, but not limited to, multilayered structure 101 of capacitor 100 in Fig. 1). According to some embodiments, stacking capacitor layers/sheets 410a-c may include, among others, press-laminating each of capacitor layers/sheets 410a-c one above the other.

According to some embodiments, and as depicted in Fig. 4D, stacking the plurality of capacitor layers/sheets 410a-c one above the other may include applying an adhesive polymer resin 422 between each of plurality of capacitor layers/sheets 410a-c. According to some embodiments, adhesive polymer resin 422 is configured to attach the plurality of capacitor layers 410a-c to one another and to provide electrical isolation therebetween.

According to some embodiments, adhesive polymer resin 422 may be made of or include a dielectric paste. According to some embodiments, adhesive polymer resin 422 may be made of or include an acrylic resin, an epoxy resin, polyimide, and the like, or any combination thereof. Each possibility is a separate embodiment.

According to some embodiments, the thickness of polymer resin 322 may be at least about a sum of the thicknesses of first conductive layer 412b and of second conductive layer 416a.

According to some embodiments, at step 312, the method may include through- hole drilling through first and second conductive layers 412a-c and 416a-c. According to some embodiments, drilling may be performed to electrically connect each of first layer 412a-c and each of third layer 416a-c having a positive potential each of first layer 412a- c and each of third layer 416a-c having a negative potential.

According to some embodiments, at step 314, the method may include performing a third surface treatment. According to some embodiments, the third surface treatment may include surface cleaning by any suitable process. According to some embodiments, the third surface treatment may include a third micro-etching. According to some embodiments, the third surface treatment may include electroless copper plating.

According to some embodiments, at step 316, the method may include electroplating, such as copper electroplating. According to some embodiments, the electroplating may be configured to form a conductive coating at the drilled holes walls of step 314.

According to some embodiments, at step 318, the method may include forming an external layer pattern on a top surface/surface 402 and a bottom surface/side 404, thereby forming conductive contact pads. According to some embodiments, forming the external layer pattern may include performing a second pre-patterning surface treatment. According to some embodiments, the second pre-patterning surface treatment may include cleaning and micro-etching of first conductive layer 412a or a portion thereof and second conductive layer 416c or a portion thereof. According to some embodiments, the second pre-patterning surface treatment at step 318 may be similar or identical to the prepatterning surface treatment of step 304. According to some embodiments, the conductive contact pads may include any type, shape or configuration of conductive regions, such as but not limited to, pads, lines, and the like, or a combination thereof.

According to some embodiments, at step 320, the method may include applying an isolating coating layer on a portion of top surface/surface 402 and on a portion of bottom surface/side 404 (e.g., layers 406 and 408 as depicted in Fig. 4E) of multilayered structure 401. According to some embodiments, isolating coating layer 406/408 may be made of or include one or more polymers. According to some embodiments, isolating coating layer 406/408 may include a solder mask or any other type of a protective coating, layer, and the like. According to some embodiments, protective polymer layer 406/408 may be made of or include an epoxy. According to some embodiments, isolating coating layer 406/408 may be made of or include Kapton®.

According to some embodiments, a thickness of insulating coating layer 406/408 may be in a range of about 25 um to about 50 um, about 20 um to about 40 um, about 25 um to about 35 um and the like. Each possibility is a separate embodiment.

According to some embodiments, at step 322, the method may include performing a fourth surface treatment. According to some embodiments, the fourth surface treatment may include surface cleaning and a fourth micro-etching. In particular, in some embodiments, step 322 may include performing micro-etching a second portion of first surface/side 402 (i.e., top surface/side 402) and of a second portion of second surface/side 404 (i.e., bottom surface/side 404) of multilayered structure 401. According to some embodiments, the fourth micro-etching is configured to remove oxide 418a-c (e.g., CuO and/or CuCh) from the surface of the contact pads.

According to some embodiments, the micro-etching of the fourth surface treatment may be performed by, among others, wet etching techniques.

According to some embodiments, each of the first micro-etching and/or the second micro-etching and/or the third micro-etching and/or the fourth micro-etching may be configured to remove about 0.5 um or less, about 0.4 um or less, about 0.3 um or less. Each possibility is a separate embodiment. According to some embodiments, each of the first micro-etching and/or the second micro-etching and/or the third micro-etching and/or the fourth micro-etching may be configured to remove about 0.2 um to about 0.5 um.

According to some embodiments, a total removed thickness by the first microetching, the second micro-etching, the third micro-etching and the fourth micro-etching may be not more than about 2 um.

According to some embodiments, a total removed thickness from each of first and second copper layers by the first micro-etching, the second micro-etching and the third micro-etching may be not more than about 2 um.

According to some embodiments, at step 324, the method may include performing surface finishing of capacitor 400. According to some embodiments, surface finishing may include, among others, applying a surface finish layer on the contact pads (not shown). According to some embodiments, the finish layer is configured to protect conductive pads 420a/420b from oxidation and, optionally, to facilitate the solderability thereof.

According to some embodiments, surface finishing may include applying on the conductive pads one or more metals. Put differently, the finish may include one or more metals, such as, but not limited to, nickel, gold, silver, tin, and the like, or any combination thereof. According to some embodiment, surface finishing may include, among others, performing electroless nickel plating, immersion gold, immersion silver, tin coating, and the like or any other variations thereof.

According to some embodiments, a thickness of the finish layer may be about 5 um or less, about 4 um or less, about 3 um or less, about 2 um or less. Each possibility is a separate embodiment. According to some embodiments, the thickness of the finish layer may be in a range of about 0. 1 um to about 30 um, about 0.1 um to about 2 um, about 1 um to about 10 um, and the like. As a non-limiting example, the surface finishing may include electroplated gold and/or immersion silver having a thickness of about 0. 1 um or less. As another non-limiting example, wherein surface finishing includes tin coating, the thickness of the finish layer may be in a range of about 10 um to about 20 um. In the description and claims of the application, the words “include” and “have”, and forms thereof, are not limited to members in a list with which the words may be associated.

It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiment of the disclosure. No feature described in the context of an embodiment is to be considered an essential feature of that embodiment, unless explicitly specified as such.

Although stages of methods according to some embodiments may be described in a specific sequence, methods of the disclosure may include some or all of the described stages carried out in a different order. A method of the disclosure may include a few of the stages described or all of the stages described. No particular stage in a disclosed method is to be considered an essential stage of that method, unless explicitly specified as such.

Although the disclosure is described in conjunction with specific embodiments thereof, it is evident that numerous alternatives, modifications and variations that are apparent to those skilled in the art may exist. Accordingly, the disclosure embraces all such alternatives, modifications and variations that fall within the scope of the appended claims. It is to be understood that the disclosure is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth herein. Other embodiments may be practiced, and an embodiment may be carried out in various ways. The phraseology and terminology employed herein are for descriptive purpose and should not be regarded as limiting. Citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the disclosure. Section headings are used herein to ease understanding of the specification and should not be construed as necessarily limiting.

Claims

CLAIMS What is claimed is:

1. A printed circuit ultra-thin capacitor for high breakdown voltage, the capacitor comprising: a multilayered structure comprising a plurality of capacitor layers, each of the plurality of capacitor layers comprising: a first and a second conductive layer comprising copper, each of the first and the second conductive layers having a thickness of no more than about 3 um; and a dielectric layer positioned between the first and the second conductive layers, the dielectric layer having a thickness of about 8 um to about 15 um; wherein each of the first and the second conductive layers comprises a conductive pattern; wherein the multilayered structure comprises an adhesive resin applied between each of the plurality of capacitor layers having a substantially equal potential, the adhesive resin is configured to fill gaps in the conductive pattern having the substantially equal potential, such that breakdown voltage dependency on adhesive resin properties is avoided; wherein a thickness of the adhesive resin is at least about a sum of the thicknesses the first and the second conductive layers; wherein a total thickness of a printed circuit board and of the capacitor is about

1 mm or less; and wherein the capacitor is capable of operating under an applied voltage of up to about 2,500V.

2. The printed circuit ultra-thin capacitor of claim 1, wherein the adhesive resin is configured to fill gaps in the conductive pattern between each of the plurality of capacitor layers having a positive and a negative potential, thereby increasing a capacitance thereof.

3. The printed circuit ultra-thin capacitor of claim 1 or 2, wherein a capacitance per unit area thereof and per capacitor layer is about 0.5 nF/cm²to about 1 nF/cm².

4. The printed circuit ultra-thin capacitor of any one of claims 1-3, wherein the thickness of each of the first and the second conductive layers is in a range of about 0.5 um to about 1.5 um.

5. The printed circuit ultra-thin capacitor of any one of claims 1 -4, wherein a thickness of the adhesive resin is in a range of about 12 um to about 50 um.

6. The printed circuit ultra-thin capacitor of any one of claims 1-5, wherein the adhesive resin is made of or comprises an acrylic resin, an epoxy resin, or polyimide.

7. The printed circuit ultra-thin capacitor of any one of claims 1-6, wherein the dielectric layer is made of or comprises an acrylic resin, an epoxy resin, or polyimide.

8. The printed circuit ultra-thin capacitor of claim 7, wherein the dielectric layer comprises one or more of high permittivity additives: AI2O3, TiCh, BaTiOs or a combination thereof.

9. The printed circuit ultra-thin capacitor of any one of claims 1-8, wherein the plurality of capacitor layers comprises at least about 5 capacitor layers.

10. The printed circuit ultra-thin capacitor of any one of claims 1-9, wherein the plurality of capacitor layers comprises about 20 capacitor layers, and wherein the total thickness of the printed circuit board and of the capacitor is about 0.8 mm.

11. The printed circuit ultra-thin capacitor of any one of claims 1-10, wherein a capacitance of the printed circuit ultra-thin capacitor is about 40 nF, and wherein a total area of the plurality of capacitor layers is about 5 cm².

12. The printed circuit ultra-thin capacitor of any one of claims 1-11, wherein the capacitor is flexible.

13. The printed circuit ultra-thin capacitor of claim 12, wherein each of the plurality of capacitor layers is capable of bending to a radius of about 10 cm to about 20 cm.

14. The printed circuit ultra-thin capacitor of any one of claims 1-13 wherein a top and a bottom of a first portion of the multilayered structure is coated with an insulating protective layer, the insulating protective layer is configured to provide electrical insulation, thereby avoiding a surface breakdown of the capacitor.

15. The printed circuit ultra-thin capacitor of any one of claims 1-14, wherein contact pads are formed on a top and a bottom of a second portion of the multilayered structure, wherein the contact pads comprise copper, and wherein the contact pads are coated with finish layer, the finish layer comprising one or more of: nickel, gold, silver, tin.

16. The printed circuit ultra-thin capacitor of claim 15 , wherein a thickness of the finish layer is between about 0.1 um to about 20 um.

17. A method of manufacturing a printed circuit ultra-thin capacitor, the method comprising: obtaining a plurality of capacitor layers, each of the plurality of capacitor layers comprises a first and a second conductive copper layer, and a dielectric layer positioned between the first and the second conductive copper layers; performing a first surface treatment, the first surface treatment comprising a pre-patterning surface treatment and a first micro-etching of the first and the second conductive copper layers, the first micro-etching is configured to adjust a surface roughness of the first and the second conductive copper layers; forming a pattern on each of the first and the second conductive copper layers; performing a second surface treatment, the second surface treatment comprising a post-patterning surface treatment and a second micro-etching; stacking the plurality of capacitor layers one above the other, the stacking comprises applying an adhesive resin configured to attach the plurality of capacitor layers to one another and laminating thereof, thereby forming a multilayered structure; drilling to form through-holes configured to electrically connect each of first and second conductive copper layer having positive and negative potential; electroplating the through-holes; forming an external pattern to obtain contact pads; applying an isolating coating layer on at least on a portion of the multilayered structure; performing a fourth surface treatment, the fourth surface treatment comprising surface cleaning and a fourth micro-etching, the fourth surface cleaning is configured to remove copper oxide from the contact pads; and performing surface finish of the multilayered structure.

18. The method of claim 17, wherein the first micro-etching and/or the second microetching and/or the third micro-etching and/or the fourth micro-etching comprises a wet etching process.

19. The method of claim 17 or 18, wherein the first micro-etching and/or the second micro-etching and/or the third micro-etching and/or the fourth micro-etching is configured to remove about 0.5 um or less.

20. The method of any one of claims 17-19, wherein the first micro-etching, the second micro-etching and the third micro-etching and/or the fourth micro-etching remove not more than about 2 um.

21. The method of any one of claims 17-20, wherein a thickness of the adhesive resin is at least about a sum of an approximate thickness of the first and the second conductive copper layers and an approximate depth of the gaps in the copper pattern.

22. The method of any one of claims 17-21, wherein forming the pattern comprises performing a resist lamination; laser direct imaging to expose the resist, wherein the resist is solid; developing the resist; and removing material from the first and the second conductive copper layers.

23. The method of any one of claims 17-22, wherein obtaining the plurality of capacitor layers comprises obtaining the first and the second conductive copper layer having a thickness of about 3 urn or less.