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WO2025039646A1 - Mémoire, circuit de mémoire, et procédé de fonctionnement pour circuit de mémoire - Google Patents

Mémoire, circuit de mémoire, et procédé de fonctionnement pour circuit de mémoire Download PDF

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Publication number
WO2025039646A1
WO2025039646A1 PCT/CN2024/095424 CN2024095424W WO2025039646A1 WO 2025039646 A1 WO2025039646 A1 WO 2025039646A1 CN 2024095424 W CN2024095424 W CN 2024095424W WO 2025039646 A1 WO2025039646 A1 WO 2025039646A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
voltage
memory cell
memory
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/095424
Other languages
English (en)
Chinese (zh)
Inventor
于涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Publication of WO2025039646A1 publication Critical patent/WO2025039646A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

Definitions

  • Each storage unit in the storage circuit can be individually erased, read and programmed without affecting other storage units.
  • the memory circuit is used in neural network calculations, and the transconductance value of each storage unit is used as the weight connecting the input and output in the neural network. Due to the stability of the transconductance of each storage unit structure, it is beneficial to improve the reliability of the calculation accuracy of the neural network system.
  • a programming operation is performed on a selected single memory cell, a first programming voltage is applied to a control gate line EPHGi corresponding to the memory cell, and a second programming voltage is applied to a source line SLj corresponding to the memory cell, wherein the first programming voltage is less than the second programming voltage.
  • the first read voltage ranges from 1 volt to 2 volts; the second read voltage ranges from 0.5 volt to 2 volts.
  • the erasing operation further includes: applying an anti-erase voltage to the source line SLj of the unselected memory cell, wherein the anti-erase voltage is a positive voltage to prevent an erroneous erasure operation.
  • the anti-mis-erasure voltage ranges from 5V to 10V.
  • the above storage circuit can be used in a neural network computing system, specifically for implementing a product operation.
  • the input voltage V i applied to the control gate line EPHGi in the read operation is used as the neuron value Xi of the input layer of the neural network
  • the accumulated output current I j from the bit line BLi is used as the neuron value Y j of the output layer of the neural network
  • the transconductance G ji of a single storage unit is used as the weight W ji connecting the input layer and the output layer in the neural network.
  • the input voltage V 0 applied to the control gate line EPHG0 in the read operation is used as the neuron value X 0 of the input layer of the neural network
  • the accumulated output current I 0 from the bit line BL0 is used as the neuron value Y 0 of the output layer of the neural network
  • the transconductance G 00 of a single storage cell is used as the weight W 00 connecting the input layer and the output layer in the neural network.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne une mémoire, un circuit de mémoire, et un procédé de fonctionnement pour un circuit de mémoire. Le circuit de mémoire comprend : plusieurs cellules de mémoire, qui sont agencées en un réseau, pendant une opération de programmation, des grilles de commande (206) étant utilisées pour appliquer des premières tensions de programmation, de sorte que des électrons soient extraits des grilles de commande (206) vers des grilles flottantes (204), et pendant une opération d'effacement, les grilles de commande (206) étant utilisées pour appliquer des tensions d'effacement, de sorte que les électrons soient extraits des grilles flottantes (204) vers les grilles de commande (206) ; des régions dopées par ligne de source (207), dont chacune est située dans un substrat (200) au niveau de la partie inférieure d'une couche de ligne de source (202) ; des régions dopées par ligne de bits (208), dont chacune est située dans le substrat (200) entre des grilles de lignes de mots (201) de deux structures de cellules de mémoire adjacentes ; des lignes de mots (WLi), qui sont connectées électriquement aux grilles de lignes de mots (201) des cellules de mémoire dans la même rangée ; des lignes de bits (BLj), qui sont connectées électriquement aux régions dopées par ligne de bits (208) des cellules de mémoire dans la même colonne ; des lignes de source (SLj), qui sont connectées électriquement aux couches de ligne de source (202) des cellules de mémoire dans la même colonne ; et des lignes de grille de commande (EPHGi), qui sont connectées électriquement aux grilles de commande (206) des cellules de mémoire dans la même rangée. La stabilité de transconductance des structures de cellules de mémoire est ainsi améliorée.
PCT/CN2024/095424 2023-08-18 2024-05-27 Mémoire, circuit de mémoire, et procédé de fonctionnement pour circuit de mémoire Pending WO2025039646A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202311050044.0 2023-08-18
CN202311050044.0A CN117079692A (zh) 2023-08-18 2023-08-18 存储器、存储器电路及存储器电路的工作方法

Publications (1)

Publication Number Publication Date
WO2025039646A1 true WO2025039646A1 (fr) 2025-02-27

Family

ID=88716606

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/095424 Pending WO2025039646A1 (fr) 2023-08-18 2024-05-27 Mémoire, circuit de mémoire, et procédé de fonctionnement pour circuit de mémoire

Country Status (2)

Country Link
CN (1) CN117079692A (fr)
WO (1) WO2025039646A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117079692A (zh) * 2023-08-18 2023-11-17 上海华虹宏力半导体制造有限公司 存储器、存储器电路及存储器电路的工作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102368479A (zh) * 2011-11-24 2012-03-07 上海宏力半导体制造有限公司 快闪存储器及其制作方法
US20120206969A1 (en) * 2011-02-10 2012-08-16 Grace Semiconductor Manufacturing Corporation Memory Array
CN105990359A (zh) * 2015-02-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 分离栅式闪存器件及制备方法
CN108806749A (zh) * 2018-06-08 2018-11-13 上海华虹宏力半导体制造有限公司 P沟道闪存单元的操作方法
CN117079692A (zh) * 2023-08-18 2023-11-17 上海华虹宏力半导体制造有限公司 存储器、存储器电路及存储器电路的工作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120206969A1 (en) * 2011-02-10 2012-08-16 Grace Semiconductor Manufacturing Corporation Memory Array
CN102368479A (zh) * 2011-11-24 2012-03-07 上海宏力半导体制造有限公司 快闪存储器及其制作方法
CN105990359A (zh) * 2015-02-04 2016-10-05 中芯国际集成电路制造(上海)有限公司 分离栅式闪存器件及制备方法
CN108806749A (zh) * 2018-06-08 2018-11-13 上海华虹宏力半导体制造有限公司 P沟道闪存单元的操作方法
CN117079692A (zh) * 2023-08-18 2023-11-17 上海华虹宏力半导体制造有限公司 存储器、存储器电路及存储器电路的工作方法

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