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WO2025036991A1 - Systèmes et procédés de génération de plan d'échantillonnage hybride et de projection précise de perte de puce - Google Patents

Systèmes et procédés de génération de plan d'échantillonnage hybride et de projection précise de perte de puce Download PDF

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Publication number
WO2025036991A1
WO2025036991A1 PCT/EP2024/073039 EP2024073039W WO2025036991A1 WO 2025036991 A1 WO2025036991 A1 WO 2025036991A1 EP 2024073039 W EP2024073039 W EP 2024073039W WO 2025036991 A1 WO2025036991 A1 WO 2025036991A1
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WIPO (PCT)
Prior art keywords
wafer
sampling plan
sampling
inspection
die
Prior art date
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PCT/EP2024/073039
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English (en)
Inventor
Chenxi Lin
Ying Huang
Ho Young Song
Abhishek Vikram
Zhihuan WANG
Dan Liu
Fuming Wang
Te-Sheng Wang
Nabeel Noor MOIN
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ASML Netherlands BV
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ASML Netherlands BV
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Publication of WO2025036991A1 publication Critical patent/WO2025036991A1/fr
Pending legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/706833—Sampling plan selection or optimisation, e.g. select or optimise the number, order or locations of measurements taken per die, workpiece, lot or batch
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32194—Quality prediction
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32199—If number of errors grow, augment sampling rate for testing
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • the embodiments provided herein relate to generating an inspection tool sampling plan, and more particularly to a hybrid method to improve die loss projection from an inspection result or optimize a wafer region definition and a sampling budget distribution to project die loss with improved accuracy.
  • ICs integrated circuits
  • Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed.
  • SEM scanning electron microscope
  • Various metrology tools are developed and used to check whether the ICs are correctly manufactured.
  • a computational guided inspection (CGI) machine learning model may be used to assist the tools by indicating areas of a wafer to be inspected.
  • the embodiments provided herein disclose a method to generate an inspection tool sampling plan, and more particularly, a hybrid method of improving die loss projection from an inspection result or optimizing a wafer region definition and sampling budget distribution for improved die loss projection.
  • Some embodiments provide systems, methods, apparatuses, and non-transitory computer readable mediums to generate an inspection tool sampling plan.
  • Embodiments may include generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine excursion events; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically low defect probability.
  • Embodiments provide systems, methods, apparatuses, and non-transitory computer readable mediums for defect detection using a computational guided inspection sampling plan.
  • Embodiments may include generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabrication data and a computational model; applying the baseline sampling plan to a sample; and applying the excursion event sampling plan to the sample when predicted defect probabilities exceed a threshold in an area of the sample with historically low defect probability.
  • Embodiments provide systems, methods, apparatuses, and non-transitory computer readable mediums to generate an inspection tool sampling plan.
  • Embodiments may include providing input data for a wafer to a computational defect probability prediction model; determining defective die probabilities for a first region of the wafer from the computational defect probability prediction model; and generating a sampling plan for the wafer based on the determined defective die probabilities for the first region of the wafer and based on a pre-determined second region of the wafer.
  • Fig. 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system, consistent with embodiments of the present disclosure.
  • EBI electron beam inspection
  • Fig. 2A is a schematic diagram illustrating an exemplary multi-beam system that is part of the exemplary charged particle beam inspection system of Fig. 1, consistent with embodiments of the present disclosure.
  • Fig. 2B is a schematic diagram illustrating an exemplary single -beam system that is part of the exemplary charged particle beam inspection system of Fig. 1, consistent with embodiments of the present disclosure.
  • Fig. 3 is a schematic block diagram illustrating throughput to generate input data, consistent with embodiments of the present disclosure.
  • Fig. 4 is an example flow diagram of a method to project die loss from an inspection result using a sampling plan generated from input data defining a wafer region and a sampling budget per wafer distribution, consistent with embodiments of the present disclosure.
  • Fig. 5 is an example illustration of required input for the empirical sampling plan, consistent with embodiments of the present disclosure.
  • Fig. 6 is an example flow diagram of a method to generate a dynamic sampling plan for a wafer and projecting die loss from an inspection result according to a non-uniform defect density distribution within a wafer as predicted by a computational model, consistent with embodiments of the present disclosure.
  • Fig. 7 is an example flow diagram of a method to generate a dynamic sampling plan for a wafer without a pre-determined sampling budget distribution per wafer region, consistent with embodiments of the present disclosure.
  • Fig. 8 is an example sampling plan or estimated defective die probability map, consistent with embodiments of the present disclosure.
  • Fig. 9 is an example flow diagram of a method to generate a dynamic sampling plan for a wafer without a pre-determined wafer region definition and sampling budget distribution per wafer region, consistent with embodiments of the present disclosure.
  • Figs. 10A and 10B are an example estimated defective die probability map used to evaluate a wafer region definition and an example accumulated defective die probability plot, consistent with embodiments of the present disclosure.
  • Fig. 11 is an example flow diagram of a method to directly optimize a wafer region definition and sampling budget distribution based on the die loss projection R 2 correlation score, consistent with embodiments of the present disclosure.
  • Fig. 12 shows exemplary sampling plans for a wafer, consistent with embodiments of the present disclosure.
  • Fig. 13 shows exemplary metrology sampling plans for a wafer, consistent with embodiments of the present disclosure.
  • Fig. 14 shows an example static sampling plan portion of a hybrid sampling plan, consistent with embodiments of the present disclosure.
  • Fig. 15 shows a diagram of an example static sampling plan portion of a hybrid sampling plan, consistent with embodiments of the present disclosure.
  • Fig. 16 is an example flow diagram of a method to generate a hybrid sampling plan for a wafer, consistent with embodiments of the present disclosure.
  • Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate.
  • the semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, or the like.
  • Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs.
  • the size of these circuits has decreased dramatically so that many more of them can be fit on the substrate.
  • the enhanced computing power of electronic devices while reducing the physical size of the devices, can be accomplished by significantly increasing the packing density of circuit components such as transistors, capacitors, diodes, etc. on an IC chip.
  • an IC chip of a smart phone which is the size of a thumbnail, may include over 2 billion transistors, the size of each transistor being less than l/1000th of a human hair.
  • ICs may be manufactured using lithography, which is a fabrication process involving creating complex circuit patterns drawn on a mask deposited onto a substrate.
  • Lithography may be performed by a lithographic apparatus, which is a machine that applies a source of radiation (e.g., light or X-ray) onto a target portion of the substrate to form a desired pattern.
  • the target portion of the substrate may be covered with a pattern device (e.g., mask) that may be either eliminated or developed after exposure to the radiation source.
  • This process of transferring the desired pattern to the substrate is called a patterning process.
  • the patterning process may include a patterning step to transfer a pattern from a pattern device (e.g., a mask) to the substrate.
  • Variations in experimental parameters e.g., stochastic variations, errors, or noise due to an inspection tool or pattern processing tool
  • HVM high volume manufacturing
  • process yield of ICs and introduce defects into IC structures.
  • the substrate is provided with one or more sets of alignment marks.
  • Each mark is a structure having a position that can be measured later using, for example, an electron beam inspection tool. Defects may occur in which an applied pattern structure or pattern layer is incorrectly placed in relation to a reference mark, or when the fabrication conditions are suboptimal.
  • a reference mark or layout define the desired structure, structure dimensions, and the distance between IC structures (such as gates, capacitors, etc.) or interconnect lines.
  • a critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the critical dimension determines the overall size and packing density of the designed IC.
  • a goal in IC fabrication is to faithfully reproduce the original IC design on the substrate. If an error occurs during fabrication where the created IC design pattern does not match the reference design, this may result in a defect in the IC structure and render the IC inoperable.
  • One component of improving process yield and wafer throughput may be monitoring the IC fabrication process to ensure a desired number of defect-free ICs are produced.
  • One way to monitor the fabrication process is to inspect the chip circuit structures at various stages of fabrication. Inspection using tools such as, for example, a charged particle beam inspection tool may be used to this effect to maintain high process yield and high wafer throughput.
  • Inspection of a wafer using an electron beam inspection tool may generate images of the wafer to measure IC structure dimensions. The measured dimensions may be compared to a reference structure absent any defects to determine the presence of defects in the imaged structure. If the structure is defective, then the fabrication process can be adjusted, so the defect is less likely to recur.
  • inspection of ICs for defect detection is often a time-consuming process and may not inspect a wafer at a correct location to identify a defect.
  • Typical methods have been applied to estimate, or project, a total number of defective die on a wafer at the end of production using inspection results of a wafer during HVM.
  • the total number of defective die on a wafer is referred to as the die loss per wafer.
  • Typical methods rely on an empirical or fixed sampling plan (e.g., a purely static sampling plan generated from a stacked probe probability map) to guide inspection for each wafer inspected during HVM.
  • the sampling plan is a two-dimensional map of a wafer indicating where a particular defective die may be located.
  • Typical methods use historical inspection results identifying defective die from previously inspected wafers to generate the sampling plan (e.g., by focusing on areas of a wafer with a historically high defect probability, such as the edge or the center of the wafer).
  • the sampling plan is divided into wafer regions, where each wafer region has a determined number of die to inspect (e.g., a sampling budget). Wafer inspection may occur inline with wafer fabrication and each wafer that is inspected during wafer fabrication is inspected according to this sampling plan. After obtaining inspection results for a wafer using the empirical and fixed sampling plan, the die loss for the wafer at the end of production is projected with the assumption that the defect density or distribution within each wafer region is uniform.
  • the projected die loss may be used to confirm a satisfactory wafer yield is maintained throughout manufacturing and to estimate the failure rate, or actual die loss per wafer, at the end of production. Wafer processing continues until a batch of wafers are fully fabricated, and then the actual die loss is measured by applying a probe test to the fabricated wafer in the batch. A final metric to evaluate the accuracy of this typical method may be to determine the R 2 correlation score between the projected die loss per wafer and the actual die loss per wafer.
  • the typical method described above may not be desirable because it may limit the accuracy of projecting die loss per wafer from inspection results.
  • Using a fixed sampling plan to guide inspection for every wafer inspected during HVM may not be responsive to wafer to wafer variation that occurs during wafer processing. This method may therefore not be optimal regarding efficiently capturing defective die in each wafer inspected.
  • the typical method to project die loss also assumes a uniform defect density or distribution within each wafer, which may not accurately reflect actual defect density or distribution within a wafer.
  • typical solely static sampling plans may miss any systematic defect signatures in wafer areas where defects rarely appear. Solely static sampling plans do not adequately address unexposed defect mechanisms and do not capture future excursion wafers effectively.
  • Other typical methods may include a model-based method to generate a defect probability estimate based on incoming wafer metrology data to generate a dynamic sampling plan.
  • the dynamic sampling plan may be used to guide inspection of a wafer during HVM.
  • Typical methods may provide a method to more accurately project die loss without assuming a uniform defect density or distribution within a wafer using a model-based scaling factor.
  • these typical methods may use pretrained computational models to convert a probability estimate into a dynamic sampling plan for inline e-beam inspection, thereby increasing inspection efficiency by inspecting only the areas of the wafer predicted by the model to have a high probability of defects.
  • the inspection results can also be used to project the die loss per wafer at the end of production (e.g., wafer probe results).
  • the final metrics of these dynamic sampling plans are the correlation R 2 between the projected versus the actual die loss and the capture rate of excursion fingerprints.
  • Solely dynamic sampling plan methods may also suffer from constraints.
  • a static or semi-static electron scan die-level sampling plan may be preferred for device yield monitoring purposes in the fabrication of the wafer such that any yield excursion event caught by the monitoring system can be confirmed to be a real yield fluctuation rather than a result of a change in the sampling plan from wafer to wafer.
  • Typical solely dynamic sample plans may be disadvantageous in that it forces the user to change the line monitoring method, risking an unstable baseline.
  • solely dynamic sampling plans are generated from model probability predictions based on the in-line metrology values. Due to throughput constraints, the data used by sampling plans based on in-line metrology are typically much sparser compared to probe data, which is available for every die on the wafer. Therefore, the resolution and accuracy of the model prediction results of a solely dynamic sampling plan may be limited. For example, a solely dynamic sampling plan may lead to poor defect capture capability and missing defect fingerprints. Solely dynamic sampling plans do not adequately address unexposed defect mechanisms and do not capture future excursion wafers effectively.
  • Embodiments of the present disclosure address the above described constraints by generating a hybrid sampling plan that includes a static sampling plan portion and a dynamic sampling plan portion.
  • the static sampling plan portion may maintain a stable baseline by sampling a wafer at locations that historically have wafer defects.
  • the dynamic sampling plan portion may generate an excursion event sampling plan based on fabrication data and a computational model, thereby accounting for a nonuniform defect density or distribution within a wafer and improving resolution and accuracy of the model.
  • a component may include A, B, or C
  • the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
  • FIG. 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure.
  • EBI system 100 may be used for imaging.
  • EBI system 100 includes a main chamber 101, a load/lock chamber 102, an electron beam tool 104, and an equipment front end module (EFEM) 106.
  • Electron beam tool 104 is located within main chamber 101.
  • EFEM 106 includes a first loading port 106a and a second loading port 106b.
  • EFEM 106 may include additional loading port(s).
  • First loading port 106a and second loading port 106b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably).
  • a “lot” is a plurality of wafers that may be loaded for processing as a batch.
  • One or more robotic arms (not shown) in EFEM 106 may transport the wafers to load/lock chamber 102.
  • Load/lock chamber 102 is connected to a load/lock vacuum pump system (not shown) which removes gas molecules in load/lock chamber 102 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load/lock chamber 102 to main chamber 101.
  • Main chamber 101 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by electron beam tool 104.
  • Electron beam tool 104 may be a single-beam system or a multi-beam system.
  • a controller 109 is electronically connected to electron beam tool 104. Controller 109 may be a computer configured to execute various controls of EBI system 100. While controller 109 is shown in Fig. 1 as being outside of the structure that includes main chamber 101, load/lock chamber 102, and EFEM 106, it is appreciated that controller 109 may be a part of the structure.
  • controller 109 may include one or more processors (not shown).
  • a processor may be a generic or specific electronic device capable of manipulating or processing information.
  • the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controllers, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field- Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing.
  • the processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.
  • controller 109 may further include one or more memories (not shown).
  • a memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus).
  • the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device.
  • the codes may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks.
  • the memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.
  • Embodiments of this disclosure may provide a single charged-particle beam imaging system (“single -beam system”). Compared with a single-beam system, a multiple charged-particle beam imaging system (“multi-beam system”) may be designed to optimize throughput for different scan modes. Embodiments of this disclosure provide a multi-beam system with the capability of optimizing throughput for different scan modes by using beam arrays with different geometries and adapting to different throughputs and resolution requirements.
  • FIG. 2A is a schematic diagram illustrating an exemplary electron beam tool 104 including a multi-beam inspection tool that is part of the EBI system 100 of Fig. 1, consistent with embodiments of the present disclosure.
  • electron beam tool 104 may be operated as a single-beam inspection tool that is part of EBI system 100 of Fig. 1.
  • Multi-beam electron beam tool 104 (also referred to herein as apparatus 104) comprises an electron source 201, a Coulomb aperture plate (or “gun aperture plate”) 271, a condenser lens 210, a source conversion unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by motorized stage 209 to hold a sample 208 (e.g., a wafer or a photomask) to be inspected.
  • Multi-beam electron beam tool 104 may further comprise a secondary projection system 250 and an electron detection device 240.
  • Primary projection system 230 may comprise an objective lens 231.
  • Electron detection device 240 may comprise a plurality of detection elements 241, 242, and 243.
  • a beam separator 233 and a deflection scanning unit 232 may be positioned inside primary projection system 230.
  • Electron source 201, Coulomb aperture plate 271, condenser lens 210, source conversion unit 220, beam separator 233, deflection scanning unit 232, and primary projection system 230 may be aligned with a primary optical axis 204 of apparatus 104.
  • Secondary projection system 250 and electron detection device 240 may be aligned with a secondary optical axis 251 of apparatus 104.
  • Electron source 201 may comprise a cathode (not shown) and an extractor or anode (not shown), in which, during operation, electron source 201 is configured to emit primary electrons from the cathode and the primary electrons are extracted or accelerated by the extractor and/or the anode to form a primary electron beam 202 that form a primary beam crossover (virtual or real) 203.
  • Primary electron beam 202 may be visualized as being emitted from primary beam crossover 203.
  • Source conversion unit 220 may comprise an image-forming element array (not shown), an aberration compensator array (not shown), a beam-limit aperture array (not shown), and a pre-bending micro-deflector array (not shown).
  • the pre-bending micro-deflector array deflects a plurality of primary beamlets 211, 212, 213 of primary electron beam 202 to normally enter the beam-limit aperture array, the image-forming element array, and an aberration compensator array.
  • apparatus 104 may be operated as a single -beam system such that a single primary beamlet is generated.
  • condenser lens 210 is designed to focus primary electron beam 202 to become a parallel beam and be normally incident onto source conversion unit 220.
  • the image-forming element array may comprise a plurality of micro-deflectors or micro-lenses to influence the plurality of primary beamlets 211, 212, 213 of primary electron beam 202 and to form a plurality of parallel images (virtual or real) of primary beam crossover 203, one for each of the primary beamlets 211, 212, and 213.
  • the aberration compensator array may comprise a field curvature compensator array (not shown) and an astigmatism compensator array (not shown).
  • the field curvature compensator array may comprise a plurality of micro-lenses to compensate field curvature aberrations of the primary beamlets 211, 212, and 213.
  • the astigmatism compensator array may comprise a plurality of micro-stigmators to compensate astigmatism aberrations of the primary beamlets 211, 212, and 213.
  • the beam-limit aperture array may be configured to limit diameters of individual primary beamlets 211, 212, and 213.
  • Fig. 2A shows three primary beamlets 211, 212, and 213 as an example, and it is appreciated that source conversion unit 220 may be configured to form any number of primary beamlets.
  • Controller 109 may be connected to various parts of EBI system 100 of Fig. 1, such as source conversion unit 220, electron detection device 240, primary projection system 230, or motorized stage 209. In some embodiments, as explained in further details below, controller 109 may perform various image and signal processing functions. Controller 109 may also generate various control signals to govern operations of the charged particle beam inspection system.
  • Condenser lens 210 is configured to focus primary electron beam 202. Condenser lens 210 may further be configured to adjust electric currents of primary beamlets 211, 212, and 213 downstream of source conversion unit 220 by varying the focusing power of condenser lens 210. Alternatively, the electric currents may be changed by altering the radial sizes of beam-limit apertures within the beam-limit aperture array corresponding to the individual primary beamlets. The electric currents may be changed by both altering the radial sizes of beam-limit apertures and the focusing power of condenser lens 210. Condenser lens 210 may be an adjustable condenser lens that may be configured so that the position of its first principal plane is movable.
  • the adjustable condenser lens may be configured to be magnetic, which may result in off-axis beamlets 212 and 213 illuminating source conversion unit 220 with rotation angles. The rotation angles change with the focusing power or the position of the first principal plane of the adjustable condenser lens.
  • Condenser lens 210 may be an anti-rotation condenser lens that may be configured to keep the rotation angles unchanged while the focusing power of condenser lens 210 is changed.
  • condenser lens 210 may be an adjustable anti-rotation condenser lens, in which the rotation angles do not change when its focusing power and the position of its first principal plane are varied.
  • Objective lens 231 may be configured to focus beamlets 211, 212, and 213 onto a sample 208 for inspection and may form, in the current embodiments, three probe spots 221, 222, and 223 on the surface of sample 208.
  • Coulomb aperture plate 271 in operation, is configured to block off peripheral electrons of primary electron beam 202 to reduce Coulomb effect. The Coulomb effect may enlarge the size of each of probe spots 221, 222, and 223 of primary beamlets 211, 212, 213, and therefore deteriorate inspection resolution.
  • Beam separator 233 may, for example, be a Wien filter comprising an electrostatic deflector generating an electrostatic dipole field and a magnetic dipole field (not shown in Fig. 2A).
  • beam separator 233 may be configured to exert an electrostatic force by electrostatic dipole field on individual electrons of primary beamlets 211, 212, and 213.
  • the electrostatic force is equal in magnitude but opposite in direction to the magnetic force exerted by magnetic dipole field of beam separator 233 on the individual electrons.
  • Primary beamlets 211, 212, and 213 may therefore pass at least substantially straight through beam separator 233 with at least substantially zero deflection angles.
  • Deflection scanning unit 232 in operation, is configured to deflect primary beamlets 211, 212, and 213 to scan probe spots 221, 222, and 223 across individual scanning areas in a section of the surface of sample 208.
  • primary beamlets 211, 212, and 213 or probe spots 221, 222, and 223 on sample 208 electrons emerge from sample 208 and generate three secondary electron beams 261, 262, and 263.
  • Each of secondary electron beams 261, 262, and 263 typically comprise secondary electrons (having electron energy ⁇ 50eV) and backscattered electrons (having electron energy between 50eV and the landing energy of primary beamlets 211, 212, and 213).
  • Beam separator 233 is configured to deflect secondary electron beams 261, 262, and 263 towards secondary projection system 250.
  • Secondary projection system 250 subsequently focuses secondary electron beams 261, 262, and 263 onto detection elements 241, 242, and 243 of electron detection device 240.
  • Detection elements 241, 242, and 243 are arranged to detect corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals which are sent to controller 109 or a signal processing system (not shown), e.g., to construct images of the corresponding scanned areas of sample 208.
  • detection elements 241, 242, and 243 detect corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109).
  • each detection element 241, 242, and 243 may comprise one or more pixels.
  • the intensity signal output of a detection element may be a sum of signals generated by all the pixels within the detection element.
  • controller 109 may comprise image processing system that includes an image acquirer (not shown), a storage (not shown).
  • the image acquirer may comprise one or more processors.
  • the image acquirer may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof.
  • the image acquirer may be communicatively coupled to electron detection device 240 of apparatus 104 through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, among others, or a combination thereof.
  • the image acquirer may receive a signal from electron detection device 240 and may construct an image.
  • the image acquirer may thus acquire images of sample 208.
  • the image acquirer may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like.
  • the image acquirer may be configured to perform adjustments of brightness and contrast, etc. of acquired images.
  • the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer readable memory, and the like.
  • the storage may be coupled with the image acquirer and may be used for saving scanned raw image data as original images, and post-processed images.
  • the image acquirer may acquire one or more images of a sample based on an imaging signal received from electron detection device 240.
  • An imaging signal may correspond to a scanning operation for conducting charged particle imaging.
  • An acquired image may be a single image comprising a plurality of imaging areas.
  • the single image may be stored in the storage.
  • the single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of sample 208.
  • the acquired images may comprise multiple images of a single imaging area of sample 208 sampled multiple times over a time sequence.
  • the multiple images may be stored in the storage.
  • controller 109 may be configured to perform image processing steps with the multiple images of the same location of sample 208.
  • controller 109 may include measurement circuitries (e.g., analog-to- digital converters) to obtain a distribution of the detected secondary electrons.
  • the electron distribution data collected during a detection time window in combination with corresponding scan path data of each of primary beamlets 211, 212, and 213 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection.
  • the reconstructed images can be used to reveal various features of the internal or external structures of sample 208, and thereby can be used to reveal any defects that may exist in the wafer.
  • controller 109 may control motorized stage 209 to move sample 208 during inspection of sample 208. In some embodiments, controller 109 may enable motorized stage 209 to move sample 208 in a direction continuously at a constant speed. In other embodiments, controller 109 may enable motorized stage 209 to change the speed of the movement of sample 208 over time depending on the steps of scanning process.
  • Fig. 2A shows that apparatus 104 uses three primary electron beams, it is appreciated that apparatus 104 may use one, two, or more number of primary electron beams. The present disclosure does not limit the number of primary electron beams used in apparatus 104. In some embodiments, apparatus 104 may be a SEM used for lithography. In some embodiments, electron beam tool 104 may be a single-beam system or a multi-beam system.
  • an electron beam tool 100B may be a single -beam inspection tool that is used in EBI system 10, consistent with embodiments of the present disclosure.
  • Apparatus 100B includes a wafer holder 136 supported by motorized stage 134 to hold a wafer 150 to be inspected.
  • Electron beam tool 100B includes an electron emitter, which may comprise a cathode 103, an anode 121, and a gun aperture 122.
  • Electron beam tool 100B further includes a beam limit aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144.
  • Objective lens assembly 132 may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an exciting coil 132d.
  • an electron beam 161 emanating from the tip of cathode 103 may be accelerated by anode 121 voltage, pass through gun aperture 122, beam limit aperture 125, condenser lens 126, and be focused into a probe spot 170 by the modified SORIL lens and impinge onto the surface of wafer 150.
  • Probe spot 170 may be scanned across the surface of wafer 150 by a deflector, such as deflector 132c or other deflectors in the SORIL lens.
  • Secondary or scattered primary particles, such as secondary electrons or scattered primary electrons emanated from the wafer surface may be collected by detector 144 to determine intensity of the beam and so that an image of an area of interest on wafer 150 may be reconstructed.
  • Image acquirer 120 may comprise one or more processors.
  • image acquirer 120 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof.
  • Image acquirer 120 may connect with detector 144 of electron beam tool 100B through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof.
  • Image acquirer 120 may receive a signal from detector 144 and may construct an image. Image acquirer 120 may thus acquire images of wafer 150.
  • Image acquirer 120 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. Image acquirer 120 may be configured to perform adjustments of brightness and contrast, etc. of acquired images.
  • Storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, other types of computer readable memory, and the like. Storage 130 may be coupled with image acquirer 120 and may be used for saving scanned raw image data as original images, and post-processed images.
  • Image acquirer 120 and storage 130 may be connected to controller 109. In some embodiments, image acquirer 120, storage 130, and controller 109 may be integrated together as one electronic control unit.
  • image acquirer 120 may acquire one or more images of a sample based on an imaging signal received from detector 144.
  • An imaging signal may correspond to a scanning operation for conducting charged particle imaging.
  • An acquired image may be a single image comprising a plurality of imaging areas that may contain various features of wafer 150.
  • the single image may be stored in storage 130. Imaging may be performed on the basis of imaging frames.
  • the condenser and illumination optics of the electron beam tool may comprise or be supplemented by electromagnetic quadrupole electron lenses.
  • electron beam tool 100B may comprise a first quadrupole lens 148 and a second quadrupole lens 158.
  • the quadrupole lenses are used for controlling the electron beam.
  • first quadrupole lens 148 can be controlled to adjust the beam current
  • second quadrupole lens 158 can be controlled to adjust the beam spot size and beam shape.
  • Fig. 2B illustrates a charged particle beam apparatus in which an inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with wafer 150.
  • Detector 144 may be placed along optical axis 105, as in the embodiment shown in Fig. 2B.
  • the primary electron beam may be configured to travel along optical axis 105.
  • detector 144 may include a hole at its center so that the primary electron beam may pass through to reach wafer 150.
  • FIG. 3 is an example block diagram for generating input data, consistent with embodiments of the present disclosure.
  • Input data may be generated using two steps as illustrated in Fig. 3.
  • a lithographic projection apparatus 301 may be used to fabricate a wafer at a constant fabrication condition (e.g., a focus and dose for a radiation source).
  • An inspection tool 302 e.g., EBI system 100 of Fig. 1, electron beam tool 104 of Fig. 2A, electron beam tool 100B of Fig. 2B
  • Metrology information may include, but is not limited to, necking, line pull back, line thinning, critical dimension, edge placement, overlapping (e.g., overlay between layers of a wafer), resist top loss, resist undercut, missing defects, and bridging defects of an IC structure on a wafer.
  • a processor 303 e.g., controller 109 in Fig. 1, controller 109 of Fig. 2A, controller 109 of Fig. 2B
  • a memory may be communicatively connected to inspection tool 302 to store the measured metrology information.
  • the images generated by inspection tool 302 may be used for wafer inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region.
  • the reference image may be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect may be identified.
  • inspection tool 302 may scan multiple regions of the wafer, each region including a test device region designed as the same and generate multiple images capturing those test device regions as manufactured. The multiple images may be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect may be identified.
  • processor 303 may be a generic or specific electronic device capable of manipulating or processing information.
  • processor 303 may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing.
  • Processor 303 may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.
  • processor 303 may further include one or more memories (not shown).
  • a memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus).
  • the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device.
  • the codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks.
  • the memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.
  • sampling plan may be generated by compiling historical inspection results (e.g., probe data of one or more wafers) that identify certain locations of wafer defects (e.g., historical probe data that includes die defect data during inspection of a plurality of wafers).
  • generating this sampling plan may include generating a probability estimate map based on the historical probe data of a plurality of samples by averaging the historical probe data (e.g., averaging stacking maps; the probability estimate from stacking/averaging may be the number of wafers where a die is defective divided by the total number of wafers), and generating the static sampling plan based on the generated probability estimate map.
  • applying this sampling plan includes inspecting the sample in an area corresponding to historically high defect probabilities (e.g., gray areas of wafer 1001 of Fig. 10A, sampling regions in sampling plan 1210 of Fig. 12). [0072] This sampling plan is also used for each wafer that is inspected during wafer processing and is thus considered “fixed” or “static.” Once an inspection result for a wafer is obtained via the static sampling plan, the projected die loss may be calculated via the following equations:
  • Equation 1 ' K q lc number of defective dies identified, s v ected j s q-je number of dies inspected, and N d is the number of dies within a wafer zone. Since the static method assumes the defect density or distribution within a wafer region, or zone, is uniform, multiplied by a scaling factor. According to Equation 1, the scaling factor may be considered to be the ratio of N d to j ⁇ / ⁇ ls v ected w
  • static methods require a pre-determined wafer region definition and sampling budget per wafer region distribution in the sampling plan.
  • this may limit the accuracy of the projected die loss (e.g., a suboptimal R 2 correlation score) since defect density or distribution may not be uniform within a wafer region and the pre-determined wafer region definition and sampling budget per wafer region distribution may be highly empirical.
  • static methods maintain the same wafer region definition and sampling budget distribution per wafer region for all incoming wafers. This may limit the versatility of the static method to accurately project the die loss in a variety of wafers, since each wafer may have differences in optimal wafer region definitions or a sampling budget per wafer region.
  • a hybrid sampling plan may use both a static sampling plan and a dynamic sampling plan (e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig. 11), thereby accounting for a nonuniform defect density or distribution within a wafer while still sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • a hybrid sampling plan may use both a static sampling plan and a dynamic sampling plan (e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig. 11), thereby accounting for a nonuniform defect density or distribution within a
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Fig. 4 is an example flow diagram of a method 400 to project die loss for a wafer according to inspection results collected from an empirical static (e.g., constant from wafer to wafer) sampling plan with a fixed wafer region definition and sampling budget per wafer region distribution, consistent with embodiments of the present disclosure.
  • the steps of Fig. 4 may be performed by a computing device (e.g., processor 303 of Fig. 3) and an inspection tool (e.g., inspection tool 302 of Fig. 3).
  • an empirical sampling plan is generated.
  • the sampling plan may be generated based on historical data from a previously inspected wafer or a batch of previously inspected wafers.
  • the historical data may be inspection images that contain identified defects on a wafer.
  • the generated sampling plan may include this historical defect signature.
  • the sampling plan is generated according to a pre-determined wafer region definition and sampling budget per wafer region.
  • the empirical sampling plan is used to guide inspection of a wafer using an inspection tool.
  • the sampling plan may be used to guide the inspection tool during inspection of the wafer.
  • Wafer inspection is conducted according to the pre-determined sampling budget for each wafer region in the sampling plan. Wafer inspection is conducted in-line with HVM. The number of dies inspected in a first wafer region is equal to the sampling budget for the first wafer region, and the same is true for a second wafer region.
  • the die loss for a wafer is projected for a wafer at the end of wafer processing using the obtained inspection results.
  • the die loss for a wafer may be projected for a wafer after development, etching, etc. of the wafer.
  • the die loss projection may be performed as described above in Equation 1 and Equation 2 (e.g., assumes that defect density or distribution within a wafer region is uniform).
  • the actual die loss is obtained by applying a probe test to a wafer at the end of wafer processing.
  • probe results may be applied to the wafer during various steps of wafer processing (e.g., after development, after etching, etc.).
  • the probe test determines if each die on a wafer is defective or not.
  • a R 2 correlation score is evaluated from the actual die loss and the projected die loss. It is appreciated that the R 2 correlation score may be determined from a population of wafers. A first wafer and a second wafer may be inspected according to step 402 and two projected die loss values may be determined according to step 403.
  • the first wafer and the second wafer at the end of wafer processing may be measured according to step 404 to obtain two actual die loss values.
  • a first layer of a wafer and a second layer of the same wafer may be inspected according to step 402 and two projected die loss values may be determined according to step 403.
  • the wafer at the end of wafer processing may be measured according to step 404 to obtain an actual die loss value.
  • a hybrid sampling plan may use both method 400 and a dynamic sampling plan (e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig. 11), thereby accounting for a nonuniform defect density or distribution within a wafer while still sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • a dynamic sampling plan e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig. 11
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Fig. 5 is an example illustration of required input for the empirical sampling plan, consistent with embodiments of the present disclosure.
  • Fig. 5 illustrates a wafer 501 with a first wafer region 502, a second wafer region 503, and a third wafer region 504.
  • Each wafer region has a corresponding sampling budget.
  • Each wafer region definition and corresponding sampling budget per wafer region may not be adjusted according to conventional methods.
  • each wafer region definition is kept constant for each wafer inspected.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig. 5) and a dynamic sampling plan (e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig.
  • a static sampling plan e.g., method 400 of Fig. 4, wafer 501 of Fig. 5
  • a dynamic sampling plan e.g., method 600 of Fig. 6, method 700 of Fig. 7, using wafer 801 of Fig. 8, method 900 of Fig. 9, using wafer 1001 of Fig. 10A, using the plot of Fig. 10, method 1100 of Fig.
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • embodiments of the present disclosure may provide a model-based approach to project die loss during wafer processing.
  • Computational guided inspection processes guide inspection tools to locations on a wafer where there is a higher probability of defects.
  • a machine learning-based CGI model receives input from various data sources, such as wafer characteristic data (which may include scanner data, metrology data, and fabrication process data) and data from inspection results to train the model.
  • a CGI machine learning model may be built and used to output a sampling plan indicating a location on a wafer where defects have likely formed after a wafer processing step, so the inspection tool will go to the sampling location to inspect with a higher efficiency than inspecting wafer locations based on experience (e.g., a history of prior defects detected during scanning).
  • a machine learning-based CGI model may be trained using historical data (e.g., history of prior defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan.
  • the CGI process occurs in-line with wafer fabrication and increases inspection tool efficiency by increasing the accuracy of finding defects on the wafer with capture rates of finding defects higher than a baseline value.
  • the inspection results may be used to confirm a satisfactory wafer yield is maintained throughout manufacturing and to project the failure rate, or die loss per wafer, at the end of production. This projected failure rate may be compared to the results of a wafer probe test, which determines a failure rate for each die fabricated on the wafer.
  • a final metric of a CGI model use case may be the R 2 correlation score between the estimated and measured die defects for a wafer.
  • a CGI model may be applied to characteristic wafer data to estimate a defect probability for each die on a wafer.
  • a sampling plan optimizer or sampling plan generator then converts the estimated defective die probability for each die on a wafer to a die-level sampling decision wafer map (also known as a sampling plan).
  • the sampling plan may be used to modify processing parameters of tools in the fabrication (e.g., parameters of the scanner, parameters of the etcher, etc.) to feedback or feedforward in the fabrication process, thereby mitigating for defects that were identified.
  • the sampling plan may be generated according to input information that defines a pre-determined wafer region definition and sampling budget per wafer region, as well as user- specified sampling options.
  • the sampling plan may provide a die-level binary sampling decision (e.g., inspect or do not inspect a die on a wafer).
  • the sampling plan may then be used to guide an inspection tool (e.g., a scanning electron microscope, SEM, or an optical tool) to a region on the wafer where the sampling plan has a set number of dies to inspect (e.g., a sampling budget).
  • the inspection results obtained via the sampling plan indicate a number of actual defective die present, and the inspection results may then be used to project an estimated die loss for a wafer.
  • a CGI model may be trained using historical data (e.g., history of prior defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan.
  • An R 2 correlation score for the defective die projection provided by the CGI model sampling plan may be determined by collecting the “ground truth” results for a wafer.
  • the “ground truth” results indicate the actual defective die results of a wafer at the end of production and correspond to a probe test result for a fully completed wafer. Accordingly, a probe test result provides accurate identification of defects for each die on a wafer.
  • the final metric of the CGI model and sampling plan optimizer may be the correlation R 2 score between the projected estimated die loss determined by the CGI model and the actual die loss determined by the probe test results.
  • the CGI model provides an output of a defective die probability at a die-to-die level. This means the CGI model estimates a defect probability for each die on a wafer, which may vary from die to die, and from wafer to wafer. The estimated defective die probability may be aggregated to generate a sampling plan for a wafer. Since a sampling plan may be generated for each wafer based on the specific defective die probability for each die on a wafer, the CGI model-generated sampling plan may be referred to as a “dynamic” sampling plan. The dynamic sampling plan may be used to guide the inspection tool during inspection of a wafer to project a die loss for a wafer at the end of wafer processing.
  • the projected die loss is determined without assuming a uniform defect density or distribution within a wafer region.
  • die loss may be projected after an inspection result is collected from an inspection tool guided by the CGI generated dynamic sampling plan.
  • the projected die loss may be calculated via the following equations, consistent with embodiments of the present disclosure: (Equation 3) j . r . sumfdefective die probability of non-sampled dies in region i) ZT .
  • Equation 3 N dd is the number of defective dies, N d is the total number of dies on the wafer, and S L is the scaling factor.
  • the summation in Equation 3 is from one wafer region, i, to the total number of wafer regions, M, on a wafer.
  • the non-sampled dies are the dies not inspected according to the CGI-generated sampling plan, whereas the sampled dies are the dies that are inspected. However, each die in wafer region i has a defective die probability determined by the CGI model.
  • the summation in the numerator in Equation 4 is equivalent to the expected number of defective dies that are not inspected, and the summation in the denominator in the Equation 4 is equivalent to the expected number of defective dies that are inspected.
  • the scaling factor, 5 in Equation 4 may account for non-uniform defect density distribution.
  • the CGI model may determine the dies to inspect (e.g., sampled dies) by ranking the defective die probabilities according to a per-wafer region basis and selecting, for each wafer region, a number of dies based on the ranking of defective die probabilities. The number of dies may be less than or equal to the sampling budget for a wafer region.
  • the CGI-generated dynamic sampling plan may combine an Ni number of dies with the highest defective die probabilities, where Ni is the sampling budget for wafer region i.
  • generating the dynamic sampling plan portion of a hybrid sampling plan may include determining defective die probabilities for a first region of a wafer using a (e.g., trained) computational defect probability prediction model as described above.
  • the first region of the wafer may exclude areas of the wafer that are already included in the static sampling plan portion of the hybrid sampling plan.
  • generating the dynamic sampling plan portion of the hybrid sampling plan may include converting the estimated defective die probabilities of the first region that are above a threshold to a die-level sampling decision wafer map. That is, a hybrid sampling plan may include areas of the wafer covered by the static sampling plan portion and areas of the wafer that historically have low defective die probabilities (the dynamic sampling plan portion). However, the dynamic sampling plan portion may only include dies with defective die probabilities above a certain threshold. Therefore, it is possible that none of the defective die probabilities in the first region of the wafer meet the threshold and the hybrid sampling plan may only include the static sampling plan.
  • the defective die probabilities of the dies in the first region may be lower than the defective die probabilities in the regions of the wafer covered by the static sampling plan (e.g., gray regions of wafer 1001 of Fig. 10A, sampling regions in sampling plan 1210 of Fig. 12).
  • the dynamic sampling plan portion of a hybrid sampling plan may be applied to a sample (in addition to apply the static sampling plan) by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically lower defect probability (e.g., dynamic sampling plans may determine excursion events on a wafer).
  • Fig. 6 is an example flow diagram of a method 600 to generate a dynamic sampling plan for a wafer and projecting die loss from an inspection result assuming non-uniform defect density or distribution within a wafer, consistent with embodiments of the present disclosure.
  • the steps of method 600 may be performed by a computing device, e.g., processor 303 of Fig. 3. It is appreciated that the illustrated method 600 may be altered to modify the order of steps and to include additional steps.
  • a non-uniform defect density or distribution may be obtained from a static stacked probe defect probability estimate or from a prediction of a computational defect probability prediction model.
  • step 601 input data is acquired and supplied to a CGI model.
  • the input data may correspond to metrology information collected from one or more images of a first wafer and a second wafer that are acquired via wafer processing during HVM.
  • the input data may correspond to metrology information collected from one or more images of a first layer of a wafer and a second layer of the same wafer that are acquired.
  • a wafer may be fabricated at a constant fabrication condition (e.g., a lithographic focus, dose condition, etc.).
  • the input data may include a pre-determined wafer region definition and sampling budget distribution.
  • the metrology information may include, but is not limited to, necking, line pull back, line thinning, critical dimension, edge placement, overlapping (e.g., overlay between layers of a wafer), resist top loss, resist undercut, missing defects, and bridging defects on a wafer.
  • an estimated defective die probability for each die on the first wafer is calculated based on the input data for the first wafer.
  • the calculation may be based on identified defects in the input data and is influenced by the input data quality.
  • the calculation may be performed by a processor (e.g., processor 303 in Fig. 3) which may apply the CGI model to the first wafer.
  • the estimated defective die probabilities for all dies on the first wafer are ranked.
  • the estimated defective die probabilities may be ranked on a per-wafer-region basis such that the top Ni dies with the top Ni highest estimated defective die probabilities for each wafer region are considered. As described above, Ni is the sampling budget per wafer region.
  • step 604 a sampling plan for the first wafer is generated based on the wafer region definition and the top Ni dies for each wafer region as determined in step 603.
  • step 605 the generated sampling plan for the first wafer is used to guide the inspection tool during inspection of the first wafer.
  • the inspection tool collects inspection results of the first wafer according to the predicted one or more regions of defects identified by the sampling plan.
  • step 606 the CGI model projects die loss for the first wafer according to the inspection results collected in step 605 and according to Equations 3 and 4.
  • the generated sampling plan may be used to modify processing parameters of tools in the fabrication (e.g., parameters of the scanner, parameters of the etcher, etc.) to feedback or feedforward in the fabrication process, thereby mitigating for defects that were identified.
  • an estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer.
  • the calculation may be performed by one or more processors (e.g., processor 303 in Fig. 3) that may apply the CGI model to the second wafer.
  • the input data of the second wafer is as described above in step 601 and may include a wafer region definition for the second wafer and a sampling budget distribution.
  • the estimated defective die probabilities for all dies on the second wafer may be ranked on a per-wafer-region basis, a sampling plan based on the ranked estimated defective die probabilities may be generated, and a die loss may be projected by repeating steps 603 to 606 but with respect to the second wafer.
  • the sampling plan may be used to modify processing parameters of tools in the fabrication (e.g., parameters of the scanner such as a focus dose, parameters of the etcher, etc.) to compensate for the defect-prone regions.
  • parameters of the scanner e.g., parameters of the scanner such as a focus dose, parameters of the etcher, etc.
  • probe test results may be obtained for the first wafer and the second wafer once fully processed at the end of wafer processing.
  • probe test results may be obtained for the first wafer or the second wafer during various steps of wafer processing (e.g., after development, after etching, etc.).
  • an R 2 correlation score is evaluated by comparing the actual defective die result (e.g., actual die loss) for the first wafer and the second wafter to the estimated defective die probability (e.g., projected die loss) as described above.
  • method 600 may provide a dynamic sampling plan that may guide the inspection tool to an area on a wafer that may contain a greater concentration of possible defective dies compared to the conventional method. Moreover, method 600 may provide a more robust method to project die loss at the end stages of wafer processing. In some embodiments, method 600 may provide a more robust method to project die loss after various stages of wafer processing (e.g., after development, after etching, etc.). Therefore, the die loss projected by method 600 may match better with the ground truth results and the resulting R 2 correlation score may be increased compared to that of a conventional method. In some embodiments, method 600 may compensate for and mitigate die loss by, for example, generating sampling plans which may be used to modify processing parameters of tools in the fabrication (e.g., parameters of the scanner such as a focus dose, parameters of the etcher, etc.).
  • parameters of the scanner such as a focus dose, parameters of the etcher, etc.
  • constraints from a solely dynamic sampling plan may be improved by using a hybrid sampling plan.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig. 5) and a dynamic sampling plan as described above for method 600, thereby accounting for a nonuniform defect density or distribution within a wafer, improving resolution and accuracy of the model, and maintaining a stable baseline by sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Fig. 7 is an example flow diagram of a method 700 to generate a dynamic sampling plan for a wafer without a pre-determined sampling budget distribution per wafer region, consistent with embodiments of the present disclosure.
  • the steps of method 700 may be performed by a computing device, e.g., processor 303 of Fig. 3. It is appreciated that the illustrated method 700 may be altered to modify the order of steps and to include additional steps.
  • step 701 input data is acquired and supplied to a CGI model.
  • the input data may correspond to metrology information collected from one or more images of a first wafer and a second wafer that are acquired via wafer processing during HVM.
  • the input data may correspond to metrology information collected from one or more images of a first layer of a wafer and a second layer of the same wafer that are acquired.
  • a wafer may be fabricated at a constant fabrication condition (e.g., a lithographic focus, dose condition, etc.).
  • the input data may include a pre-determined wafer region definition.
  • the metrology information may include, but is not limited to, necking, line pull back, line thinning, critical dimension, edge placement, overlapping (e.g., overlay between layers of a wafer), resist top loss, resist undercut, missing defects, and bridging defects on a wafer.
  • an estimated defective die probability for each die on the first wafer is calculated based on the input data for the first wafer.
  • the calculation may be based on identified defects in the input data and is influenced by the input data quality.
  • the calculation may be performed by a processor (e.g., processor 303 in Fig. 3) which may apply the CGI model to the first wafer.
  • step 703 a sampling budget for each region on the first wafer is distributed according to the estimated defective die probability for each wafer region.
  • the calculation performed in step 703 may be as follows:
  • SBi represents the sampling budget for a region i on a wafer
  • SB W represents a full wafer sampling budget.
  • the sampling budget for a region on a wafer may be determined by a full wafer sampling budget multiplied by the ratio of the sum of defective die probability in a wafer region to the sum of defective die probability in a full wafer.
  • Nff represents the total number of dies per wafer.
  • the full wafer sampling ratio is a number from 0 to 1 and represents a percentage of dies on a wafer that may be sampled for inspection.
  • step 704 a sampling plan for the first wafer is generated based on the wafer region definition and the distributed sampling budget per wafer region calculated in step 703.
  • the generated sampling plan for the first wafer is used to guide inspection of the first wafer using an inspection tool.
  • the generated sampling plan may be used to guide the inspection tool during inspection of the first wafer.
  • the inspection tool collects inspection results of the first wafer according to the predicted one or more regions of defects identified by the sampling plan.
  • the CGI model projects die loss for the first wafer according to the inspection results collected in step 705. The die loss projection may be performed via Equations 3 and 4.
  • an estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer.
  • the calculation may be performed by a processor (e.g., processor 303 in Fig. 3) which may apply the CGI model to the second wafer.
  • the input data of the second wafer is as described above in step 701 and may include a wafer region definition for the second wafer and a total sampling budget.
  • a sampling budget may be distributed for each wafer region, a sampling plan based on the estimated defective die probability may be generated, and a die loss may be projected by repeating steps 703 to 706 but with respect to the second wafer.
  • probe test results may be obtained for the first wafer and the second wafer once fully processed at the end of wafer processing.
  • probe test results may be obtained for the first wafer or the second wafer during various steps of wafer processing (e.g., after development, after etching, etc.).
  • an R 2 correlation score is evaluated by comparing the actual defective die result (e.g., actual die loss) for the first wafer and the second wafter to the estimated defective die probability (e.g., projected die loss) as described above.
  • method 700 may provide a sampling plan that allocates a greater percentage of the total sampling budget to a wafer region that is identified to contain a greater concentration of possible defective dies compared to the conventional method. Therefore, the estimated defective die probability map may match better with the ground truth results and the resulting R 2 correlation score may be increased compared to that of a conventional method. In some embodiments, method 700 may compensate for and mitigate die loss by, for example, generating sampling plans which may be used to modify processing parameters of tools in the fabrication (e.g., parameters of the scanner such as a focus dose, parameters of the etcher, etc.).
  • constraints from a solely dynamic sampling plan may be improved by using a hybrid sampling plan.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig. 5) and a dynamic sampling plan as described above for method 700, thereby accounting for a nonuniform defect density or distribution within a wafer, improving resolution and accuracy of the model, and maintaining a stable baseline by sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Fig. 8 is an example sampling plan or estimated defective die probability map generated by method 700, consistent with embodiments of the present disclosure.
  • Fig. 8 corresponds to a wafer 801, which contains a die 802.
  • Each die 802 is represented as a square on wafer 801 that is outlined in black.
  • method 700 uses a pre-determined wafer region definition, and so the estimated defective die probability map of Fig. 8 may contain the same definition and number of wafer regions, as for example, that of Fig. 5. It is appreciated that Fig. 8 is for illustration purposes and the wafer region may be any shape or size and the wafer region number may not be so limited.
  • Fig. 8 is for illustration purposes and the wafer region may be any shape or size and the wafer region number may not be so limited.
  • FIG. 8 is represented as a gradient image, where darker color indicates a larger defective die probability and lighter color represents a lower defective die probability.
  • Three wafer regions are illustrated in Fig. 8, where the dotted line 803 represents a first wafer region boundary between a first wafer region and a second wafer region, and the dotted line 804 represents a second wafer region boundary between the second wafer region and a third wafer region.
  • the second wafer region e.g., the region between dotted line 803 and dotted line 804 exhibits the darkest color and thus indicates a wafer region with the largest defective die probability.
  • the sampling plan generated according to method 700 (Fig.
  • Fig. 8 may illustrate different defective die probabilities per wafer region compared to an estimated defective die probability map that may be generated for that of Fig. 5. Therefore, Fig. 8 may illustrate an improved sampling plan or more accurate die loss projection that was generated by following method 700 (in Fig. 7) to optimize a sampling budget distribution per wafer region for wafer inspection while maintaining a pre-determined wafer region definition and total sampling budget per wafer.
  • constraints from a solely dynamic sampling plan may be improved by using a hybrid sampling plan.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig. 5) and a dynamic sampling plan as described above for wafer 801, thereby accounting for a nonuniform defect density or distribution within a wafer, improving resolution and accuracy of the model, and maintaining a stable baseline by sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Fig. 9 is an example flow diagram of a method 900 to generate a sampling plan for a wafer without a pre-determined wafer region definition and sampling budget distribution per wafer region, consistent with embodiments of the present disclosure.
  • the steps of method 900 may be performed by a computing device, e.g., processor 303 of Fig. 3. It is appreciated that the illustrated method 900 may be altered to modify the order of steps and to include additional steps.
  • step 901 input data is acquired and supplied to a CGI model.
  • the input data may correspond to metrology information collected from one or more images of a first wafer and a second wafer that are acquired via wafer processing during HVM.
  • the input data may correspond to metrology information collected from one or more images of a first layer of a wafer and a second layer of the same wafer that are acquired.
  • the wafer processing and metrology information may be as described above. However, the input data does not require a pre-determined wafer region definition and sampling budget distribution per wafer region.
  • an estimated defective die probability for each die on the first wafer is calculated based on the input data for the first wafer.
  • the calculation may be based on identified defects in the input data and is influenced by the input data quality.
  • the calculation may be performed by a processor (e.g., processor 303 in Fig. 3) which may apply the CGI model to the first wafer.
  • an estimated defective die probability map is generated for the first wafer by compiling the defective die probability as described above.
  • a boundary of a wafer region is evaluated to improve uniformity of defective die probability density on the defective die probability map.
  • the uniformity of defective die probability density may be improved by grouping a first die on a wafer with a second die that exhibits a similar defective die probability.
  • Step 904 may be performed in two alternative steps.
  • Step 904_l may be performed by applying the CGI-generated sampling plan from step 903 and performing an image segmentation technique, which may include, but is not limited to, graph cut, Otsu’ s algorithm, edge-based segmentation, threshold-based segmentation, region-based segmentation, cluster-based segmentation, watershed segmentation, semantic segmentation, instance segmentation, panoptic segmentation, and other methods of dividing an image into subgroups.
  • the resulting image segmentation may define a region of dies on a wafer with improved uniformity of defective die probability density.
  • the estimated defective die probability map or sampling plan illustrated in Fig. 8 may correspond to the map or sampling plan generated in step 903.
  • step 904_l applies a wafer region boundary to an estimated defective die probability map based on the radial distribution of defective die probabilities. Dies on a wafer may therefore be more uniformly grouped in a wafer region.
  • a boundary of wafer region is determined by integrating the estimated defective die probably map with respect to radial distance to generate an accumulated defective die probability map.
  • a wafer region boundary may be evaluated by a region of uniform slope or change in the accumulated defective die probability.
  • an evaluated wafer region may contain dies on the wafer with similar defective die probability and improve uniformity of defective die probability density on the generated defective die probability map.
  • step 905 the sampling plan with an evaluated wafer region boundary is used to guide inspection of the first wafer with an inspection tool.
  • the sampling plan may be used to guide the inspection tool during inspection of the first wafer.
  • the CGI model projects die loss for the first wafer according to the inspection results collected in step 905. The die loss projection may be performed via Equations 3 and 4.
  • an estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer.
  • a sampling plan based on the estimated defective die probability may be generated, wafer regions may be evaluated, and die loss is projected for the second wafer by repeating steps 903 to 906, but with respect to the second wafer.
  • probe test results may be obtained for the first wafer and the second wafer once fully processed at the end of wafer processing. In some embodiments, probe test results may be obtained for the first wafer or the second wafer during various steps of wafer processing (e.g., after development, after etching, etc.).
  • an R 2 correlation score is evaluated by comparing the actual defective die result (e.g., actual die loss) for the first wafer and the second wafter to the estimated defective die probability (e.g., projected die loss) as described above.
  • method 900 may provide a sampling plan that has increased versatility for different wafers.
  • the evaluated wafer regions of method 900 may guide the inspection tool towards an area of larger defective die probability that may have been cut off from the pre-determined and constant wafer region definition of conventional methods.
  • constraints from a solely dynamic sampling plan may be improved by using a hybrid sampling plan.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig. 5) and a dynamic sampling plan as described above for method 900, thereby accounting for a nonuniform defect density or distribution within a wafer, improving resolution and accuracy of the model, and maintaining a stable baseline by sampling a wafer at locations that historically have wafer defects (e.g., sampling a wafer at locations that are historically prone to having defects or that are shown to have defects).
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • Figs. 10A and 10B are an example estimated defective die probability map used to evaluate a wafer region definition and an example accumulated defective die probability plot, consistent with embodiments of the present disclosure.
  • Fig. 10A may illustrate step 903 of method 900 (see Fig. 9).
  • a defective die probability map of a wafer 1001 may contain a first probability boundary 1002 and a second probability boundary 1003 which exhibit a difference in defective die probability.
  • first probability boundary 1002 illustrates a cutoff from an area of wafer 1001 where the defective die probability is higher (e.g., illustrated as gray) and an area of wafer 1001 where the defective die probability is lower (e.g., illustrated as white).
  • a radial distance 1004 is illustrated as starting from a center of wafer 1001, extending past first probability boundary 1002, past second probability boundary 1003, and ending at the edge of wafer 1001 (e.g., radius of wafer 1001).
  • Fig. 10B is an example illustration of evaluating a wafer region definition by integrating a defective die probability map of a wafer with respect to radial distance, consistent with embodiments of the present disclosure.
  • Fig. 10B may correspond to step 904_2 of method 900 (see Fig. 9).
  • the plot illustrated in Fig. 10B may be obtained by integrating the defective die probability map of wafer 1001 in Fig. 10A with respect radial distance 1004.
  • Fig. 10B represents an accumulated defective die probability 1005 as a function of radial distance 1004 of wafer 1001.
  • the dotted lines appearing from left to right, starting at the origin of Fig. 10B represent first probability boundary 1002, then second probability boundary 1003, and the edge of wafer 1001. Since radial distance 1004 begins at the center of wafer 1001, accumulated defective die probability
  • first wafer region 1006 begins at 0 and increases as radial distance 1004 increases.
  • the radial distance between the origin and first probability boundary 1002 may correspond to a first wafer region 1006, which may correspond to the gray area enclosed by first probability boundary 1002 in Fig. 10A.
  • first wafer region 1006 exhibits a steep slope in the plotted accumulated defective die probability since first wafer region
  • a wafer region may be defined such that a defective die probability density is uniform within the wafer region. For example, as illustrated in Fig. 10B, this may correspond to the slope of the plotted accumulated defective die probability remaining constant throughout a wafer region.
  • a wafer region boundary may then be applied to the defective die probability map at the corresponding radial distance (e.g., wafer region boundary 803 and wafer region boundary 804 in Fig. 8).
  • Method 1100 may optimize the die loss projection R 2 correlation score based on a training set of wafers using parameterized wafer region definition and sampling budget per wafer region variables as optimization variables. Method 1100 may be performed after an R 2 correlation score is obtained for a wafer that has been inspected according to a CGI-generated sampling plan using an inspection tool and inspected via a probe test to obtain a ground truth result.
  • Method 1100 may be also performed without a pre-determined wafer region definition and a sampling budget distribution per wafer region.
  • the steps of method 1100 may be performed by a computing device, e.g., processor 303 of Fig. 3. It is appreciated that the illustrated method 1100 may be altered to modify the order of steps and to include additional steps.
  • step 1101 input data is supplied to the CGI model.
  • the input data may be a probe test result and an image for a training wafer acquired via wafer processing containing metrology information as described above.
  • a wafer region definition and sampling budget per wafer region are parameterized for the training wafer.
  • the wafer region definition may be parameterized where the wafer contains two wafer region variables. These parameterized variables may be ri and , where ri is the radial distance from a center of a wafer to a first wafer region boundary and is the radial distance from the center of a wafer to a second wafer region boundary. Given this definition, ri is constrained to be less than , and 0 ⁇ r , rz ⁇ r max , where r max is the maximum radial distance from the center of a wafer to the edge of the wafer. r max may be 150 mm.
  • a third wafer region is defined by the radial distance between and r ma x- It is further appreciated that a wafer may contain fewer or more than three wafer regions.
  • the sampling budget per wafer region may be parameterized into variables N], Ng, and N3, where Nj corresponds to a sampling budget for a first wafer region, N2 corresponds to a sampling budget for a second wafer region, and N3 corresponds to a sampling budget for a third wafer region.
  • the parameterized wafer region variables and the parameterized sampling budget per wafer region variables are optimized to maximize the R 2 correlation score.
  • the optimization may be performed by any constrained global optimization technique which uses a forward solver to map a parameterized wafer region variable or parameterized sampling budget per wafer region variable to a defective die loss R 2 correlation score based on the training wafer.
  • a constrained global optimization technique may include, but is not limited to, Bayesian optimization, Coordinate descent, Adaptive coordinate descent, Cuckoo search, Beetle antennae search, Data-based online nonlinear extremumseeker, Evolution strategies, Genetic algorithms, Multilevel coordinate search algorithm, Nelder-Mead method, Particle swarm optimization, Pattern search, Random search, Simulated annealing, Stochastic optimization, Subgradient method, or any other derivative-free optimization algorithm.
  • Step 1103 may be performed repeatedly until the parameterized variables described above are co-optimized to yield a maximum R 2 correlation score.
  • step 1104 the co-optimized parameterized wafer region and sampling budget per wafer region variables are used to generate a sampling plan.
  • step 1105 the generated sampling plan is applied to a first wafer and a second wafer in a testing set to guide the inspection tool during inspection of the first wafer and the second wafer in the testing set.
  • the updated sampling plan may indicate a different wafer region definition and sampling budget distribution per wafer region compared to the sampling plan used to guide the inspection tool for the training wafer before method 1100 is implemented.
  • step 1106 the inspection result collected for the first wafer and the second wafer in the testing set is used to project die loss for the first wafer and the second in the testing set.
  • the die loss projection may be performed via Equations 3 and 4.
  • step 1107 probe test results are collected for the first wafer and the second wafer in the testing set after wafer processing is completed to obtain an actual die loss.
  • step 1108 a verification R 2 correlation score is evaluated. The verification R 2 correlation score is compared to the starting R 2 correlation score of method 1100. If the verification R 2 correlation score is higher than the starting R 2 correlation score, then the co-optimized parameterized wafer region and sampling budget distribution per wafer region variables may be applied to a wafer for subsequent wafer processing.
  • method 1100 may provide an optimization-based approach to generating an optimal fixed sampling plan setting (e.g., wafer region definition or sampling budget distribution) that has increased versatility for predicting defective die on different wafers with improved accuracy. It is further appreciated that optimized parameterized wafer region definition and sampling budget definitions determined from method 700 or method 900 may be applied as initial guesses in method 1100. This may reduce time and computational cost associated with the optimization of method 1100. [0135] Reference is now made to Table 1, which displays R 2 correlation score improvements relative to the conventional method of three wafer datasets that were determined by method 600 and method 700 of the present disclosure.
  • Table 1 displays R 2 correlation score improvements relative to the conventional method of three wafer datasets that were determined by method 600 and method 700 of the present disclosure.
  • each dataset comprises a batch over 100 wafers in which sampling plans were generated to guide the inspection tool according to the method 600 and method 700 of the present disclosure.
  • a projected die loss was calculated, and a probe test result was obtained for a fraction of wafers in the batch for Dataset 1, whereas a projected die loss was calculated, and probe test results were obtained for each wafer in Dataset 2 and Dataset 3. It is appreciated that die loss was projected using Equations 3 and 4 for both method 600 and method 700 (e.g., assuming non- uniform defect density or distribution).
  • the R 2 correlation score was determined as described above, and it was found that the R 2 correlation score was improved for each dataset of wafers when either method 600 or method 700 was applied instead of the conventional method.
  • the R 2 correlation score improvement compared to the conventional method for all three datasets when method 600 is applied indicates the benefit of assuming a non-uniform defect density or distribution in die loss projection.
  • the R 2 correlation score exhibited further improvement for Dataset 2 and Dataset 3 when method 700 was applied compared to method 600.
  • an R 2 correlation score may be further improved when a model-based sampling budget distribution is applied in addition to assuming a non-uniform defect density or distribution in die loss projection.
  • a benefit provided by embodiments of the present disclosure may be an improved R 2 correlation score of actual die loss to projected die loss using a CGI model without required input variables.
  • the present disclosure may provide a method to project die loss without the assumption the defect density or distribution is uniform within a wafer region and improve an R 2 correlation score.
  • a sampling budget distribution for a wafer or a wafer region definition may be optimized to improve an R 2 correlation score.
  • an optimization-based model is provided that may further improve the R 2 correlation score.
  • Some embodiments of the present disclosure may provide a method to improve a CGI model performance and versatility to guide wafer inspection.
  • Some embodiments of the present disclosure may provide a method to increase defect inspection accuracy and yield of defect-free wafers throughout HVM.
  • constraints from a solely dynamic sampling plan such as generating an unstable baseline and reduced resolution and accuracy of the model prediction, may be improved by using a hybrid sampling plan.
  • a hybrid sampling plan may use both a static sampling plan (e.g., method 400 of Fig. 4, wafer 501 of Fig.
  • generating the static sampling plan portion of the hybrid method may include generating a baseline sampling plan based on historical inspection data.
  • generating the dynamic sampling plan portion of the hybrid method may include generating an excursion event sampling plan based on fabrication data and a computational model (e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction).
  • a computational model e.g., based on the scanner recipe of a computational lithography model, including resolution enhancing techniques of the scanner, such as optical proximity correction.
  • FIG. 12 shows exemplary sampling plans 1210, 1220, and 1230 for a wafer, consistent with embodiments of the present disclosure.
  • sampling plan 1210 may show a static sampling plan (e.g., generated using method 400 of Fig. 4, corresponding to wafer 501 of Fig. 5) for wafers 1201, 1202, 1203, 1204, 1205, and 1206.
  • wafers 1201, 1202, 1203, 1204, 1205, and 1206 include uniform sampling regions 1211 and 1212.
  • sampling regions 1211 and 1212 may correspond to regions of the wafer that historically have wafer defects (e.g., regions of a wafer that are historically prone to having defects or that are shown to have defects).
  • sampling plan 1220 may show a dynamic sampling plan (e.g., generated using method 600 of Fig. 6, method 700 of Fig. 7, corresponding to wafer 801 of Fig. 8, method 900 of Fig. 9, corresponding to wafer 1001 of Fig. 10A, corresponding to the plot of Fig. 10B, method 1100 of Fig. 11) for wafers 1201, 1202, 1203, 1204, 1205, and 1206.
  • wafers 1201, 1202, 1203, 1204, 1205, and 1206 include nonuniform sampling regions (e.g., sampling regions 1221 and 1222 of wafer 1201). That is, the sampling regions of wafers 1201, 1202, 1203, 1204, 1205, and 1206 vary by wafer due to differences in input data (e.g., fabrication data of the individual wafer) that are fed to a computational model to generate the dynamic sampling plan.
  • sampling regions of the dynamic sampling plan 1220 may correspond to regions of the wafer that do not historically have wafer defects (e.g., regions of a wafer that are not historically prone to having defects or that are not shown to have defects).
  • sampling plan 1230 may show a hybrid sampling plan that is generated based on static sampling plan 1210 and dynamic sampling plan 1220. As shown in hybrid sampling plan 1230, sampling regions 1211 and 1212 are included for each of wafers 1201, 1202, 1203, 1204, 1205, and 1206.
  • the dynamic sampling plan portion of hybrid sampling plan 1230 may only include dies with defective die probabilities above a certain threshold (e.g., sampling regions of dynamic sampling plan 1220 outside of static sampling plan 1210 and above a threshold).
  • hybrid sampling plan 1230 may include static sampling plan 1210 and sampling regions 1223 and 1224 of dynamic sampling plan 1220 (e.g., the defective die probabilities corresponding to sampling regions 1223 and 1224 may be above a threshold).
  • Fig. 13 shows exemplary metrology sampling plans 1310 and 1320 for a wafer, consistent with embodiments of the present disclosure.
  • sampling plan 1310 may correspond to a typical metrology sampling plan to obtain input data (e.g., fabrication data) for generating dynamic sampling plans (e.g., generated using method 600 of Fig. 6, method 700 of Fig. 7, corresponding to wafer 801 of Fig. 8, method 900 of Fig. 9, corresponding to wafer 1001 of Fig. 10A, corresponding to the plot of Fig. 10B, method 1100 of Fig. 11, dynamic sampling plan 1220 of Fig. 12).
  • input data e.g., fabrication data
  • dynamic sampling plans e.g., generated using method 600 of Fig. 6, method 700 of Fig. 7, corresponding to wafer 801 of Fig. 8, method 900 of Fig. 9, corresponding to wafer 1001 of Fig. 10A, corresponding to the plot of Fig. 10B, method 1100 of Fig. 11, dynamic sampling plan 1220 of Fig. 12).
  • sampling plan 1310 may be an inefficient distribution of the sampling budget since a static sampling plan (e.g., static sampling plan 1210 of Fig. 12) is applied. Therefore, in some embodiments, the sampling budget may be redistributed to improve accuracy of the dynamic sampling plan portion of a hybrid sampling plan.
  • sampling plan 1320 may be generated.
  • sampling plan 1320 may be a modification of an existing metrology sampling plan (e.g., a modification of sampling plan 1310).
  • sampling regions may be redistributed from areas corresponding to the static sampling plan portion to areas corresponding to the dynamic sampling plan portion (e.g., redistributed to sampling region 1322, a region with historically lower defect probability) to improve accuracy of the dynamic sampling plan portion.
  • the sampling budget ratio of a wafer may be adjusted to allocate dies to be sampled using a static sampling plan and dies to be sampled using a dynamic sampling plan based on real-time needs and historical data (e.g., the number of dies to be sampled using static sampling and the number of dies to be sampled using dynamic sampling per wafer may be adjusted).
  • the dynamic sampling plan of a hybrid sampling plan may use a fixed sampling budget per wafer or per zone (e.g., region of a wafer, quadrant of a wafer, concentric ring region of a wafer, etc.) based on dynamic sampling optimization.
  • Fig. 14 shows an example static sampling plan portion 1400 of a hybrid sampling plan (e.g., sampling plan 1230 of Fig. 12), consistent with embodiments of the present disclosure.
  • fixed die locations 1410 in the static sampling plan portion 1400 may be selected for inspection in addition to the CGI-generated dynamic sampling plan portion of the hybrid sampling plan.
  • this option allows targeted sampling of areas known from experience (e.g., historical data) or suspected to be problematic.
  • Fig. 15 shows a diagram 1500 of an example static sampling plan portion of a hybrid sampling plan (e.g., sampling plan 1230 of Fig. 12), consistent with embodiments of the present disclosure.
  • a hybrid sampling plan e.g., sampling plan 1230 of Fig. 12
  • maps 1510, 1520, and 1530 may be generated from historical defect data across multiple wafers.
  • each of maps 1510, 1520, and 1530 may correspond to a different wafer.
  • Maps 1510, 1520, and 1530 may represent the defect probability for each die of a wafer.
  • points 1512, 1522, and 1532 may represent dies on a wafer that “failed” (e.g., are likely to have a defect) and points 1514, 1524, and 1534 may represent dies on a wafer that “passed” (e.g., are unlikely to have a defect).
  • Equation 7 may be used to average maps 1510, 1520, and 1530 to generate map 1540.
  • Equation 7 may be used to average maps 1510, 1520, and 1530 to generate map 1540.
  • n train may represent the number wafers (e.g., number of wafers corresponding to maps 1510, 1520, and 1530)
  • Probe_result( x y) may represent a defect probability result (e.g., “failed” or “passed”) for a die at coordinate (x,y) of a wafer map (e.g., maps 1510, 1520, and 1530).
  • the stacked probe probability at a coordinate (x,y) of n tram wafers may be calculated by summing the defect probability result for each die at coordinate (x,y) for n tram wafers.
  • Map 1540 may be generated by using Equation 7 to calculate the stacked probe probability for dies at various coordinates (x,y) of various wafers.
  • Map 1540 may be used to generate a static sampling portion of a hybrid sampling plan.
  • map 1540 may be used to generate a static sampling portion of a hybrid sampling plan by determining fixed sampling locations on map 1540 based on the highest defect probabilities.
  • a static sampling portion of a hybrid sampling plan may be generated by determining different zones (e.g., quadrants of map 1540, concentric rings of map 1540, etc.) of map 1540 to ensure a more strategic coverage of the wafer.
  • a wafer map may be used to generate the static sampling plan portion.
  • each die of the wafer map may correspond to a historical sampling frequency data.
  • each die of the wafer map may correspond to a probability that the die in that position will be sampled.
  • a static sampling plan portion of a hybrid sampling plan may be generated.
  • the static sampling plan portion may target historically unsampled or least sampled areas of a wafer based on a probability map of past sampling data.
  • this method aims to explore and address areas of higher uncertainty on a wafer.
  • the system may use Equation 8 to generate a stacked wafer map.
  • n stacked wa fers may represent the number wafers (e.g., number of wafers corresponding to wafer maps) and Sampling_decision xy may represent a sampling probability result (e.g., the die is likely to be sampled, the die is unlikely to be sampled, etc.) for a die at coordinate (x,y) of a wafer map.
  • the stacked sampling probability at a coordinate (x,y) of n stacked wafers wafers may be calculated by summing the sampling probability result for each die at coordinate (x,y) for n stacked wa fers wafers.
  • a wafer map may be generated by using Equation 8 to calculate the stacked sampling probability for dies at various coordinates (x,y) of various wafers.
  • projected die losses may be calculated based on the hybrid sampling plan approach. For example, based on Equation 9, the static or fixed sampling probability may be combined with CGI-generated defect probability (based on the dynamic sampling plan) to generate a more accurate and comprehensive risk assessment.
  • the Hybrid Sampling Probability for a die at coordinate (x,y) may be determined based on the CGI model predicted probability (the probability that a die at coordinate (x,y) will fail or be defective in the dynamic sampling portion) and the stacked probe probability (e.g., Equation 7) or the stacked sampling probability (e.g., Equation 8).
  • the dynamic sampling ratio and the fixed sampling ratio may be the ratio of dies in a sampling budget (e.g., the ratio of dies under dynamic sampling and the ratio of dies under static sampling).
  • Equation 10 may be used to determine the projected die loss: number of defective dies captured
  • Projected die loss x total number of dies inspected
  • the projected die loss may be calculated based on the number of defective dies captured, the total number of dies inspected, and a scaling factor (e.g., determined by the hybrid sampling probability of Equation 9).
  • a system e.g., controller 109 of Figs. 2A and 2B, processor 303 of Fig. 3 may utilize a sampling plan of the disclosed embodiments to guide sample inspection of a sample, calculate a projected die loss using the inspection result of the sample (e.g., using Equation 10), obtain a probe test result for the sample, and evaluate an R 2 correlation score by comparing the probe test result to the projected die loss.
  • Embodiments of the present disclosure describing hybrid sampling plans advantageously result in increased defect detection rates. By combining strategic static sampling (e.g., Figs. 14 and 15) with dynamic, data-driven sampling plans, the hybrid sampling plans target defects more effectively across the wafer, and are also able to predict the projected die loss with higher accuracy [0161] Embodiments of the present disclosure describing hybrid sampling plans advantageously result in improved adaptability and coverage. For example, embodiments of the present disclosure provide flexibility, which allows for tailored inspection strategies that adapt to new and evolving defect patterns, which significantly improves coverage. Embodiments of the present disclosure increase throughput by focusing on areas of the wafer that are less likely to have a defect.
  • Embodiments of the present disclosure describing hybrid sampling plans advantageously provide enhanced model robustness by incorporating a broader data set and multiple sampling strategies to strengthen the overall model's predictive power and reliability.
  • Fig. 16 is an example flow diagram of a method 1400 to generate a hybrid sampling plan for a wafer, consistent with embodiments of the present disclosure.
  • a system e.g., processor 303 of Fig. 3 may generate a static sampling plan to determine a baseline for inspection (e.g., generate a baseline sampling plan based on historical inspection data).
  • the static sampling plan may include pre-determined regions of a wafer.
  • step 1601 may be performed as described above for method 400 of Fig. 4, wafer 501 of Fig. 5, static sampling plan 1210 of Fig. 12, static sampling plan portion 1400 of Fig. 14, diagram 1500 of Fig. 15, embodiments described with respect to the above figures, etc.
  • step 1602 the system may generate a dynamic sampling plan to determine excursion events (e.g., generate an excursion event sampling plan based on fabrication data and a computational model).
  • generating a dynamic sampling plan may include providing input data for a wafer to a computational defect probability prediction model and determining defective die probabilities for a region of the wafer from the computational defect probability prediction model.
  • step 1602 may be performed as described above for method 600 of Fig. 6, method 700 of Fig. 7, wafer 801 of Fig. 8, method 900 of Fig. 9, wafer 1001 of Fig. 10A, the plot of Fig. 10B, method 1100 of Fig. 11, or dynamic sampling plan 1220 of Fig. 12.
  • step 1603 the system may apply the static sampling plan.
  • step 1603 may be performed as described above for method 400 of Fig. 4, wafer 501 of Fig. 5, or static sampling plan 1210 of Fig. 12, static sampling plan portion 1400 of Fig. 14, diagram 1500 of Fig. 15, embodiments described with respect to the above figures, etc.
  • step 1604 the system may apply the dynamic sampling plan by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically lower defect probability.
  • step 1604 may be performed as described above for method 600 of Fig. 6, method 700 of Fig. 7, wafer 801 of Fig. 8, method 900 of Fig. 9, wafer 1001 of Fig. 10A, the plot of Fig. 10B, method 1100 of Fig. 11, or dynamic sampling plan 1220 of Fig. 12.
  • a non-transitory computer readable medium may be provided that may store instructions for a processor of a controller (e.g., controller 109 of Fig. 1, controller 109 of Fig. 2A, controller 109 of Fig. 2A) to carry out, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjusting, activating charged- particle source, beam deflecting, store instructions for a processor of a lithographic projection apparatus (e.g., lithographic projection apparatus 301 of Fig. 3) and inspection tool (e.g., inspection tool 302 of Fig. 3) to determine input data of a sample, perform method 600 of Fig. 6, perform method 700 of Fig.
  • a controller e.g., controller 109 of Fig. 1, controller 109 of Fig. 2A, controller 109 of Fig. 2A
  • image inspection image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjusting, activating
  • non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.
  • NVRAM Non-Volatile Random Access Memory
  • a method to generate an inspection tool sampling plan comprising: providing input data for a wafer to a computational defect probability prediction model; dividing the wafer into a plurality of wafer regions having dies; determining defective die probabilities per wafer region from the computational defect probability prediction model; selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities; and generating a sampling plan for the wafer based on the selected dies.
  • selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities further comprises: ranking the determined defective die probabilities per wafer region; and selecting, for each wafer region of the plurality of wafer regions, a number of dies based on the ranking of determined defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for the respective wafer region.
  • a method to optimize an inspection tool sampling plan comprising: providing input data for a wafer to a computational defect probability prediction model; and distributing a sampling budget for a region of a wafer based on an expected number of defective die count for the region compared to an expected number of defective die count for the wafer; wherein the expected number of defective die count for the region is a summation of predicted defective die probability for the region and the expected number of defective die count for the wafer is a summation of predicted defective die probability for the wafer; and wherein the predicted defective die probability for the region and the predicted defective die probability for the wafer are obtained from the computational defect probability prediction model.
  • a method to optimize an inspection tool sampling plan comprising: providing input data for a wafer to a computational defect probability prediction model; determining a defective die probability for each die of the wafer from the computational defect probability prediction model; generating a sampling plan; evaluating a wafer region from the defective die probability for each die of the wafer; evaluating a sampling budget distribution for each evaluated wafer region; and using the sampling plan with the evaluated wafer region and sampling budget distribution to guide wafer inspection of the wafer.
  • a method of optimizing an inspection tool sampling plan comprising: providing input data for a wafer to a computational defect probability prediction model; parameterizing a wafer region definition and a sampling budget for a wafer region, wherein the parameterized wafer region definition and sampling budget for the wafer region have certain constraints; and optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region according to the certain constraints to maximize a projected value.
  • An apparatus to generate an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a wafer to a computational defect probability prediction model; dividing the wafer into a plurality of wafer regions having dies; determining defective die probabilities per wafer region from the computational defect probability prediction model; selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities; and generating a sampling plan for the wafer based on the selected dies.
  • selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities further comprises: ranking the determined defective die probability for each die per wafer region; and selecting, for each wafer region of the plurality of wafer regions, a number of dies based on the ranking of determined defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for the respective wafer region.
  • An apparatus for optimizing an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a wafer to a computational defect probability prediction model; and distributing a sampling budget for a region of a wafer based on an expected number of defective die count for the region compared to an expected number of defective die count for the wafer; wherein the expected number of defective die count for the region is a summation of predicted defective die probability for the region and the expected number of defective die count for the wafer is a summation of predicted defective die probability for the wafer; and wherein the predicted defective die probability for the region and the predicted defective die probability for the wafer are obtained from the computational defect probability prediction model.
  • An apparatus for optimizing an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a wafer to a computational defect probability prediction model; determining a defective die probability for each die of the wafer from the computational defect probability prediction model; generating a sampling plan; evaluating a wafer region from the defective die probability for each die of the wafer; evaluating a sampling budget distribution for each evaluated wafer region; and using the sampling plan with the evaluated wafer region and sampling budget distribution to guide wafer inspection of the wafer.
  • An apparatus for optimizing an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a wafer to a computational defect probability prediction model; parameterizing a wafer region definition and a sampling budget for a wafer region, wherein the parameterized wafer region definition and sampling budget for the wafer region have certain constraints; and optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region according to the certain constraints to maximize a projected value.
  • a constraint for the first variable and the second variable comprises 0 ⁇ ri, ⁇ r max , wherein r max is a radius of the wafer.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations comprising: providing input data for a wafer to a computational defect probability prediction model; dividing the wafer into a plurality of wafer regions having dies; determining defective die probabilities per wafer region from the computational defect probability prediction model; selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities; and generating a sampling plan for the wafer based on the selected dies.
  • selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities further comprises: ranking the determined defective die probability for each die per wafer region; and selecting, for each wafer region of the plurality of wafer regions, a number of dies based on the ranking of determined defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for the respective wafer region.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing an inspection tool sampling plan, the operations comprising: providing input data for a wafer to a computational defect probability prediction model; and distributing a sampling budget for a region of a wafer based on an expected number of defective die count for the region compared to an expected number of defective die count for the wafer; wherein the expected number of defective die count for the region is a summation of predicted defective die probability for the region and the expected number of defective die count for the wafer is a summation of predicted defective die probability for the wafer; and wherein the predicted defective die probability for the region and the predicted defective die probability for the wafer are obtained from the computational defect probability prediction model.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing an inspection tool sampling plan, the operations comprising: providing input data for a wafer to a computational defect probability prediction model; determining a defective die probability for each die of the wafer from the computational defect probability prediction model; generating a sampling plan; evaluating a wafer region from the defective die probability for each die of the wafer; evaluating a sampling budget distribution for each evaluated wafer region; and using the sampling plan with the evaluated wafer region and evaluated sampling budget distribution to guide wafer inspection of the wafer.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing an inspection tool sampling plan, the operations comprising: providing input data for a wafer to a computational defect probability prediction model; parameterizing a wafer region definition and a sampling budget for a wafer region, wherein the parameterized wafer region definition and sampling budget for the wafer region have certain constraints; and optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region according to the certain constraints to maximize a projected value.
  • the input data comprises a probe test result of the wafer.
  • a constraint for the first variable and the second variable comprises 0 ⁇ ri, ⁇ r max , wherein r max is a radius of the wafer.
  • a system using a computational model to generate an inspection tool sampling plan comprising: one or more processors configured to execute instructions to cause the system to perform: providing input data for a wafer to a computational defect probability prediction model; dividing the wafer into a plurality of wafer regions having dies; determining defective die probabilities per wafer region from the computational defect probability prediction model; selecting at least one die from each wafer region of the plurality of wafer regions using the determined defective die probabilities; and generating a sampling plan for the wafer based on the selected dies.
  • a method to generate an inspection tool sampling plan comprising: generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine excursion events; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically low defect probability.
  • generating the static sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the static sampling plan based on the generated probability estimate map.
  • generating the dynamic sampling plan comprises: feeding fabrication data of a sample into the trained computational model; generating a probability estimate of the sample; and converting the probability estimate into the dynamic sampling plan.
  • the metrology data comprises one or more of necking, line pull back, line thinning, critical dimension, edge placement, overlapping, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on a sample.
  • a method for defect detection using a computational guided inspection sampling plan comprising: generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabrication data and a computational model; applying the baseline sampling plan to a sample; and applying the excursion event sampling plan to the sample when predicted defect probabilities exceed a threshold in an area of the sample with historically low defect probability.
  • a method to generate an inspection tool sampling plan comprising: providing input data for a wafer to a computational defect probability prediction model; determining defective die probabilities for a first region of the wafer from the computational defect probability prediction model; and generating a sampling plan for the wafer based on the determined defective die probabilities for the first region of the wafer and based on a pre-determined second region of the wafer.
  • generating the baseline sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the baseline sampling plan based on the generated probability estimate map.
  • the metrology data comprises one or more of necking, line pull back, line thinning, critical dimension, edge placement, overlapping, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on a sample.
  • An apparatus to generate an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine excursion events; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically low defect probability.
  • generating the static sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the static sampling plan based on the generated probability estimate map.
  • applying the static sampling plan comprises inspecting the sample in an area corresponding to historically high defect probabilities.
  • generating the dynamic sampling plan comprises: feeding fabrication data of a sample into the trained computational model; generating a probability estimate of the sample; and converting the probability estimate into the dynamic sampling plan.
  • the metrology data comprises one or more of necking, line pull back, line thinning, critical dimension, edge placement, overlapping, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on a sample.
  • An apparatus for defect detection using a computational guided inspection sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabrication data and a computational model; applying the baseline sampling plan to a sample; and applying the excursion event sampling plan to the sample when predicted defect probabilities exceed a threshold in an area of the sample with historically low defect probability.
  • generating the baseline sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the baseline sampling plan based on the generated probability estimate map.
  • generating the excursion event sampling plan comprises: feeding fabrication data of a sample into the trained computational model; generating a probability estimate of the sample; and converting the probability estimate into the excursion event sampling plan.
  • the metrology data comprises one or more of necking, line pull back, line thinning, critical dimension, edge placement, overlapping, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on a sample.
  • An apparatus to generate an inspection tool sampling plan comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a wafer to a computational defect probability prediction model; determining defective die probabilities for a first region of the wafer from the computational defect probability prediction model; and generating a sampling plan for the wafer based on the determined defective die probabilities for the first region of the wafer and based on a pre-determined second region of the wafer.
  • a non- transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations comprising: generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine excursion events; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when predicted defect probabilities exceed a threshold in an area of a sample with historically low defect probability.
  • generating the static sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the static sampling plan based on the generated probability estimate map.
  • generating the dynamic sampling plan comprises: feeding fabrication data of a sample into the trained computational model; generating a probability estimate of the sample; and converting the probability estimate into the dynamic sampling plan.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for defect detection using a computational guided inspection sampling plan, the operations comprising: generating a baseline sampling plan based on historical inspection data; generating an excursion event sampling plan based on fabrication data and a computational model; applying the baseline sampling plan to a sample; and applying the excursion event sampling plan to the sample when predicted defect probabilities exceed a threshold in an area of the sample with historically low defect probability.
  • generating the baseline sampling plan comprises: generating a probability estimate map based on the historical probe data of the plurality of samples by averaging the historical probe data; and generating the baseline sampling plan based on the generated probability estimate map.
  • applying the baseline sampling plan comprises inspecting the sample in an area corresponding to historically high defect probabilities.
  • generating the excursion event sampling plan comprises: feeding fabrication data of a sample into the trained computational model; generating a probability estimate of the sample; and converting the probability estimate into the excursion event sampling plan.
  • a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations comprising: providing input data for a wafer to a computational defect probability prediction model; determining defective die probabilities for a first region of the wafer from the computational defect probability prediction model; and generating a sampling plan for the wafer based on the determined defective die probabilities for the first region of the wafer and based on a pre-determined second region of the wafer.
  • a system to generate an inspection tool sampling plan comprising: a memory storing a set of instructions; and one or more processors configured to execute the set of instructions to cause the system to perform operations according to any one of clauses 269-279.
  • a system for defect detection using a computational guided inspection sampling plan comprising: a memory storing a set of instructions; and one or more processors configured to execute the set of instructions to cause the system to perform operations according to any one of clauses 280-292.
  • a non- transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method to generate an inspection tool sampling plan according to any one of clauses 269-279.
  • a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method for defect detection using a computational guided inspection sampling plan according to any one of clauses 280-292.
  • Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure.
  • each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit.
  • Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions.
  • functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted.
  • each block of the block diagrams, and combination of the blocks may be implemented by special purpose hardware -based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

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Abstract

L'invention concerne des systèmes, des procédés, des appareils et des supports non transitoires lisibles par ordinateur pour générer un plan d'échantillonnage d'outil d'inspection. Des systèmes, des procédés, des appareils et des supports non transitoires lisibles par ordinateur peuvent faire appel à la génération d'un plan d'échantillonnage statique pour déterminer une ligne de base d'inspection; la génération d'un plan d'échantillonnage dynamique pour déterminer des événements d'excursion; l'application du plan d'échantillonnage statique; et l'application du plan d'échantillonnage dynamique par déclenchement d'un échantillonnage supplémentaire lorsque des probabilités de défaut prédites dépassent un seuil dans une zone d'un échantillon avec une probabilité de défaut historiquement faible.
PCT/EP2024/073039 2023-08-16 2024-08-15 Systèmes et procédés de génération de plan d'échantillonnage hybride et de projection précise de perte de puce Pending WO2025036991A1 (fr)

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US20080133163A1 (en) * 2001-06-19 2008-06-05 Shanmugasundram Arulkumar P Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing

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US20080133163A1 (en) * 2001-06-19 2008-06-05 Shanmugasundram Arulkumar P Dynamic metrology schemes and sampling schemes for advanced process control in semiconductor processing

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MCLOONE SEAN ET AL: "A Methodology for Efficient Dynamic Spatial Sampling and Reconstruction of Wafer Profiles", IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 15, no. 4, 1 October 2018 (2018-10-01), pages 1692 - 1703, XP011691061, ISSN: 1545-5955, [retrieved on 20181004], DOI: 10.1109/TASE.2017.2786213 *

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