WO2025036099A1 - Method and system for processing task to be processed, and storage medium and electronic apparatus - Google Patents

Abstract

Provided in the embodiments of the present disclosure are a method and system for processing a task to be processed, and a storage medium and an electronic apparatus. The method for processing a task to be processed comprises: on the basis of parameter information and demand information of a task to be processed, determining an instruction set corresponding to the task to be processed, wherein the demand information is used for indicating a processing result corresponding to the task to be processed; determining a first instruction address of each instruction to be executed in the instruction set; and on the basis of the first instruction address of each instruction to be executed, executing each instruction to be executed, so as to process the task to be processed. By means of the present disclosure, the problem of the flexibility in designing a chip being relatively low is solved, thereby achieving the effect of improving the flexibility of the chip.

Description

Method and system for processing tasks to be processed, storage medium and electronic device

This disclosure claims the priority of the Chinese patent application filed with the Chinese Patent Office on August 15, 2023, with application number 202311034305.X and invention name “Processing method and system for pending tasks, storage medium and electronic device”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The embodiments of the present disclosure relate to the field of communications, and in particular, to a method and system for processing tasks to be processed, a storage medium, and an electronic device.

Background Art

Existing large-scale ASIC chips generally adopt the design of CPU processor plus hardware accelerator. The CPU has a large area and high power consumption, but is highly versatile. It has low performance when processing complex services and generally handles flexible and changeable services. If it is a specific or complex service with low flexibility, it is generally implemented using a hardware accelerator, which can improve performance, save power consumption and area, but the disadvantage is that it is inflexible.

One of the major design difficulties of ASIC chips is the division of software and hardware, that is, which services are implemented by the CPU and which services are implemented by the hardware accelerator. Because the chip development cycle is long, the scenarios in commercial use are often quite different from those in the early stages of design, which requires a certain degree of flexibility to be reserved in the early stages of chip design, but this means an increase in chip costs, which leads to a dilemma.

With regard to the problems in related technologies such as low flexibility in chip design, no effective solutions have been proposed yet.

Summary of the invention

The embodiments of the present disclosure provide a method and system for processing a task to be processed, a storage medium, and an electronic device, so as to at least solve the problem of low flexibility in chip design in the related art.

According to an embodiment of the present disclosure, a method for processing a task to be processed is provided, which is applied to a hardware accelerator, and includes: determining an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; determining a first instruction address of each instruction to be executed in the instruction set; and executing each instruction to be executed based on the first instruction address of each instruction to be executed to process the task to be processed.

According to another embodiment of the present disclosure, a processing system for a task to be processed is provided, including: an instruction extraction unit, configured to determine an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; determining an instruction address of each instruction to be executed in the instruction set; and an execution unit, configured to execute each instruction to be executed according to the instruction address of each instruction to be executed to process the task to be processed.

According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.

According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a hardware structure block diagram of a computer terminal of a method for processing a task to be processed according to an embodiment of the present disclosure;

FIG2 is a flow chart of a method for processing a task to be processed according to an embodiment of the present disclosure;

FIG3 is a flow chart of a method for processing a task to be processed according to an optional embodiment of the present disclosure;

FIG4 is an internal structure diagram of a hardware accelerator according to an embodiment of the present disclosure;

FIG5 is a schematic diagram of a general register according to an embodiment of the present disclosure;

FIG6 is a schematic diagram of an instruction according to an embodiment of the present disclosure (I);

FIG7 is a schematic diagram of an instruction according to an embodiment of the present disclosure (II);

FIG8 is a schematic diagram of an instruction according to an embodiment of the present disclosure (III);

FIG9 is a schematic diagram of an instruction according to an embodiment of the present disclosure (IV);

FIG10 is a schematic diagram of an instruction according to an embodiment of the present disclosure (V);

FIG11 is a schematic diagram of an instruction according to an embodiment of the present disclosure (VI);

FIG12 is a schematic diagram of an instruction according to an embodiment of the present disclosure (VII);

FIG13 is a schematic diagram of a packet header format according to an embodiment of the present disclosure;

FIG. 14 is a structural block diagram of a system for processing tasks to be processed according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

The method embodiments provided in the embodiments of the present disclosure can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, FIG1 is a hardware structure block diagram of a computer terminal of a processing method for a task to be processed in an embodiment of the present disclosure. As shown in FIG1 , the computer terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a hardware accelerator, a microprocessor (Central Processing Unit, MCU), a programmable logic device (Field Programmable Gate Array, FPGA), an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), a digital signal processor, a floating-point unit, a coprocessor, a multi-core processor, a multi-threaded processor, etc.) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input/output device 108 for communication functions. It can be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

The memory 104 may be configured to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the processing methods of the tasks to be processed in the embodiments of the present disclosure. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, that is, to implement the above-mentioned methods. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The transmission device 106 is configured to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is configured to communicate with the Internet wirelessly.

In this embodiment, a method for processing a pending task running on the above-mentioned computer terminal is provided. FIG. 2 is a flow chart of the method for processing a pending task according to an embodiment of the present disclosure. As shown in FIG. 2 , the process includes the following steps:

Step S202, determining an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed;

It should be noted that the task requirement information is the specific requirements and goals of the task, including the content, time requirements, quantity requirements, etc. The parameter information refers to the parameters needed in the task, including input parameters and output parameters. The input parameters are the data that need to be input when the task is executed, and the output parameters are the results obtained after the task is completed. These parameters can be different types of data such as numbers, text, dates, files, etc. During the task execution process, the task execution and the output of the results are completed according to the requirement information and parameter information.

Step S204, determining the first instruction address of each instruction to be executed in the instruction set;

It should be noted that the instruction address refers to the address of the memory location or storage unit that indicates the specific instruction to be executed in the computer program. In the computer's instruction set architecture, each instruction has a unique address, through which the instruction can be loaded into the processor for execution. The instruction address can be represented as a number or a memory address, which is not limited in the embodiments of the present disclosure.

Step S206: Execute each of the to-be-executed instructions according to the first instruction address of each of the to-be-executed instructions to process the to-be-processed tasks.

Through the above steps, when the computer terminal receives the task to be processed, the task to be processed is sent to the hardware accelerator located on the computer terminal. Since the hardware accelerator can determine the instruction set of the task to be processed according to the preset instructions (i.e., it realizes the task programming of the task to be processed), and then processes the task to be processed by executing the instructions in the instruction set, that is, the hardware accelerator can also flexibly process different tasks. Therefore, the problem of low flexibility in chip design can be solved, thereby achieving the effect of improving chip flexibility.

The execution subject of the above steps may be a hardware accelerator in the terminal, etc., but is not limited thereto.

Optionally, the above step S202 can be implemented by the following steps:

Step 11: Determine multiple logical processing modes of the task to be processed according to the parameter information and the requirement information;

Step 12: Determine the instructions corresponding to the multiple logical processing modes, and determine the multiple instructions as the instruction set.

That is to say, the above-mentioned multiple logical processing methods can be understood as a method of determining the result obtained after the task is executed according to the parameter information and requirement information of the task to be processed.

The above logic processing methods include but are not limited to:

1. AND operation: When both logical values are true, the result is true; otherwise, the result is false.

2. OR operation: When at least one of the two logical values is true, the result is true; otherwise, the result is false.

3. NOT: Perform the inversion operation on a logical value, that is, true becomes false and false becomes true.

For example, taking the parsing of classified messages as an example, assuming that a message header format is shown in Figure 13, where bit0 to bit11 are DA fields, used to indicate the destination address; bit12 to bit23 are SA fields, used to indicate the source address; bit24 to bit27 are type is used to indicate the frame type; bit28 to bit31 are subtype, which are used to indicate the frame subtype.

In the embodiment of the present disclosure, the message type is determined by the subtype field. For example, messages with subtype equal to 0 are classified into the first category, and other cases are classified into the second category.

Write the packet header to DTCM address 0 through the upstream logic.

The instructions are written as follows and written into the instruction cache memory (ITCM) by the master CPU writing registers:

0: ADDI (32’b000000000001_00000_000_00011_0010011) initializes the data in address 3 of regfile to 1;

1: LW (32’b0000000000000_00000_010_00001_0000011) reads the data in DTCM address 0 into regfile address 1 LW instruction: reads back 32 bits of data from memory and writes it back to register rd;

2: SLLI (32’b0000000_11100_00001_001_00010_0010011) The data in regfile address 1 is shifted left by 28 bits and written to regfile address 2;

3: SRLI (32’b0000000_11100_00010_101_00001_0010011) The data in regfile address 2 is shifted right by 28 bits and written to regfile address 1;

4: BEQI (32’b0000000_00000_00001_010_00010_1100111) If the data in address 1 of regfile is equal to 0, jump to the sixth line of instructions, otherwise, jump to the fifth line of instructions;

5: SW(32’b0000000_00000_00000_010_00001_0100011) writes 0 to DTCM address 1;

6: SW (32’b0000000_00011_00000_010_00001_0100011) writes 1 to DTCM address 1.

After starting the device, the downstream only needs to read the data in DTCM address 1. If it is 0, it means that the message is of the second category, and if it is 1, it means that the message is of the first category.

Optionally, if the demand for message classification changes, DA, SA, and type need to be used as the basis for classification judgment. You only need to modify the instruction combination in ITCM to complete the combination judgment of any field in the 32-bit packet header, and it is no longer subject to the requirements of traditional hardware logic, thereby improving the flexibility of the chip.

Optionally, the above step S208 can be implemented by the following steps:

Step 21: Processing step: obtaining a second instruction address in a program counter, wherein the program counter is used to store an instruction address of a next instruction to be executed;

Step 22: determining the instruction to be executed corresponding to the second instruction address in the instruction set according to the first instruction address of each instruction to be executed, and executing the instruction to be executed;

Step 23: Execute the processing steps in a loop until each instruction to be executed in the instruction set is completed.

It should be noted that the program counter is a register in the computer that stores the address of the currently executed instruction or the address of the next instruction. It is continuously incremented during the execution of instructions to indicate the location of the next instruction to be executed. When the computer executes an instruction, the program counter automatically increments to the address of the next instruction so that the instruction can be fetched and executed. The value of the program counter is usually expressed in binary form and is updated in every clock cycle of the computer. Therefore, the instruction to be executed is determined according to the instruction address in the program counter until all instructions are executed.

Optionally, before obtaining the instruction set corresponding to the task to be processed, the instructions need to be written. Specifically, the instructions can be written in the following way: determine the second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; determine the instruction to be written according to the second instruction information.

The instructions to be written in the embodiments of the present disclosure include: DTCM read and write instructions, basic integer operation instructions (addition, comparison, OR, AND, shift), unconditional jump instructions, conditional jump instructions (equal, unequal, greater than, less than, greater than or equal to, less than or equal to).

The contents of the instructions to be written include:

1) Instruction code (required), used to identify the action the instruction is intended to complete;

2) Operation address (required), the read/write address of DTCM (equivalent to the source operand in the above embodiment) or the read/write address of regfile (equivalent to the target operand in the above embodiment);

) immediate value (optional), a specific operand.

Optionally, the instruction to be executed is executed in the following manner, including: parsing the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate number; generating a control signal corresponding to the first instruction information, and sending the control signal to the corresponding execution unit of the hardware accelerator to execute the instruction to be executed.

That is to say, in the embodiment of the present disclosure, the execution unit of the hardware accelerator executes the instruction to be executed, and the execution unit performs corresponding arithmetic and logical operations, such as addition, multiplication, displacement, logical operations, etc.

Specifically, generating a control signal corresponding to the first instruction information includes at least one of the following: when the first instruction information includes: the first instruction code and the first source operand, generating first sub-control information according to the type of the first instruction code, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal; when the first instruction information includes: the first instruction code, the first source operand and the first target operand, generating first sub-control information according to the type of the first instruction code, generating a second sub-control signal for reading an operand register according to the first source operand, and generating a third sub-control signal for writing into a general register according to the first target operand, wherein the control signal includes: the first sub-control signal, the second sub-control signal and the third sub-control signal; when the first instruction information includes: the first instruction code, the first immediate number and the first target operand, generating first sub-control information according to the type of the first instruction code, generating a fourth sub-control signal for reading the first immediate number, and generating a third sub-control signal for writing into a general register according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal and the third sub-control signal.

It can be understood that the first sub-control signal is a control signal for implementing operations such as addition, multiplication, displacement, and logical operations; the second sub-control signal is a control signal for reading the operand register; the third sub-control signal is a control signal for writing target information to the target location of the general register; and the fourth sub-control signal is a control signal for reading the first immediate value.

For example: the Add Immediate Instruction (ADDI) instruction is used to instruct the addition operation of the integer value in the operand register rs1 and the 12-bit immediate value (with sign bit extension), and the result is written back to the register RD. The SW instruction is parsed, the first sub-control signal is the control signal for the addition operation, the second sub-control signal is the control signal for reading the integer value in the operand register rs1, and the third sub-control signal is the control signal for writing the result back to the general register RD.

In order to better understand the process of the method for processing the above-mentioned tasks to be processed, the implementation method flow of the processing of the above-mentioned tasks to be processed is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present disclosure.

In this embodiment, a method for processing a task to be processed is provided. FIG3 is a flow chart of the method for processing a task to be processed according to an optional embodiment of the present disclosure. As shown in FIG3 , the details are as follows:

Read instructions, decode instructions, execute instructions, access memory, and write results back. The disclosed embodiment uses a 2-level Pipeline, in which reading instructions uses 1 beat, decoding, execution, memory access, and write back use 1 beat together. Through the arrangement of different instructions, the state machine can be programmed.

In this embodiment, a hardware accelerator for processing a task to be processed is also provided. FIG. 4 is an internal structure diagram of a hardware accelerator according to an embodiment of the present disclosure. As shown in FIG. 4 , the hardware accelerator specifically includes:

Data Tightly-Coupled Memory (DTCM), configured as a high-speed data cache;

Instruction Fetch Unit (IFU), which is set to complete instruction fetch and PC jump;

Instruction Tightly Coupled Memory (ITCM) is the instruction cache space that supports offline reading and writing.

Instruction Decode Unit: (DeCode for short), set to decode;

Execution Unit (EXU), which is set to complete the execution of instructions;

Register File (Register File, referred to as RegFile for short) is set to complete the operation of internal general registers.

In order to improve the flexibility of the chip, the present disclosure imposes certain constraints on the input content (instructions), that is, a solution for instruction design is provided in the embodiment of the present disclosure, specifically:

The instructions include DTCM read and write instructions, basic integer operation instructions (addition, comparison, OR, AND, shift), unconditional jump instructions, and conditional jump instructions (equal, unequal, greater than, less than, greater than or equal to, less than or equal to).

The content of the instruction needs to include:

The instruction code (required), used to identify the action the instruction is intended to complete;

Operation address (required), read/write address of DTCM or read/write address of regfile;

Immediate value (optional), a specific operand;

regfile is 32 32-bit general registers, which are used with instructions, as shown in Figure 5. The general register at address 0 is always 0 and cannot be written. PC is the address of the instruction currently being processed.

In the disclosed embodiment, the designed instructions are written into the ITCM by the CPU and the device is started; the IFU controls the instruction reading address and reads the instruction; the DeCode completes the instruction parsing; and the EXU completes the instruction execution and data writeback.

The instructions designed in the disclosed embodiments are based on the RV32I basic instruction set in RSIC-V, directly borrowing some instructions and supplementing some custom instructions. The instruction design can be freely defined and expanded. The necessary instructions are read and write instructions, basic logical operation instructions and jump instructions.

1. Storage read and write instructions:

This group of instructions performs memory read or write operations, and the address used to access the memory is obtained by adding the value in the operand register rs1 to a 12-bit immediate value (with sign bit extension).

The LW instruction, as shown in Figure 6, reads 32 bits of data from the memory and writes it back to register rd;

The SW instruction, as shown in Figure 7, writes the 32-bit data in operand register rs2 back to the memory;

2. Basic integer operation instructions:

This group of instructions performs basic integer operations on registers and immediate values.

The ADDI instruction, as shown in Figure 8, adds the integer value in the operand register rs1 to the 12-bit immediate value (with the sign bit extended), and writes the result back to the register RD. If the result overflows, no special processing is required, and the overflowed bits are discarded, leaving only the lower 32 bits of the result.

The SLTIU instruction, as shown in Figure 9, compares the integer value in operand register rs1 with the 12-bit immediate value (sign extended) as an unsigned number. If the value in rs1 is less than the immediate value, the result is 1, otherwise it is 0. The result is written back to register RD.

ANDI instruction, as shown in FIG9 , performs an AND operation on the integer value in operand register rs1 and the 12-bit immediate value (with sign bit extended), and writes the result back to register rd.

The ORI instruction, as shown in FIG9 , performs an OR operation on the integer value in the operand register rs1 and the 12-bit immediate value (with sign bit extension), and writes the result back to the register rd.

The XORI instruction, as shown in FIG9 , performs an exclusive OR (XOR) operation on the integer value in the operand register rs1 and the 12-bit immediate value (with sign bit extension), and writes the result back to the register rd.

The SLLI instruction, as shown in FIG9 , performs a logical left shift operation on the integer value in the operand register rs1 (filling the low bits with 0), the shift amount is a 5-bit immediate value, and the result is written back to the register rd.

The SRLI instruction, as shown in FIG9 , performs a logical right shift operation on the integer value in the operand register rs1 (filling the high bits with 0), the shift amount is a 5-bit immediate value, and the result is written back to the register rd.

3. Data construction instructions:

The LUI instruction, as shown in FIG10 , shifts the value of the 20-bit immediate number left by 12 bits (fills the lower 12 bits with 0) to become a 32-bit number, and writes the number back to register rd.

4. Jump instruction, as shown in Figure 11 and Figure 12:

Figure 11 shows an unconditional jump instruction:

JAL instruction: Use a 20-bit immediate number (signed number) as an offset, and then add it to the PC of the instruction to generate the final jump target address. The jal instruction writes the value of the PC of the next instruction (that is, the current instruction PC+1) into its result register rd.

JALR instruction: Use 12-bit immediate number (signed number) as offset and add it to the value in operand register rs1 to get the final jump target address. The jalr instruction writes the value of the PC of the next instruction (i.e. the current instruction PC+1) into its result register rd.

Figure 12 shows the conditional jump instruction:

This group of instructions is a conditional jump instruction, which uses a 12-bit immediate number (signed number) as an offset, and then adds it to the PC of the instruction to generate the final jump target address. The conditional jump instruction needs to jump only when the condition is true, as follows.

BEQI instruction: It will jump only if the value in operand register rs1 is equal to the value of the 5-bit immediate value in the operand register.

BNEI instruction: It will jump only if the value in operand register rs1 is not equal to the value of the 5-bit immediate value in the operand register.

BGTUI instruction: It will jump only if the unsigned number in operand register rs1 is greater than the unsigned number of the 5-bit immediate value in the operand register.

BLEUI instruction: It will jump only if the unsigned number in operand register rs1 is less than or equal to the unsigned number in operand register 5-bit immediate value.

BLTUI instruction: It will jump only if the unsigned number in operand register rs1 is less than the unsigned number of the 5-bit immediate value in the operand register.

BGEUI instruction: It will jump only if the unsigned number in operand register rs1 is greater than or equal to the unsigned number in operand register 5-bit immediate value.

The disclosed embodiment designs a set of hardware architecture and imposes certain constraints on its input content (instructions). Based on the common hardware design, the programmable function similar to software is added, which realizes the programmability of state machine and even logic function, and provides a certain flexibility without increasing the chip power consumption area. To a certain extent, it solves the dilemma of chip design that requires both flexibility and low cost.

Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as a read-only memory/random access memory (ROM/RAM), a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

In the present embodiment, a processing system for a task to be processed is also provided, and the system is used to implement the above-mentioned embodiment and preferred implementation mode, and the descriptions that have been made are not repeated. As used below, the term "module" can implement a combination of software and/or hardware of a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

The embodiment of the present disclosure provides a processing system for a task to be processed. The processing system for the task to be processed in the embodiment of the present disclosure is located in the above-mentioned hardware accelerator. FIG. 14 is a structural block diagram of the processing system for the task to be processed according to the embodiment of the present disclosure. As shown in FIG. 14 , the system includes:

The instruction extraction unit 1402 is configured to determine an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; and determine an instruction address of each instruction to be executed in the instruction set;

The execution unit 1404 is configured to execute each of the to-be-executed instructions according to the instruction address of each of the to-be-executed instructions to process the to-be-processed tasks.

Through the above device, since the hardware accelerator can determine the instruction set of the task to be processed according to the preset instructions (i.e., it realizes the task programming of the task to be processed), and then processes the task to be processed by executing the instructions in the instruction set, the hardware accelerator can also flexibly process different tasks. Therefore, the problem of low flexibility in chip design can be solved, thereby achieving the effect of improving chip flexibility.

It should be noted that the processing system for the tasks to be processed in the embodiment of the present disclosure is located in the above-mentioned hardware accelerator, and the hardware accelerator processes the tasks to be processed through the processing system for the tasks to be processed. Therefore, the system structure of the processing system for the tasks to be processed in the embodiment of the present disclosure is similar to the internal structure of the above-mentioned hardware accelerator.

Since the system structure of the processing system for the task to be processed in the embodiment of the present disclosure is similar to the internal structure of the above-mentioned hardware accelerator, as shown in Figure 4, the processing system for the task to be processed also includes: a data tightly coupled memory, an instruction tightly coupled memory unit, an instruction decoding unit, an execution unit, and a register file.

It should be noted that, when the task to be processed is completed, the processing result is written back to the data tightly coupled memory in a preset format.

A register file is a component inside a processing system that is used to store and manage system registers. A register is a high-speed memory inside a system that is used to temporarily store instructions and data. A regfile usually contains multiple registers, such as general registers, program counter (PC), etc. A register file can provide the system with fast data storage and access capabilities to support the execution of instructions and the processing of data.

In an exemplary embodiment, the instruction extraction unit 1402 is configured to determine based on the parameter information and the requirement information A plurality of logical processing modes for the task to be processed; determining instructions corresponding to the plurality of logical processing modes, and determining the plurality of instructions as the instruction set.

In an exemplary embodiment, the instruction extraction unit is further configured to obtain a second instruction address in a program counter, wherein the program counter is used to store the instruction address of the next instruction to be executed; determine the instruction to be executed corresponding to the second instruction address in the instruction set based on the first instruction address of each instruction to be executed; and the execution unit is further configured to execute the instruction to be executed.

In an exemplary embodiment, an instruction decoding unit is configured to parse the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate number; generate a control signal corresponding to the first instruction information, and send the control signal to a corresponding execution unit to execute the instruction to be executed.

In an exemplary embodiment, the instruction decoding unit is further configured to be one of the following:

In a case where the first instruction information includes: the first instruction code and the first source operand, generating first sub-control information according to the type of the first instruction code, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal;

In a case where the first instruction information includes: the first instruction code, the first source operand, and the first target operand, generating first sub-control information according to the type of the first instruction code, generating a second sub-control signal for reading an operand register according to the first source operand, and generating a third sub-control signal for writing into a general register according to the first target operand, wherein the control signal includes: the first sub-control signal, the second sub-control signal, and the third sub-control signal;

In the case where the first instruction information includes: the first instruction code, the first immediate value and the first target operand, first sub-control information is generated according to the type of the first instruction code, a fourth sub-control signal for reading the first immediate value is generated, and a third sub-control signal for writing into a general register is generated according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal and the third sub-control signal.

In an exemplary embodiment, the above-mentioned device also includes: an instruction writing unit, configured to determine second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; the instruction to be written is determined according to the second instruction information.

It should be noted that the programmed instructions are stored in the instruction tightly coupled memory unit, and the instruction set is also stored in the instruction tightly coupled memory unit before being fetched.

It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

To facilitate the understanding of the technical solutions provided by the present disclosure, embodiments of the present invention will be described in detail below in conjunction with specific scenarios.

An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: a USB flash drive, a read-only storage medium, Various media that can store computer programs include Read-Only Memory (ROM), Random Access Memory (RAM), mobile hard disk, magnetic disk or CD, etc.

An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

In an exemplary embodiment, the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

Obviously, those skilled in the art should understand that the above modules or steps of the present disclosure can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims (11)

A method for processing a task to be processed, characterized in that it is applied to a hardware accelerator, comprising: Determine an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; Determining a first instruction address of each instruction to be executed in the instruction set; Each of the instructions to be executed is executed according to the first instruction address of each of the instructions to be executed, so as to process the task to be processed. The method according to claim 1, wherein determining the instruction set corresponding to the task to be processed according to the parameter information and requirement information of the task to be processed comprises: Determine multiple logical processing modes of the task to be processed according to the parameter information and the requirement information; Instructions corresponding to the multiple logical processing modes are determined, and the multiple instructions are determined as the instruction set. The method according to claim 1, wherein executing each of the instructions to be executed according to the first instruction address of each of the instructions to be executed comprises: Processing steps: obtaining a second instruction address in a program counter, wherein the program counter is configured to store an instruction address of a next instruction to be executed; Determine, in the instruction set, the instruction to be executed corresponding to the second instruction address according to the first instruction address of each instruction to be executed, and execute the instruction to be executed; The processing steps are executed in a loop until each instruction to be executed in the instruction set is completed. The method according to claim 3, wherein executing the to-be-executed instruction comprises: Parsing the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; Generate a control signal corresponding to the first instruction information, and send the control signal to the corresponding execution unit of the hardware accelerator to execute the instruction to be executed. The method according to claim 4, wherein generating a control signal corresponding to the first instruction information comprises at least one of the following: In a case where the first instruction information includes: the first instruction code and the first source operand, generating first sub-control information according to the type of the first instruction code, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal; In the case where the first instruction information includes: the first instruction code, the first source operand, and the first target operand, first sub-control information is generated according to the type of the first instruction code, a second sub-control signal for reading an operand register is generated according to the first source operand, and a second sub-control signal for writing a general register is generated according to the first target operand. A third sub-control signal, wherein the control signal includes: the first sub-control signal, the second sub-control signal and the third sub-control signal; In the case where the first instruction information includes: the first instruction code, the first immediate value and the first target operand, first sub-control information is generated according to the type of the first instruction code, a fourth sub-control signal for reading the first immediate value is generated, and a third sub-control signal for writing into a general register is generated according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal and the third sub-control signal. The method according to claim 1, wherein before obtaining the instruction set corresponding to the task to be processed, the method further comprises: Determine second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; The instruction to be written is determined according to the second instruction information. A processing system for tasks to be processed, comprising: An instruction extraction unit is configured to determine an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; and determine an instruction address of each instruction to be executed in the instruction set; The execution unit is configured to execute each of the instructions to be executed according to the instruction address of each of the instructions to be executed, so as to process the task to be processed. The system according to claim 7, further comprising: The instruction fetching unit is further configured to obtain a second instruction address in a program counter, wherein the program counter is used to store an instruction address of a next instruction to be executed; and determine, in the instruction set, an instruction to be executed corresponding to the second instruction address according to the first instruction address of each instruction to be executed; The execution unit is further configured to execute the instruction to be executed. The system according to claim 8, further comprising: An instruction decoding unit is configured to parse the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; Generate a control signal corresponding to the first instruction information, and send the control signal to a corresponding execution unit to execute the instruction to be executed. A computer-readable storage medium having a computer program stored therein, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6. An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of claims 1 to 6 when executing the computer program.