WO2025034215A1

WO2025034215A1 - Wireless communication device

Info

Publication number: WO2025034215A1
Application number: PCT/US2023/029832
Authority: WO
Inventors: Kanta HIROKI; Hiroyuki Tanabe; Ken Sakuma; Mark Yeck
Original assignee: Fujikura Ltd; International Business Machines Corp
Current assignee: Fujikura Ltd; International Business Machines Corp
Priority date: 2023-08-09
Filing date: 2023-08-09
Publication date: 2025-02-13
Anticipated expiration: 2026-02-09

Abstract

A wireless communication device includes a sensor control unit and a sensor unit. The sensor control unit operates in synchronization with a first clock. The sensor unit operates in synchronization with a second clock. The sensor control unit includes a counter. The counter counts rising edges of the first clock from 0 to 2M−1 (M is a natural number). The second clock rises at a rising edge of the first clock when a count value of the counter is 0 and falls at a rising edge of the first clock when the count value of the counter is M. The sensor control unit transmits a control signal to the sensor unit at a rising edge of the first clock when the count value of the counter is M.

Description

[DESCRIPTION]

[Title of Invention]

WIRELESS COMMUNICATION DEVICE

[Technical Field] [0001]

The present invention relates to a wireless communication device.

[Background Art]

[0002]

In recent years, wireless communication devices that perform wireless communication using high-frequency signals such as microwaves, quasi-millimeter waves, and millimeter waves have come into the spotlight. Such wireless communication devices include a master device and an RF front end controlled by the master device. The RF front end includes, for example, an analog/digital (A/D) converter, a sensor, and the like. The RF front end performs adjustment processing of transmission/reception strengths of wireless signals according to radio wave power, a temperature, a power supply voltage, and the like detected by sensors, and the like. In recent years, there have been a large number of types of RF front ends that perform beamforming processing.

[0003]

Patent Literature 1 below discloses a wireless communication system. In the wireless communication system, a master device and a plurality of RF front ends are connected via a serial communication bus. The wireless communication system discloses a technology in which the RF front ends each generate a new clock from a digital signal supplied from the master device via the serial communication bus and the generated clocks are appropnately used.

[Citation List]

[Patent Literature]

[0004]

[Patent Literature 1]

United States Patent No. 8774735

[Summary of Invention]

[Technical Problem] [0005]

Incidentally, the above-described Patent Literature 1 describes that an RF front end generates a new clock (second clock) by frequency-dividing a clock (first clock) supplied from a master device. However, there is no description of timing control between the first clock and the second clock. In the RF front end, in order to smoothly exchange signals between a circuit (for example, sensor control unit) operating in synchronization with the high-speed first clock and a circuit (for example, sensor unit) operating in synchronization with the low-speed second clock, it is extremely important to define timing control between the first clock and the second clock.

[0006]

The present invention has been made in view of the above circumstances, and an objective of the present invention is to provide a wireless communication device capable of smoothly exchanging signals between circuits operating with different clocks.

[Solution to Problem]

[0007]

In order to solve the above-described problems, a wireless communication device according to one aspect of the present invention includes a sensor unit and a sensor control unit. The sensor control unit is configured to operate in synchronization with a first clock. The sensor unit is configured to operate in synchronization with a second clock. The sensor control unit includes a counter. The counter is configured to count rising edges of the first clock from 0 to 2M-1 (M is a natural number). The second clock rises at a rising edge of the first clock when a count value of the counter is 0. The second clock falls at a rising edge of the first clock when the count value of the counter is M. The sensor control unit is configured to transmit a control signal to the sensor unit at a rising edge of the first clock when the count value of the counter is M.

[0008]

In the wireless communication device according to one aspect of the present invention, the sensor control unit operates in synchronization with the first clock. The sensor control unit generates the second clock that rises at a rising edge of the first clock when the count value of the counter is 0 and falls at a rising edge of the first clock when the count value of the counter is M by using the counter. Then, the sensor control unit transmits the control signal to the sensor unit that operates in synchronization with the second clock at a rising edge of the first clock when the count value of the counter is M. Thereby, exchange of signals can be smoothly performed between circuits operating with different clocks.

[0009]

Also, in the wireless communication device according to one aspect of the present invention, the sensor unit may be configured to transmit a read value of the sensor unit at a rising edge of the first clock when the count value of the counter is 0.

[0010]

Also, in the wireless communication device according to one aspect of the present invention, the sensor unit may include a plurality of sensors and one analog/digital converter. The analog/digital converter may be configured to convert a sensor signal output from the sensor selected by a selecting sensor signal into a sensor value. The sensor control unit may be configured to transmit a trigger signal for starting conversion by the analog/digital converter with a delay of the second clock by N (N is an integer of 0 or more) cycles after the selecting sensor signal has been transmitted.

[001 1 ]

Also, in the wireless communication device according to one aspect of the present invention, N may be a variable, and the sensor control unit may include a memory for storing N.

[0012]

Also, the wireless communication device according to one aspect of the present invention may further include a master control unit. The sensor control unit may be configured to control the trigger signal for starting conversion by the analog/digital converter on the basis of an input signal from the master control unit. The tngger signal for starting conversion by the analog/digital converter may be a pulse signal. A width of the pulse signal may be equal to one cycle of the second clock. A transmission interval of the trigger signal for starting conversion by the analog/digital converter may be twice a cycle of the second clock or more.

[0013] Also, in the wireless communication device according to one aspect of the present invention, the sensor control unit and the sensor unit may be mounted on the same integrated circuit.

[Advantageous Effects of Invention]

[0014]

According to one aspect of the present invention, there is an effect that exchange of signals can be smoothly performed between circuits operating with different clocks. [Brief Description of Drawings] [0015]

[FIG. 1]

FIG. 1 is a block diagram showing a configuration of a main portion of a wireless communication device according to a first embodiment of the present invention.

[FIG. 2]

FIG. 2 is a timing chart showing transmission timings of an input signal and a control signal in the first embodiment of the present invention.

[FIG. 3]

FIG. 3 is a timing chart showing transmission timings of a return signal and an output signal in the first embodiment of the present invention.

[FIG. 4]

FIG. 4 is a block diagram showing a configuration of a main portion of a wireless communication device according to a second embodiment of the present invention. [FIG. 5]

FIG. 5 is a timing chart showing transmission timings of an input signal, a selecting sensor signal, and a control signal in the second embodiment of the present invention. [FIG. 6]

FIG. 6 is a block diagram showing a configuration for setting a transmission timing of a trigger signal of the wireless communication device according to the second embodiment of the present invention.

[FIG. 7]

FIG. 7 is a timing chart showing transmission timings of an input signal and a control signal in a third embodiment of the present invention.

[FIG. 8] FIG. 8 is a diagram showing a state transition of a sensor control unit according to a fourth embodiment of the present invention.

[Descnption of Embodiments]

[0016]

Hereinafter, wireless communication devices according to embodiments of the present invention will be described in detail with reference to the drawings.

[0017]

<First Embodiment

A wireless communication device according to a first embodiment of the present invention performs wireless communication using, for example, a millimeter waveband. The wireless communication device includes, for example, a phased array antenna module, and is capable of beamforming that can freely change a beam pattern. The phased array antenna module includes, for example, a plurality of integrated circuits (ICs) mounted on one surface of a substrate such as a known printed circuit board, and an antenna array mounted on the other surface of the substrate.

[0018]

The plurality of TCs and the antenna array constituting the phased array antenna module are formed using known materials and using known methods. Also, an electrical connection structure between the plurality of ICs and an electrical connection structure between the ICs and the antenna array are not particularly limited. A know n connection structure is employed as the electrical connection structure.

[0019]

FIG. 1 is a block diagram showing a configuration of a main portion of a wireless communication device according to the first embodiment of the present invention. As shown in FIG. 1, a wireless communication device 1 includes a master control unit 10, a sensor control unit 20, and a sensor unit 30. The master control unit 10 performs control of the entire wireless communication device 1. For example, the master control unit 10 performs control of transmission/reception of wireless signals, control of the beamforming described above, and control of transmission/reception strength of wireless signals according to radio wave power, a temperature, a power supply voltage, and the like detected by the sensor unit 30, or the like.

[0020] The sensor control unit 20 performs control of the sensor unit 30. Specifically, the sensor control unit 20 performs control for starting an operation of the sensor unit 30 and acquiring a sensor value obtained by the sensor unit 30. The sensor unit 30 includes sensors and an analog/digital (A/D) converter. Under control of the sensor control unit 20, the sensor unit 30 converts the detected sensor signal (analog signal) into a sensor value (digital signal) and outputs the sensor value to the sensor control unit 20. As the sensors provided in the sensor unit 30, a sensor that detects power of radio waves transmitted from the antenna array, a sensor that detects a temperature, a sensor that detects a power supply voltage, and the like can be mentioned. Further, the sensor control unit 20 and the sensor unit 30 may be mounted on, for example, the same integrated circuit. [0021]

As shown in FIG. 1, a first clock (FCLK) and an input signal (INPUT SIGNAL) are transmitted from the master control unit 10 to the sensor control unit 20. The first clock is a clock that is used as a reference for operations of the master control unit 10 and the sensor control unit 20. That is, the master control unit 10 and the sensor control unit 20 operate in synchronization with the first clock. A frequency of the first clock is, for example, about hundreds of MHz. The input signal is a signal for causing the sensor control unit 20 to acquire a sensor value from the sensor unit 30. [0022]

A second clock (SNCLK) and a control signal (CONTROL SIGNAL) are transmitted from the sensor control unit 20 to the sensor unit 30. The second clock is a clock that is used as a reference for an operation of the sensor unit 30. That is, the sensor unit 30 operates in synchronization with the second clock. A frequency of the second clock is, for example, about tens of MHz. The second clock is a clock generated by dividing the frequency of the first clock in the sensor control unit 20. Some reasons why the frequency of the second clock is lower than that of the first clock are that a response time of the sensor unit 30 is longer than response times of the master control unit 10 and the sensor control unit 20, there is a difference in setup/hold time, and the like. [0023]

The sensor control unit 20 includes a counter. The counter counts rising edges of the first clock from 0 to 2M-1 (M is a natural number). The sensor control unit 20 generates the second clock by dividing the frequency of the first clock by 2M. For example, if the frequency of the first clock is 100 MHz and the frequency of the second clock is 10 MHz, then M = 5. That is, the sensor control unit 20 generates the second clock with a frequency of 10 MHz by dividing the first clock with a frequency of 100 MHz by 10. The control signal is a signal for controlling the sensor unit 30. Specifically, the control signal is a signal for performing control for starting an operation of the sensor unit 30 and acquiring a sensor value obtained by the sensor unit 30.

[0024]

A return signal (RETURN SIGNAL) is transmitted from the sensor unit 30 to the sensor control unit 20. The return signal is a signal in response to the control signal transmitted from the sensor control unit 20 to the sensor unit 30, and is a signal containing, for example, a sensor value (read value of the sensor unit 30). An output signal (OUTPUT SIGNAL) is transmitted from the sensor control unit 20 to the master control unit 10. The output signal is a signal in response to the input signal transmitted from the master control unit 10 to the sensor control unit 20, and is a signal containing, for example, the sensor value described above.

[0025]

FIG. 2 is a timing chart showing transmission timings of the input signal and the control signal in the first embodiment of the present invention. Further, in FIG. 2, a case in which M = 3 is shown as an example. That is, a case in which the sensor control unit 20 generates the second clock by dividing the frequency of the first clock by 6 is shown as an example.

[0026]

As show n in FIG. 2, the counter (FCLK edge counter) provided in the sensor control unit 20 counts rising edges of the first clock (FCLK). The second clock (SNCLK) rises at a rising edge of the first clock when the count value of the counter is 0, and falls at a rising edge of the first clock when the count value of the counter is M. Further, when the count value of the counter is 2M-1, the count value of the counter is 0 at the rising edge of the first clock.

[0027] As shown in FIG. 2, it is assumed that the input signal (INPUT SIGNAL) is transmitted from the master control unit 10 to the sensor control unit 20 at a time tl 1. Further, the time tl 1 shown in FIG. 2 is a time at which the count value of the counter provided in the sensor control unit 20 is 2M-I. The sensor control unit 20 transmits the control signal (CONTROL SIGNAL) based on this input signal to the sensor unit 30 at the rising edge of the first clock when the count value of the counter is M. That is, for the sensor unit 30, the sensor control unit 20 transmits the control signal based on the input signal to the sensor unit 30 at a time tl 2 at which a half cycle or more of the second clock has elapsed from the time tl 1 at which the input signal has been transmitted. Here, the time tl 2 is also a timing at which the second clock falls.

[0028]

As described above, in the present embodiment, the control signal is transmitted from the sensor control unit 20 to the sensor unit 30 at a timing at which the first clock rises and the second clock falls when the count value of the counter provided in the sensor control unit 20 is M. Therefore, exchange of the control signal based on the input signal transmitted from the master control unit 10 can be smoothly performed between the sensor control unit 20 operating in synchronization with the first clock and the sensor unit 30 operating in synchronization with the second clock.

[0029]

FIG. 3 is a timing chart showing transmission timings of the return signal and the output signal in the first embodiment of the present invention. Further, in FIG. 3, a case in which M = 3 is shown as an example as in FIG. 2. That is, a case in which the sensor control unit 20 generates the second clock by dividing the frequency of the first clock by 6 is shown as an example. Further, since a method of generating the second clock from the first clock using the counter provided in the sensor control unit 20 is the same as the method described with reference to FIG. 2, description thereof will be omitted. [0030]

As shown in FIG. 3, it is assumed that the return signal (RETURN SIGNAL) is transmitted from the sensor unit 30 to the sensor control unit 20 at a time t21. Further, the time t21 shown in FIG. 3 is a time at which the count value of the counter provided in the sensor control unit 20 is 0, and both the first clock and the second clock rise. The sensor control unit 20 transmits the output signal (OUTPUT SIGNAL) based on the return signal to the master control unit 10 at a rising edge of the first clock when the count value of the counter is M. That is, the sensor control unit 20 transmits the output signal based on the return signal to the master control unit 10 at a time t22 at which a half cycle of the second clock has elapsed from the time t21 at which the return signal has been transmitted. Here, the time t22 is also a timing at which the second clock falls. [0031]

As described above, in the present embodiment, the output signal is transmitted from the sensor control unit 20 to the master control unit 10 at a timing at which the first clock rises and the second clock falls when the count value of the counter provided in the sensor control unit 20 is M. Therefore, exchange of the output signal based on the return signal transmitted from the sensor unit 30 can be smoothly performed between the sensor control unit 20 operating in synchronization with the first clock and the sensor unit 30 operating in synchronization with the second clock.

[0032]

Also, in the present embodiment, since it may take longer time than one cycle of the first clock until a read value of the sensor stabilizes, the sensor unit 30 operates in synchronization with the second clock which has a lower frequency than the first clock. In the present embodiment, since the sensor control unit 20 transmits the return signal containing the read value of the sensor unit 30 to the master control unit 10 as an output signal after a half cycle of the second clock has elapsed, the read value of the sensor unit 30 after being stabilized can be transmitted to the master control unit 10.

[0033]

<Second Embodiment

FIG. 4 is a block diagram showing a configuration of a main portion of a wireless communication device according to a second embodiment of the present invention. As shown in FIG. 4, a wireless communication device 2 according to the present embodiment includes a sensor control unit 20A instead of the sensor control unit 20 shown in FIG. 1, and a sensor unit 30A instead of the sensor unit 30 shown in FIG. 1. Further, in FIG. 4, illustration of the master control unit 10 shown in FIG. 1 is omitted. [0034]

The sensor control unit 20A performs control of the sensor unit 30A. Specifically, the sensor control unit 20A performs control for starting an operation of the sensor unit 30A and acquiring a sensor value obtained by the sensor unit 30A. The sensor unit 30A includes a plurality of sensors 31 and one A/D converter 32, and converts a sensor signal (analog signal) detected by any of the plurality of sensors 31 into a sensor value (digital signal) to output it to the sensor control unit 20A under control of the sensor control unit 20 A.

[0035]

As the plurality of sensors 31, a sensor that detects power of radio waves transmitted from an antenna array, a sensor that detects a temperature, a sensor that detects a power supply voltage, and the like can be mentioned. The sensor that detects power of radio waves may be provided for each of a plurality of antenna elements forming the antenna array. Further, the sensor control unit 20A and the sensor unit 30A may be mounted on, for example, the same integrated circuit.

[0036]

Similarly to the first embodiment, a first clock (FCLK) and an input signal (INPUT SIGNAL) are transmitted from the master control unit 10 (not shown) to the sensor control unit 20A. Also, an output signal (OUTPUT SIGNAL) is transmitted from the sensor control unit 20 A to the master control unit 10 (not shown) as in the first embodiment.

[0037]

A second clock (SNCLK), a control signal (CONTROL SIGNAL), and a selecting sensor signal (SELECTING SENSOR SIGNAL) are transmitted from the sensor control unit 20A to the sensor unit 30A. The second clock is a clock that is used as a reference for an operation of the sensor unit 30A. That is, the sensor unit 30A operates in synchronization with the second clock. Further, similarly to the sensor control unit 20 shown in FIG. 1, the sensor control unit 20A includes a counter that counts rising edges of the first clock from 0 to 2M-1, and generates the second clock by dividing a frequency of the first clock by 2M.

[0038]

The control signal is a signal for controlling the sensor unit 30A. Specifically, the control signal is a signal containing a trigger signal (ADC TRIGGER: see FIG. 5) for starting conversion by the A/D converter 32 provided in the sensor unit 30A. The selecting sensor signal is a signal for selecting one sensor 31 from the plurality of sensors 31 provided in the sensor unit 30A. The sensor unit 30A is configured to include one A/D converter 32, and a read value of the sensor unit 30A is limited to one sensor value at a time. Therefore, the selecting sensor signal for selecting one sensor 31 from the plurality of sensors 31 provided in the sensor unit 30A is used.

[0039]

A return signal (RETURN SIGNAL) is transmitted from the sensor unit 30A to the sensor control unit 20A as in the first embodiment. The return signal is a signal in response to the control signal transmitted from the sensor control unit 20A to the sensor unit 30A. The return signal is, for example, a signal containing a sensor value (read value of the sensor unit 30A) of the sensor 31 selected by the selecting sensor signal. [0040]

FIG. 5 is a timing chart showing transmission timings of the input signal, the selecting sensor signal, and the control signal in the second embodiment of the present invention. Further, in FIG. 5, a case in which M = 3 is shown as an example as in FIGS. 2 and 3. That is, a case in which the sensor control unit 20A generates the second clock by dividing the frequency of the first clock by 6 is shown as an example. Further, since a method of generating the second clock from the first clock using the counter provided in the sensor control unit 20A is the same as that in the first embodiment, description thereof will be omitted.

[0041]

As shown in FIG. 5, it is assumed that the input signal (INPUT SIGNAL) is transmitted from the master control unit 10 to the sensor control unit 20A at a time t31. Further, similarly to the time tl 1 shown in FIG. 2, the time 131 shown in FIG. 5 is a time at which a count value of the counter provided in the sensor control unit 20A is 2M-1. The sensor control unit 20A transmits the selecting sensor signal (SELECTING SENSOR SIGNAL in FIG. 5) based on the input signal to the sensor unit 30A at a rising edge of the first clock when the count value of the counter is M. That is, the sensor control unit 20A transmits the selecting sensor signal based on the input signal to the sensor unit 30A at a time 132 at which a half cycle or more of the second clock has elapsed from the time t31 at which the input signal has been transmitted. Here, the time t32 is also a timing at which the second clock falls.

[0042] As described above, in the present embodiment, the selecting sensor signal is transmitted from the sensor control unit 20A to the sensor unit 30A at a timing at which the first clock rises and the second clock falls when the count value of the counter provided in the sensor control unit 20A is M. Therefore, exchange of the selecting sensor signal based on the input signal transmitted from the master control unit 10 can be smoothly performed between the sensor control unit 20A operating in synchronization with the first clock and the sensor unit 30A operating in synchronization with the second clock.

[0043]

Also, in the present embodiment, the control signal (trigger signal: ADC TRIGGER) is transmitted from the sensor control unit 20A to the sensor unit 30A with a delay of the second clock by N cycles after the selecting sensor signal has been transmitted from the sensor control unit 20A to the sensor unit 30A. In the example show n in FIG. 5, the trigger signal is transmitted at a time t33 which is delayed by one cycle of the second clock from the time t32 at which the selecting sensor signal has been transmitted. [0044]

Here, if the conversion by the A/D converter 32 is started before the sensor signal (analog signal) output from the sensor 31 selected by the selecting sensor signal reaches a steady state, the read value of the sensor unit 30A is an incorrect value. Therefore, in the present embodiment, it is configured such that the control signal (trigger signal: ADC TRIGGER) is transmitted from the sensor control unit 20 A to the sensor unit 30A with a delay of the second clock by N cycles after the selecting sensor signal has been transmitted from the sensor control unit 20A to the sensor unit 30A.

[0045]

As shown in FIG. 5, similarly to the selecting sensor signal, the control signal (trigger signal: ADC TRIGGER) is transmitted at a timing at which the first clock rises and the second clock falls when the count value of the counter provided in the sensor control unit 20A is M. Therefore, exchange of the trigger signal can be smoothly performed between the sensor control unit 20A operating in synchronization with the first clock and the sensor unit 30A operating in synchronization with the second clock.

[0046] The above-described N is defined according to a time required for the sensor signal output from the sensor 31 selected by the selecting sensor signal to reach a steady state. That is, the above-described N is a variable. Here, if the time required for the sensor signal (analog signal) output from the sensor 31 selected by the selecting sensor signal to reach a steady state is short, the selecting sensor signal and the trigger signal may be transmitted at the same time. That is, the above-described N is set to an integer of 0 or more.

[0047]

FIG. 6 is a block diagram showing a configuration for setting a transmission timing of the trigger signal of the wireless communication device according to the second embodiment of the present invention. As shown in FIG. 6, the sensor control unit 20A includes a memory 21 and an ADC state machine 22. The memory 21 stores the abovedescribed N. The memory 21 may be a non-volatile memory such as a flash memory or a volatile memory using a flip-flop or the like. The ADC state machine 22 is a configuration that defines a state transition of the A/D converter 32 provided in the sensor unit 30A.

[0048]

As show n in FIG. 6, the above-described N is stored in the memory 21 of the sensor control unit 20A by the master control unit 10. Then, when the ADC state machine 22 reads and sets the above-described N stored in the memory 21, a timing at which the trigger signal is transmitted is defined. Further, the timing at which the trigger signal is transmitted can be changed by changing a value of the above-described N that is stored in the memory 21 of the sensor control unit 20A by the master control unit 10. [0049]

<Third Embodiment

FIG. 7 is a timing chart showing transmission timings of an input signal and a control signal in a third embodiment of the present invention. Further, in FIG. 7, a case in which M = 3 is shown as an example as in FIGS. 2, 3, and 5. That is, a case in which a sensor control unit 20A generates a second clock by dividing the frequency of a first clock by 6 is shown as an example. Further, a configuration of the wireless communication device in the present embodiment is assumed to be the same as that of the wireless communication device 2 shown in FIG. 4. Also, since a method of generating the second clock from the first clock using a counter provided in the sensor control unit 20A is the same as that in the first embodiment, description thereof will be omitted.

[0050]

Further, signals S2 and S3 shown in FIG. 7 are internal signals generated inside the sensor control unit 20 A.

[0051]

As shown in FIG. 7, it is assumed that an input signal (INPUT SIGNAL) is transmitted from a master control unit 10 to the sensor control unit 20A at a time t41. Further, similarly to the time tl 1 shown in FIG. 2 and the time t31 shown in FIG. 5, the time t41 shown in FIG. 7 is a time at which a count value of the counter provided in the sensor control unit 20A is 2M-1. Further, in the present embodiment, in order to simplify the explanation, a case in which the selecting sensor signal and the trigger signal shown in FIG. 4 are transmitted at the same time will be described.

[0052]

When the input signal transmitted from the master control unit 10 is input, the internal signal S2 shown in FIG. 7 is generated in the sensor control unit 20A. The internal signal S2 is a pulse signal having a pulse width for one cycle of the first clock and having a cycle for two cycles of the second clock. Also, in the sensor control unit 20A, the internal signal S3 is generated using the internal signal S2. The internal signal S3 is a pulse signal rising at a rising edge of the first clock when the internal signal S2 is 1, having a pulse width for one cycle of the second clock, and having a cycle for two cycles of the second clock. Further, the internal signal S3 may be a pulse signal having a cycle equal to or more than two cycles of the second clock.

[0053]

The sensor control unit 20 A generates a control signal (trigger signal: ADC TRIGGER) based on the input signal using the internal signal S3. Specifically, the sensor control unit 20A transmits the internal signal S3 generated from the input signal to the sensor unit 30A as a control signal at a rising edge of the first clock when the count value of the counter is M. That is, the sensor control unit 20A transmits the internal signal S3 generated from the input signal to the sensor unit 30A as a control signal at a time t42 at which a half cycle or more of the second clock has elapsed from the time t41 at which the input signal has been transmitted. Here, the time t42 is also a timing at which the second clock falls.

[0054]

Here, the internal signal S3 generated from the input signal is a pulse signal having a pulse width for one cycle of the second clock and having a cycle for two cycles of the second clock as described above. Therefore, as shown in FIG. 7, the control signal is also transmitted to the sensor unit 30A at a time t43 at which a time for two cy cles of the second clock has elapsed since the time t42.

[0055]

In this way, in the present embodiment, the control signal is transmitted from the sensor control unit 20A to the sensor unit 30A at a timing at which the first clock rises and the second clock falls when the count value of the counter provided in the sensor control unit 20A is M. Therefore, exchange of the control signal based on the input signal transmitted from the master control unit 10 can be smoothly performed between the sensor control unit 20A operating in synchronization with the first clock and the sensor unit 30A operating in synchronization with the second clock.

[0056]

Also, in the present embodiment, while the input signal transmitted from the master control unit 10 is being input, the control signal is transmitted from the sensor control unit 20A to the sensor unit 30A with a time interval corresponding to two cycles of the second clock. Thereby, a plurality of sensor values can be acquired without the master control unit 10 transmitting the input signal to the sensor control unit 20A a plurality of times to acquire a plurality of sensor values. As a result, a processing load of the master control unit 10 can be reduced, and a processing capability of the master control unit 10 can be distributed to other processing of the wireless communication device.

[0057]

<Fourth Embodiment?*

FIG. 8 is a diagram showing a state transition of a sensor control unit according to a fourth embodiment of the present invention. In the present embodiment, it is based on the premise that a transmission interval of a control signal with respect to a sensor unit 30A is longer than a time from a rise to a fall of a control signal (trigger signal) for starting acquisition of a sensor value. Further, a configuration of a wireless communication device in the present embodiment is assumed to be the same as that of the wireless communication device 2 shown in FIG. 4. Also, since a method of generating a second clock from a first clock using a counter provided in a sensor control unit 20A is the same as that in the first embodiment, description thereof will be omitted. [0058]

As shown in FIG. 8, states of the sensor control unit 20A include a sensor setting state STI, a buffer state ST2, and a read state ST3. State transitions are possible between the sensor setting state STI and the buffer state ST2. Also, if the buffer state ST2 has transitioned to the read state ST3, it is only possible to transition from the read state ST3 to the sensor setting state STI.

[0059]

When an input signal from a master control unit 10 is received, the sensor control unit 20A transitions to the buffer state ST2 in which it waits for transmission of a control signal (trigger signal) to the sensor unit 30A. In the buffer state ST2, the sensor control unit 20A transmits the control signal to the sensor unit 30A after waiting for a time longer than the time from the rise to the fall of the trigger signal for starting acquisition of the sensor value. When the transmission of the control signal is completed, the sensor control unit 20A transitions to the read state ST3.

[0060]

In the buffer state ST2, the standby time is longer than the time from the rise to the fall of the trigger signal for starting acquisition of the sensor value. Therefore, acquisition of the sensor value can be reliably started at a stage when setting of the sensor is completed. Thereby, it is possible to prevent a situation in which acquisition of the sensor value fails.

[0061]

If the master control unit 10 transmits the input signal to the sensor control unit 20A when a state of the sensor control unit 20A is the buffer state ST2 or the read state ST3, the state of the sensor control unit 20A transitions to the sensor setting state STI. Thereby, resetting of the sensor unit 30A is possible.

[0062]

Although the wireless communication devices according to the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be freely changed within the scope of the present invention. For example, the wireless communication devices according to the first to fourth embodiments descnbed above have been described as performing wireless communication using a millimeter waveband, but they may perform wireless communication using frequency bands other than the millimeter waveband. Also, the wireless communication devices according to the first to fourth embodiments described above capable of beamforming have been described as an example, but they may not be capable of beamforming.

[0063]

Also, in the wireless communication devices according to the first to fourth embodiments described above, as the sensors provided in the sensor units 30 and 30A, a sensor that detects power of radio waves transmitted from an antenna array, a sensor that detects a temperature, a sensor that detects a power supply voltage, and the like have been mentioned. However, the sensors provided in the sensor units 30 and 30A are not limited to these sensors, and other sensors may be provided. For example, a sensor that measures a quality of wireless signals such as a received signal strength indicator (RSST) may be provided.

[Reference Signs List]

[0064]

1, 2 Wireless communication device

20, 20A Sensor control unit

21 Memory

30, 30A Sensor unit

31 Sensor

32 A/D Converter

CONTROL SIGNAL Control signal

FCLK First clock

SELECTING SENSOR SIGNAL Selecting sensor signal SNCLK Second clock

Claims

[CLAIMS]

[Claim 1]

A wireless communication device comprising: a sensor control unit configured to operate in synchronization with a first clock; and a sensor unit configured to operate in synchronization with a second clock, wherein the sensor control unit comprises a counter, the counter is configured to count rising edges of the first clock from 0 to 2M-1 (M is a natural number), the second clock rises at a rising edge of the first clock when a count value of the counter is 0, the second clock falls at a rising edge of the first clock when the count value of the counter is M, and the sensor control unit is configured to transmit a control signal to the sensor unit at a rising edge of the first clock when the count value of the counter is M.

[Claim 2]

The wireless communication device according to claim 1, wherein the sensor unit is configured to transmit a read value of the sensor unit at a rising edge of the first clock when the count value of the counter is 0.

[Claim 3]

The wireless communication device according to claim 1 or 2, wherein the sensor unit comprises a plurality of sensors and one analog/digital converter, the analog/digital converter is configured to convert a sensor signal output from the sensor selected by a selecting sensor signal into a sensor value, and the sensor control unit is configured to transmit a trigger signal for starting conversion by the analog/digital converter with a delay of the second clock by N (N is an integer of 0 or more) cycles after the selecting sensor signal has been transmitted.

[Claim 4]

The wireless communication device according to claim 3, wherein

N is a variable, and the sensor control unit comprises a memory' for storing N.

[Claim 5] The wireless communication device according to claim 3, further comprising a master control unit, wherein the sensor control unit is configured to control the trigger signal for starting conversion by the analog/digital converter on the basis of an input signal from the master control unit, the trigger signal for starting conversion by the analog/digital converter is a pulse signal, a width of the pulse signal is equal to one cycle of the second clock, and a transmission interval of the trigger signal for starting conversion by the analog/digital converter is twice a cycle of the second clock or more.

[Claim 6]

The wireless communication device according to claim 1, wherein the sensor control unit and the sensor unit are mounted on the same integrated circuit.