WO2025030359A1

WO2025030359A1 - Interleaver design for modulation with polar codes

Info

Publication number: WO2025030359A1
Application number: PCT/CN2023/111660
Authority: WO
Inventors: Liangming WU; Kirill Ivanov; Jian Li
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2023-08-08
Filing date: 2023-08-08
Publication date: 2025-02-13
Anticipated expiration: 2026-02-08

Abstract

Aspects of the disclosure are directed to techniques for wireless communication, and specifically, to methods for interleaving and deinterleaving wireless data. In some examples, a wireless node may encode a plurality of bits to yield encoded bits. In some examples, the wireless node may interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset. In some examples, the wireless node may map: (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level.

Description

INTERLEAVER DESIGN FOR MODULATION WITH POLAR CODES

BACKGROUND Technical Field

The present disclosure generally relates to communication systems, and more particularly, to interleaver designs for modulation with polar codes.

Introduction

Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. Typical wireless communication systems may employ multiple-access technologies capable of supporting communication with multiple users by sharing available system resources. Examples of such multiple-access technologies include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, and time division synchronous code division multiple access (TD-SCDMA) systems.

These multiple access technologies have been adopted in various telecommunication standards to provide a common protocol that enables different wireless devices to communicate on a municipal, national, regional, and even global level. An example telecommunication standard is 5G New Radio (NR) . 5G NR is part of a continuous mobile broadband evolution promulgated by Third Generation Partnership Project (3GPP) to meet new requirements associated with latency, reliability, security, scalability (e.g., with Internet of Things (IoT) ) , and other requirements. 5G NR includes services associated with enhanced mobile broadband (eMBB) , massive machine type communications (mMTC) , and ultra-reliable low latency communications (URLLC) . Some aspects of 5G NR may be based on the 4G Long Term Evolution (LTE) standard. There exists a need for further improvements in 5G NR technology. These improvements may also be applicable to other multi-access technologies and the telecommunication standards that employ these technologies.

SUMMARY

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

In some aspects, the techniques described herein relate to an apparatus for wireless communication, including: one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to: encode a plurality of bits to yield encoded bits; interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; map the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and output, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

In some aspects, the techniques described herein relate to an apparatus for wireless communication, including: one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to: obtain, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset; deinterleave the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and decode the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

In some aspects, the techniques described herein relate to a method for wireless communication at a wireless node, including: encoding a plurality of bits to yield encoded bits; interleaving: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and outputting, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

In some aspects, the techniques described herein relate to a method for wireless communication at a wireless node, including: obtaining, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset; deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

In some aspects, the techniques described herein relate to an apparatus for wireless communication, including: means for encoding a plurality of bits to yield encoded bits; interleaving: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; means for mapping the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and means for outputting, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

In some aspects, the techniques described herein relate to an apparatus for wireless communication, including: means for obtaining, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset; means for deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and means for decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

A non-transitory, computer-readable medium comprising computer executable code, the code when executed by one or more processors causes the one or more processors to, individually or in combination: encode a plurality of bits to yield encoded bits; interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; map the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and output, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

A non-transitory, computer-readable medium comprising computer executable code, the code when executed by one or more processors causes the one or more processors to, individually or in combination: obtain, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset; deinterleave the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and decode the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example of a wireless communications system and an access network.

FIG. 2A is a diagram illustrating an example of a first frame, in accordance with various aspects of the present disclosure.

FIG. 2B is a diagram illustrating an example of DL channels within a subframe, in accordance with various aspects of the present disclosure.

FIG. 2C is a diagram illustrating an example of a second frame, in accordance with various aspects of the present disclosure.

FIG. 2D is a diagram illustrating an example of UL channels within a subframe, in accordance with various aspects of the present disclosure.

FIG. 3 is a diagram illustrating an example of a base station and user equipment (UE) in an access network.

FIG. 4 is a block diagram illustrating an example disaggregated base station architecture.

FIG. 5 is a block diagram illustrating an example of a device for use in wireless communications that supports polar codes and modulation mapping.

FIG. 6 is a block diagram illustrating another example of a device for use in wireless communications that supports polar codes and modulation mapping.

FIG. 7 is a block diagram illustrating an example technique for separating a block of encoded bits (X) .

FIG. 8 is a block diagram illustrating an example of a pair of interleavers receiving subsets of encoded bits and outputting interleaved subsets.

FIG. 9 is a flowchart of a method of wireless communication.

FIG. 10 is a diagram illustrating an example of a hardware implementation for an example apparatus.

FIG. 11 is a flowchart of a method of wireless communication.

FIG. 12 is a diagram illustrating another example of a hardware implementation for another example apparatus.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Aspects of the disclosure are directed to interleaver designs for modulation with polar codes. In some examples, the interleaver designs may be used with high order modulation schemes (e.g., modulation with an order of 4 or higher, such as quadrature phase-shift keying (QPSK) , and m-ary quadrature amplitude modulation (m-QAM) ) .

Generally, the described techniques provide for a transmitting entity (e.g., a base station or other network entity) and a receiver (e.g., a user equipment or other mobile entity) including a polar coder, an interleaver, and a modulation mapper that cooperate to provide polar encoding/decoding. In certain aspects, the transmitting entity be configured to use multiple interleavers for interleaving polar encoded bits. The transmitting entity may then map the interleaved encoded bits to different bit levels. For example, instead of using a single interleaver to interleave an entire encoded block of bits, the transmitting entity may split the encoded block of bits into subsets of encoded bits and input each subset into a one of the multiple interleavers to maximize diversity combining.

In some examples, the multiple interleavers may all use a same interleaver pattern (e.g., each of the interleavers is a triangular interleaver, a rectangular interleaver, or any other suitable interleaver pattern) . In some examples, different interleavers may be used for different bit-levels. Here, a block of encoded bits may be split such that the number of subsets of encoded bits equals the number of bit-levels. Thus, for example, using a 4-QAM modulation scheme, each modulated symbol can be represented by k= log₂ (4) = 2 bit-levels.

In certain aspects, the multiple interleavers may all be the same interleaver, but configured to shift encoded bits based on their respective indices. For example, the transmitting device may split a block of eight encoded bits into two subsets of four encoded bits, wherein the four bits of each subset each subset are identifiable by an index value. Here, the four encoded bits of the first subset may be indexed as 1-4, and the four encoded bits of the second subset may be indexed as 1-4. Accordingly, the encoded bits of the first subset may be input into a first interleaver in order (e.g., 1, 2, 3, 4) . However, the encoded bits of the second subset may be input into a second interleaver after a cyclic shift (e.g., 2, 3, 4, 1) . Thus, in this example, the cyclic shift may be a shift of 1-bit relative to the previous interleaver (e.g., a 1-bit shift may be successively applied to additional interleavers by shifting the corresponding four-bit subset by 1-bit relative to the previous shift) .

Thus, multiple interleavers, each having a pseudo-randomized input order of bits may be used across different bit-levels to increase polarization and improve performance of a polar coded scheme.

Several aspects of telecommunication systems will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as “elements” ) . These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs) , central processing units (CPUs) , application processors, digital signal processors (DSPs) , reduced instruction set computing (RISC) processors, systems on a chip (SoC) , baseband processors, field programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

Accordingly, in one or more example embodiments, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random-access memory (RAM) , a read-only memory (ROM) , an electrically erasable programmable ROM (EEPROM) , optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

FIG. 1 is a diagram illustrating an example of a wireless communications system and an access network 100. The wireless communications system (also referred to as a wireless wide area network (WWAN) ) includes base stations 102, user equipment (s) (UE) 104, an Evolved Packet Core (EPC) 160, and another core network 190 (e.g., a 5G Core (5GC) ) . The base stations 102 may include macrocells (high power cellular base station) and/or small cells (low power cellular base station) . The macrocells include base stations. The small cells include femtocells, picocells, and microcells.

The base stations 102 configured for 4G Long Term Evolution (LTE) (collectively referred to as Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) ) may interface with the EPC 160 through first backhaul links 132 (e.g., S1 interface) . The base stations 102 configured for 5G New Radio (NR) (collectively referred to as Next Generation RAN (NG-RAN) ) may interface with core network 190 through second backhaul links 184. In addition to other functions, the base stations 102 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity) , inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, Multimedia Broadcast Multicast Service (MBMS) , subscriber and equipment trace, RAN information management (RIM) , paging, positioning, and delivery of warning messages. The base stations 102 may communicate directly or indirectly (e.g., through the EPC 160 or core network 190) with each other over third backhaul links 134 (e.g., X2 interface) . The first backhaul links 132, the second backhaul links 184, and the third backhaul links 134 may be wired or wireless.

The base stations 102 may wirelessly communicate with the UEs 104. Each of the base stations 102 may provide communication coverage for a respective geographic coverage area 110. There may be overlapping geographic coverage areas 110. For example, the small cell 102' may have a coverage area 110' that overlaps the coverage area 110 of one or more macro base stations 102. A network that includes both small cell and macrocells may be known as a heterogeneous network. A heterogeneous network may also include Home Evolved Node Bs (eNBs) (HeNBs) , which may provide service to a restricted group known as a closed subscriber group (CSG) . The communication links 120 between the base stations 102 and the UEs 104 may include uplink (UL) (also referred to as reverse link) transmissions from a UE 104 to a base station 102 and/or downlink (DL) (also referred to as forward link) transmissions from a base station 102 to a UE 104. The communication links 120 may use multiple-input and multiple-output (MIMO) antenna technology, including spatial multiplexing, beamforming, and/or transmit diversity. The communication links may be through one or more carriers. The base stations 102 /UEs 104 may use spectrum up to Y megahertz (MHz) (e.g., 5, 10, 15, 20, 100, 400, etc. MHz) bandwidth per carrier allocated in a carrier aggregation of up to a total of Yx MHz (x component carriers) used for transmission in each direction. The carriers may or may not be adjacent to each other. Allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated for DL than for UL) . The component carriers may include a primary component carrier and one or more secondary component carriers. A primary component carrier may be referred to as a primary cell (PCell) and a secondary component carrier may be referred to as a secondary cell (SCell) .

Certain UEs 104 may communicate with each other using device-to-device (D2D) communication link 158. The D2D communication link 158 may use the DL/UL WWAN spectrum. The D2D communication link 158 may use one or more sidelink channels, such as a physical sidelink broadcast channel (PSBCH) , a physical sidelink discovery channel (PSDCH) , a physical sidelink shared channel (PSSCH) , and a physical sidelink control channel (PSCCH) . D2D communication may be through a variety of wireless D2D communications systems, such as for example, WiMedia, Bluetooth, ZigBee, Wi-Fi based on the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, LTE, or NR.

The wireless communications system may further include a Wi-Fi access point (AP) 150 in communication with Wi-Fi stations (STAs) 152 via communication links 154, e.g., in a 5 gigahertz (GHz) unlicensed frequency spectrum or the like. When communicating in an unlicensed frequency spectrum, the STAs 152 /AP 150 may perform a clear channel assessment (CCA) prior to communicating in order to determine whether the channel is available.

The small cell 102' may operate in a licensed and/or an unlicensed frequency spectrum. When operating in an unlicensed frequency spectrum, the small cell 102' may employ NR and use the same unlicensed frequency spectrum (e.g., 5 GHz, or the like) as used by the Wi-Fi AP 150. The small cell 102', employing NR in an unlicensed frequency spectrum, may boost coverage to and/or increase capacity of the access network.

The electromagnetic spectrum is often subdivided, based on frequency/wavelength, into various classes, bands, channels, etc. In 5G NR, two initial operating bands have been identified as frequency range designations FR1 (410 MHz –7.125 GHz) and FR2 (24.25 GHz –52.6 GHz) . The frequencies between FR1 and FR2 are often referred to as mid-band frequencies. Although a portion of FR1 is greater than 6 GHz, FR1 is often referred to (interchangeably) as a “sub-6 GHz” band in various documents and articles. A similar nomenclature issue sometimes occurs with regard to FR2, which is often referred to (interchangeably) as a “millimeter wave” band in documents and articles, despite being different from the extremely high frequency (EHF) band (30 GHz –300 GHz) which is identified by the International Telecommunications Union (ITU) as a “millimeter wave” band.

With the above aspects in mind, unless specifically stated otherwise, it should be understood that the term “sub-6 GHz” or the like if used herein may broadly represent frequencies that may be less than 6 GHz, may be within FR1, or may include mid-band frequencies. Further, unless specifically stated otherwise, it should be understood that the term “millimeter wave” or the like if used herein may broadly represent frequencies that may include mid-band frequencies, may be within FR2, or may be within the EHF band.

A base station 102, whether a small cell 102' or a large cell (e.g., macro base station) , may include and/or be referred to as an eNB, gNodeB (gNB) , or another type of base station. Some base stations, such as gNB 180 may operate in a traditional sub 6 GHz spectrum, in millimeter wave frequencies, and/or near millimeter wave frequencies in communication with the UE 104. When the gNB 180 operates in millimeter wave or near millimeter wave frequencies, the gNB 180 may be referred to as a millimeter wave base station. The millimeter wave base station 180 may utilize beamforming 182 with the UE 104 to compensate for the path loss and short range. The base station 180 and the UE 104 may each include a plurality of antennas, such as antenna elements, antenna panels, and/or antenna arrays to facilitate the beamforming.

The base station 180 may transmit a beamformed signal to the UE 104 in one or more transmit directions 182'. The UE 104 may receive the beamformed signal from the base station 180 in one or more receive directions 182” . The UE 104 may also transmit a beamformed signal to the base station 180 in one or more transmit directions. The base station 180 may receive the beamformed signal from the UE 104 in one or more receive directions. The base station 180 /UE 104 may perform beam training to determine the best receive and transmit directions for each of the base station 180 /UE 104. The transmit and receive directions for the base station 180 may or may not be the same. The transmit and receive directions for the UE 104 may or may not be the same.

The EPC 160 may include a Mobility Management Entity (MME) 162, other MMEs 164, a Serving Gateway 166, an MBMS Gateway 168, a Broadcast Multicast Service Center (BM-SC) 170, and a Packet Data Network (PDN) Gateway 172. The MME 162 may be in communication with a Home Subscriber Server (HSS) 174. The MME 162 is the control node that processes the signaling between the UEs 104 and the EPC 160. Generally, the MME 162 provides bearer and connection management. All user Internet protocol (IP) packets are transferred through the Serving Gateway 166, which itself is connected to the PDN Gateway 172. The PDN Gateway 172 provides UE IP address allocation as well as other functions. The PDN Gateway 172 and the BM-SC 170 are connected to the IP Services 176. The IP Services 176 may include the Internet, an intranet, an IP Multimedia Subsystem (IMS) , a PS Streaming Service, and/or other IP services. The BM-SC 170 may provide functions for MBMS user service provisioning and delivery. The BM-SC 170 may serve as an entry point for content provider MBMS transmission, may be used to authorize and initiate MBMS Bearer Services within a public land mobile network (PLMN) , and may be used to schedule MBMS transmissions. The MBMS Gateway 168 may be used to distribute MBMS traffic to the base stations 102 belonging to a Multicast Broadcast Single Frequency Network (MBSFN) area broadcasting a particular service, and may be responsible for session management (start/stop) and for collecting eMBMS related charging information.

The core network 190 may include a Access and Mobility Management Function (AMF) 192, other AMFs 193, a Session Management Function (SMF) 194, and a User Plane Function (UPF) 195. The AMF 192 may be in communication with a Unified Data Management (UDM) 196. The AMF 192 is the control node that processes the signaling between the UEs 104 and the core network 190. Generally, the AMF 192 provides Quality of Service (QoS) flow and session management. All user IP packets are transferred through the UPF 195. The UPF 195 provides UE IP address allocation as well as other functions. The UPF 195 is connected to the IP Services 197. The IP Services 197 may include the Internet, an intranet, an IMS, a Packet Switch (PS) Streaming Service, and/or other IP services.

The base station may include and/or be referred to as a gNB, Node B, eNB, an access point, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a basic service set (BSS) , an extended service set (ESS) , a transmit reception point (TRP) , or some other suitable terminology. The base station 102 provides an access point to the EPC 160 or core network 190 for a UE 104. Examples of UEs 104 include a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a personal digital assistant (PDA) , a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., MP3 player) , a camera, a game console, a tablet, a smart device, a wearable device, a vehicle, an electric meter, a gas pump, a large or small kitchen appliance, a healthcare device, an implant, a sensor/actuator, a display, or any other similar functioning device. Some of the UEs 104 may be referred to as IoT devices (e.g., parking meter, gas pump, toaster, vehicles, heart monitor, etc. ) . The UE 104 may also be referred to as a station, a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. A wireless node may comprise a UE, a base station, or a network entity of the base station.

Wireless devices in the access network 100 may support polar coding techniques for wireless communications. A transmitting device (e.g., a UE 104, a base station 102/180, and/or another network entity) may perform polar coding to encode information bits (e.g., data bits, control bits, etc. ) . The polar coding may include using a number of component channels (W) that are based on a polar code length (N) . A transmitting device may interleave the encoded bits using multiple interleavers and map the interleaved encoded bits to one or more bit levels. The interleaving of encoded bits may be based on a number of bit-levels.

Referring again to FIG. 1, the UE 104 may include an interleaver module 198. As described in more detail elsewhere herein, the interleaver module 198 may be configured to encode a plurality of bits to yield encoded bits; interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; map: (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level; and output, via the first bit level and the second bit level of one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission. Additionally, or alternatively, the interleaver module 198 may perform one or more other operations described herein.

The base station 102/180 may include an interleaver module 199. As described in more detail elsewhere herein, the interleaver module 199 may be configured to obtain, via one or more symbols, a first subset of one or more encoded bits and a second subset of one or more encoded bits, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset, wherein the first subset of one or more encoded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more encoded bits is interleaved via a second interleaving scheme; deinterleave the first subset of one or more encoded bits via the first interleaving scheme and the second subset of one or more encoded bits via the second interleaving scheme; and decode the deinterleaved first subset of one or more encoded bits and the deinterleaved second subset of one or more encoded bits. Additionally, or alternatively, the interleaver module 199 may perform one or more other operations described herein.

FIG. 2A is a diagram 200 illustrating an example of a first subframe within a 5G NR frame structure. FIG. 2B is a diagram 230 illustrating an example of DL channels within a 5G NR subframe. FIG. 2C is a diagram 250 illustrating an example of a second subframe within a 5G NR frame structure. FIG. 2D is a diagram 280 illustrating an example of UL channels within a 5G NR subframe. The 5G NR frame structure may be frequency division duplexed (FDD) in which for a particular set of subcarriers (carrier system bandwidth) , subframes within the set of subcarriers are dedicated for either DL or UL, or may be time division duplexed (TDD) in which for a particular set of subcarriers (carrier system bandwidth) , subframes within the set of subcarriers are dedicated for both DL and UL. In the examples provided by FIGs. 2A, 2C, the 5G NR frame structure is assumed to be TDD, with subframe 4 being configured with slot format 28 (with mostly DL) , where D is DL, U is UL, and F is flexible for use between DL/UL, and subframe 3 being configured with slot format 34 (with mostly UL) . While subframes 3, 4 are shown with slot formats 34, 28, respectively, any particular subframe may be configured with any of the various available slot formats 0-61. Slot formats 0, 1 are all DL, UL, respectively. Other slot formats 2-61 include a mix of DL, UL, and flexible symbols. UEs are configured with the slot format (dynamically through DL control information (DCI) , or semi-statically/statically through radio resource control (RRC) signaling) through a received slot format indicator (SFI) . Note that the description infra applies also to a 5G NR frame structure that is TDD.

Other wireless communication technologies may have a different frame structure and/or different channels. A frame, e.g., of 10 milliseconds (ms) , may be divided into 10 equally sized subframes (1 ms) . Each subframe may include one or more time slots. Subframes may also include mini-slots, which may include 7, 4, or 2 symbols. Each slot may include 7 or 14 symbols, depending on the slot configuration. For slot configuration 0, each slot may include 14 symbols, and for slot configuration 1, each slot may include 7 symbols. The symbols on DL may be cyclic prefix (CP) orthogonal frequency-division multiplexing (OFDM) (CP-OFDM) symbols. The symbols on UL may be CP-OFDM symbols (for high throughput scenarios) or discrete Fourier transform (DFT) spread OFDM (DFT-s-OFDM) symbols (also referred to as single carrier frequency-division multiple access (SC-FDMA) symbols) (for power limited scenarios; limited to a single stream transmission) . The number of slots within a subframe is based on the slot configuration and the numerology. For slot configuration 0, different numerologies μ 0 to 4 allow for 1, 2, 4, 8, and 16 slots, respectively, per subframe. For slot configuration 1, different numerologies 0 to 2 allow for 2, 4, and 8 slots, respectively, per subframe. Accordingly, for slot configuration 0 and numerology μ, there are 14 symbols/slot and 2^μslots/subframe. The subcarrier spacing and symbol length/duration are a function of the numerology. The subcarrier spacing may be equal to 2^μ*15 kilohertz (kHz) , whereμis the numerology 0 to 4. As such, the numerology μ=0 has a subcarrier spacing of 15 kHz and the numerology μ=4 has a subcarrier spacing of 240 kHz. The symbol length/duration is inversely related to the subcarrier spacing. FIGs. 2A-2D provide an example of slot configuration 0 with 14 symbols per slot and numerology μ=2 with 4 slots per subframe. The slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 μs. Within a set of frames, there may be one or more different bandwidth parts (BWPs) (see FIG. 2B) that are frequency division multiplexed. Each BWP may have a particular numerology.

A resource grid may be used to represent the frame structure. Each time slot includes a resource block (RB) (also referred to as physical RBs (PRBs) ) that extends 12 consecutive subcarriers. The resource grid is divided into multiple resource elements (REs) . The number of bits carried by each RE depends on the modulation scheme.

As illustrated in FIG. 2A, some of the REs carry reference (pilot) signals (RS) for the UE.The RS may include demodulation RS (DM-RS) (indicated as R_x for one particular configuration, where 100x is the port number, but other DM-RS configurations are possible) and channel state information reference signals (CSI-RS) for channel estimation at the UE. The RS may also include beam measurement RS (BRS) , beam refinement RS (BRRS) , and phase tracking RS (PT-RS) .

FIG. 2B illustrates an example of various DL channels within a subframe of a frame. The physical downlink control channel (PDCCH) carries DCI within one or more control channel elements (CCEs) , each CCE including nine RE groups (REGs) , each REG including four consecutive REs in an OFDM symbol. A PDCCH within one BWP may be referred to as a control resource set (CORESET) . Additional BWPs may be located at greater and/or lower frequencies across the channel bandwidth. A primary synchronization signal (PSS) may be within symbol 2 of particular subframes of a frame. The PSS is used by a UE 104 to determine subframe/symbol timing and a physical layer identity. A secondary synchronization signal (SSS) may be within symbol 4 of particular subframes of a frame. The SSS is used by a UE to determine a physical layer cell identity group number and radio frame timing. Based on the physical layer identity and the physical layer cell identity group number, the UE can determine a physical cell identifier (PCI) . Based on the PCI, the UE can determine the locations of the aforementioned DM-RS. The physical broadcast channel (PBCH) , which carries a master information block (MIB) , may be logically grouped with the PSS and SSS to form a synchronization signal (SS) /PBCH block (also referred to as SS block (SSB) ) . The MIB provides a number of RBs in the system bandwidth and a system frame number (SFN) . The physical downlink shared channel (PDSCH) carries user data, broadcast system information not transmitted through the PBCH such as system information blocks (SIBs) , and paging messages.

As illustrated in FIG. 2C, some of the REs carry DM-RS (indicated as R for one particular configuration, but other DM-RS configurations are possible) for channel estimation at the base station. The UE may transmit DM-RS for the physical uplink control channel (PUCCH) and DM-RS for the physical uplink shared channel (PUSCH) . The PUSCH DM-RS may be transmitted in the first one or two symbols of the PUSCH. The PUCCH DM-RS may be transmitted in different configurations depending on whether short or long PUCCHs are transmitted and depending on the particular PUCCH format used. The UE may transmit sounding reference signals (SRS) . The SRS may be transmitted in the last symbol of a subframe. The SRS may have a comb structure, and a UE may transmit SRS on one of the combs. The SRS may be used by a base station for channel quality estimation to enable frequency-dependent scheduling on the UL.

FIG. 2D illustrates an example of various UL channels within a subframe of a frame. The PUCCH may be located as indicated in one configuration. The PUCCH carries uplink control information (UCI) , such as scheduling requests, a channel quality indicator (CQI) , a precoding matrix indicator (PMI) , a rank indicator (RI) , and hybrid automatic repeat request (HARQ) acknowledgement (ACK) /non-acknowledgement (NACK) feedback. The PUSCH carries data, and may additionally be used to carry a buffer status report (BSR) , a power headroom report (PHR) , and/or UCI.

FIG. 3 is a block diagram of a base station 102/180 in communication with a UE 104 in an access network. In the DL, IP packets from the EPC 160 may be provided to a controller/processor 375. The controller/processor 375 implements layer 3 and layer 2 functionality. Layer 3 includes a radio resource control (RRC) layer, and layer 2 includes a service data adaptation protocol (SDAP) layer, a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, and a medium access control (MAC) layer. The controller/processor 375 provides RRC layer functionality associated with broadcasting of system information (e.g., MIB, SIBs) , RRC connection control (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release) , inter radio access technology (RAT) mobility, and measurement configuration for UE measurement reporting; PDCP layer functionality associated with header compression /decompression, security (ciphering, deciphering, integrity protection, integrity verification) , and handover support functions; RLC layer functionality associated with the transfer of upper layer packet data units (PDUs) , error correction through ARQ, concatenation, segmentation, and reassembly of RLC service data units (SDUs) , re-segmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto transport blocks (TBs) , demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction through HARQ, priority handling, and logical channel prioritization.

The transmit (TX) processor 316 and the receive (RX) processor 370 implement layer 1 functionality associated with various signal processing functions. Layer 1, which includes a physical (PHY) layer, may include error detection on the transport channels, forward error correction (FEC) coding/decoding of the transport channels, interleaving, rate matching, mapping onto physical channels, modulation/demodulation of physical channels, and MIMO antenna processing. The TX processor 316 handles mapping to signal constellations based on various modulation schemes (e.g., binary phase-shift keying (BPSK) , quadrature phase-shift keying (QPSK) , M-phase-shift keying (M-PSK) , M-quadrature amplitude modulation (M-QAM) ) . The coded and modulated symbols may then be split into parallel streams. Each stream may then be mapped to an OFDM subcarrier, multiplexed with a reference signal (e.g., pilot) in the time and/or frequency domain, and then combined together using an Inverse Fast Fourier Transform (IFFT) to produce a physical channel carrying a time domain OFDM symbol stream. The OFDM stream is spatially precoded to produce multiple spatial streams. Channel estimates from a channel estimator 374 may be used to determine the coding and modulation scheme, as well as for spatial processing. The channel estimate may be derived from a reference signal and/or channel condition feedback transmitted by the UE 104. Each spatial stream may then be provided to a different antenna 320 via a separate transmitter 318TX. Each transmitter 318TX may modulate an RF carrier with a respective spatial stream for transmission.

At the UE 104, each receiver 354RX receives a signal through its respective antenna 352. Each receiver 354RX recovers information modulated onto an RF carrier and provides the information to the receive (RX) processor 356. The TX processor 368 and the RX processor 356 implement layer 1 functionality associated with various signal processing functions. The RX processor 356 may perform spatial processing on the information to recover any spatial streams destined for the UE 104. If multiple spatial streams are destined for the UE 104, they may be combined by the RX processor 356 into a single OFDM symbol stream. The RX processor 356 then converts the OFDM symbol stream from the time-domain to the frequency domain using a Fast Fourier Transform (FFT) . The frequency domain signal comprises a separate OFDM symbol stream for each subcarrier of the OFDM signal. The symbols on each subcarrier, and the reference signal, are recovered and demodulated by determining the most likely signal constellation points transmitted by the base station 102/180. These soft decisions may be based on channel estimates computed by the channel estimator 358. The soft decisions are then decoded and deinterleaved to recover the data and control signals that were originally transmitted by the base station 102/180 on the physical channel. The data and control signals are then provided to the controller/processor 359, which implements layer 3 and layer 2 functionality.

The controller/processor 359 can be associated with a memory 360 that stores program codes and data. The memory 360 may be referred to as a computer-readable medium. In the UL, the controller/processor 359 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, and control signal processing to recover IP packets from the EPC 160. The controller/processor 359 is also responsible for error detection using an ACK and/or NACK protocol to support HARQ operations.

Similar to the functionality described in connection with the DL transmission by the base station 102/180, the controller/processor 359 provides RRC layer functionality associated with system information (e.g., MIB, SIBs) acquisition, RRC connections, and measurement reporting; PDCP layer functionality associated with header compression /decompression, and security (ciphering, deciphering, integrity protection, integrity verification) ; RLC layer functionality associated with the transfer of upper layer PDUs, error correction through ARQ, concatenation, segmentation, and reassembly of RLC SDUs, re-segmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto TBs, demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction through HARQ, priority handling, and logical channel prioritization.

Channel estimates derived by a channel estimator 358 from a reference signal or feedback transmitted by the base station 102/180 may be used by the TX processor 368 to select the appropriate coding and modulation schemes, and to facilitate spatial processing. The spatial streams generated by the TX processor 368 may be provided to different antenna 352 via separate transmitters 354TX. Each transmitter 354TX may modulate an RF carrier with a respective spatial stream for transmission.

The UL transmission is processed at the base station 102/180 in a manner similar to that described in connection with the receiver function at the UE 104. Each receiver 318RX receives a signal through its respective antenna 320. Each receiver 318RX recovers information modulated onto an RF carrier and provides the information to a RX processor 370.

The controller/processor 375 can be associated with a memory 376 that stores program codes and data. The memory 376 may be referred to as a computer-readable medium. In the UL, the controller/processor 375 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover IP packets from the UE 104. IP packets from the controller/processor 375 may be provided to the EPC 160. The controller/processor 375 is also responsible for error detection using an ACK and/or NACK protocol to support HARQ operations.

At least one of the TX processor 368, the RX processor 356, and the controller/processor 359 may be configured to perform aspects in connection with the interleaver module 198 of FIG. 1.

At least one of the TX processor 316, the RX processor 370, and the controller/processor 375 may be configured to perform aspects in connection with the interleaver module 199 of FIG. 1.

FIG. 4 is a block diagram illustrating an example disaggregated base station 400 architecture. The disaggregated base station 400 architecture may include one or more CUs 410 that can communicate directly with a core network 420 via a backhaul link, or indirectly with the core network 420 through one or more disaggregated base station units (such as a near real-time (RT) RIC 425 via an E2 link, or a non-RT RIC 415 associated with a service management and orchestration (SMO) Framework 405, or both) . A CU 410 may communicate with one or more DUs 430 via respective midhaul links, such as an F1 interface. The DUs 430 may communicate with one or more RUs 440 via respective fronthaul links. The RUs 440 may communicate with respective UEs 104 via one or more radio frequency (RF) access links. In some implementations, the UE 104 may be simultaneously served by multiple RUs 440. As used herein, a network entity may correspond to a base station or to a disaggregated aspect (e.g., CU/DU/RU, etc. ) of the base station.

Each of the units, i.e., the CUs 410, the DUs 430, the RUs 440, as well as the near-RT RICs 425, the non-RT RICs 415 and the SMO framework 405, may include one or more interfaces or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively, signals) via a wired or wireless transmission medium. Each of the units, or an associated processor or controller providing instructions to the communication interfaces of the units, can be configured to communicate with one or more of the other units via the transmission medium. For example, the units can include a wired interface configured to receive or transmit signals over a wired transmission medium to one or more of the other units. Additionally, the units can include a wireless interface, which may include a receiver, a transmitter or transceiver (such as a radio frequency (RF) transceiver) , configured to receive or transmit signals, or both, over a wireless transmission medium to one or more of the other units.

In some aspects, the CU 410 may host higher layer control functions. Such control functions can include radio resource control (RRC) , packet data convergence protocol (PDCP) , service data adaptation protocol (SDAP) , or the like. Each control function can be implemented with an interface configured to communicate signals with other control functions hosted by the CU 410. The CU 410 may be configured to handle user plane functionality (i.e., central unit –user plane (CU-UP) ) , control plane functionality (i.e., central unit –control plane (CU-CP) ) , or a combination thereof. In some implementations, the CU 410 can be logically split into one or more CU-UP units and one or more CU-CP units. The CU-UP unit can communicate bidirectionally with the CU-CP unit via an interface, such as the E1 interface when implemented in an O-RAN configuration. The CU 410 can be implemented to communicate with the DU 430, as necessary, for network control and signaling.

The DU 430 may correspond to a logical unit that includes one or more base station functions to control the operation of one or more RUs 440. In some aspects, the DU 430 may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, or the like) depending, at least in part, on a functional split, such as those defined by the 3^rd Generation Partnership Project (3GPP) . In some aspects, the DU 430 may further host one or more low PHY layers. Each layer (or module) can be implemented with an interface configured to communicate signals with other layers (and modules) hosted by the DU 430, or with the control functions hosted by the CU 410.

Lower-layer functionality can be implemented by one or more RUs 440. In some deployments, an RU 440, controlled by a DU 430, may correspond to a logical node that hosts RF processing functions, or low-PHY layer functions (such as performing fast Fourier transform (FFT) , inverse FFT (iFFT) , digital beamforming, physical random access channel (PRACH) extraction and filtering, or the like) , or both, based at least in part on the functional split, such as a lower layer functional split. In such an architecture, the RU (s) 440 can be implemented to handle over the air (OTA) communication with one or more UEs 104. In some implementations, real-time and non-real-time aspects of control and user plane communication with the RU (s) 440 can be controlled by the corresponding DU 430. In some scenarios, this configuration can enable the DU (s) 430 and the CU 410 to be implemented in a cloud-based RAN architecture, such as a virtual RAN (vRAN) architecture.

The SMO Framework 405 may be configured to support RAN deployment and provisioning of non-virtualized and virtualized network elements. For non-virtualized network elements, the SMO framework 405 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements, which may be managed via an operations and maintenance interface (such as an O1 interface) . For virtualized network elements, the SMO framework 405 may be configured to interact with a cloud computing platform (such as an open cloud (O-cloud) 490) to perform network element life cycle management (such as to instantiate virtualized network elements) via a cloud computing platform interface (such as an O2 interface) . Such virtualized network elements can include, but are not limited to, CUs 410, DUs 430, RUs 440 and near-RT RICs 425. In some implementations, the SMO framework 405 can communicate with a hardware aspect of a 4G RAN, such as an open eNB (O-eNB) 411, via an O1 interface. Additionally, in some implementations, the SMO Framework 405 can communicate directly with one or more RUs 440 via an O1 interface. The SMO framework 405 also may include the non-RT RIC 415 configured to support functionality of the SMO Framework 405.

The non-RT RIC 415 may be configured to include a logical function that enables non-real-time control and optimization of RAN elements and resources, artificial intelligence/machine learning (AI/ML) workflows including model training and updates, or policy-based guidance of applications/features in the near-RT RIC 425. The non-RT RIC 415 may be coupled to or communicate with (such as via an A1 interface) the near-RT RIC 425. The near-RT RIC 425 may be configured to include a logical function that enables near-real-time control and optimization of RAN elements and resources via data collection and actions over an interface (such as via an E2 interface) connecting one or more CUs 410, one or more DUs 430, or both, as well as an O-eNB, with the near-RT RIC 425.

In some implementations, to generate AI/ML models to be deployed in the near-RT RIC 425, the non-RT RIC 415 may receive parameters or external enrichment information from external servers. Such information may be utilized by the near-RT RIC 425 and may be received at the SMO Framework 405 or the non-RT RIC 415 from non-network data sources or from network functions. In some examples, the non-RT RIC 415 or the near-RT RIC 425 may be configured to tune RAN behavior or performance. For example, the non-RT RIC 415 may monitor long-term trends and patterns for performance and employ AI/ML models to perform corrective actions through the SMO Framework 405 (such as reconfiguration via O1) or via creation of RAN management policies (such as A1 policies) .

Polar Coding Background

FIG. 5 is a block diagram illustrating an example of a device 500 for use in wireless communications that supports polar codes and modulation mapping. In some cases, device 500 may represent aspects of techniques performed by a transmitting device, such as a UE 104 or base station 102/180 as described with reference to FIGs. 1 and 3. In some cases, device 500 may be a transmitter, a transceiver, or a sub-component of a transmitter or transceiver. Device 500 may include a polar coder 505, an interleaver 510, a modulation mapper 515, and an analog front end (AFE) 520. Although device 500 is shown having one polar coder 505, it is to be understood that device 500 may include more than one polar coder 505 (e.g., a set of polar coders 505) .

As background, the fundamentals of polar coding may begin with a binary-input memoryless channel W: X→Y. The capacity of the channel W may be given as C=I (X; Y) , where I represents mutual information between X and Y. In the example of binary-input 0≤C≤1, C being the capacity of channel W identified above, the following transformation may start with N copies of channel W. Using a one-to-one mapping from U to X, where G_N×N: {0, 1} ^N→ {0, 1} ^N, may result in an effective channel W_vec being created, where X^N=U^N·G_N×N, and U^N represents a vector of bits to be encoded.

Polar coding may be given as C (W_vec) =I (U^N; Y^N) =Σ_i=1 ^NI (U_i; Y^N|U^i-1) =Σ_i=1 ^NC (W_i) =N·C (W) , where channel W_i: U_i→ (Y^N, U^i-1) . For certain values of the matrix, G_N×N, C (W₃) becomes polarized. That is, the linear one-to-one transformation, G_N×N, converts N equal capacity channel W's into N channels, W_i, with unequal capacity. As N tends to infinity, C (W_i) degenerates to a bi-modal distribution around 0, 1 for binary input (i.e., polarized) .

For example, consider the case where N=2, giving:

In the example where W is a binary erasure channel (BEC) with erasure probability “ε. ” It may be deduced that U₁=X₁⊕X₂=Y₁⊕Y₂ and U₂=X₂=X₁⊕U₁. For channel W₁:U₁→Y^N, the erasure probability may be ε^-=1- (1-ε) ²=2ε-ε². For channel W2: U₁→Y^N, the (Y^N, U₁) , the erasure probability may be ε⁺=ε² (denoting W⁺=W₂ and W^-=W₁) . This illustrates that channel W2 may be considered to be a better performing channel than channel W1. This operation may be performed recursively, yielding more polarization across N. It is to be understood that the example BEC erasure probability is being used for illustrative purposes only. The described techniques may also be applicable for other channel types (e.g., additive white Gaussian noise (AWGN) channels, fading channels, etc. ) .

Turning now to the example device 500, polar coder 505 may perform polar coding to encode a plurality of bits, shown as unencoded bits U₁-U₄. The polar coding may have a polar code length N that defines a number of component channels, also referred to as bit channels, used for polar coding. For ease of explanation and as a non-limiting example only, the polar code length N is four for device 500, corresponding to four component channels and a group of four bits that are encoded in parallel. Each component channel may have an associated reliability, ε, which may correspond to an erasure probability for the channel.

In the example device 500, polar coder 505 may perform polar coding on bits U₁-U₄ and output encoded bits X₁-X₄, where polar coder 505 may create polarization of encoded bits, i.e., with higher and lower reliabilities. Each component channel may therefore have a different reliability ε, illustrated as ε⁺ for component channels corresponding to encoded bits X₁ and X₂ and as ε⁺ for component channels corresponding to encoded bits X₃ and X₄. A component channel reliability of ε⁺ (e.g., a high erasure probability) represents a low probability that an encoded bit will be successfully decoded after transmission to a receiver over a physical channel, and a reliability of ε^- (e.g., a low erasure probability) represents a high probability that an encoded bit will be successfully decoded after transmission to a receiver over a physical channel. In some aspects, the component channels are from the interleaver/modulation mapping perspective. That is, the unequal reliability ε⁺ and ε^- may be assumed to come from a modulator, for example. Thus, a modulator may act as a polarizer to some extent.

Interleaver 510 relies on an asymmetry in the polar coding to decide how to connect encoded bits associated with different reliabilities (e.g., ε^-and ε⁺) to X₁-X₄. Put differently, interleaver 510 reorders the bits output by polar coder 505 based on the asymmetry of the matrix G_N×N of the polar code structure. In some cases, the output of interleaver 510 (e.g., Z₁-Z₄) may be different than the input of encoded bits.

The order of the encoded bits output by interleaver 510 affects how those bits are mapped to a modulation symbol by modulation mapper 515. For example, in a 16-quadrature amplitude modulation (16-QAM) scheme, the first two bits input to the modulation mapper 515 may control a first dimension of the modulation symbol (e.g., a selected quadrant in a modulation constellation or a position along a first axis of the constellation) , and the second two bits input to the modulation mapper 515 may control a second dimension of the modulation symbol (e.g., a position within the selected quadrant or a position along a second axis of the constellation) . Interleaver 510 may feed the encoded (e.g., by polar coder 505) and interleaved bits into modulation mapper 515 such that bits of similar polarization affect the same dimension of modulation mapping by modulation mapper 515. For example, the encoded bits with a reliability of ε⁺ (e.g., X₁ and X₂) may control the selection of a quadrant or a position along a first axis of the modulation constellation, and the encoded bits with a reliability of ε^- (e.g., X₃ and X₄) may control the selection of a position within the selected quadrant or a position along a second axis of the modulation constellation.

Modulation mapper 515 may map the interleaved encoded bits to a modulation symbol. The mapping scheme implemented by modulation mapper 515 may be such that a maximum polarization of the reliability of each component channel is preserved during modulation. Because the polarization of the encoded bits is a result of an asymmetry in the matrix used to encode the bits, both the interleaving scheme and the modulation mapping scheme may be selected according to the asymmetry of the polar code construction. Modulation mapper 515 may select or use a mapping scheme based on the modulation scheme being used. In one example, modulation mapper 515 may use a natural binary mapping or a Gray mapping for a 16-QAM scheme. In another example, modulation mapper 515 may use a Gray mapping or a random mapping for a 2^2M-QAM modulation scheme.

In some aspects, such as for quadrature phase shift keying (QPSK) modulation, anti-Gray mapping may be used (e.g., Gray mapping may make modulated bits unpolarized) . For 16-QAM, Gray mapping may polarize the output of log-likelihood ratios (LLRs) . As an example, the described techniques may use natural binary mapping on in-phase (I) and quadrature (Q) dimensions independently to increase polarization. Two dimensional (2-D) modulation mappings (e.g., joint with I, Q) may be associated with more complicated demappers, although 2-D modulation mappings may increase polarization further.

In some aspects, QPSK (anti-Gray mapped) and 16-QAM may work with conventional polar code derived from:

For example, an interleaved first subset of encoded bits (e.g., b₁= [0 1 1 0] ) and an interleaved second subset of encoded bits (e.g., b₂= [1 1 0 0] ) may be mapped to different bit indices of one or more symbols according to a given bit-to-symbol mapping rule (e.g., Gray mapping) . In this example, the first subset and the second subset may be transmitted via four symbols defined as: x (i) =f (b₁ (i) , b₂ (i) ) , where f (…) is the bit-to-symbol mapping function. In the case of 16QAM modulation, quadruplets of bits b (4i) , b (4i+1) , b (4i+2) , b (4i+3) may be mapped to complex-valued modulation symbols d (i) according to:

Here, b (4i) , b (4i+1) correspond to the bits related to the interleaved first subset of encoded bits, andb (4i+2) , b (4i+3) are bits from the interleaved second subset of encoded bits.

The described techniques may be extended to generic modulations such as phase shift keying (PSK) , amplitude shift keying (ASK) , etc. In some aspects, a joint multi-stage decoding receiver (over coding and modulation) may obtain improved performance. One-shot demodulation followed by a polar decoder may be less preferred in some non-Gray mapping cases.

AFE 520 may transmit the interleaved encoded bits as modulated according to the mapping. For example, AFE 520 may transmit the interleaved encoded bits via an antenna, or more than one antennas.

As discussed above, device 500 uses interleaver 510, which may be designed to improve polarization, resulting in improved performance for wireless communications. In some examples, polarization can be maximized by using multiple interleavers based on a number of bit-layers associated with a block of encoded bits.

Examples of Bit-Level Interleaving

In certain aspects, for polar codes at a relatively higher order of modulation, an interleaver may be used to improve wireless communication by reducing bit error rate and improving transmission efficiency over fading channels. For example, interleaving polar encoded bits may distribute transmitted bits in time to achieve a desirable bit error distribution to counter the effects of fading channels. The interleaver can change the permutation of the signal bit stream without changing the information content. Therefore, the interleaver can maximize the dispersion of continuous error bits generated by bursts in the process of transmission. In this way, the error correction and error detection capabilities of the receiver can be improved. To further randomize inter-symbol bit-level log likelihood ratios (LLRs) at a receiver, different interleavers may be used for different bit levels.

FIG. 6 is a block diagram illustrating another example of a device 600 for use in wireless communications that supports polar codes and modulation mapping. In some cases, device 600 may represent aspects of techniques performed by a transmitting device, such as a UE 104 or base station 102/180 as described with reference to FIGs. 1 and 3. In some cases, device 600 may be a transmitter, a transceiver, or a sub-component of a transmitter or transceiver. Device 600 may include a polar coder 605, multiple interleavers (e.g., a first interleaver 610a and an nth interleaver 610n, collectively referred to as interleavers 610) , a modulation mapper 615, and an AFE 620. Although device 600 is shown having one polar coder 605, it is to be understood that device 600 may include more than one polar coder 605 (e.g., a set of polar coders 605) .

The polar coder 605 may perform polar coding to encode a plurality of bits, shown as a block of unencoded bits U. For example, the device 600 may generate data that includes the block of unencoded bits for transmission to another wireless node. The polar coder 605 may perform polar coding on the block of bits U and output encoded bits X.

In certain aspects, the encoded bits X may be grouped into n subsets of encoded bits (e.g., first encoded subset X₁ and nth encoded subset X_n as illustrated in FIG. 6) . The number (n) of subsets may be based on a number of bit-levels associated with a modulation scheme used by the modulation mapper 615. For example, each of the encoded subsets (X₁-X_n) may be mapped to different bit levels of a QAM symbol. Thus, two bit-levels may result in two encoded bit subsets. The modulation mapper 615 may use any suitable modulation scheme, including phase shift keying (PSK) , amplitude shift keying (ASK) , etc. For example, the encoded bits X may be separated into two subsets based on a 4-ASK modulation scheme having two bit-levels such that the two subsets of encoded bits are mapped to two bit-levels of a QAM symbol. Thus, in this example, n is equal to 2. In another example, the number of bit-levels may be based on a log₂ of a modulation order. For example, QAM 256 may be used to carry 8-bit levels, but the two 8-bit levels from I and Q branch is 16 ASK, so there are 4 different bit-levels with different capacity. Thus, in this example, n is equal to four. It should be noted that in some examples each subset of encoded bits may be exclusive relative to all other subsets. For example, as illustrated in FIG. 7, each subset of bits may not share any bits with another subset.

FIG. 7 is a block diagram illustrating an example technique for separating a block 700 of encoded bits (X) . Initially, the device 600 of FIG. 6 may generate a block of unencoded bits (U) and input the unencoded bits into the polar coder 605. For example, U may be a 10-bit block of data, and the polar encoder 605 may transform U into a 16-bit block 700 of encoded bits. Each bit of the block 700 includes an index 1-16 for identifying each block and its location within the block 700. The device 600 may then separate the block 700 of encoded bits into two subsets 702a of bits: a first subset 704 and a second subset 706a. The two subsets 702a of bits maintain the same indices as the block 700 for exemplary purposes. In some examples, the indices of the second subset may be renumbered as illustrated by another subset 702b. Here, the other subset 702b includes the same bits as the second subset 706a, but the indices have been renumbered as shown in a third subset 706b. It should be noted that any suitable indexing system may be used to index the bits of the encoded block 700 and the subsets.

Referring to FIG. 6, each of the n encoded subset of blocks (X₁ -X_n) may be input to a corresponding parallel interleaver 610a-610n. For example, where n is equal to 2, a first subset (X₁) may be input into a first interleaver 610a and a second subset may be input into a second interleaver (e.g., 610n) . Accordingly, the device 600 may separately interleave each bit-level of encoded bits. In some examples, each interleaver 610 may be defined by one or more of an interleaver pattern and/or a shift pattern. For example, interleaver patterns may include a triangular interleaver, a rectangular interleaver, and any other suitable shape of interleaver.

Interleaver shift patterns may include cyclic shifts of one or more subsets of encoded bits input into each interleaver 610. For example, the first encoded subset (X₁) of bits may be input into the first interleaver 610a without a cyclic shift. Here, the first subset of encoded bits may be input to the first interleaver 610a in an unmodified order, while the second subset of encoded bits (X_n) may be input into the second interleaver 610n after a cyclic shift of the bits.

FIG. 8 is a block diagram illustrating an example of a pair of interleavers receiving subsets of encoded bits and outputting interleaved subsets. While this example shows two interleavers (e.g., a first interleaver 806 and a second interleaver 808) using a triangular interleaver shape, any other suitable interleaver shape may be used. Although FIG. 8 illustrates two interleavers, it is understood that device 600 may include more than two interleavers and may more than two subsets of encoded bits.

The polar coder 605 may output a block of twenty encoded and may separate the block into two subsets of encoded bits (e.g., a first subset 802 and a second subset 804) . Initially, each subset may be ordered such that the order of bits is unmodified from the order in which they are output from the polar coder 605. For example, the first subset and the second may be indexed as 1-10. However, prior to being input into respective interleavers, the device 600 may shift one or more of the subsets by one or more spaces. The one or more subsets may be shift by any suitable number (e.g., 0, 1, 2, 3, etc. ) . In the example of FIG. 8, the first subset 802 is not shifted, but the second subset 804 is cyclically shifted by 1.

In some examples, the cyclic shifting may be successive for each additional subset of encoded bits. For example, a third subset of encoded bits (no shown) may be cyclically shifted by 2, a fourth subset of encoded bits (not shown) may be cyclically shifted by 3, etc. In another example, the second interleaver may be based on the cyclic shift version of the first interleaver. That is, the order of bits in the second subset 804 may be rearranged to match the order of bits output (e.g., the first interleaved bits 810) from the first interleaver 806. In such an example, the second subset 804 may be input to the second interleaver 808 with the bits rearranged as [1, 2, 4, 7, 3, 5, 8, 6, 9, 10] . Such an arrangement may be used successively for any additional subsets of encoded bits.

As illustrated, the subsets of encoded bits may be input to their respective interleavers “row in” and output “column out. ” That is, each interleaver may perform interleaving of each subset of bits by filling an interleaver matrix with the input bits row-by-row and then outputting the matrix contents column-by-column. The first interleaver 806 may output a first interleaved subset of bits 810 (e.g., Z₁ of FIG. 6) and the output, and the second interleaver 808 may output a second interleaved subset of bits 812 (e.g., Z_n of FIG. 6) .

Referring back to FIG. 6, the interleavers 610 may output their respective interleaved subset of bits (Z₁ and Z_n) and the modulation mapper 615 may use the interleaver outputs as input. The modulation mapper 615 may map the interleaved encoded bits to one or more bit-levels of a modulation symbol, and the AFE 620 may transmit the interleaved encoded bits as modulated according to the mapping.

FIG. 9 is a flowchart 900 of a method of wireless communication. The method may be performed by a wireless node (e.g., the UE 104; base station 102; the apparatus 1002) . At 902, the UE may optionally output for transmission an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme. For example, 902 may be performed by an outputting component 1040. Here, the wireless node may provide a receiving device with information related to how the wireless node encodes and interleaves data it will transmit to the receiving device. In certain aspects, the cyclic shift pattern is configured to define a cyclic shift of a first indexed order of the second subset of one or more encoded bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more encoded bits. For example, the wireless node may divide a block of data into subsets, and encode and interleave each subset. Each subset may be interleaved using a different pattern and/or a different indexing scheme. For example, if each subset has N bits (indexed 1-N) , then a first subset may be interleaved in the following order: 1, 2, 3, …, N. However, a second subset may be interleaved according to a cyclic shift of 1 of the indexed bits: 2, 3, …, N, 1. In some examples, a third subset may be interleaved after a cyclic shift of 1 relative to the second subset: 3, …, N, 1, 2.

In certain aspects, the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme. For example, the interleaving pattern may be one of a triangular pattern (e.g., illustrated in FIG. 8) or a rectangular pattern.

At 904, the wireless node may encode a plurality of bits to yield encoded bits. For example, 904 may be performed by an encoding component 1042. Here, the wireless node may have a block of bits to transmit to a receiving device. Prior to transmission, the wireless node may encode the bits.

At 906, the wireless node may optionally split the encoded bits into n subsets including the first subset and the second subset, wherein n is a number of bit-levels associated with a modulation scheme used to map the interleaved first subset and the interleaved second subset. For example, 906 may be performed by a splitting component 1044. Here, the wireless node may divide a block of bits into a plurality of subsets, wherein the number of subsets is based on bit-levels associated with a modulation scheme used to map each subset to a corresponding symbol.

At 908, the wireless node may interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset relevant. For example, 908 may be performed by an interleaving component 1046. Here, the wireless node may interleave each of the subsets of encoded bits such that each subset is independently interleaved. In some examples, each subset may be interleaved using a different interleaver scheme and/or cyclic shift.

At 910, the wireless node may map: (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level. For example, 910 may be performed by a mapping component 1048. Here, the wireless node may map each subset to a bit-level of a symbol.

At 912, the wireless node may output, via the first bit level and the second bit level of one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission. For example, 912 may be performed by the outputting component 1040. Here, the wireless node may map each subset to one or more symbols for transmission.

In certain aspects, the first interleaving scheme is configured to interleave the first subset of one or more encoded bits based on a first indexed order of the one or more encoded bits of the first subset, and the second interleaving scheme is configured to interleave the second subset of one or more encoded bits based on a cyclic shift of a second indexed order of the one or more encoded bits of the second subset.

In certain aspects, the cyclic shift is based on a shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.

In certain aspects, the interleaved first subset includes an indexed order of one or more encoded bits, and wherein interleaving the second subset of one or more encoded bits further comprises interleaving the second subset based on the indexed order of the interleaved first subset.

In certain aspects, the cyclic shift pattern is configured to define a cyclic shift of a first indexed order of the second subset of one or more encoded bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more encoded bits.

In certain aspects, the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme.

In certain aspects, the first subset of one or more encoded bits is interleaved in parallel with the second subset of one or more encoded bits.

In certain aspects, the plurality of bits are encoded via polar encoding.

FIG. 10 is a diagram 1000 illustrating an example of a hardware implementation for an apparatus 1002. The apparatus 1002 may be implemented as a UE, a network entity or base station. The apparatus 1002 includes a cellular baseband processor 1004 (also referred to as a modem) coupled to a cellular RF transceiver 1022 and one or more subscriber identity modules (SIM) cards 1020, an application processor 1006 coupled to a secure digital (SD) card 1008 and a screen 1010, a Bluetooth module 1012, a wireless local area network (WLAN) module 1014, a Global Positioning System (GPS) module 1016, and a power supply 1018. The cellular baseband processor 1004 communicates through the cellular RF transceiver 1022 with the UE 104 and/or BS 102/180. The cellular baseband processor 1004 may include a computer-readable medium /memory. The computer-readable medium /memory may be non-transitory. The cellular baseband processor 1004 is responsible for general processing, including the execution of software stored on the computer-readable medium /memory. The software, when executed by the cellular baseband processor 1004, causes the cellular baseband processor 1004 to perform the various functions described supra. The computer-readable medium /memory may also be used for storing data that is manipulated by the cellular baseband processor 1004 when executing software. The cellular baseband processor 1004 further includes a reception component 1030, a communication manager 1032, and a transmission component 1034. The communication manager 1032 includes the one or more illustrated components. The components within the communication manager 1032 may be stored in the computer-readable medium /memory and/or configured as hardware within the cellular baseband processor 1004. The cellular baseband processor 1004 may be a component of the UE 104 and may include the memory 360 and/or at least one of the TX processor 368, the RX processor 356, and the controller/processor 359. In one configuration, the apparatus 1002 may be a modem chip and include just the baseband processor 1004, and in another configuration, the apparatus 1002 may be the entire wireless node and include the aforediscussed additional modules of the apparatus 1002. In various examples, the apparatus 1002 can be a chip, SoC, chipset, package or device that may include: one or more modems (such as a Wi-Fi (IEEE 802.11) modem or a cellular modem such as 3GPP 4G LTE or 5G compliant modem) ; one or more processors, processing blocks or processing elements (collectively “the processor” ) ; one or more radios (collectively “the radio” ) ; and one or more memories or memory blocks (collectively “the memory” ) .

The communication manager 1032 includes an outputting component 1040 that is configured to output for transmission an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme; and output, via the first bit level and the second bit level of one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission; e.g., as described in connection with 902 and 912 of FIG. 9.

The communication manager 1032 further includes an encoding component 1042 configured to encode a plurality of bits to yield encoded bits, e.g., as described in connection with 904.

The communication manager 1032 further includes a splitting component 1044 configured to split the encoded bits into n subsets including the first subset and the second subset, wherein n is a number of bit-levels associated with a modulation scheme used to map the interleaved first subset and the interleaved second subset, e.g., as described in connection with 906.

The communication manager 1032 further includes an interleaving component 1046 configured to interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset, e.g., as described in connection with 908.

The communication manager 1032 further includes a mapping component 1048 configured to map: (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level, e.g., as described in connection with 910.

The apparatus may include additional components that perform each of the blocks of the algorithm in the aforementioned flowchart of FIG. 9. As such, each block in FIG. 9 may be performed by a component and the apparatus may include one or more of those components. The components may be one or more hardware components specifically configured to carry out the stated processes/algorithm, implemented by a processor configured to perform the stated processes/algorithm, stored within a computer-readable medium for implementation by a processor, or some combination thereof.

In one configuration, the apparatus 1002, and in particular the cellular baseband processor 1004, includes means for outputting for transmission an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme; means for encoding a plurality of bits to yield encoded bits; means for splitting the encoded bits into n subsets including the first subset and the second subset, whereinn is a number of bit-levels associated with a modulation scheme used to map the interleaved first subset and the interleaved second subset; means for interleaving: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; means for mapping: (i) the interleaved first subset to a first bit level, and (ii) the interleaved second subset to a second bit level; and means for outputting, via the first bit level and the second bit level of one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

The aforementioned means may be one or more of the aforementioned components of the apparatus 1002 configured to perform the functions recited by the aforementioned means. As described supra, the apparatus 1002 may include the TX Processor 368, the RX Processor 356, and the controller/processor 359. As such, in one configuration, the aforementioned means may be the TX Processor 368, the RX Processor 356, and the controller/processor 359 configured to perform the functions recited by the aforementioned means.

Means for receiving or means for obtaining may include a receiver (such as the RX processor 370) and/or an antenna (s) 320 of the base station 102/180 or the RX processor 356 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3. Means for transmitting or means for outputting may include a transmitter (such as the TX processor 316) or an antenna (s) 320 of the base station 102/180 or the TX processor 368 or antenna (s) 352 of the UE 104 illustrated in FIG. 3. Means for encoding, means for splitting, means for interleaving, and means for mapping may include a processing system, which may include one or more processors, such as the controller/processor 359/375, the memory 360/376, and/or any other suitable hardware components of the UE 104 and base station 102/180 illustrated in FIG. 3.

In some cases, rather than actually transmitting a frame a device may have an interface to output a frame for transmission (a means for outputting) . For example, a processor may output a frame, via a bus interface, to a radio frequency (RF) front end for transmission. Similarly, rather than actually receiving a frame, a device may have an interface to obtain a frame received from another device (a means for obtaining) . For example, a processor may obtain (or receive) a frame, via a bus interface, from an RF front end for reception.

FIG. 11 is a flowchart 1100 of a method of wireless communication. The method may be performed by a wireless node (e.g., the UE 104; base station 102/180; the apparatus 1202) . At 1102, the wireless node may optionally obtain an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme. For example, 1102 may be performed by an obtaining component 1240. Here, the wireless node may receive, from a transmitting device, an indication of an interleaver (e.g., interleaver pattern, cyclic shifts, etc. ) that the transmitting device will use to transmit data to the wireless node.

At 1104, the wireless node may obtain, via one or more symbols, a first subset of one or more encoded bits and a second subset of one or more encoded bits, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset, wherein the first subset of one or more encoded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more encoded bits is interleaved via a second interleaving scheme. For example, 1104 may be performed by the obtaining component 1240. Here, the transmitting device may divide a block of data into multiple subsets and interleave each subset separately using a unique interleaver pattern, cyclic shift of bits in a corresponding subset, etc. The transmitting device may transmit each subset and the wireless node may receive the subsets (e.g., the wireless node determines the first subset and the second subset of encoded bits by demodulating the one or more modulated symbols it receives) .

At 1106, the wireless node may deinterleave the first subset of one or more encoded bits via the first interleaving scheme and the second subset of one or more encoded bits via the second interleaving scheme. For example, 1106 may be performed by a deinterleaving component 1242. Here, the wireless node may individually deinterleave each subset of data received from the transmitting device. In some examples, one or more of the multiple subsets may be interleaved as a function of another subset. For example, a first subset may be interleaved as a function of bit indices of a second subset. Thus, the wireless node may deinterleave each subset based on the particular interleaving of each subset.

Finally, at 1108, the wireless node may decode the deinterleaved first subset of one or more encoded bits and the deinterleaved second subset of one or more encoded bits. For example, 1108 may be performed by a decoding component 1244. Here, the wireless node may decode and process the deinterleaved subsets of data.

In certain aspects, the interleaving pattern is one of a triangular pattern or a rectangular pattern.

In certain aspects, the first subset of one or more encoded bits is deinterleaved in parallel with the second subset of one or more encoded bits.

In certain aspects, each of the first subset of one or more encoded bits and the second subset of one or more encoded bits is decoded via polar decoding.

FIG. 12 is a diagram 1200 illustrating an example of a hardware implementation for an apparatus 1202. The apparatus 1202 may be implemented as a wireless node and includes a baseband unit 1204. The baseband unit 1204 may communicate through a cellular RF transceiver with another wireless node. The baseband unit 1204 may include a computer-readable medium /memory. The baseband unit 1204 is responsible for general processing, including the execution of software stored on the computer-readable medium /memory. The software, when executed by the baseband unit 1204, causes the baseband unit 1204 to perform the various functions described supra. The computer-readable medium /memory may also be used for storing data that is manipulated by the baseband unit 1204 when executing software. The baseband unit 1204 further includes a reception component 1230, a communication manager 1232, and a transmission component 1234. The communication manager 1232 includes the one or more illustrated components. The components within the communication manager 1232 may be stored in the computer-readable medium /memory and/or configured as hardware within the baseband unit 1204. The baseband unit 1204 may be a component of the BS 102/180 and may include the memory 376 and/or at least one of the TX processor 316, the RX processor 370, and the controller/processor 375. In various examples, the apparatus 1202 can be a chip, SoC, chipset, package or device that may include: one or more modems (such as a Wi-Fi (IEEE 802.11) modem or a cellular modem such as 3GPP 4G LTE or 5G compliant modem) ; one or more processors, processing blocks or processing elements (collectively “the processor” ) ; one or more radios (collectively “the radio” ) ; and one or more memories or memory blocks (collectively “the memory” ) .

The communication manager 1232 includes an obtaining component 1240 configured to obtain an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme; and obtain, via one or more symbols, a first subset of one or more encoded bits and a second subset of one or more encoded bits, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset, wherein the first subset of one or more encoded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more encoded bits is interleaved via a second interleaving scheme; e.g., as described in connection with 1102 and 1104 of FIG. 11.

The communication manager 1232 further includes a deinterleaving component 1242 configured to deinterleave the first subset of one or more encoded bits via the first interleaving scheme and the second subset of one or more encoded bits via the second interleaving scheme, e.g., as described in connection with 1106.

The communication manager 1232 further includes a decoding component 1244 configured to decode the deinterleaved first subset of one or more encoded bits and the deinterleaved second subset of one or more encoded bits, e.g., as described in connection with 1108.

The apparatus may include additional components that perform each of the blocks of the algorithm in the aforementioned flowchart of FIG. 11. As such, each block in the aforementioned flowchart may be performed by a component and the apparatus may include one or more of those components. The components may be one or more hardware components specifically configured to carry out the stated processes/algorithm, implemented by a processor configured to perform the stated processes/algorithm, stored within a computer-readable medium for implementation by a processor, or some combination thereof.

In one configuration, the apparatus 1202, and in particular the baseband unit 1204, includes means for obtaining an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme; means for obtain, via one or more symbols, a first subset of one or more encoded bits and a second subset of one or more encoded bits, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset, wherein the first subset of one or more encoded bits is interleaved via a first interleaving scheme, and wherein the second subset of one or more encoded bits is interleaved via a second interleaving scheme; means for deinterleaving the first subset of one or more encoded bits via the first interleaving scheme and the second subset of one or more encoded bits via the second interleaving scheme; and means for decoding the deinterleaved first subset of one or more encoded bits and the deinterleaved second subset of one or more encoded bits.

The aforementioned means may be one or more of the aforementioned components of the apparatus 1202 configured to perform the functions recited by the aforementioned means. As described supra, the apparatus 1202 may include the TX Processor 316, the RX Processor 370, and the controller/processor 375. As such, in one configuration, the aforementioned means may be the TX Processor 316, the RX Processor 370, and the controller/processor 375 configured to perform the functions recited by the aforementioned means.

Means for receiving or means for obtaining may include a receiver (such as the RX processor 370) and/or an antenna (s) 320 of the base station 102/180 or the RX processor 356 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3. Means for decoding and means for deinterleaving may include a processing system, which may include one or more processors, such as the controller/processor 359/375, the memory 360/376, and/or any other suitable hardware components of the UE 104 and base station 102/180 illustrated in FIG. 3.

Additional Considerations

As used herein, a processor, at least one processor, and/or one or more processors, individually or in combination, configured to perform or operable for performing a plurality of actions is meant to include at least two different processors able to perform different, overlapping or non-overlapping subsets of the plurality actions, or a single processor able to perform all of the plurality of actions. In one non-limiting example of multiple processors being able to perform different ones of the plurality of actions in combination, a description of a processor, at least one processor, and/or one or more processors configured or operable to perform actions X, Y, and Z may include at least a first processor configured or operable to perform a first subset of X, Y, and Z (e.g., to perform X) and at least a second processor configured or operable to perform a second subset of X, Y, and Z (e.g., to perform Y and Z) . Alternatively, a first processor, a second processor, and a third processor may be respectively configured or operable to perform a respective one of actions X, Y, and Z. It should be understood that any combination of one or more processors each may be configured or operable to perform any one or any combination of a plurality of actions.

As used herein, a memory, at least one memory, and/or one or more memories, individually or in combination, configured to store or having stored thereon instructions executable by one or more processors for performing a plurality of actions is meant to include at least two different memories able to store different, overlapping or non-overlapping subsets of the instructions for performing different, overlapping or non-overlapping subsets of the plurality actions, or a single memory able to store the instructions for performing all of the plurality of actions. In one non-limiting example of one or more memories, individually or in combination, being able to store different subsets of the instructions for performing different ones of the plurality of actions, a description of a memory, at least one memory, and/or one or more memories configured or operable to store or having stored thereon instructions for performing actions X, Y, and Z may include at least a first memory configured or operable to store or having stored thereon a first subset of instructions for performing a first subset of X, Y, and Z (e.g., instructions to perform X) and at least a second memory configured or operable to store or having stored thereon a second subset of instructions for performing a second subset of X, Y, and Z (e.g., instructions to perform Y and Z) . Alternatively, a first memory, and second memory, and a third memory may be respectively configured to store or have stored thereon a respective one of a first subset of instructions for performing X, a second subset of instruction for performing Y, and a third subset of instructions for performing Z. It should be understood that any combination of one or more memories each may be configured or operable to store or have stored thereon any one or any combination of instructions executable by one or more processors to perform any one or any combination of a plurality of actions. Moreover, one or more processors may each be coupled to at least one of the one or more memories and configured or operable to execute the instructions to perform the plurality of actions. For instance, in the above non-limiting example of the different subset of instructions for performing actions X, Y, and Z, a first processor may be coupled to a first memory storing instructions for performing action X, and at least a second processor may be coupled to at least a second memory storing instructions for performing actions Y and Z, and the first processor and the second processor may, in combination, execute the respective subset of instructions to accomplish performing actions X, Y, and Z. Alternatively, three processors may access one of three different memories each storing one of instructions for performing X, Y, or Z, and the three processor may in combination execute the respective subset of instruction to accomplish performing actions X, Y, and Z. Alternatively, a single processor may execute the instructions stored on a single memory, or distributed across multiple memories, to accomplish performing actions X, Y, and Z.

It is understood that the specific order or hierarchy of blocks in the processes /flowcharts disclosed is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes /flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more. ” Terms such as “if, ” “when, ” and “while” should be interpreted to mean “under the condition that” rather than imply an immediate temporal relationship or reaction. That is, these phrases, e.g., “when, ” do not imply an immediate action in response to or during the occurrence of an action, but simply imply that if a condition is met then an action will occur, but without requiring a specific or immediate time constraint for the action to occur. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration. ” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C, ” “one or more of A, B, or C, ” “at least one of A, B, and C, ” “one or more of A, B, and C, ” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C, ” “one or more of A, B, or C, ” “at least one of A, B, and C, ” “one or more of A, B, and C, ” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module, ” “mechanism, ” “element, ” “device, ” and the like may not be a substitute for the word “means. ” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for. ”

Example Aspects

The following examples are illustrative only and may be combined with aspects of other embodiments or teachings described herein, without limitation.

Clause 1. A method for wireless communication at a wireless node, comprising: encoding a plurality of bits to yield encoded bits; interleaving: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset; mapping the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and outputting, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.

Clause 2. The method of clause 1, further comprising: splitting the encoded bits into n subsets including the first subset and the second subset, wherein n is a number of bit-levels associated with a modulation scheme used to map the interleaved first subset and the interleaved second subset.

Clause 3. The method of any of clauses 1 and 2, wherein the first interleaving scheme is configured to interleave the first subset based on a first indexed order of the one or more encoded bits of the first subset, and wherein the second interleaving scheme is configured to interleave the second subset based on a cyclic shift of a second indexed order of the one or more encoded bits of the second subset.

Clause 4. The method of clause 3, wherein the cyclic shift is based on a shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.

Clause 5. The method of any of clauses 1-4, wherein the interleaved first subset includes an indexed order of one or more encoded bits of the first subset, and wherein interleaving the second subset of one or more encoded bits further comprises interleaving the second subset based on the indexed order of the interleaved first subset.

Clause 6. The method of any of clauses 1-5, further comprising: outputting, for transmission, an indication of an interleaving pattern, wherein the interleaving pattern is applied to interleavers associated with the first interleaving scheme and the second interleaving scheme.

Clause 7. The method of clause 6, further comprising: configuring the second interleaving scheme with a cyclic shift pattern defining a cyclic shift of a first indexed order of the second subset of one or more encoded bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more encoded bits being interleaved via the first interleaving scheme.

Clause 8. The method of any of clauses 6 and 7, wherein the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme.

Clause 9. The method of any of clauses 6-8, wherein the interleaving pattern is one of a triangular pattern or a rectangular pattern.

Clause 10. The method of any of clauses 1-9, wherein the first subset and the second subset are being interleaved in parallel.

Clause 11. The method any of clauses 1-10, wherein the plurality of bits are encoded via polar encoding.

Clause 12. A method for wireless communication at a wireless node, comprising: obtaining, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset; deinterleaving the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and decoding the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.

Clause 13. The method of clause 12, further comprising: obtaining an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.

Clause 14. The method of clause 13, wherein the cyclic shift pattern is configured to define a cyclic shift of a first indexed order of the second subset of one or more interleaved bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more interleaved bits.

Clause 15. The method of any of clauses 13 and 14, wherein the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme.

Clause 16. The method of any of clauses 13-15, wherein the interleaving pattern is one of a triangular pattern or a rectangular pattern.

Clause 17. The method of any of clauses 12-16, wherein the first subset of one or more interleaved bits is deinterleaved in parallel with the second subset of one or interleaved bits.

Clause 18. The method of any of clauses 12-17, wherein each of the first subset of one or more deinterleaved bits and the second subset of one or more deinterleaved bits is decoded via polar decoding.

Clause 19. A wireless node, comprising: a transceiver; one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the wireless node to perform a method in accordance with any one of examples 1-11, wherein the transceiver is configured to: transmit the interleaved first subset and the interleaved second subset for transmission.

Clause 20. A wireless node, comprising: a transceiver; one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the wireless node to perform a method in accordance with any one of examples 12-18, wherein the transceiver is configured to: receive the first subset of one or more interleaved bits and the second subset of one or more interleaved bits.

Clause 21. An apparatus for wireless communications, comprising means for performing a method in accordance with any one of examples 1-11.

Clause 22. An apparatus for wireless communications, comprising means for performing a method in accordance with any one of examples 12-18.

Clause 23. A non-transitory computer-readable medium comprising instructions that, when executed by an apparatus, cause the apparatus to perform a method in accordance with any one of examples 1-11.

Clause 24. A non-transitory computer-readable medium comprising instructions that, when executed by an apparatus, cause the apparatus to perform a method in accordance with any one of examples 12-18.

Clause 25. An apparatus for wireless communications, comprising: one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to perform a method in accordance with any one of examples 1-11.

Clause 26. An apparatus for wireless communications, comprising: one or more memories, individually or in combination, having instructions; and one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to perform a method in accordance with any one of examples 12-18.

Claims

An apparatus for wireless communication, comprising:

one or more memories, individually or in combination, having instructions; and

one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to:

encode a plurality of bits to yield encoded bits;

interleave: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset;

map the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and

output, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.
The apparatus of claim 1, wherein the one or more processors are further configured to cause the apparatus to:

split the encoded bits into n subsets including the first subset and the second subset, wherein n is a number of bit-levels associated with a modulation scheme used to map the interleaved first subset and the interleaved second subset.
The apparatus of claim 1, wherein the first interleaving scheme is configured to interleave the first subset based on a first indexed order of the one or more encoded bits of the first subset, and wherein the second interleaving scheme is configured to interleave the second subset based on a cyclic shift of a second indexed order of the one or more encoded bits of the second subset.
The apparatus of claim 3, wherein the cyclic shift is based on a shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.
The apparatus of claim 1, wherein the interleaved first subset includes an indexed order of one or more encoded bits of the first subset, and wherein interleaving the second subset of one or more encoded bits further comprises interleaving the second subset based on the indexed order of the interleaved first subset.
The apparatus of claim 1, wherein the one or more processors are further configured to cause the apparatus to:

output, for transmission, an indication of an interleaving pattern, wherein the interleaving pattern is applied to interleavers associated with the first interleaving scheme and the second interleaving scheme.
The apparatus of claim 6, wherein the one or more processors are further configured to cause the apparatus to:

configure the second interleaving scheme with a cyclic shift pattern defining a cyclic shift of a first indexed order of the second subset of one or more encoded bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more encoded bits being interleaved via the first interleaving scheme.
The apparatus of claim 6, wherein the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme.
The apparatus of claim 6, wherein the interleaving pattern is one of a triangular pattern or a rectangular pattern.
The apparatus of claim 1, wherein the first subset and the second subset are being interleaved in parallel.
The apparatus of claim 1, wherein the plurality of bits are encoded via polar encoding.
The apparatus of claim 1, further comprising a transceiver configured to:

transmit the interleaved first subset and the interleaved second subset, wherein the apparatus is configured as a wireless node.
An apparatus for wireless communication, comprising:

one or more memories, individually or in combination, having instructions; and

one or more processors, individually or in combination, configured to execute the instructions and cause the apparatus to:

obtain, via one or more symbols, a first subset of one or more interleaved bits and a second subset of one or more interleaved bits, wherein the one or more interleaved bits of the second subset are different from the one or more interleaved bits of the first subset;

deinterleave the first subset of one or more interleaved bits via a first interleaving scheme and the second subset of one or more interleaved bits via a second interleaving scheme; and

decode the deinterleaved first subset of one or more deinterleaved bits and the deinterleaved second subset of one or more deinterleaved bits.
The apparatus of claim 13, wherein the one or more processors are further configured to cause the apparatus to:

obtain an indication of one or more of an interleaving pattern and a cyclic shift pattern applied to a plurality of interleavers associated with the first interleaving scheme and the second interleaving scheme.
The apparatus of claim 14, wherein the cyclic shift pattern is configured to define a cyclic shift of a first indexed order of the second subset of one or more interleaved bits input into the second interleaving scheme relative to a second indexed order of the first subset of one or more interleaved bits.
The apparatus of claim 14, wherein the interleaving pattern is based on a shape of each of the first interleaving scheme and the second interleaving scheme.
The apparatus of claim 14, wherein the interleaving pattern is one of a triangular pattern or a rectangular pattern.
The apparatus of claim 13, wherein the first subset of one or more interleaved bits is deinterleaved in parallel with the second subset of one or interleaved bits.
The apparatus of claim 13, wherein each of the first subset of one or more deinterleaved bits and the second subset of one or more deinterleaved bits is decoded via polar decoding.
A method for wireless communication at a wireless node, comprising:

encoding a plurality of bits to yield encoded bits;

interleaving: (i) a first subset of one or more encoded bits via a first interleaving scheme, and (ii) a second subset of one or more encoded bits via a second interleaving scheme, wherein the one or more encoded bits of the second subset are different from the one or more encoded bits of the first subset;

mapping the interleaved first subset and the interleaved second subset to one or more modulated symbols based on a corresponding bit level of each of the interleaved first subset and the interleaved second subset; and

outputting, via the one or more modulated symbols, the interleaved first subset and the interleaved second subset for transmission.