WO2025027845A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

The objective of the present invention is to provide a technology that can suppress cracking of an insulating substrate even when a product warps after transfer molding. Provided is a semiconductor device comprising: an insulating substrate having an insulating layer, a front surface pattern, and a back surface pattern; a semiconductor element mounted on the front surface pattern; and a mold resin that seals the insulating substrate and the semiconductor element in a state in which the surface of the back surface pattern on the opposite side of the surface thereof that opposes the insulating layer is exposed. The back surface pattern is joined to a heatsink through use of solder, the surface of the back surface pattern that is joined to the heat sink is located at the same height as the surface of the mold resin that opposes the heatsink, the front surface pattern is provided with a first slit for dividing the front surface pattern into a plurality of regions, the back surface pattern is provided with a second slit for dividing the back surface pattern into a plurality of regions. The first slit and the second slit do not overlap or only partially overlap as viewed from the thickness direction of the insulating substrate.

Description

Semiconductor device and method for manufacturing the same

This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

For example, Patent Document 1 discloses a semiconductor device including a plurality of wiring layers (corresponding to a front surface pattern), an insulating substrate (corresponding to an insulating layer) to which the first rear surfaces of the plurality of wiring layers are bonded, a plurality of heat dissipation layers (corresponding to a rear surface pattern) whose second main surface is bonded to the insulating substrate, a semiconductor element bonded to any of the first main surfaces of the plurality of wiring layers, and a sealing resin that covers the insulating substrate, the plurality of wiring layers, and the semiconductor element. By arranging the plurality of wiring layers bonded to the front surface of the insulating substrate and the plurality of heat dissipation layers bonded to the rear surface of the insulating substrate so as to overlap when viewed in the thickness direction of the insulating substrate, the difference in the amount of expansion and contraction between the front surface side and the rear surface side of the insulating substrate due to temperature changes is reduced, thereby suppressing warping that occurs in the insulating substrate.

International Publication No. 2020/149225

However, the technology described in Patent Document 1 does not take into consideration the warping of the product that occurs after transfer molding. In particular, the slits that divide the insulating substrate into multiple wiring layers on the front side and the slits that divide the insulating substrate into multiple heat dissipation layers on the back side are in the same position when viewed from the thickness direction of the insulating substrate, which causes the entire substrate including the multiple wiring layers and multiple heat dissipation layers to bend and crack easily.

The present disclosure therefore aims to provide a technology that can prevent the insulating substrate from cracking even if the product warps after transfer molding.

The semiconductor device according to the present disclosure comprises an insulating substrate having an insulating layer, a surface pattern formed on the surface of the insulating layer, and a back surface pattern formed on the back surface of the insulating layer, a semiconductor element mounted on the surface pattern, and a sealing resin that seals the insulating substrate and the semiconductor element while exposing a surface of the back surface pattern opposite to a surface facing the insulating layer, the back surface pattern is soldered to a heat sink, the surface of the back surface pattern that is joined to the heat sink is located at the same height as the surface of the sealing resin that faces the heat sink, the front surface pattern is provided with a first slit for dividing the front surface pattern into a plurality of regions, and the back surface pattern is provided with a second slit for dividing the back surface pattern into a plurality of regions, and the first slit and the second slit do not overlap or only partially overlap when viewed from the thickness direction of the insulating substrate.

According to the present disclosure, when viewed from the thickness direction of the insulating substrate, the overlapping portion between the first slit on the front side of the insulating substrate and the second slit on the back side is reduced, so that even if the product warps after transfer molding, cracking of the insulating substrate can be suppressed.

　Objectives, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a cross-sectional view of a semiconductor device according to an embodiment; 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. 4A to 4C are cross-sectional views showing a die bonding step in the embodiment. 5A to 5C are cross-sectional views showing a lead bonding process in the embodiment. 4A to 4C are cross-sectional views showing a wire bonding step in the embodiment. 4A to 4C are cross-sectional views showing a molding process in the embodiment. 4A to 4C are cross-sectional views showing a solder mounting process in the embodiment. 1 is a cross-sectional view of a semiconductor device for explaining the occurrence of solder voids in an embodiment; 2 is a bottom view illustrating an example of an insulating substrate included in the semiconductor device according to the embodiment; FIG. 11 is a bottom view showing another example of an insulating substrate included in the semiconductor device according to the embodiment. FIG. 4 is an enlarged cross-sectional view of the periphery of a second slit provided in a back surface pattern of the semiconductor device according to the embodiment; 13 is an enlarged cross-sectional view of the periphery of a second slit provided in a back surface pattern of a semiconductor device according to a modified example of the embodiment; FIG. 1 is a cross-sectional view of a semiconductor device for explaining the occurrence of solder voids in a related art.

<Embodiment>
<Configuration of Semiconductor Device>
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

As shown in FIG. 1, the semiconductor device includes an insulating substrate 1, a plurality of semiconductor elements 2, a plurality of lead frames 3, and a molded resin 5 as a sealing resin.

The insulating substrate 1 includes an insulating layer 1a, a surface pattern 1b, and a back pattern 1c. The insulating layer 1a is made of ceramics. The surface pattern 1b is made of a metal such as copper or aluminum, and is formed on the surface of the insulating layer 1a. The surface pattern 1b is provided with a first slit 6 for dividing the surface pattern 1b into a plurality of regions. The back pattern 1c is made of a metal such as copper or aluminum, and is formed on the back surface of the insulating layer 1a. The back pattern 1c is provided with a second slit 7 for dividing the back pattern 1c into a plurality of regions. The second slit 7 is provided in a lattice shape when viewed from the thickness direction of the insulating substrate 1. The second slit 7 is also provided so as to surround the periphery of the semiconductor element 2 when viewed from the thickness direction of the insulating substrate 1.

The multiple semiconductor elements 2 are mounted on the surface pattern 1b via solder 4. The multiple semiconductor elements 2 are elements that function as, for example, switching elements or rectifying elements. The switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The rectifying elements are diode elements.

The material constituting the multiple semiconductor elements 2 is, for example, silicon (Si). Note that the material constituting the multiple semiconductor elements 2 is not limited to silicon, and may be, for example, a wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C). A wide bandgap semiconductor material is a material that has a bandgap wider than that of Si. The multiple semiconductor elements 2 made of a wide bandgap semiconductor material are capable of operating using a large current and in a high-temperature environment. For this reason, it is preferable that the material constituting the multiple semiconductor elements 2 is a wide bandgap semiconductor material.

The material of the multiple lead frames 3 is, for example, copper. The multiple lead frames 3 are joined to the surface electrodes of the semiconductor element 2 by solder 4, joined to the surface pattern 1b by solder 4, or connected to the wire pads of the semiconductor element 2 via aluminum wires 8.

The molded resin 5 is, for example, an epoxy-based thermosetting resin. The molded resin 5 seals the insulating substrate 1 and the semiconductor element 2 while leaving the surface of the back pattern 1c opposite the surface facing the insulating layer 1a exposed.

Here, the semiconductor device is bonded to a heat sink 10 (see FIG. 7), but the surface of the back pattern 1c that is bonded to the heat sink 10 is located at the same height as the surface of the molded resin 5 that faces the heat sink 10, so no step is created between the back pattern 1c and the molded resin 5.

<Method of Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device will be described with reference to Figures 2 to 7. Figure 2 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment. Figure 3 is a cross-sectional view showing a die bonding process in the embodiment. Figure 4 is a cross-sectional view showing a lead bonding process in the embodiment. Figure 5 is a cross-sectional view showing a wire bonding process in the embodiment. Figure 6 is a cross-sectional view showing a molding process in the embodiment. Figure 7 is a cross-sectional view showing a solder mounting process in the embodiment. Note that Figure 2 is a simplified illustration of only the main steps of the method for manufacturing a semiconductor device.

First, as shown in Figures 2 and 3, in step S1, solder 4 is placed on the surface pattern 1b of the insulating substrate 1, the semiconductor element 2 is mounted thereon, and the solder 4 is melted by reflow or the like to bond the semiconductor element 2 to the insulating substrate 1. Note that in the embodiment, bonding with solder 4 is given as an example, but this is not limiting, and sintering with silver or copper may also be performed.

Next, as shown in Figures 2 and 4, in step S2, solder 4 is placed on the surface electrodes of the semiconductor element 2 and on the surface pattern 1b, and the lead frame 3 is placed on top of them. The solder 4 is melted by reflow or the like, thereby joining the surface electrodes of the semiconductor element 2 to the lead frame 3 and also joining the surface pattern 1b to the lead frame 3.

Next, as shown in Figures 2 and 5, in step S3, the wire pads of the semiconductor element 2 and the signal terminals of the lead frame 3 are ultrasonically bonded with aluminum wires 8 having a wire diameter of approximately 100 to 400 μm.

Next, as shown in Figures 2 and 6, in step S4, the wire-bonded product and tablet-shaped resin that will be the material for molded resin 5 are placed in the lower die of a metal mold (not shown), the upper die is closed, and the resin is gelled at a high temperature of about 180°C, and pressure is applied to force it through the runner and gate into the space (cavity) within the metal mold. The gelled resin hardens again at high temperature to become molded resin 5 that has the same shape as the cavity. This is then removed from the metal mold.

Next, as shown in Figures 2 and 7, in step S5, solder 11 and the semiconductor device, which is a molded product, are placed on the heat sink 10, which is a heat dissipation member, and the solder 11 is melted by reflow or the like to join the semiconductor device and the heat sink 10.

Of the above processes, the insulating substrate 1 is exposed to high temperatures in the die bonding process (step S1), lead bonding process (step S2), molding process (step S4), and solder mounting process (step S5). The ceramics that make up the insulating layer 1a of the insulating substrate 1 are brittle materials and have low bending resistance, so it is important to minimize warping in each process.

However, since the insulating substrate 1 requires electrical conductivity and heat dissipation for its function, the front and back patterns 1b and 1c are bonded and patterned on the front and back surfaces, respectively. Copper is generally used for the front and back patterns 1b and 1c because of its superior performance. Copper is a highly rigid material and has a different linear expansion coefficient from ceramics, so if the balance between the front and back sides of the insulating layer 1a is poor, warping will occur with temperature changes. The front pattern 1b is generally divided into multiple regions by first slits 6 to allow electrical conductivity, and is less rigid than the undivided front pattern 1b. To balance the lowered rigidity of the front pattern 1b, second slits 7 are provided in the back pattern 1c to reduce its rigidity.

Also, because the back surface pattern 1c serves as a heat dissipation path for transmitting heat generated from the semiconductor element 2 to the heat sink 10, the second slits 7 are not provided directly below the semiconductor element 2, but are provided around the area directly below the semiconductor element 2. In other words, the second slits 7 are provided so as to surround the area of the front surface pattern 1b that corresponds to the location where the semiconductor element 2 is mounted.

Next, we will explain the solder voids 12 that occur in the solder 11. Figure 13 is a cross-sectional view of a semiconductor device to explain the occurrence of solder voids 12 in related technology. Figure 8 is a cross-sectional view of a semiconductor device to explain the occurrence of solder voids 12 in an embodiment.

If air is entrained during soldering to the heat sink 10 and remains in the solder 11, as shown in FIG. 13, it becomes a solder void 12 that inhibits heat dissipation. The smaller the area of the joining member joined to the heat sink 10, the easier it is for the solder void 12 to escape, but it is difficult to escape from a joining member with a large area such as the insulating substrate 1. However, even in the insulating substrate 1 with a large area, it is mainly directly below the semiconductor element 2 that contributes to heat dissipation. Therefore, if the solder void 12 can be discharged to the second slit 7 provided in the back pattern 1c as shown in FIG. 8, the effect on heat dissipation is reduced, and a semiconductor device with good heat dissipation can be realized. Since the position where the solder void 12 occurs is not specific, the effect of discharging the solder void 12 from directly below the semiconductor element 2 is further enhanced by creating a reduced pressure atmosphere or rocking.

As described above, in order to discharge the solder voids 12 into the second slits 7, it is necessary to prevent the second slits 7 from being filled with the molding resin 5. When setting the wire-bonded product in the lower die of the metal mold, its positioning must be performed using the lead frame 3. This is because the lead frame 3 and the metal mold are machined so that there is no gap between them, so that the resin does not leak when the upper and lower dies are closed and the resin is injected into the cavity. However, since some misalignment occurs due to the precision and clearance of the jig used to join the lead frame 3 and the insulating substrate 1 with the solder 4, it is possible to bring the insulating substrate 1 into contact only with the surface of the lower die, but it is difficult to fit the periphery of the back surface pattern 1c into the lower die without any gaps.

Therefore, by connecting only the outermost periphery of the back pattern 1c, rather than completely dividing it like the front pattern 1b, it is possible to prevent the molding resin 5 from flowing into the second slit 7. The width of the connected portion of the outermost periphery of the back pattern 1c depends on the pressure when the resin is injected and the flatness of the insulating substrate 1, but it is preferable for it to be about 1 mm.

FIG. 9 is a bottom view showing an example of an insulating substrate 1 included in a semiconductor device according to an embodiment. FIG. 10 is a bottom view showing another example of an insulating substrate 1 included in a semiconductor device according to an embodiment. As shown in FIG. 9, if the outermost periphery of the back surface pattern 1c is not connected, it is necessary to suppress the inflow of resin from the outermost periphery of the back surface pattern 1c by pressing a cushioning sheet or the like against the back surface pattern 1c during transfer molding, but this becomes more difficult as the thickness of the back surface pattern 1c increases. As shown in FIG. 10, at the outermost periphery of the back surface pattern 1c, the back surface pattern 1c is connected, so that a cushioning sheet or the like is not required, making it possible to suppress the inflow of resin without any restrictions on the thickness of the back surface pattern 1c.

As explained above, warping of the insulating substrate 1 alone is suppressed, but it is also important to suppress cracking of the insulating substrate 1 if warping occurs in the product after transfer molding. Warping of the product after transfer molding is caused by differences in expansion and contraction between the mold resin 5 and the insulating substrate 1. Therefore, it is important to make the linear expansion coefficients of the mold resin 5 and the insulating substrate 1 close to each other.

The main components that determine the mechanical properties such as the linear expansion coefficient of the mold resin 5 are resin and filler, and the linear expansion coefficient can be reduced by increasing the filler ratio. However, if the filler ratio is too high, the fluidity of the resin deteriorates during transfer molding, so in practice the filler ratio is adjusted so that the linear expansion coefficient is in the range of 10 ppm/℃ to 20 ppm/℃.

On the other hand, if the insulating substrate 1 is a composite of ceramics (insulating layer 1a) and front and back copper patterns (front pattern 1b and back pattern 1c), the linear expansion coefficient can be adjusted by changing the thickness. For example, silicon nitride is often used as ceramic, and has a linear expansion coefficient of 3.5 ppm/°C, while the copper pattern has a linear expansion coefficient of 16.7 ppm/°C. The linear expansion coefficient of these composites will be a value between those values, and which one it approaches is determined by the ratio of their respective rigidities. The rigidity ratio can be approximated by the ratio of the products of the volumes and elastic coefficients of each.

The linear expansion coefficient of the molded resin 5, 10 ppm/°C, is intermediate between the linear expansion coefficients of silicon nitride and copper, and it is sufficient if the rigidity of each is equivalent. The elastic coefficient of silicon nitride is 300 GPa, the elastic coefficient of copper is 117 GPa, the thickness of silicon nitride is t1, the thickness of copper is t2, and the area ratio of copper varies depending on the design specifications but is approximately 90%, so 300 x t1 x 1 = 117 x t2 x 0.9, and t2 = 300/(117 x 0.9) x t1 ≒ 2.85 x t1.

In other words, if the total thickness of the copper patterns on the front and back is 2.8 times the thickness of the ceramic, or 1.4 times the thickness of the copper patterns on the front and back if they are the same thickness, the linear expansion coefficient will be about 10 ppm/°C. By further increasing the thickness of the copper pattern, it can be made greater than 10 ppm/°C, and by making it copper-rich, the linear expansion coefficient can theoretically be made as close as possible to that of copper. However, taking into account the manufacturing constraints of the insulating substrate 1 and the size constraints of the semiconductor device, the thickness of the copper patterns on the front and back is thought to be at most 3 to 3.5 times the thickness of the ceramic.

It is impossible to eliminate warping of the insulating substrate 1 alone, and warping of the product after transfer molding. Therefore, it is also important to make the insulating layer 1a, which is made of ceramics, a brittle material, less likely to crack.

If no slits are provided in the front pattern 1b and the back pattern 1c, the front pattern 1b and the back pattern 1c protect the insulating layer 1a and are resistant to bending. On the other hand, if slits are provided, the difference in rigidity between the part with the front pattern 1b (or back pattern 1c) and the part with the first slit 6 (or second slit 7) is large, so bending occurs in the part with the first slit 6 (or second slit 7), making it more likely to crack. If the first slit 6 and the second slit 7 overlap when viewed from the thickness direction of the insulating substrate 1, it becomes even more likely to crack.

In order to solve such a problem, in the embodiment, the first slit 6 and the second slit 7 do not overlap or only partially overlap when viewed from the thickness direction of the insulating substrate 1. Below, a case where the first slit 6 and the second slit 7 only partially overlap will be described. The first slit 6 and the second slit 7 both have at least one straight portion, and when the first slit 6 and the second slit 7 partially overlap when viewed from the thickness direction of the insulating substrate 1, the length of the overlapping portion between the predetermined straight portion of the first slit 6 and the predetermined straight portion of the second slit 7 when viewed from the thickness direction of the insulating substrate 1 is 50% or less of the sum of the length of the predetermined straight portion of the first slit 6 and the length of the predetermined straight portion of the second slit 7. In addition, in FIG. 9 and FIG. 10, the second slit 7 is formed in a lattice shape and has multiple straight portions.

In this way, by reducing the overlapping area between the first slit 6 and the second slit 7, a structure can be achieved in which the insulating substrate 1 is less likely to crack, even if the product warps after transfer molding.

＜Effects＞
As described above, the semiconductor device according to the embodiment includes an insulating substrate 1 having an insulating layer 1a, a front pattern 1b formed on the front surface of the insulating layer 1a, and a rear pattern 1c formed on the rear surface of the insulating layer 1a, a semiconductor element 2 mounted on the front pattern 1b, and a molded resin 5 that seals the insulating substrate 1 and the semiconductor element 2 while exposing a surface of the rear pattern 1c opposite to a surface facing the insulating layer 1a. The rear pattern 1c is bonded to a heat sink 10 with solder 11, and the surface of the rear pattern 1c bonded to the heat sink 10 is located at the same height as the surface of the molded resin 5 facing the heat sink 10. The front pattern 1b is provided with a first slit 6 for dividing the front pattern 1b into a plurality of regions, and the rear pattern 1c is provided with a second slit 7 for dividing the rear pattern 1c into a plurality of regions. When viewed from the thickness direction of the insulating substrate 1, the first slit 6 and the second slit 7 do not overlap or only partially overlap.

Specifically, both the first slit 6 and the second slit 7 have at least one straight portion, and when viewed from the thickness direction of the insulating substrate 1, the length of the overlapping portion between a predetermined straight portion of at least one straight portion of the first slit 6 and a predetermined straight portion of at least one straight portion of the second slit 7 is 50% or less of the sum of the length of the predetermined straight portion of the first slit 6 and the length of the predetermined straight portion of the second slit 7.

As a result, when viewed from the thickness direction of the insulating substrate 1, the overlapping portion between the first slit 6 on the front side of the insulating substrate 1 and the second slit 7 on the back side is small, so that even if the product warps after transfer molding, the insulating substrate 1 can be prevented from cracking. As a result, the semiconductor device can be used for a long period of time.

In addition, since the second slit 7 is not filled with the molding resin 5, the solder voids 12 remaining in the solder 4 during solder joining can be discharged to the second slit 7. This allows the heat generated by the semiconductor element 2 to be dissipated efficiently.

In addition, since the rear pattern 1c is connected at the outermost periphery of the rear pattern 1c, it is possible to prevent the molding resin 5 from flowing into the second slit 7 during transfer molding.

In addition, because the second slits 7 surround the periphery of the position on the surface pattern 1b corresponding to the location where the semiconductor element 2 is mounted, solder voids 12 are less likely to occur directly below the semiconductor element 2. This improves the heat dissipation of the semiconductor device.

In addition, the thicknesses of the front surface pattern 1b and the back surface pattern 1c are both 1.4 times or more the thickness of the insulating layer 1a. This increases the effect of suppressing warping of the insulating substrate 1, and therefore also increases the effect of suppressing warping of the product after transfer molding.

In addition, because the semiconductor element 2 is a wide band gap semiconductor element, it can operate at higher temperatures than a Si semiconductor element, but because the heat dissipation effect of the semiconductor device can be increased as described above, it is possible to suppress the temperature rise of the semiconductor element 2. This makes it possible to suppress losses in the semiconductor element 2.

In addition, although SiC MOSFETs can operate at high temperatures, loss increases drastically at high temperatures, so it is desirable to use them at temperatures as low as possible. The configuration of the semiconductor device according to the embodiment is particularly suitable for SiC MOSFETs, since it is possible to efficiently transfer heat generated by the semiconductor element 2 to the heat sink 10 and suppress the temperature rise of the semiconductor element 2.

<Modifications of the embodiment>
Next, a modified example of the embodiment will be described. Fig. 11 is an enlarged cross-sectional view of the periphery of a second slit 7 provided in a back pattern 1c of a semiconductor device according to the embodiment. Fig. 12 is an enlarged cross-sectional view of the periphery of a second slit 7 provided in a back pattern 1c of a semiconductor device according to the modified example of the embodiment.

In semiconductor devices, high voltages may be applied to the front and back sides of the insulating substrate 1. For example, in an electric vehicle, the voltage is about 400V to 1000V. As shown in FIG. 11, if the second slit 7 is formed through the back pattern 1c to the back side of the insulating layer 1a, and there is a solder void 12 (see FIG. 8) in the second slit 7, the solder void 12 may come into contact with the insulating layer 1a, causing partial discharge 13 to occur from the insulating layer 1a.

To avoid this problem, in a modified embodiment, as shown in FIG. 12, the second slits 7 are not formed to the back surface of the insulating layer 1a without penetrating the back surface pattern 1c. In other words, the back surface pattern 1c is in close contact with the back surface of the insulating layer 1a even in the area where the second slits 7 are provided.

Next, a method for manufacturing the insulating substrate 1 will be described. There are two methods: a method in which a back pattern 1c on which the second slits 7 have been formed by punching using a press or the like is attached to the insulating layer 1a, and a method in which a back pattern 1c on which the second slits 7 have not been formed is attached, and then the copper is melted by etching and patterned to form the second slits 7; the latter manufacturing method is generally used.

In the back surface pattern 1c, the portions where the second slits 7 are not to be formed are masked, and an etching solution is sprayed and dissolved only in the portions where the second slits 7 are to be formed, to perform patterning. Normally, the insulating layer 1a is exposed in the etched portions, but in this modified embodiment, the second slits 7 are formed by half-etching, which stops etching midway through the thickness direction of the insulating substrate 1 when etching the back surface pattern 1c. Therefore, the insulating layer 1a is not exposed in the etched portions. As a result, the solder voids 12 do not come into contact with the insulating layer 1a, and the occurrence of partial discharges 13 can be suppressed.

Although this disclosure has been described in detail, the above description is illustrative in all respects and is not limiting. It is understood that countless variations not illustrated can be envisioned.

In addition, each embodiment can be freely combined, modified, or omitted as appropriate.

1 insulating substrate, 1a insulating layer, 1b surface pattern, 1c back pattern, 2 semiconductor element, 5 molded resin, 6 first slit, 7 second slit, 10 heat sink, 11 solder.

Claims (9)

an insulating substrate having an insulating layer, a front pattern formed on a front surface of the insulating layer, and a back pattern formed on a back surface of the insulating layer;
a semiconductor element mounted on the surface pattern;
a sealing resin that seals the insulating substrate and the semiconductor element in a state where a surface of the back surface pattern opposite to a surface facing the insulating layer is exposed,
The rear pattern is soldered to a heat sink;
a surface of the rear surface pattern that is bonded to the heat sink is located at the same height as a surface of the sealing resin that faces the heat sink,
the surface pattern is provided with a first slit for dividing the surface pattern into a plurality of regions;
a second slit is provided in the rear surface pattern to divide the rear surface pattern into a plurality of regions;
The semiconductor device, wherein the first slit and the second slit do not overlap or only partially overlap when viewed in a thickness direction of the insulating substrate. The semiconductor device according to claim 1, wherein the sealing resin is not filled in the second slit. The semiconductor device according to claim 1 or claim 2, wherein the back surface pattern is connected at the outermost periphery of the back surface pattern. The semiconductor device according to any one of claims 1 to 3, wherein the second slit surrounds a position on the surface pattern that corresponds to the location where the semiconductor element is mounted. Each of the first slit and the second slit has at least one straight portion;
5. The semiconductor device according to claim 1, wherein, when viewed from the thickness direction of the insulating substrate, a length of an overlapping portion between a predetermined one of the at least one straight portion of the first slit and a predetermined one of the at least one straight portion of the second slit is 50% or less of a sum of a length of the predetermined straight portion of the first slit and a length of the predetermined straight portion of the second slit. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the front surface pattern and the back surface pattern is at least 1.4 times the thickness of the insulating layer. The semiconductor device according to any one of claims 1 to 6, wherein the second slit is not formed to the back surface of the insulating layer without penetrating the back surface pattern. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor element is a wide band gap semiconductor element. A method for manufacturing the semiconductor device according to claim 7, comprising the steps of:
The second slit is formed by half-etching, which stops etching midway in the thickness direction of the insulating substrate when etching the rear surface pattern.

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