WO2025025502A1 - Preparation method for heterojunction back-contact battery, and heterojunction back-contact battery - Google Patents

Abstract

A preparation method for a heterojunction back-contact battery, and a heterojunction back-contact battery. The method comprises: forming a first initial semiconductor passivation layer on one side of a semiconductor substrate layer; forming a first initial doped semiconductor layer on the surface of the side of the first initial semiconductor passivation layer away from the semiconductor substrate layer; performing first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, and performing first cleaning treatment after the first laser ablation treatment, to form a first opening, cause the first initial semiconductor passivation layer to form a first semiconductor passivation layer located on the side part of the first opening, and cause the first initial doped semiconductor layer to form a first doped semiconductor layer located on the side part of the first opening; and forming, in the first opening, a second semiconductor passivation layer, and a second doped semiconductor layer located on the surface of the side of the second semiconductor passivation layer away from the semiconductor substrate layer. The method can effectively simplify the process, reduce costs, improve patterning precision and reduce damage.

Description

Preparation method of heterojunction back contact battery and heterojunction back contact battery

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310966147.5 and invention name “Method for preparing heterojunction back contact battery and heterojunction back contact battery”, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a heterojunction back-contact cell and a heterojunction back-contact cell.

Background Art

In recent years, energy crisis and environmental pressure have promoted the rapid development of solar cell research and industry. At present, the mainstream photovoltaic cell is crystalline silicon solar cell, which accounts for more than 90% of the photovoltaic market and will dominate for a long time in the future.

Due to the limitation of its technical mechanism, the N-type TOPCon (Tunnel Oxide Passivated Contact) tunnel oxide passivated contact cell has encountered a bottleneck in improving the conversion efficiency. The back-contact cell is a special structure in which the positive and negative grid lines are all located on the back, achieving an unobstructed front effect, so it can maximize the use of light, thereby significantly improving the conversion efficiency. At the same time, the design of no grid lines on the front also makes the components more beautiful. The N-type HBC (heterojunction back contact cell) combines the advantages of full light reception of the back contact cell and high-quality passivation of the heterojunction cell. Its experimental efficiency reaches 26.63%, and the efficiency is greatly improved. On the one hand, it increases the power generation per watt of the cell itself, and on the other hand, it is conducive to reducing the power generation cost of the entire industry chain.

HBC currently uses a mask etching process to generate the opposite PN junction area, and uses a mask etching process to remove part of the conductive layer to separate the conductive layers, thereby avoiding short circuits between the positive and negative gate lines. However, the mask etching process is complex, has low precision, and is difficult to control etching quality, which limits the large-scale production of HBC.

Therefore, a method for preparing HBC heterojunction back contact cells that effectively simplifies the process, has high production efficiency and low cost is urgently needed by the market.

Summary of the invention

The technical problem to be solved by this application is to overcome the problems in the prior art in preparing heterojunction back contact cells. To solve the problems in the process, a method for preparing a heterojunction back contact battery and a heterojunction back contact battery are provided, which can not only effectively simplify the process, improve production efficiency and reduce costs, but also improve the accuracy of graphics, reduce damage and facilitate large-scale production.

In order to solve the above technical problems, the present application provides a method for preparing a heterojunction back contact battery, comprising: providing a semiconductor substrate layer; forming a first initial semiconductor passivation layer on a side surface of the semiconductor substrate layer; forming a first initial doped semiconductor layer on a side surface of the first initial semiconductor passivation layer away from the semiconductor substrate layer; performing a first laser ablation treatment on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, performing a first cleaning treatment after the first laser ablation treatment, forming a first opening, and making the first initial semiconductor passivation layer form a first semiconductor passivation layer located at a side portion of the first opening, and making the first initial doped semiconductor layer form a first doped semiconductor layer located at a side portion of the first opening; forming a second A semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer, the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; a first transparent conductive film is formed on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; a second transparent conductive film is formed on a surface of the second doped semiconductor layer facing away from the semiconductor substrate layer; a first gate line is formed on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and a second gate line is formed on a surface of the second transparent conductive film facing away from the semiconductor substrate layer.

Optionally, the parameters of the first laser ablation process include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W.

Optionally, the wavelength of the laser used is 355 nm or 532 nm.

Optionally, the parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is KOH solution or NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

Optionally, it also includes: before performing the first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, an initial isolation layer is formed on the surface of the first initial doped semiconductor layer facing away from the semiconductor substrate layer; in the process of performing the first laser ablation treatment on part of the first initial doped semiconductor layer and part of the first initial semiconductor passivation layer, the initial isolation layer is also subjected to the first laser ablation treatment to form an isolation layer; the preparation method of the heterojunction back contact battery also includes: in the process of forming the second semiconductor passivation layer and the second doped semiconductor layer, a second additional passivation layer and a second additional doped layer are formed on the surface of part of the isolation layer facing away from the semiconductor substrate layer, the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, The material of the second additional doped layer is the same as that of the second doped semiconductor layer. The second additional doped layer is located on a surface of the second additional passivation layer facing away from the semiconductor substrate layer. A second opening is formed in the isolation layer, and the second opening exposes the first doped semiconductor layer.

Optionally, the steps of forming the second semiconductor passivation layer and the second doped semiconductor layer, the second additional passivation layer and the second additional doped layer include: sequentially forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer facing away from the semiconductor substrate layer; performing a second laser ablation treatment and a second cleaning treatment on part of the isolation layer and part of the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer facing away from the semiconductor substrate layer forms a second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer facing away from the semiconductor substrate layer forms a second additional doped layer, and a second opening is formed in the isolation layer; sequentially performing a third laser ablation treatment and a third cleaning treatment on the area where the second initial passivation film and the second initial doped semiconductor film in the first opening and the first semiconductor passivation layer and the first doped semiconductor layer intersect, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer.

Optionally, the parameters of the second laser ablation treatment include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; optionally, the wavelength of the laser used is 355nm or 532nm.

Optionally, the parameters of the second cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

Optionally, parameters of the third laser ablation process include: the laser used is a green laser, and the pulse width of the laser used is in nanosecond level.

Optionally, the wavelength of the laser used is 532 nm.

Optionally, the parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is KOH solution or NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

Optionally, it also includes: performing texturing treatment on the other side surface of the semiconductor substrate layer to form an anti-reflection velvet surface; forming a third semiconductor passivation layer on the reflective velvet surface; and forming an anti-reflection layer on the side surface of the third semiconductor passivation layer away from the semiconductor substrate layer.

Optionally, the step of forming the first transparent conductive film and the second transparent conductive film includes: after performing the second cleaning process and before performing the third laser ablation process, on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and on a surface of the second initial doped semiconductor film facing away from the semiconductor substrate layer, A transparent conductive film is formed on one surface of the conductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the boundary area between the transparent conductive film in the first opening and the first semiconductor passivation layer and the first doped semiconductor layer, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film.

The present application also provides a heterojunction back contact battery, comprising: a semiconductor substrate layer; a first semiconductor passivation layer located on one side surface of the semiconductor substrate layer, and a first doped semiconductor layer located on one side surface of the first semiconductor passivation layer away from the semiconductor substrate layer; a first opening, penetrating the first doped semiconductor layer and the first semiconductor passivation layer; a second semiconductor passivation layer and a second doped semiconductor layer located in the first opening, the second doped semiconductor layer located on one side surface of the second semiconductor passivation layer away from the semiconductor substrate layer, the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; a first transparent conductive film located on one side surface of the first doped semiconductor layer away from the semiconductor substrate layer; a second transparent conductive film located on one side surface of the second doped semiconductor layer away from the semiconductor substrate layer; a first gate line located on one side surface of the first transparent conductive film away from the semiconductor substrate layer; a second gate line located on one side surface of the second transparent conductive film away from the semiconductor substrate layer.

The technical solution of this application has the following technical effects:

The technical solution of the present application provides a method for preparing a heterojunction back-contact battery, which performs a first laser ablation treatment on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, performs a first cleaning treatment after the first laser ablation treatment, forms a first opening, and makes the first initial semiconductor passivation layer form the first semiconductor passivation layer on the side of the first opening, makes the first initial doped semiconductor layer form the first doped semiconductor layer on the side of the first opening, forms a second semiconductor passivation layer and a second doped semiconductor layer located on the surface of the second semiconductor passivation layer away from the semiconductor substrate layer in the first opening, the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer, thereby reducing the lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer, and reducing the lateral electrical crosstalk between the second semiconductor passivation layer and the first semiconductor passivation layer, the first laser ablation treatment has a fast processing speed, high precision, low cost, and low pollution, can effectively simplify the process, reduce costs, and improve the accuracy of patterning and reduce damage.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a flow chart of a heterojunction back contact cell provided by an embodiment of the present application;

2 to 11 are structural diagrams of a process for preparing a heterojunction back contact cell according to an embodiment of the present application.

Figure ID:
Semiconductor substrate layer 100; third semiconductor passivation layer 110; anti-reflection layer 120; first initial semiconductor passivation layer 130; first initial doped semiconductor layer 140; first doped semiconductor layer 140a; initial isolation layer 150; isolation layer 150a; first opening 160; second initial passivation film 170; second additional passivation layer 170a; second semiconductor passivation layer 170b; second initial doped semiconductor film 180; second additional doped layer 180a; second doped semiconductor layer 180b; second opening 190; transparent conductive film 200; first transparent conductive film 200a; second transparent conductive film 200b.

DETAILED DESCRIPTION

The technical solution of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

This embodiment provides a method for preparing a heterojunction back contact cell, referring to FIG1 , comprising:

Step S1: providing a semiconductor substrate layer;

Step S2: forming a first initial semiconductor passivation layer on one side of the semiconductor substrate layer;

Step S3: forming a first initial doped semiconductor layer on a surface of the first initial semiconductor passivation layer that is away from the semiconductor substrate layer;

Step S4: performing a first laser ablation process on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, and performing a first cleaning process after the first laser ablation process to form a first opening, and to form the first initial semiconductor passivation layer into a first semiconductor passivation layer located at a side of the first opening, and to form the first initial doped semiconductor layer into a first doped semiconductor layer located at a side of the first opening;

Step S5: forming a second semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer in the first opening, wherein the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer;

Step S6: forming a first transparent conductive film on a surface of the first doped semiconductor layer away from the semiconductor substrate layer; forming a second transparent conductive film on a surface of the second doped semiconductor layer away from the semiconductor substrate layer;

Step S7: forming a first gate line on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and forming a second gate line on a surface of the second transparent conductive film facing away from the semiconductor substrate layer.

In the preparation method of the heterojunction back-contact battery of this embodiment, the first laser ablation treatment has fast processing speed, high precision, low cost and little pollution, which can effectively simplify the process, reduce cost, improve the accuracy of graphics, reduce damage, and facilitate large-scale production.

The second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer, thereby reducing the lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer, and reducing the lateral electrical crosstalk between the second semiconductor passivation layer and the first semiconductor passivation layer.

2 to 11 are structural diagrams of a process for preparing a heterojunction back contact cell according to an embodiment of the present application.

2 , a semiconductor substrate layer 100 is provided.

The material of the semiconductor substrate layer 100 includes N-type single crystal silicon. In one embodiment, the thickness of the semiconductor substrate layer 100 is 145 micrometers to 155 micrometers, for example, 150 micrometers.

4 , a first initial semiconductor passivation layer 130 is formed on one side of the semiconductor substrate layer 100 ; and a first initial doped semiconductor layer 140 is formed on one side of the first initial semiconductor passivation layer 130 away from the semiconductor substrate layer 100 .

The material of the first initial semiconductor passivation layer 130 includes intrinsic hydrogenated amorphous silicon.

In one embodiment, the thickness of the first initial semiconductor passivation layer is 6 nm-10 nm.

The conductivity type of the first initially doped semiconductor layer 140 is different from the conductivity type of the semiconductor substrate layer 100. In other embodiments, the conductivity type of the first initially doped semiconductor layer 140 is the same as the conductivity type of the semiconductor substrate layer 100.

The material of the first initial doped semiconductor layer 140 includes amorphous silicon doped with first conductive ions.

In one embodiment, the thickness of the first initial doped semiconductor layer 140 is 28 nm to 32 nm, for example 30nm.

In this embodiment, referring to Figure 3, optionally, before forming the first initial semiconductor passivation layer 130 and the first initial doped semiconductor layer 140, it also includes: forming a third semiconductor passivation layer 110 on the other side surface of the semiconductor substrate layer 100; and forming an anti-reflection layer 120 on the side surface of the third semiconductor passivation layer 110 away from the semiconductor substrate layer 100.

The third semiconductor passivation layer 110 is formed before forming the first initial semiconductor passivation layer 130 and the first initial doped semiconductor layer 140 . The third semiconductor passivation layer 110 can protect the other side surface of the semiconductor substrate layer 100 from being contaminated by subsequent process steps.

The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side, and the side of the semiconductor substrate layer 100 facing the first initial semiconductor passivation layer 140 is the back side. The defects on the surface of the side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 have a greater impact on the electrical performance of the heterojunction back contact battery, and the front side of the semiconductor substrate layer 100 needs to be better protected. Therefore, in this embodiment, the first initial semiconductor passivation layer 130 is formed after the third semiconductor passivation layer 110 is formed. In other embodiments, the third semiconductor passivation layer 110 may be formed after the first initial semiconductor passivation layer 130 is formed.

The process of forming the third semiconductor passivation layer 110 includes a plasma enhanced chemical vapor deposition process (PECVD). The process of forming the anti-reflection layer 120 includes a plasma enhanced chemical vapor deposition process (PECVD). In one embodiment, the thickness of the third semiconductor passivation layer 110 is 6nm-10nm, and the thickness of the anti-reflection layer 120 is 80nm-100nm.

The material of the third semiconductor passivation layer 110 includes intrinsic hydrogenated amorphous silicon.

The anti-reflection layer 120 is made of silicon nitride.

In this embodiment, the third semiconductor passivation layer 110 and the anti-reflection layer 120 are formed before forming the first initial semiconductor passivation layer 140. In other embodiments, the third semiconductor passivation layer 110 and the anti-reflection layer 120 may be formed after forming the subsequent first transparent conductive film and the second transparent conductive film.

In this embodiment, it also includes: before forming the third semiconductor passivation layer 110, the other side surface of the semiconductor substrate layer 100 is textured so that the other side surface of the semiconductor substrate layer 100 presents an anti-reflection velvet surface; forming the third semiconductor passivation layer 110 on the reflective velvet surface; and forming an anti-reflection layer 120 on the side surface of the third semiconductor passivation layer 110 away from the semiconductor substrate layer 100.

Before the other side surface of the semiconductor substrate layer 100 is subjected to the texturing treatment and before the first initial semiconductor passivation layer 130 is formed, in the example, before the other side surface of the semiconductor substrate layer 100 is subjected to the texturing treatment and before the first initial semiconductor passivation layer 130 is formed, it also includes: pre-cleaning the semiconductor substrate layer 100; after the pre-cleaning, polishing the surface of the semiconductor substrate layer 100; after the polishing of the surface of the semiconductor substrate layer 100, performing the main cleaning treatment on the surface of the semiconductor substrate layer 100.

In one embodiment, the texturing process is as follows: the other side surface of the semiconductor substrate layer is etched by a reactive plasma etching process, so that the other side surface of the semiconductor substrate layer 100 is anti-reflective. Shot suede.

In one embodiment, the parameters of the reactive plasma etching process include: the gases used include _SF6 , _O2 and _SiCl4 , the flow rate of _SF6 is 1120sccm-1600sccm, the flow rate of _O2 is 1400sccm-2000sccm, the flow rate of _SiCl4 is 700sccm-1000sccm, the chamber pressure is 25Pa-30Pa, the temperature is 150℃～200℃, and the etching rate is 10mm/s-18mm/s.

Since the anti-reflection suede is formed by reactive plasma etching, the reflectivity of the anti-reflection suede is less than or equal to 7%. The reflectivity of the anti-reflection suede formed by conventional wet etching is greater than 10%. The reflectivity of the anti-reflection suede in this embodiment is significantly reduced, resulting in better light absorption and optimal short-circuit current.

5 , an initial isolation layer 150 is formed on a surface of the first initial doped semiconductor layer 140 that is away from the semiconductor substrate layer 100 .

The material of the initial isolation layer 150 includes silicon nitride.

In one embodiment, the thickness of the initial isolation layer 150 is 60 nm-120 nm.

The process for forming the initial isolation layer includes a plasma enhanced chemical vapor deposition process, and the parameters include: the gases used include _SiH4 and _NH3 , the temperature is 180-200°C, the chamber pressure is 220mtorr-2200mtorr, the deposition time is 1min-2min, the flow rate of _SiH4 is 1800ml/min-2300ml/min, and the flow rate of _NH3 is 6000ml/min-7000ml/min.

Referring to Figure 6, a first laser ablation treatment is performed on a portion of the first initial doped semiconductor layer 140 and a portion of the first initial semiconductor passivation layer 130. During the process of performing the first laser ablation treatment on a portion of the first initial doped semiconductor layer 140 and a portion of the first initial semiconductor passivation layer 130, a first laser ablation treatment is also performed on the initial isolation layer 150. After the first laser ablation treatment, a first cleaning treatment is performed to form a first opening 160, and the first initial semiconductor passivation layer 130 is formed into a first semiconductor passivation layer 130a, the first initial doped semiconductor layer 140 is formed into a first doped semiconductor layer 140a, and the initial isolation layer 150 is formed into an isolation layer 150a.

In one embodiment, the parameters of the first laser ablation process include: the laser used is ultraviolet light or green laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W. Optionally, the wavelength of the laser used in the first laser ablation process is 355nm or 532nm.

In one embodiment, the parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

The method for preparing the heterojunction back contact battery further includes: in the process of forming the second semiconductor passivation layer and the second doped semiconductor layer, forming a second additional passivation layer and a second additional doped layer on a surface of a part of the isolation layer away from the semiconductor substrate layer, wherein the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, the material of the second additional doped layer is the same as the material of the second doped semiconductor layer, and the second additional doped layer is located on the side of the second additional passivation layer away from the semiconductor substrate layer. A second opening is formed in the isolation layer on one side surface, and the second opening exposes the first doped semiconductor layer.

The steps of forming the second semiconductor passivation layer and the second doped semiconductor layer, the second additional passivation layer and the second additional doped layer include: sequentially forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer away from the semiconductor substrate layer; performing a second laser ablation process and a second cleaning process on a part of the isolation layer and the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional doped layer, and forming a second opening in the isolation layer. Performing a third laser ablation process and a third cleaning process on the area where the second initial passivation film and the second initial doped semiconductor film in the first opening intersect with the first semiconductor passivation layer and the first doped semiconductor layer, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer.

The steps of forming the first transparent conductive film and the second transparent conductive film include: after performing a second cleaning treatment and before performing a third laser ablation treatment, forming a transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and a surface of the second initial doped semiconductor film facing away from the semiconductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes a portion of the transparent conductive film, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film, and the first transparent conductive film and the second transparent conductive film are separated.

7 , a second initial passivation film 170 and a second initial doped semiconductor film 180 are sequentially formed in the first opening 160 and on a side of the isolation layer 150 a away from the semiconductor substrate layer 100 .

It should be noted that the second initial passivation film 170 is conformally deposited, and the second initial doped semiconductor film 180 is conformally deposited, that is, the second initial passivation film 170 in the first opening 160 and the second initial passivation film 170 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 are connected together, and the second initial doped semiconductor film 180 in the first opening 160 and the second initial doped semiconductor film 180 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 are connected together.

The material of the second initial passivation film 170 includes intrinsic hydrogenated silicon. In one embodiment, the thickness of the second initial passivation film 170 is 6 nm-10 nm.

The material of the second initially doped semiconductor film 180 includes amorphous silicon doped with second conductive ions. The second conductive ions and the first conductive ions have different conductive types.

In one embodiment, the thickness of the second initial doped semiconductor film 180 is 28 nm to 32 nm, for example, 30 nm.

8, a portion of the isolation layer 150a and a portion of the isolation layer 150a away from the semiconductor substrate layer 100 The second initial passivation film 170 and the second initial doped semiconductor film 180 on one side are subjected to a second laser ablation treatment and a second cleaning treatment, so that the second initial passivation film 170 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 forms a second additional passivation layer 170a, and the second initial doped semiconductor film 180 on the side of the isolation layer 150a away from the semiconductor substrate layer 100 forms a second additional doped layer 180a, and a second opening 190 is formed in the isolation layer 150a.

In one embodiment, the parameters of the second laser ablation treatment include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; optionally, the wavelength of the laser used in the second laser ablation treatment is 355nm or 532nm.

In one embodiment, the parameters of the second cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

Referring to Figure 9, after the second cleaning treatment and before the third laser ablation treatment, a transparent conductive film 200 is formed on the side surface of the first doped semiconductor layer 140a facing away from the semiconductor substrate layer 100 and on the side surface of the second initial doped semiconductor film 180 in the first opening 160 facing away from the semiconductor substrate layer 100.

The material of the transparent conductive film 200 includes indium tin oxide. In one embodiment, the thickness of the transparent conductive film 200 is 70nm-100nm.

Referring to Figures 10 and 11, Figure 10 is a schematic diagram based on Figure 9, and Figure 11 is a top view of Figure 10. The second initial passivation film 170 and the second initial doped semiconductor film 180 in the first opening and the area where the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a intersect each other are sequentially subjected to a third laser ablation treatment and a third cleaning treatment, so that the second initial passivation film 170 in the first opening 160 forms a second semiconductor passivation layer 170b, and the second initial doped semiconductor film 180 in the first opening 160 forms a second doped semiconductor layer 180b; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the boundary area between the transparent conductive film 200 in the first opening 160 and the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a, so that the transparent conductive film 200 forms the first transparent conductive film 200a and the second transparent conductive film 200b, and the first transparent conductive film 200a and the second transparent conductive film 200b are separated.

The parameters of the third laser ablation process include: the laser used is a green laser, and the pulse width of the laser used is in the nanosecond level; optionally, the wavelength of the laser used in the third laser ablation process is 532 nm.

The parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; or, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds.

The preparation method of the heterojunction back contact cell of this embodiment adopts laser ablation to form The front-side connecting gate lines and the back-side connecting gate lines on the back side improve the patterning accuracy of the gate lines and optimize the aspect ratio.

In this embodiment, the present invention further includes: forming a first gate line on a surface of the first transparent conductive film 200 a facing away from the semiconductor substrate layer 100 , and forming a second gate line on a surface of the second transparent conductive film 200 b facing away from the semiconductor substrate layer 100 .

In one embodiment, the second transparent conductive film 200 b and the first transparent conductive film 200 a are arranged in parallel and in an alternating manner.

The first doped semiconductor layer 140a and the second doped semiconductor layer 180b have opposite conductivity types. When the conductivity type of the first doped semiconductor layer 140a is opposite to that of the semiconductor substrate layer 100, the first doped semiconductor layer 140a and the semiconductor substrate layer 100 form a PN junction. When the conductivity type of the second doped semiconductor layer 180b and the semiconductor substrate layer 100 are opposite, the second doped semiconductor layer 180b and the semiconductor substrate layer 100 form a PN junction. The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side. Light is irradiated into the semiconductor substrate layer 100 through the anti-reflection layer 120 and the third semiconductor passivation layer 110. The anti-reflection layer 120 can reduce the reflectivity of light and increase the transmittance. Light irradiation generates photogenerated carriers at the PN junction. The third semiconductor passivation layer 110 is located on the front side, and the field barrier prevents minority carriers from moving toward the front side. The first transparent conductive film 200a and the second transparent conductive film 200b collect photogenerated carriers.

The present application also provides a heterojunction back contact battery formed by the above-mentioned preparation method of the heterojunction back contact battery, with reference to Figures 10 and 11, comprising: a semiconductor substrate layer 100; a first semiconductor passivation layer 130a located on one side surface of the semiconductor substrate 100 layer, and a first doped semiconductor layer 140a located on the side surface of the first semiconductor passivation layer 130a away from the semiconductor substrate layer 100; a first opening 160, penetrating the first doped semiconductor layer 140a and the first semiconductor passivation layer 130a; a second semiconductor passivation layer 170b and a second doped semiconductor layer 180b located in the first opening 160, the second doped semiconductor layer 180b is located on the side surface of the second semiconductor passivation layer 170b away from the semiconductor substrate layer 100, and the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a. The second doped semiconductor layer 180b and the first doped semiconductor layer 140a have opposite conductivity types and are located on the same side of the semiconductor substrate layer.

The second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first semiconductor passivation layer 130a and the first doped semiconductor layer 140a, which means that the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first semiconductor passivation layer 130a, and the second doped semiconductor layer 180b and the second semiconductor passivation layer 170b are separated from the first doped semiconductor layer 140a.

In this embodiment, it also includes: a first transparent conductive film 200a and a second transparent conductive film 200b. The first transparent conductive film 200a is located on a side surface of the first doped semiconductor layer 140a away from the semiconductor substrate layer 100, and the second transparent conductive film 200b is located on a side surface of the second doped semiconductor layer 180b away from the semiconductor substrate layer 100. The first transparent conductive film 200a and the second transparent conductive film 200b are separated.

In this embodiment, the present invention further includes: an isolation layer 150a, located on a side surface of a portion of the first doped semiconductor layer 140a away from the semiconductor substrate layer 100; a second additional passivation layer 170a, located on a side surface of the isolation layer 150a away from the semiconductor substrate layer 100; and a second additional doped layer 180a, located on a side surface of the second additional passivation layer 170a away from the semiconductor substrate layer 100. The isolation layer 150a has a second opening 190 (see FIG. 8 ), and the first transparent conductive film 200a is located in the second opening 190.

In this embodiment, the process further includes forming a first gate line on a surface of the first transparent conductive film 200 a facing away from the semiconductor substrate layer 100 , and forming a second gate line on a surface of the second transparent conductive film 200 b facing away from the semiconductor substrate layer 100 .

In this embodiment, it also includes: a third semiconductor passivation layer 110 located on a surface of the semiconductor substrate layer 100 facing away from the first semiconductor passivation layer 130 a ; and an anti-reflection layer 120 located on a surface of the third semiconductor passivation layer 110 facing away from the semiconductor substrate layer 100 .

Taking the semiconductor substrate layer 100 as an N-type substrate as an example, since the conductivity types of the first doped semiconductor layer 140a and the second doped semiconductor layer 180b are opposite, when the doping type of the first doped semiconductor layer 140a is P-type, the doping type of the second doped semiconductor layer 180b is N-type. The first doped semiconductor layer 140a and the semiconductor substrate layer 100 form a PN junction, and the electrons of the photogenerated carriers move into the semiconductor substrate layer 100, and the holes move into the first doped semiconductor layer 140a; the doping concentration of the second doped layer 180b is much higher than the doping concentration of the semiconductor substrate layer 100, and a built-in electric field is formed between the second doped semiconductor layer 180b and the semiconductor substrate layer 100, so that the electrons of the photogenerated carriers move into the second doped semiconductor layer 180b, and the holes move into the semiconductor substrate 100. Therefore, when carriers are generated by light, electrons move to the second doped semiconductor layer 180b, which is the negative electrode of the battery, and holes move to the first doped semiconductor layer 140a, which is the positive electrode of the battery. Similarly, if the first doped semiconductor layer 140a is N-type doped, the second doped semiconductor layer 180b is P-type doped, then the first doped semiconductor layer 140a is the negative electrode of the battery, and the second doped semiconductor layer 180b is the positive electrode of the battery.

The side of the semiconductor substrate layer 100 facing the third semiconductor passivation layer 110 is the front side. Light is irradiated into the semiconductor substrate layer 100 through the anti-reflection layer 120 and the third semiconductor passivation layer 110. The anti-reflection layer 120 can reduce the reflectivity of light and increase the transmittance. The third semiconductor passivation layer 110 is located on the front side, and the field barrier prevents minority carriers from moving toward the front. The first transparent conductive film 200a and the second transparent conductive film 200b collect photogenerated carriers. The first transparent conductive film 200a and the second transparent conductive film 200b respectively collect photogenerated carriers with different electrical properties.

Since there is no grid line blocking the front of the heterojunction back-contact battery, the light is strong and the area is fully utilized, and the battery conversion efficiency is high; although the first grid line and the second grid line are set on the back of the heterojunction back-contact battery, the light on the back is not as direct as the front (including reflection, etc.), so it has little effect on optical loss.

In summary, the heterojunction back contact cell can reduce optical loss. In addition, the second doped semiconductor layer and the second semiconductor passivation layer are separated from the first semiconductor passivation layer and the first doped semiconductor layer. The lateral electrical crosstalk between the second doped semiconductor layer and the first doped semiconductor layer is reduced; and the electrode grid lines are printed on the back, so there is no need to consider the shading area factor, and there is no special requirement for the grid line width (wide grid lines can be designed), so the resistance loss is small and the resistance loss can be reduced. In summary, the heterojunction back contact cell can reduce optical loss and resistance loss to a certain extent due to the improved patterning accuracy of the grid lines and the optimized aspect ratio, and can improve Jsc and FF. Jsc can be increased by more than 6% compared with conventional HJT cells, and the efficiency can be increased by more than 1.5%.

Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims (10)

A method for preparing a heterojunction back contact battery, characterized by comprising: providing a semiconductor substrate layer; Forming a first initial semiconductor passivation layer on a surface of one side of the semiconductor substrate layer; forming a first initial doped semiconductor layer on a surface of the first initial semiconductor passivation layer facing away from the semiconductor substrate layer; Performing a first laser ablation process on a portion of the first initial doped semiconductor layer and a portion of the first initial semiconductor passivation layer, and performing a first cleaning process after the first laser ablation process to form a first opening, and to form the first initial semiconductor passivation layer into a first semiconductor passivation layer located at a side of the first opening, and to form the first initial doped semiconductor layer into a first doped semiconductor layer located at a side of the first opening; A second semiconductor passivation layer and a second doped semiconductor layer located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer are formed in the first opening, the second doped semiconductor layer and the second semiconductor passivation layer are both separated from the first semiconductor passivation layer and the first doped semiconductor layer, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; forming a first transparent conductive film on a surface of the first doped semiconductor layer away from the semiconductor substrate layer; forming a second transparent conductive film on a surface of the second doped semiconductor layer away from the semiconductor substrate layer; A first gate line is formed on a surface of the first transparent conductive film on a side away from the semiconductor substrate layer, and a second gate line is formed on a surface of the second transparent conductive film on a side away from the semiconductor substrate layer. The method for preparing a heterojunction back contact battery according to claim 1 is characterized in that the parameters of the first laser ablation process include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; Preferably, the wavelength of the laser used is 355 nm or 532 nm. The method for preparing a heterojunction back contact battery according to claim 1, characterized in that the parameters of the first cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; Alternatively, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds. The method for preparing a heterojunction back contact battery according to claim 1, characterized in that it also includes: performing a Before the first laser ablation treatment, an initial isolation layer is formed on the surface of the first initial doped semiconductor layer facing away from the semiconductor substrate layer; in the process of performing the first laser ablation treatment on a part of the first initial doped semiconductor layer and a part of the first initial semiconductor passivation layer, the initial isolation layer is also subjected to the first laser ablation treatment, so that the initial isolation layer forms an isolation layer; The preparation method of the heterojunction back contact battery also includes: in the process of forming a second semiconductor passivation layer and a second doped semiconductor layer, forming a second additional passivation layer and a second additional doped layer on the surface of a side of the isolation layer away from the semiconductor substrate layer, the material of the second additional passivation layer is the same as the material of the second semiconductor passivation layer, the material of the second additional doped layer is the same as the material of the second doped semiconductor layer, the second additional doped layer is located on the surface of the side of the second additional passivation layer away from the semiconductor substrate layer, and a second opening is formed in the isolation layer, and the second opening exposes the first doped semiconductor layer. The method for preparing a heterojunction back contact battery according to claim 4 is characterized in that the steps of forming the second semiconductor passivation layer and the second doped semiconductor layer, the second additional passivation layer and the second additional doped layer include: sequentially forming a second initial passivation film and a second initial doped semiconductor film in the first opening and on the side of the isolation layer away from the semiconductor substrate layer; performing a second laser ablation process and a second cleaning process on part of the isolation layer and part of the second initial passivation film and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer, so that the second initial passivation film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional passivation layer, and the second initial doped semiconductor film on the side of the isolation layer away from the semiconductor substrate layer forms a second additional doped layer, and forming a second opening in the isolation layer; The second initial passivation film and the second initial doped semiconductor film in the first opening are subjected to a third laser ablation treatment and a third cleaning treatment in sequence at the junction of the first semiconductor passivation layer and the first doped semiconductor layer, so that the second initial passivation film in the first opening forms the second semiconductor passivation layer, and the second initial doped semiconductor film in the first opening forms the second doped semiconductor layer. The method for preparing a heterojunction back contact battery according to claim 5 is characterized in that the parameters of the second laser ablation process include: the laser used is ultraviolet light or green light laser, the pulse width of the laser used is picosecond or femtosecond, and the laser power is 30W to 50W; preferably, the wavelength of the laser used is 355nm or 532nm; Preferably, the parameters of the second cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds. The method for preparing a heterojunction back contact cell according to claim 5, characterized in that the parameters of the third laser ablation process include: the laser used is a green laser, the laser used is The pulse width is in the nanosecond range; preferably, the wavelength of the laser used is 532nm; Preferably, the parameters of the third cleaning treatment include: the cleaning solution used is an alkaline solution, the mass concentration of the alkaline solution is 3%-5%, the alkaline solution is a KOH solution or a NaOH solution, and the cleaning time is 100 seconds to 130 seconds; Alternatively, the parameters of the first cleaning treatment include: the cleaning solution used is a mixture of HF solution and HCl solution, the mass concentration of HF in the cleaning solution is 40% to 55%, the mass concentration of HCl in the cleaning solution is 30% to 40%, and the cleaning time is 100 seconds to 130 seconds. The method for preparing a heterojunction back-contact battery according to any one of claims 1 to 4 is characterized in that it also includes: performing a texturing treatment on the other side surface of the semiconductor substrate layer to form an anti-reflection texturing surface; forming a third semiconductor passivation layer on the reflective texturing surface; and forming an anti-reflection layer on the side surface of the third semiconductor passivation layer away from the semiconductor substrate layer. The method for preparing a heterojunction back-contact battery according to claim 8 is characterized in that the step of forming the first transparent conductive film and the second transparent conductive film includes: after performing a second cleaning treatment and before performing a third laser ablation treatment, forming a transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and a surface of the second initial doped semiconductor film facing away from the semiconductor substrate layer; in the step of performing the third laser ablation treatment, the third laser ablation treatment also removes the boundary area between the transparent conductive film in the first opening and the first semiconductor passivation layer and the first doped semiconductor layer, so that the transparent conductive film forms the first transparent conductive film and the second transparent conductive film. A heterojunction back contact battery, characterized by comprising: Semiconductor substrate layer; A first semiconductor passivation layer located on a surface of one side of the semiconductor substrate layer, and a first doped semiconductor layer located on a surface of the first semiconductor passivation layer facing away from the semiconductor substrate layer; a first opening, penetrating the first doped semiconductor layer and the first semiconductor passivation layer; a second semiconductor passivation layer and a second doped semiconductor layer located in the first opening, the second doped semiconductor layer being located on a surface of the second semiconductor passivation layer facing away from the semiconductor substrate layer, the second doped semiconductor layer and the second semiconductor passivation layer being separated from the first semiconductor passivation layer and the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types and are located on the same side of the semiconductor substrate layer; A first transparent conductive film located on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer; A second transparent conductive film located on a surface of the second doped semiconductor layer on a side away from the semiconductor substrate layer; A first gate line located on a surface of the first transparent conductive film on a side away from the semiconductor substrate layer; A second gate line is located on a surface of the second transparent conductive film on a side away from the semiconductor substrate layer.