WO2025024613A1 - Methods and systems for generation and execution of brain circuit simulators - Google Patents

Abstract

A system for generation and execution of brain circuit simulators includes at least one modular, hierarchical design comprising a plurality of micro-circuits. The system includes a neural control circuit simulator executing a simulation of the at least one design. The system includes a user interface comprising at least one interface element for manipulating output of the neural control circuit simulator. A method includes receiving, by a neural control circuit simulator, an identification of at least one modular, hierarchical design comprising a plurality of micro-circuits, the at least one modular, hierarchical design generated by a first user. The neural control circuit simulator executes a first simulation of the at least one design, using a first data set as simulation input. The neural control circuit simulator receives a second data set and executes a second simulation of the at least one modular, hierarchical design, using the second data set as simulation input.

Description

PATENT APPLICATION METHODS AND SYSTEMS FOR GENERATION AND EXECUTION OF BRAIN CIRCUIT SIMULATORS BACKGROUND The disclosure relates to methods for generating and executing brain circuit simulations. More particularly, the methods and systems described herein relate to functionality for generating modular, hierarchical circuits and executing simulations of the modular, hierarchical circuits. Conventionally, models of brain circuits are trained on a data set and are incompatible with other data sets. Conventionally, systems for generating such brain circuit models lack functionality allowing validation of a model (e.g., via execution of data sets other that the initial training data set) by users other than the users that generated the model. That is, typical systems lack platforms allowing users to access, validate, or improve upon models generated by other users. Therefore, there is a need for technology for generating brain circuit simulations and for technology allowing for distributed access to, and modification of, such brain circuits by a plurality of users. BRIEF SUMMARY In one aspect, a control circuit system to generate a brain circuit simulation includes at least one modular, hierarchical design comprising a plurality of micro- circuits. The control circuit system includes a neural control circuit simulator executing a simulation of the at least one modular, hierarchical design. The control circuit system includes a user interface comprising at least one interface element for manipulating an output of the neural control circuit simulator. In another aspect, a system for distributed access to modular, hierarchical design includes a first user interface comprising at least one interface element for generating, by a first user, at least one modular, hierarchical design comprising a plurality of micro-circuits. The system includes a neural control circuit simulator executing a simulation of the at least one modular, hierarchical design. The system 1 Attorney Docket No.: SSB.1001PC includes a second user interface comprising at least one interface element for accessing, by a second user, the at least one modular, hierarchical design. In still another aspect, a method for distributed access to modular, hierarchical design includes receiving, by a neural control circuit simulator executing on a computing device, from a first user interface, an identification of at least one modular, hierarchical design comprising a plurality of micro-circuits, the at least one modular, hierarchical design generated by a first user. The method includes receiving, by the neural control circuit simulator, from the first user interface, a first data set. The method includes executing, by the neural control circuit simulator, a first simulation of the at least one modular, hierarchical design, using the first data set as input to the simulation. The method includes providing, by a second user interface, to a second user, access to the at least one modular, hierarchical design. The method includes receiving, by the neural control circuit simulator, from the second user interface, a second data set. The method includes executing, by the neural control circuit simulator, a second simulation of the at least one modular, hierarchical design, using the second data set as input to the simulation. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, aspects, features, and advantages of the disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which: FIG. 1A is a block diagram depicting an embodiment of a control circuit system to generate a brain circuit simulation; FIG.1B is a block diagram depicting an embodiment of a micro-circuit design modeling brain function at a variety of scales; FIG. 1C is a block diagram depicting an embodiment of a user interface engine generates interfaces for interacting with micro-circuit generators and with micro-circuit simulators; FIG. 1D is a block diagram depicting one embodiment of a user interface generated by the user interface engine 107; 2 Attorney Docket No.: SSB.1001PC FIG. 1E is a block diagram depicting an embodiment of interface elements generated by a user interface engine; FIG.1F is a block diagram depicting an embodiment of a micro-circuit design including a plurality of micro-circuits; FIG. 2 is a flow diagram depicting an embodiment of a method for distributed access to modular, hierarchical design; and FIGs.3A-3C are block diagrams depicting embodiments of computers useful in connection with the methods and systems described herein. DETAILED DESCRIPTION In some embodiments, the systems and methods described herein are configured for execution of computational neuroscience applications, including basic and clinical (e.g., neurology, psychiatry) applications. The systems and methods described herein may include control circuit system identification and brain circuit simulations, bridging scales from spiking neurons to fMRI-derived circuits. The systems and methods described herein may include execution of parameter-fitting models. The systems and methods described herein may include functionality for processing neuroimaging data. The systems and methods described herein may include functionality for reinforcement learning. The systems and methods described herein may include functionality for modeling interactions between the brain and other physiological systems. The systems and methods described herein may include functionality for experimental optimization. The systems and methods described herein may execute one or more scientific machine learning systems. The systems and methods described herein may be configured to provide a comprehensive platform for computational neuroscience and its applications to psychiatric and neurological disorders. Referring now to FIG. 1A, a block diagram depicts one embodiment of a control circuit system to generate a brain circuit simulation. In brief overview, the system 100 includes a computing device 106, a micro-circuit design 103, a neural control circuit simulator 105, a user interface engine 107, and a database 120. The computing device 106 may be a modified type or form of computing device (as described in greater detail below in connection with FIGs. 3A-3C) that has been 3 Attorney Docket No.: SSB.1001PC modified to execute instructions for providing the functionality described herein; these modifications result in a new type of computing device that provides a technical solution to problems rooted in computer technology, such as computer modeling and simulation of brain circuits and providing distributed access to a comprehensive platform for executing computational neuroscience applications, including the modeling of brain circuits and execution of such simulations. The micro-circuit design 103 may be provided as a software component. The micro-circuit design 103 may be provided as a hardware component. The computing device 106 may execute the functionality for generating the micro- circuit design 103. The computing device 106 may execute the functionality for modifying the micro-circuit design 103. The micro-circuit design 103 may be a modular, hierarchical design comprising a plurality of micro-circuits. The system 100 may include a library storing (e.g., on the database 120) the plurality of micro-circuits. The micro-circuits may be referred to as modular computational building blocks. The micro-circuits may be referred to as “blox”. The micro-circuits may be in the form of systems of symbolic dynamic differential equations that can be combined to describe large-scale brain dynamics and which may then be provided as input to the neural control circuit simulator 105 which may execute to generate a simulation of the brain functionality represented by the micro- circuits. The micro-circuits may function as computational primitives. By way of example, and without limitation, micro-circuits may be used to model and validate methods for quantifying regulation of fMRI-derived control circuits (for example, and again without limitation, validation of methods for quantifying regulation against macaque electrophysiology data). As another example, and without limitation, multi-scale multi-model circuits permit neuroscientists to run simulations of either hypothesis-driven or data-driven neural circuit architectures and to estimate behavior of those architectures under different conditions, as well as to model trajectories over time. The system 100 may include an application (which may be referred to as a modeling toolkit or, in FIG. 1C, the micro-circuit design generator 109) providing functionality for describing dynamical behavior of a micro-circuit as symbolic (ordinary/stochastic/delay) differential equations. Libraries of modular micro- 4 Attorney Docket No.: SSB.1001PC circuits may include individual neurons (e.g., Hodgkin-Huxley, Integrate-and-Fire, Quadratic-Integrate-and-Fire, Leaky- Integrate-and-Fire), neural mass models (e.g., Jansen-Rit, Wilson-Cowan, Lauter-Breakspear, Next- Generation, microcanonical circuits) and biomimetically constrained control circuit elements (BCPs). Benchmarks show that the increase in simulation speed resulting from execution of the methods and systems described herein often exceeds a factor of 100 as compared to neural mass model implementation by the Virtual Brain (python) and similar packages in MATLAB. For parameter fitting of brain circuit dynamical models, the system 100 may execute an optimization application to minimize the cost-function. The system 100 may execute an application (not shown) to perform probabilistic modeling, including Hamilton-Monte-Carlo sampling and Automated Differentiation Variational Inference; this application may be part of the neural control circuit simulator 105 or a separate application. The micro-circuits may therefore be modular components that may be assembled to create larger macro-circuits which are provided to the neural control circuit simulator 105 for execution. By way of example, a user interface may display a visual representation of a data structure (the micro-circuit) that itself represents a mechanism in the brain (e.g., where the functionality enabled by the data structure has constraints placed upon it that mimics constraints in brain processing, such that the data structure describes and may be used to execute a simulation of the brain functionality). Continuing with this example, the user interface may include functionality allowing for the establishment of connections between micro-circuits in order to create larger circuits that mimic more complex brain function. Therefore, the micro-circuits may also be or include biomimetically constrained control circuit elements. The micro-circuits may be or include biomimetic computational primitives (BCPs). Such BCPs may be the smallest unit in the system 100 capable of eliciting a specific functionality process in the brain (e.g., a “winner takes all” as a biomimetic mechanism to elicit an effective neural filter. The micro-circuits may include at least one simulated neuron. The micro- circuits may include at least one neural mass model. The micro-circuits may include a plurality of spiking neurons. The micro-circuits may include a plurality 5 Attorney Docket No.: SSB.1001PC of fMRI-derived circuits. The micro-circuits may include a micro-circuit generated by execution of at least one machine learning model (e.g., via automated circuit discovery mechanisms, including without limitation scientific machine learning techniques such as Sindy and Universal Differential Equations). Referring ahead to FIG. 1B, a micro-circuit design 103 may model brain function at one or more levels. By way of example, a micro-circuit design 103 may model one or more ion channels and such micro-circuits may be combined with other micro-circuits to model brain function at the level of neurons, which may then be combined to model brain function at the level of neural masses and those may be combined to model brain function at the level of brain regions. Referring back to FIG.1A, once a model is built from a plurality of the micro- circuits, the model can be simulated. The model may be simulated efficiently and fit to electrophysiological and neuroimaging data. The simulation may be a simulation of a plurality of spiking neurons. The simulation may be a simulation of a plurality of fMRI-derived circuits. The simulation may be a simulation of a brain- based dynamical disease process. The simulation may be a simulation of an application of a deep brain simulation process. The simulation may include a simulation of at least one component associated with an output of a machine learning model. The simulation may include simulated stimuli; for example, a simulation may have the ability to simulate experimental stimuli received as an input to a micro-circuit or combination of micro-circuits. The simulation may include the ability to introduce other inputs to the micro-circuits. Output from executing such simulations may include, without limitation, clinical signs, symptoms, and behaviors. Executing the simulations may include execution of functionality for parameter-fitting to experimental data at all scales, Hebbian and reinforcement learning, integration with mechanism-specific spatial heterogeneity within the brain, quantification of degree of optimal control or dysregulation within neural control circuits (e.g., control error), interactions between the brain and other physiological systems, experimental optimization, and scientific machine learning for automated circuit discovery (including BCPs) at all scales. 6 Attorney Docket No.: SSB.1001PC The neural control circuit simulator 105 may be provided as a software component. The neural control circuit simulator 105 may be provided as a hardware component. The computing device 106 may execute the neural control circuit simulator 105. The neural control circuit simulator 105 may be a neural control circuit simulator executing a simulation of the at least one modular, hierarchical design. The neural control circuit simulator 105 may generate an output from the simulation, the output including a quantification of a dysregulation of at least one neural control circuit. The system 100 includes a user interface 107 designed to be intuitive to users such as neuroscientists and clinicians while allowing even non-computational users to build models that automatically generate high-performance systems of numerical ordinary/stochastic/delay differential equations from which one can run simulations with parameters fit to experimental data. The user interface engine 107 may be provided as a software component. The user interface engine 107 may be provided as a hardware component. The computing device 106 may execute the user interface engine 107. The user interface engine 107 may include at least one interface element for manipulating an output of the neural control circuit simulator. The user interface engine 107 may execute functionality for combining a subset of the plurality of the micro-circuits to form a macro-circuit. The user interface engine 107 may include functionality for executing a plurality of simulations. The user interface engine 107 may include functionality for comparing outputs generated by the execution of each of the plurality of simulations. Referring ahead to FIG. 1C, in one embodiment, the system 100 includes a micro-circuit design generator 109 and the user interface engine 107 includes a micro-circuit design generator interface 111 and a micro-circuit design access interface 113. The user interface engine 107 generates user interfaces for interacting with system functionality for generating and accessing circuit designs and for executing simulations of such circuit designs. The user interface engine 107 may generate a first user interface 111 comprising at least one interface element for interacting with the micro-circuit design generator 109 to generate at least one modular, hierarchical design comprising a plurality of micro-circuits. The user interface 107 may include a micro-circuit design access interface 113. The micro- 7 Attorney Docket No.: SSB.1001PC circuit design access interface 113 may be a second user interface comprising at least one interface element for accessing, by a second user, the at least one modular, hierarchical design and interact with the system 100 (e.g., the neural control circuit simulator 105). The system 100 may further include one or more computers 102 from which users may access the computing device 106 via at least one computer network. The neural control circuit simulator 105 (which, as shown in FIG.1A, may be in communication with the user interface engine 107) may receive, from the micro- circuit design access interface 113, data for validating a simulation of the micro- circuit design; the neural control circuit simulator 105 may receive such data from a user other than the user that generated the at least one modular, hierarchical design generated via the first micro-circuit design generator 109. Referring ahead to FIG. 1D, a block diagram depicts one embodiment of a user interface generated by the user interface engine 107. As depicted in FIG. 1D, the generated user interface may depict user interface elements for interacting with a canvas, for setting or modifying at least one parameter choice, and for viewing simulation results panels. FIG. 1D depicts a non-limiting example of the micro- circuit design generator interface 109 alongside the micro-circuit design access interface 113. Referring ahead to FIG.1E, a block diagram depicts another embodiment of interface elements generated by the user interface engine 107. As depicted in FIG. 1E, the user interface engine 107 may be in communication with the micro-circuit design generator 109, which allows users to define and modify the micro-circuits. In the example shown in FIG. 1E, the user interface engine 107 generates a user interface element 111 for using the micro-circuit design generator 109 to define neural mass models and generates a second user interface element 113 for building one or more circuits from the neural mass models. Referring ahead to FIG. 1F, a block diagram depicts an embodiment of a micro-circuit design including a plurality of micro-circuits. Referring back to FIG. 1A, the computing device 106 may include or be in communication with the database 120. The database 120 may store data related to the modular, hierarchical designs. The database 120 may store data related to the 8 Attorney Docket No.: SSB.1001PC micro-circuits The database 120 may be an ODBC-compliant database. For example, the database 120 may be provided as an ORACLE database, manufactured by Oracle Corporation of Redwood Shores, CA. In other embodiments, the database 120 can be a Microsoft ACCESS database or a Microsoft SQL server database, manufactured by Microsoft Corporation of Redmond, WA. In other embodiments, the database 120 can be a SQLite database distributed by Hwaci of Charlotte, NC, or a PostgreSQL database distributed by The PostgreSQL Global Development Group. In still other embodiments, the database 120 may be a custom-designed database based on an open source database, such as the MYSQL family of freely available database products distributed by Oracle Corporation of Redwood City, CA. In other embodiments, examples of databases include, without limitation, structured storage (e.g., NoSQL-type databases and BigTable databases), HBase databases distributed by The Apache Software Foundation of Forest Hill, MD, MongoDB databases distributed by 10Gen, Inc., of New York, NY, an AWS DynamoDB distributed by Amazon Web Services and Cassandra databases distributed by The Apache Software Foundation of Forest Hill, MD. In further embodiments, the database 120 may be any form or type of database. Although, for ease of discussion, the micro-circuit design 103, the neural control circuit simulator 105, the user interface engine 107, and the database 120 are described in FIG.1A as separate modules, it should be understood that this does not restrict the architecture to a particular implementation. For instance, these components may be encompassed by a single circuit or software function or, alternatively, distributed across a plurality of computing devices. Therefore, the system 100 may include a platform for multiple users to interact with, execute, and modify models. As will be understood by those of skill in the art, conventional tools do not typically allow users to access or modify models generated by other users. In contrast, the methods and systems described herein provide such access to multiple users. In one embodiment, the methods and systems described herein include a software platform configured for collaborative computational neuroscience, configurable for modeling of regulatory dynamics of control circuits (as adapted from control theory), including multi-scale biophysical modeling. Models may be 9 Attorney Docket No.: SSB.1001PC derived from, as well as tested against, independent estimation-validation, spiking- neuron, and local field potential data (e.g., from a macaque), as well as intracranial electrophysiology, M/EEG, and fMRI data (e.g., from humans). The neural control circuit structure described herein enables, amongst other things, simulation of brain-based dynamical disease processes. This may have clinical implications because while psychiatric disorders are almost universally considered to reflect “dysregulation of neural circuits,” standard ways of interpreting data within the neuroscience and neuroimaging fields (e.g., activation, connectivity) cannot measure control processes or their dysregulation. The micro-circuits described herein may be configured to quantify dysregulation of neural control circuits. As such, these micro-circuits can provide a new class of biomarkers, providing an objective metric for the severity of an individual’s brain-based disorder as well as a measure of its treatment’s success. Referring now to FIG. 2, in brief overview, a block diagram depicts one embodiment of a method 200 for distributed access to modular, hierarchical designs. The method 200 includes receiving, by a neural control circuit simulator executing on a computing device, from a first user interface, an identification of at least one modular, hierarchical design comprising a plurality of micro-circuits, the at least one modular, hierarchical design generated by a first user (202). The method 200 includes receiving, by the neural control circuit simulator, from the first user interface, a first data set (204). The method 200 includes executing, by the neural control circuit simulator, a first simulation of the at least one modular, hierarchical design, using the first data set as input to the simulation (206). The method 200 includes providing, by a second user interface, to a second user, access to the at least one modular, hierarchical design (208). The method 200 includes receiving, by the neural control circuit simulator, from the second user interface, a second data set (210). The method 200 includes executing, by the neural control circuit simulator, a second simulation of the at least one modular, hierarchical design, using the second data set as input to the simulation (212). Embodiments of the methods and systems described herein are capable of providing both modeling and simulation of neural control circuits, across a plurality of scales, as well as the dysregulation of those circuits. Once a model is built, as 10 Attorney Docket No.: SSB.1001PC described above, the model may be simulated efficiently and fit to electrophysiological and neuroimaging data. Moreover, the circuit behavior of multiple model variants can be compared in parallel between competing hypotheses, establishing the set of models consistent with data. Scientifically, the ability to consider the entire search space at once radically extends discovery beyond individual hypothesis testing, reducing confirmation bias, and forms the foundation for experimental design optimization processes described below. Clinically, the ability to run simulations to determine how different mechanistic parameters affect the system, using individual-specific values for those parameters, forms the foundation for drug discovery processes and personalized clinical treatment processes described herein. therefore, in some embodiments, execution of the methods and systems described herein enables innovative approaches to the technical problems involved in providing collaborative modeling platforms and platforms for the generation and execution of simulations of multi-scale brain circuits. Referring now to FIG. 2, in greater detail and in connection with FIGs. 1A- 1B, the method 200 includes receiving, by a neural control circuit simulator executing on a computing device, from a first user interface, an identification of at least one modular, hierarchical design comprising a plurality of micro-circuits, the at least one modular, hierarchical design generated by a first user (202). The method 200 includes receiving, by the neural control circuit simulator, from the first user interface, a first data set (204). The method 200 includes executing, by the neural control circuit simulator, a first simulation of the at least one modular, hierarchical design, using the first data set as input to the simulation (206). Executing the first simulation may include parallelizing, over at least one parameter, execution of the first simulation. The method 200 includes providing, by a second user interface, to a second user, access to the at least one modular, hierarchical design (208). The method 200 includes receiving, by the neural control circuit simulator, from the second user interface, a second data set (210). As will be understood by those of skill in the art, models must be validated but conventional tools do not 11 Attorney Docket No.: SSB.1001PC allow for crowd-sourcing of neuroscience models. By specifying a common “grammar” of micro-circuits for use in modeling a variety of brain functions, and by providing the interface for accessing and modifying the micro-circuits by a variety of users (whether or not they are affiliated with the user originally modeling a particular micro-circuit), the methods and systems described herein provide functionality for independent testing of circuits and for community-wide curation of libraries of integrated models, experimentally validated across different species, populations, and applications. Therefore, execution of a method for receiving data set from a user other than a user that generated one or more micro-circuits and of the underlying system for doing so results in an improved technical solution to a technical problem of how to receive data sets for use in validation processes from users outside of the original user. The method 200 includes executing, by the neural control circuit simulator, a second simulation of the at least one modular, hierarchical design, using the second data set as input to the simulation (212). Executing the second simulation may include parallelizing, over at least one parameter, execution of the second simulation. The method 200 may include executing a comparison between different models of the same circuits to highlight the spatial, temporal, and/or output measures by which the models overlap and/or diverge most significantly, allowing for identification of which model component experiments to target in subsequent experimentation. Similarly, different models of the same circuit may be compared with respect to trajectories to identify experimental parameters (e.g., timing and location of measurements) that maximize their divergence. Model components may be graphically represented with respect to a degree of validation (or consensus), e.g., a “confidence interval” for each part of a circuit. Model components that are inferred without direct empirical validation may be labeled as such to indicate an objective metric by which one may quantify the scientific impact of new experiments. The method 200 may include determining, by an analysis engine (not shown), whether the execution of the second simulation validates a level of accuracy of the at least one modular, hierarchical design. The method 200 may include providing, by the second user interface 111, to the first user, the determination 12 Attorney Docket No.: SSB.1001PC generated by the analysis engine. The method 200 may include providing, by the second user interface 111, to the second user, the determination generated by the analysis engine. The method 200 may include determining, by the analysis engine, whether the execution of the second simulation replicates an outcome generated during execution of the first simulation. As researchers generate new micro-circuits and/or combinations of micro- circuits, execution of the methods and systems described herein results in improved systems for independent testing of those circuits and combinations of circuits by other users’ experiments, allowing for community-wide curation of libraries of integrated models, experimentally validated across different species, populations, and applications. As an example, and without limitation, the methods and systems described herein may allow for development of models for cortico-circuit that may receive as input information about a medication and simulate the impact of the medication on the cortico-circuit modeled. As another example, the methods and systems described herein may allow for generation and simulation of brain circuit models where the output of the simulation represents the impact of a medical device, such as a deep brain simulation device – allowing users to determine the impact of implementing the medical device in different areas of the brain and/or the effectiveness for different functions of the medical device. Providing such input prior to a surgery, for example, may result in improved patient outcomes. Embodiments of the system and method described herein also provide modeling and simulations of neuroimaging-derived neural control circuits for patient neuro-diagnostics or decision-making regarding treatment strategy. The micro-circuits described herein are configurable to permit researchers and clinicians to run simulations of either hypothesis or data-driven neural circuit architectures (using Scientific Machine Learning (SciML)-driven approaches for automated discovery of dynamical systems, parameter estimation, and model reduction), to estimate their behavior under different conditions and their trajectories, including clinical trajectories, over time. The latter can provide predictive capabilities for personalized medicine for brain-based disorders, by allowing for clinicians to simulate how a particular patient’s brain (made possible by using individual-specific clinically derived parameters within the micro-circuit 13 Attorney Docket No.: SSB.1001PC models) responds to different treatment options. Applications to psychiatric and neurological disorders may be designed to derive clinical-scale emergent properties from cellular-scale mechanisms and to stimulate clinical trajectories using individual-specific parameters; therefore, in some embodiments, execution of the methods and systems described herein may result in improved approaches for developing personalized medicine. Embodiments of the system and method described herein may include functionality to execute neural circuit simulations to determine how different mechanisms of drug action affect neural circuits and clinical trajectories. As indicated above, conventional models are proprietary to a particular group of users and are not typically made available via a distributed platform to other users, with the resulting drawback that users outside of the group of users cannot validate the functioning of the model or compare the outcome of simulating a model on different data sets. Therefore, by executing the methods and systems described herein, in some embodiments, a technical platform for multi-party access to models may result in improved technology for generating and simulating the functioning of micro-circuits that model brain functionality. Technology for receiving data to use as input to brain circuit models during simulations may result in improved micro-circuits that perform more effectively across populations and/or species. In some embodiments, the method 200 further includes generating an indication of a level of participation of a user of the second interface. By way of example, the method 200 may include generating a participation score for each user of the system and increasing a score when the user participates in a simulation. The score may reflect a number of times a user has contributed data sets and run simulations on other users’ models. The score may reflect a number of times a user has generated a micro-circuit that was used by other users in generating combinations of micro-circuits. The score may be a numeric, alphabetic, or alphanumeric score quantifying the level of participation. The score may be a range of numbers or letters. The score may be a description instead of a specific quantification of the participation level. The score may reflect a level of reputation of the user across one or more communities of users. The score may be a citable 14 Attorney Docket No.: SSB.1001PC score that the user can reference in describing professional credentials. By providing a score for participating in use of another user’s model, the system may provide an incentive for collaboration across groups of users and improving the likelihood of users participating in the crowd-sourced platform described above to leverage expertise across groups of users. In some embodiments, the system 100 includes non-transitory, computer- readable medium comprising computer program instructions tangibly stored on the non-transitory computer-readable medium, wherein the instructions are executable by at least one processor to perform each of the steps described above in connection with FIG.2. It should be understood that the systems described above may provide multiple ones of any or each of those components and these components may be provided on either a standalone machine or, in some embodiments, on multiple machines in a distributed system. The phrases ‘in one embodiment,’ ‘in another embodiment,’ and the like, generally mean that the particular feature, structure, step, or characteristic following the phrase is included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure. Such phrases may, but do not necessarily, refer to the same embodiment. However, the scope of protection is defined by the appended claims; the embodiments mentioned herein provide examples. The terms "A or B", "at least one of A or/and B", “at least one of A and B”, “at least one of A or B”, or "one or more of A or/and B" used in the various embodiments of the present disclosure include any and all combinations of words enumerated with it. For example, "A or B", "at least one of A and B" or "at least one of A or B" may mean (1) including at least one A, (2) including at least one B, (3) including either A or B, or (4) including both at least one A and at least one B. Any step or act disclosed herein as being performed, or capable of being performed, by a computer or other machine, may be performed automatically by a computer or other machine, whether or not explicitly disclosed as such herein. A step or act that is performed automatically is performed solely by a computer or other machine, without human intervention. A step or act that is performed automatically may, for example, operate solely on inputs received from a computer 15 Attorney Docket No.: SSB.1001PC or other machine, and not from a human. A step or act that is performed automatically may, for example, be initiated by a signal received from a computer or other machine, and not from a human. A step or act that is performed automatically may, for example, provide output to a computer or other machine, and not to a human. Although terms such as “optimize” and “optimal” may be used herein, in practice, embodiments of the present invention may include methods which produce outputs that are not optimal, or which are not known to be optimal, but which nevertheless are useful. For example, embodiments of the present invention may produce an output which approximates an optimal solution, within some degree of error. As a result, terms herein such as “optimize” and “optimal” should be understood to refer not only to processes which produce optimal outputs, but also processes which produce outputs that approximate an optimal solution, within some degree of error. The systems and methods described above may be implemented as a method, apparatus, or article of manufacture using programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The techniques described above may be implemented in one or more computer programs executing on a programmable computer including a processor, a storage medium readable by the processor (including, for example, volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Program code may be applied to input entered using the input device to perform the functions described and to generate output. The output may be provided to one or more output devices. Each computer program within the scope of the claims below may be implemented in any programming language, such as assembly language, machine language, a high-level procedural programming language, or an object-oriented programming language. The programming language may, for example, be LISP, PROLOG, PERL, C, C++, C#, JAVA, Python, Rust, Go, Julia or any compiled or interpreted programming language. Each such computer program may be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a 16 Attorney Docket No.: SSB.1001PC computer processor. Method steps may be performed by a computer processor executing a program tangibly embodied on a computer-readable medium to perform functions of the methods and systems described herein by operating on input and generating output. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, the processor receives instructions and data from a read-only memory and/or a random access memory. Storage devices suitable for tangibly embodying computer program instructions include, for example, all forms of computer-readable devices, firmware, programmable logic, hardware (e.g., integrated circuit chip; electronic devices; a computer-readable non-volatile storage unit; non-volatile memory, such as semiconductor memory devices, including EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto- optical disks; and CD-ROMs). Any of the foregoing may be supplemented by, or incorporated in, specially-designed ASICs (application-specific integrated circuits) or FPGAs (Field-Programmable Gate Arrays). A computer can generally also receive programs and data from a storage medium such as an internal disk (not shown) or a removable disk. These elements will also be found in a conventional desktop or workstation computer as well as other computers suitable for executing computer programs implementing the methods described herein, which may be used in conjunction with any digital print engine or marking engine, display monitor, or other raster output device capable of producing color or gray scale pixels on paper, film, display screen, or other output medium. A computer may also receive programs and data (including, for example, instructions for storage on non- transitory computer-readable media) from a second computer providing access to the programs via a network transmission line, wireless transmission media, signals propagating through space, radio waves, infrared signals, etc. Referring now to FIGs. 3A, 3B, and 3C, block diagrams depict additional detail regarding computing devices that may be modified to execute novel, non- obvious functionality for implementing the methods and systems described above. Referring now to FIG. 3A, an embodiment of a network environment is depicted. In brief overview, the network environment comprises one or more clients 302a-302n (also generally referred to as local machine(s) 302, client(s) 302, 17 Attorney Docket No.: SSB.1001PC client node(s) 302, client machine(s) 302, client computer(s) 302, client device(s) 302, computing device(s) 302, endpoint(s) 302, or endpoint node(s) 302) in communication with one or more remote machines 306a-306n (also generally referred to as server(s) 306 or computing device(s) 306) via one or more networks 304. Although FIG. 3A shows a network 304 between the clients 302 and the remote machines 306, the clients 302 and the remote machines 306 may be on the same network 304. The network 304 can be a local area network (LAN), such as a company Intranet, a metropolitan area network (MAN), or a wide area network (WAN), such as the Internet or the World Wide Web. In some embodiments, there are multiple networks 304 between the clients 302 and the remote machines 306. In one of these embodiments, a network 304’ (not shown) may be a private network and a network 304 may be a public network. In another of these embodiments, a network 304 may be a private network and a network 304’ a public network. In still another embodiment, networks 304 and 304’ may both be private networks. In yet another embodiment, networks 304 and 304’ may both be public networks. The network 304 may be any type and/or form of network and may include any of the following: a point to point network, a broadcast network, a wide area network, a local area network, a telecommunications network, a data communication network, a computer network, an ATM (Asynchronous Transfer Mode) network, a SONET (Synchronous Optical Network) network, an SDH (Synchronous Digital Hierarchy) network, a wireless network, a wireline network, an Ethernet, a virtual private network (VPN), a software-defined network (SDN), a network within the cloud such as AWS VPC (Virtual Private Cloud) network or Azure Virtual Network (VNet), and a RDMA (Remote Direct Memory Access) network. In some embodiments, the network 304 may comprise a wireless link, such as an infrared channel or satellite band. The topology of the network 304 may be a bus, star, or ring network topology. The network 304 may be of any such network topology as known to those ordinarily skilled in the art capable of supporting the operations described herein. The network may comprise mobile telephone networks utilizing any protocol or protocols used to communicate among mobile devices (including tables and handheld devices generally), including AMPS, 18 Attorney Docket No.: SSB.1001PC TDMA, CDMA, GSM, GPRS, UMTS, or LTE. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same types of data may be transmitted via different protocols. A client 302 and a remote machine 306 (referred to generally as computing devices 300 or as machines 300) can be any workstation, desktop computer, laptop or notebook computer, server, portable computer, mobile telephone, mobile smartphone, or other portable telecommunication device, media playing device, a gaming system, mobile computing device, or any other type and/or form of computing, telecommunications or media device that is capable of communicating on any type and form of network and that has sufficient processor power and memory capacity to perform the operations described herein. A client 302 may execute, operate or otherwise provide an application, which can be any type and/or form of software, program, or executable instructions, including, without limitation, any type and/or form of web browser, web-based client, client-server application, an ActiveX control, a JAVA applet, a webserver, a database, an HPC (high performance computing) application, a data processing application, or any other type and/or form of executable instructions capable of executing on client 302. In one embodiment, a computing device 306 provides functionality of a web server. The web server may be any type of web server, including web servers that are open-source web servers, web servers that execute proprietary software, and cloud-based web servers where a third party hosts the hardware executing the functionality of the web server. In some embodiments, a web server 306 comprises an open-source web server, such as the APACHE servers maintained by the Apache Software Foundation of Delaware. In other embodiments, the web server executes proprietary software, such as the INTERNET INFORMATION SERVICES products provided by Microsoft Corporation of Redmond, WA, the ORACLE IPLANET web server products provided by Oracle Corporation of Redwood Shores, CA, or the ORACLE WEBLOGIC products provided by Oracle Corporation of Redwood Shores, CA. In some embodiments, the system may include multiple, logically-grouped remote machines 306. In one of these embodiments, the logical group of remote 19 Attorney Docket No.: SSB.1001PC machines may be referred to as a server farm 338. In another of these embodiments, the server farm 338 may be administered as a single entity. As will be understood by those of skill in the art, in some embodiments, a computing device 300 may provide a virtualization environment. In such embodiments, the computing device 300 may include a hypervisor layer, a virtualization layer, and a hardware layer. The hypervisor layer includes a hypervisor that allocates and manages access to a number of physical resources in the hardware layer (e.g., the processor(s) and disk(s)) by at least one virtual machine executing in the virtualization layer. The virtualization layer includes at least one operating system and a plurality of virtual resources allocated to the at least one operating system. Virtual resources may include, without limitation, a plurality of virtual processors and virtual disks, as well as virtual resources such as virtual memory and virtual network interfaces. The plurality of virtual resources and the operating system may be referred to as a virtual machine. A hypervisor may provide virtual resources to an operating system in any manner that simulates the operating system having access to a physical device. A hypervisor may provide virtual resources to any number of guest operating systems. In some embodiments, a computing device executes one or more types of hypervisors. In these embodiments, hypervisors may be used to emulate virtual hardware, partition physical hardware, virtualize physical hardware, and execute virtual machines that provide access to computing environments. Hypervisors may include those manufactured by VMWare, Inc., of Palo Alto, California; the XEN hypervisor, an open source product whose development is overseen by the open source Xen.org community; the KVM hypervisor, an open source product whose development is overseen by the open source Linux community; HyperV, VirtualServer or virtual PC hypervisors provided by Microsoft, Amazon Nitro, Amazon Firecracker, or others. In some embodiments, a computing device executing a hypervisor that creates a virtual machine platform on which guest operating systems may execute is referred to as a host server. In some embodiments, a hypervisor executes within an operating system executing on a computing device. In one of these embodiments, a computing device executing an operating system and a hypervisor may be said to have a host operating system (the operating system executing on the computing 20 Attorney Docket No.: SSB.1001PC device), and a guest operating system (an operating system executing within a computing resource partition provided by the hypervisor). In other embodiments, a hypervisor interacts directly with hardware on a computing device, instead of executing on a host operating system. In one of these embodiments, the hypervisor may be said to be executing on “bare metal,” referring to the hardware comprising the computing device. In some embodiments, the hypervisor controls processor scheduling and memory partitioning for a virtual machine executing on the computing device. In one of these embodiments, the hypervisor controls the execution of at least one virtual machine. In another of these embodiments, the hypervisor presents at least one virtual machine with an abstraction of at least one hardware resource provided by the computing device. In other embodiments, the hypervisor controls whether and how physical processor capabilities are presented to the virtual machine. In one embodiment, the guest operating system, in conjunction with the virtual machine on which it executes, forms a fully-virtualized virtual machine which is not aware that it is a virtual machine; such a machine may be referred to as a “Domain U HVM (Hardware Virtual Machine)”. In another embodiment, a fully-virtualized machine includes software emulating a Basic Input/Output System (BIOS) in order to execute an operating system within the fully-virtualized machine. In still another embodiment, a fully-virtualized machine may include a driver that provides functionality by communicating with the hypervisor; in such an embodiment, the driver is typically aware that it executes within a virtualized environment. In another embodiment, the guest operating system, in conjunction with the virtual machine on which it executes, forms a paravirtualized virtual machine, which is aware that it is a virtual machine; such a machine may be referred to as a “Domain U PV virtual machine”. In another embodiment, a paravirtualized machine includes additional drivers that a fully- virtualized machine does not include. FIGs.3B and 3C depict block diagrams of a computing device 400 useful for practicing an embodiment of the client 302 or a remote machine 306. As shown in FIGs.3B and 3C, each computing device 300 includes a central processing unit 321, and a main memory unit 322. As shown in FIG. 3B, a computing device 300 may include a storage device 328, an installation device 316, a network interface 318, an 21 Attorney Docket No.: SSB.1001PC I/O controller 323, display devices 324a-n, a keyboard 326, a pointing device 327, such as a mouse, and one or more other I/O devices 330a-n. The storage device 328 may include, without limitation, an operating system and software. As shown in FIG. 3C, each computing device 300 may also include additional optional elements, such as a memory port 303, a bridge 370, one or more input/output devices 330a-n (generally referred to using reference numeral 330), and a cache memory 340 in communication with the central processing unit 321. The central processing unit 321 is any logic circuitry that responds to and processes instructions fetched from the main memory unit 322. In many embodiments, the central processing unit 321 is provided by a microprocessor unit, such as: those manufactured by Intel Corporation of Mountain View, CA; those manufactured by Motorola Corporation of Schaumburg, IL; those manufactured by Transmeta Corporation of Santa Clara, CA; those manufactured by International Business Machines of White Plains, NY; or those manufactured by Advanced Micro Devices of Sunnyvale, CA. Other examples include RISC-V processors, SPARC processors, ARM processors, processors used to build UNIX/LINUX “white” boxes, and processors for mobile devices. The computing device 300 may be based on any of these processors, or any other processor capable of operating as described herein. Main memory unit 322 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the microprocessor 321. The main memory 322 may be based on any available memory chips capable of operating as described herein. In the embodiment shown in FIG. 3B, the processor 321 communicates with main memory 322 via a system bus 350. FIG.3C depicts an embodiment of a computing device 300 in which the processor communicates directly with main memory 322 via a memory port 303. FIG.3C also depicts an embodiment in which the main processor 321 communicates directly with cache memory 340 via a secondary bus, sometimes referred to as a backside bus. In other embodiments, the main processor 321 communicates with cache memory 340 using the system bus 350. In the embodiment shown in FIG.3B, the processor 321 communicates with various I/O devices 330 via a local system bus 350. Various buses may be used to connect the central processing unit 321 to any of the I/O devices 330, including a 22 Attorney Docket No.: SSB.1001PC VESA VL bus, an ISA bus, an EISA bus, a MicroChannel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI-Express bus, or a NuBus. For embodiments in which the I/O device is a video display device 324, the processor 321 may use an Advanced Graphics Port (AGP) to communicate with the display device 324. FIG.3C depicts an embodiment of a computing device 300 in which the main processor 321 also communicates directly with an I/O device 330b via, for example, HYPERTRANSPORT, RAPIDIO, or INFINIBAND communications technology. One or more of a wide variety of I/O devices 330a-n may be present in or connected to the computing device 300, each of which may be of the same or different type and/or form. Input devices include keyboards, mice, trackpads, trackballs, microphones, scanners, cameras, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, 3D printers, and dye-sublimation printers. The I/O devices may be controlled by an I/O controller 323 as shown in FIG. 3B. Furthermore, an I/O device may also provide storage and/or an installation medium 316 for the computing device 300. In some embodiments, the computing device 300 may provide USB connections (not shown) to receive handheld USB storage devices such as the USB Flash Drive line of devices manufactured by Twintech Industry, Inc. of Los Alamitos, CA. Referring still to FIG. 3B, the computing device 400 may support any suitable installation device 316, such as hardware for receiving and interacting with removable storage; e.g., disk drives of any type, CD drives of any type, DVD drives, tape drives of various formats, USB devices, external hard drives, or any other device suitable for installing software and programs. In some embodiments, the computing device 300 may provide functionality for installing software over a network 304. The computing device 300 may further comprise a storage device, such as one or more hard disk drives or redundant arrays of independent disks, for storing an operating system and other software. Alternatively, the computing device 300 may rely on memory chips for storage instead of hard disks. Furthermore, the computing device 300 may include a network interface 318 to interface to the network 304 through a variety of connections including, but not limited to, standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET, RDMA), broadband connections (e.g., ISDN, Frame Relay, 23 Attorney Docket No.: SSB.1001PC ATM, Gigabit Ethernet, Ethernet-over-SONET), wireless connections, virtual private network (VPN) connections, or some combination of any or all of the above. Connections can be established using a variety of communication protocols (e.g., TCP/IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, 802.15.4, Bluetooth, ZIGBEE, CDMA, GSM, WiMax, and direct asynchronous connections). In one embodiment, the computing device 300 communicates with other computing devices 300’ via any type and/or form of gateway or tunneling protocol such as GRE, VXLAN, IPIP, SIT, ip6tnl, VTI and VTI6, IP6GRE, FOU, GUE, GENEVE, ERSPAN, Secure Socket Layer (SSL) or Transport Layer Security (TLS). The network interface 318 may comprise a built- in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other device suitable for interfacing the computing device 300 to any type of network capable of communication and performing the operations described herein. In further embodiments, an I/O device 330 may be a bridge between the system bus 350 and an external communication bus, such as a USB bus, an Apple Desktop Bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a HIPPI bus, a Super HIPPI bus, a Serial Plus bus, a SCI/LAMP bus, a Fibre Channel bus, or a Serial Attached small computer system interface bus. A computing device 300 of the sort depicted in FIGs. 3B and 3C typically operates under the control of operating systems, which control scheduling of tasks and access to system resources. The computing device 300 can be running any operating system such as any of the versions of the MICROSOFT WINDOWS operating systems, the different releases of the UNIX and LINUX operating systems, any version of the MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating systems for mobile computing devices, or any other operating system capable of running on the 24 Attorney Docket No.: SSB.1001PC computing device and performing the operations described herein. Typical operating systems include, but are not limited to: WINDOWS 7, WINDOWS 8, WINDOWS VISTA, WINDOWS 10, and WINDOWS 11 all of which are manufactured by Microsoft Corporation of Redmond, WA; MAC OS manufactured by Apple Inc. of Cupertino, CA; OS/2 manufactured by International Business Machines of Armonk, NY; Red Hat Enterprise Linux, a Linux-variant operating system distributed by Red Hat, Inc., of Raleigh, NC; Ubuntu, a freely-available operating system distributed by Canonical Ltd. of London, England; CentOS, a freely-available operating system distributed by the centos.org community; SUSE Linux, a freely-available operating system distributed by SUSE, or any type and/or form of a Unix operating system, among others. Having described certain embodiments of methods and systems for generating and executing brain circuit simulations, it will be apparent to one of skill in the art that other embodiments incorporating the concepts of the disclosure may be used. 25 Attorney Docket No.: SSB.1001PC

Claims

CLAIMS What is claimed is: 1. A control circuit system to generate a brain circuit simulation comprising: at least one modular, hierarchical design comprising a plurality of micro-circuits; a neural control circuit simulator executing a simulation of the at least one modular, hierarchical design; and a user interface comprising at least one interface element for manipulating an output of the neural control circuit simulator.

2. The control circuit system of claim 1 wherein the plurality of micro-circuits further comprise at least one biomimetically constrained control circuit element.

3. The control circuit system of claim 1 wherein the plurality of micro-circuits further comprise at least one simulated neuron.

4. The control circuit system of claim 1 wherein the plurality of micro-circuits further comprise at least one neural mass model.

5. The control circuit system of claim 1 wherein the simulation is a simulation of a plurality of spiking neurons. 1 Attorney Docket No.: SSB.1001PC

6. The control circuit system of claim 1 wherein the simulation is a simulation of a plurality of fMRI-derived circuits.

7. The control circuit system of claim 1 wherein the simulation is a simulation of a brain-based dynamical disease process.

8. The control circuit system of claim 1 wherein the simulation is a simulation of an application of a deep brain simulation process.

9. The control circuit system of claim 1 wherein the neural control circuit simulator generates an output from the simulation, the output including a quantification of a dysregulation of at least one neural control circuit.

10. The control circuit system of claim 1 further comprising a library including the plurality of micro-circuits.

11. The control circuit system of claim 1 wherein the user interface further comprises functionality for combining a subset of the plurality of the micro- circuits to form a macro-circuit.

12. The control circuit system of claim 1 wherein the user interface further comprises functionality for executing a plurality of simulations. 2 Attorney Docket No.: SSB.1001PC

13. The control circuit system of claim 9 wherein the user interface further comprises functionality for comparing outputs generated by the execution of each of the plurality of simulations.

14. The control circuit system of claim 1, wherein the simulation includes at least one component associated with an output of a machine learning model.

15. The control circuit system of claim 1, wherein at least one of the plurality of micro-circuits includes a micro-circuit generated by execution of at least one machine learning model.

16. A system for distributed access to modular, hierarchical design comprising: a first user interface comprising at least one interface element for generating, by a first user, at least one modular, hierarchical design comprising a plurality of micro-circuits; a neural control circuit simulator executing a simulation of the at least one modular, hierarchical design; and a second user interface comprising at least one interface element for accessing, by a second user, the at least one modular, hierarchical design. 3 Attorney Docket No.: SSB.1001PC

17. The system of claim 16, wherein the neural control circuit simulator further comprises functionality for receiving, from the second user interface, data for validating the simulation.

18. The system of claim 16 further comprising a computing device providing access to the first user interface via at least one network.

19. A method for distributed access to modular, hierarchical design, the method comprising: receiving, by a neural control circuit simulator executing on a computing device, from a first user interface, an identification of at least one modular, hierarchical design comprising a plurality of micro-circuits, the at least one modular, hierarchical design generated by a first user; receiving, by the neural control circuit simulator, from the first user interface, a first data set; executing, by the neural control circuit simulator, a first simulation of the at least one modular, hierarchical design, using the first data set as input to the simulation; providing, by a second user interface, to a second user, access to the at least one modular, hierarchical design; receiving, by the neural control circuit simulator, from the second user interface, a second data set; and 4 Attorney Docket No.: SSB.1001PC executing, by the neural control circuit simulator, a second simulation of the at least one modular, hierarchical design, using the second data set as input to the simulation.

20. The method of claim 19 further comprising determining, by an analysis engine, whether the execution of the second simulation validates a level of accuracy of the at least one modular, hierarchical design.

21. The method of claim 19 further comprising providing, by the second user interface, to the first user, the determination generated by the analysis engine.

22. The method of claim 21 further comprising providing, by the second user interface, to the second user, the determination generated by the analysis engine.

23. The method of claim 19 further comprising determining, by an analysis engine, whether the execution of the second simulation replicates an outcome generated during execution of the first simulation.

24. The method of claim 19, wherein executing the first simulation further comprises parallelizing, over at least one parameter, execution of the first simulation. 5 Attorney Docket No.: SSB.1001PC

5. The method of claim 19, wherein executing the second simulation further comprises parallelizing, over at least one parameter, execution of the second simulation. 6 Attorney Docket No.: SSB.1001PC