WO2025024053A1 - Systems and method for smooth transitions in a buck-boost direct current-to-direct current (dc-dc) converter - Google Patents

Abstract

Systems and methods for smooth transitions in a buck-boost direct current-to-direct current (DC-DC) converter are disclosed. In one aspect, a state machine may be used to hold the DC-DC converter in a particular mode after transition between buck and boost modes until the converter has settled. Additional control circuitry may detect such a transition so as to assist the state machine in selecting an appropriate state. Still further, pulse widths may be managed by the control circuit to help avoid race conditions. Collectively, this approach smooths transitions for the DC-DC converter resulting in greater efficiency for the DC-DC converter.

Description

Ref. No. P231294-WO-UTL 1 SYSTEMS AND METHOD FOR SMOOTH TRANSITIONS IN A BUCK-BOOST DIRECT CURRENT-TO-DIRECT CURRENT (DC-DC) CONVERTER RELATED APPLICATION [0001] This application claims the benefit of U.S. Provisional Patent Application Serial Number 63/528,438, filed July 24, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety. BACKGROUND I. Field of the Disclosure [0002] The technology of the disclosure relates generally to direct current-to-direct current (DC-DC) converters and techniques for smoothing transitions between buck modes and boost modes. II. Background [0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to reduce power consumption. One way that power consumption has been reduced is to have supply voltages for power amplifiers closely track desired output powers through an average power tracking (APT) or envelope tracking (ET) circuit. Most such tracking circuits rely on a direct current-to-direct current (DC-DC) converter and typically a buck-boost DC-DC converter. When the DC-DC converter transitions from a buck mode to a boost mode or vice versa, there may be instances where the converter rattles between the two states before settling on a desired operation mode. This rattle creates inefficiencies, and these inefficiencies provide room for innovation. ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 2 SUMMARY [0004] Aspects disclosed in the detailed description include systems and methods for smooth transitions in a buck-boost direct current-to-direct current (DC-DC) converter. In particular, exemplary aspects of the present disclosure describe a state machine that may be used to hold the DC-DC converter in a particular mode after a transition between buck and boost modes (or vice versa) until the converter has settled. Additional control circuitry may detect such an upcoming transition to assist the state machine in selecting an appropriate state. Still further, pulse widths may be managed by the control circuit to help avoid race conditions. Collectively, this approach smooths transitions for the DC- DC converter resulting in greater efficiency for the DC-DC converter. [0005] In this regard, in one aspect, a power management integrated circuit (PMIC) is disclosed. The PMIC includes a DC-DC converter that includes a state machine configured to smooth transitions between buck and boost modes by holding the DC-DC converter in a transition state for a predetermined amount of time when transitioning from a first buck mode to a first boost mode. [0006] In another aspect, a mobile terminal is disclosed. The mobile terminal includes a transceiver comprising a PMIC. The PMIC includes a DC-DC converter that includes a state machine configured to smooth transitions between buck and boost modes by holding the DC-DC converter in a transition state for a predetermined amount of time when transitioning from a first buck mode to a first boost mode. [0007] In another aspect, a method for controlling power in a DC-DC converter is disclosed. The method includes passing a pulse from a comparator to a state machine and smoothing transitions between buck and boost modes by using a transition state in the state machine. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Figure 1A is a block diagram of a conventional direct current-to-direct current (DC-DC) converter with a pulse width modulator (PWM) control circuit; [0009] Figure 1B is a state machine diagram corresponding to the conventional DC- DC converter of Figure 1A; [0010] Figure 1C is a graph of voltage versus time for the DC-DC converter of Figure 1A when there is a buck to boost transition; ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 3 [0011] Figure 2 is a block diagram of a DC-DC converter with quasi-synchronous state machine control to assist in transitions according to exemplary aspects of the present disclosure; [0012] Figure 3 is a block diagram of a DC-DC converter with a reconfigurable state machine control based on operating mode to assist in transitions according to exemplary aspects of the present disclosure; [0013] Figure 4 is a block diagram of a DC-DC converter with an illegal state condition prevention and recovery circuit to assist in transitions according to exemplary aspects of the present disclosure; [0014] Figure 5A is a simplified state diagram for the DC-DC converter of the present disclosure showing an additional state to assist in transitions; [0015] Figure 5B is a more detailed state diagram showing multiple additional states used during transitions according to aspects of the present disclosure; [0016] Figure 6 is a block diagram of a DC-DC converter using a digital state machine that sets state transitions based on a clock edge or asynchronously to assist in transitions according to exemplary aspects of the present disclosure; [0017] Figure 7 is a block diagram of a DC-DC converter with a pulse width control circuit that enforces pulse width requirements to assist in transitions according to exemplary aspects of the present disclosure; [0018] Figure 8 is a block diagram of a circuit with two DC-DC converters with a state machine that controls synchronization to avoid concurrent draws on a supply voltage to avoid stress on the battery according to exemplary aspects of the present disclosure; [0019] Figure 9A illustrates how a latched comparator may be used to prevent transitions proximate to a clock edge; [0020] Figure 9B illustrates a comparator with a hysteresis circuit and pulse stretching circuit to prevent narrow pulses from being passed to the state machine; [0021] Figure 10 is a first signal diagram showing two options for the comparator forcing a specific high signal around an active clock edge to prevent transitions at the clock edge; [0022] Figure 11 is a signal diagram showing two options for the comparator forcing a specific low signal around an active clock edge to ensure a maximum duty cycle (e.g., for boost operation) at the clock edge; ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 4 [0023] Figure 12 is a signal diagram showing two options for delaying the comparator decision until after an exclusion window at the clock edge; and [0024] Figure 13 is a block diagram of a mobile terminal, which may include the DC_DC converter of the previous Figures according to the present disclosure. DETAILED DESCRIPTION [0025] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. [0026] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. [0027] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 5 contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present. [0028] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. [0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. [0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. [0031] Aspects disclosed in the detailed description include systems and methods for smooth transitions in a buck-boost direct current-to-direct current (DC-DC) converter. In particular, exemplary aspects of the present disclosure describe a state machine that may be used to hold the DC-DC converter in a particular mode after transition between buck and boost modes (or vice versa) until the converter has settled. Additional control circuitry may detect such an upcoming transition to assist the state machine in selecting an appropriate state. Still further, pulse widths may be managed by the control circuit to help avoid race conditions. Collectively, this approach smooths transitions for the DC- DC converter resulting in greater efficiency for the DC-DC converter. [0032] Before addressing aspects of the present disclosure, a brief review of a conventional DC-DC converter and some of the issues that may arise with the use of such ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 6 a DC-DC converter is provided with reference to Figures 1A-1C. A discussion of exemplary aspects of the present disclosure begins below with reference to Figure 2. [0033] In this regard, Figure 1A is a block diagram of a DC-DC converter 100 that may use a pulse width modulation (PWM) modulator circuit 102 to generate a control signal. The control signal is used by a comparator 104 to activate switches in a DC-DC switch matrix 106 (which may also include charge pumps or the like (not shown)). An output filter 108 may be formed from an inductor 110 and a capacitor 112 to filter an output from the DC-DC switch matrix 106. An output node 114 may provide a feedback signal to the PWM modulator circuit 102. Typically, the feedback signal is a voltage signal that provides an indication of a voltage level at the output node 114. [0034] Figure 1B is a state diagram 120 of the states of the DC-DC converter 100. Specifically, the DC-DC converter 100 may transition between low boost state 122 and high boost state 124, as well as between low buck state 126 and high buck state 128. Such transitions are generally relatively smooth and do not create issues. However, there may also be transitions from the high boost state 124 to a high buck state 128 and from the low buck state 126 to the low boost state 122. The transition from buck to boost and from boost to buck may be done immediately based on the signal from the comparator 104 and may result in multiple buck-to-boost and boost-buck transitions before the output settles, as better seen in Figure 1C, where the DC-DC converter 100 transitions from buck to boost at point 130, but then transitions back to buck at point 132 and then again back to boost at point 134. Such rattling between modes may result in an undesirably long settling time, particularly when the settling time overlaps with actual transmitted data. Thus, a main drawback of a conventional DC-DC converter 100 is the lack of tight control over a trajectory of the converter and sudden changes may result in ringing or rattling, as previously mentioned. [0035] Exemplary aspects of the present disclosure help smooth transitions by adding new transition states to a digital state machine that assist in the transition. In particular, the state machine knows what state the DC-DC converter is presently using and senses qualifying signals that would cause a state change. Based on the present state and the desired target state, the DC-DC converter may transition to a transition state through the transition and then complete the change to the target state. Such transition states may be particularly useful in smoothing the transition between buck and boost modes around a ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 7 battery voltage level (e.g., Vbatt). Numerous variations on this concept are provided in the discussion below. [0036] Note that DC-DC converters are common in power management integrated circuits (PMIC) such as envelope tracking (ET) circuits and average power tracking (APT) circuits. Such PMICs may rely on the DC-DC converters to provide a supply voltage to power amplifiers or the like and may transition frequently between states for improved power amplifier efficiency. While this is one specifically contemplated use case, other use cases may also exist and fall within the present disclosure. [0037] In this regard, Figure 2 illustrates a DC-DC converter 200. The DC-DC converter 200 may be coupled to a clock generator 202 both directly and through a divider circuit 204 (e.g., divide by N). It should be appreciated that the clock generator 202 may be in the same chip as the rest of the DC-DC converter 200 or may be external thereto. Likewise, the divider circuit 204 may be in-chip or off-chip. In an exemplary aspect, the direct connection may be used during boost modes (CLKboost), and the divided connection may be used in buck modes (CLKbuck), but such is not strictly required. The clock signals (direct and divided) are provided to a digital quasi-synchronous state machine 206 (herein after just state machine 206, but also sometimes referred to as a hybrid synchronous-asynchronous state machine). The state machine 206 provides control signals to a switch matrix 208 and charge pump(s) 210. Some portion of the control signals are synchronous with transitions in the clock signals and some portion of the control signals are asynchronous. The switch matrix 208 provides an output signal that is filtered by a filter 212 formed from, for example, an inductor 214 (Lout) and a capacitor 216 (Cout). The filtered signal may then be used to drive a switch (Vcc switch) 218. The switch 218 may also have a switch control circuit 220 that receives a signal from the state machine 206. Note that the switch 218 and the switch control circuit 220 are optional. [0038] A voltage feedback signal (V feedback) may be formed by measuring a voltage level at an output node 222 between the filter 212 and the switch 218. Additionally (and optionally), a current feedback signal (I feedback) may be measured either by measuring a current through the filter 212 (e.g., through the inductor 214) or from one of the switches in the switch matrix 208. The feedback signal(s) are part of a converter stabilization loop 224 that provides a signal to a comparator 226. The ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 8 comparator 226 generates a signal that indicates a qualified state transition to the state machine 206. The state machine 206 may include various circuits, as better explained below, and may control transitions between states to avoid transitioning on a clock edge and/or for smoothing transitions between buck and boost states. [0039] The state machine 206 controls the trajectory of the DC-DC converter 200 on a tight time frame, thereby reducing or eliminating rattle. As noted, the decision of the state machine 206 is based on an output of the comparator 226. [0040] Note that the state machine may be responsible for multiple DC-DC converters and/or a given DC-DC converter may have multiple modes (e.g., buck-only, auto-boost, charge pump-only, converter-only, and the like). Accordingly, the state machine may have multiple modes of operation, each with its own respective state diagram and transitions. [0041] In this regard, Figure 3 provides a block diagram of a DC-DC converter 300 where a state machine 302 has multiple modes 304(1)-304(N), each having its respective states and state transition rules. The state machine 302 may switch between modes based on a signal from a control circuit 306. The control circuit 306 may be coupled to an external bus and receive mode information from, for example, a baseband processor (not shown). Other elements are similar/identical to those in Figure 2 or omitted for simplicity. [0042] Figure 4 provides a block diagram of a DC-DC converter 400 with an illegal detection circuit 402 in a state machine 404. Additionally, a recovery circuit 406 may be present in the state machine 404. The illegal detection circuit 402 precludes entry into an illegal state that might otherwise occur based on the feedback signal. In particular, the state machine 404 knows which state is the present state and also knows what future states are legal. Based on a qualified signal from the comparator 226, the illegal detection circuit 402 may determine if an indicated state is legal and either block transition to that state or invoke the recovery circuit 406. The recovery circuit 406 may be used to plot out a series of transitions to an allowed or legal state. This plot may be formed from a last legal state or based on a least number of state transitions to arrive at a new legal state from the last legal state. [0043] Figure 5A is a state diagram 500 for any of the state machines described above. In particular, aspects of the present disclosure add a transition state 502 between a buck high state 504 and a boost low state 506, and the state machine may hold the converter in ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 9 this transition state 502 for a predefined length of time so as to reduce rattling. It should be appreciated that instead of transitioning from the boost low state to the transition state 502, the state machine may move from boost low state 506 to boost high state 508 and then potentially back to the boost low state 506. Likewise, the state machine may move from the buck high state 504 to a buck low state 510 or to the boost high state 508. As the switch from buck high state 504 to the boost high state 508 has a large change (e.g., Vbatt to 2*Vbatt), there is less chance of rattling compared to the transition between boost low state 506 to buck high state 504 (e.g., both at or near Vbatt). [0044] Figure 5B is a state diagram 550 with a larger number of states based on having multiple charge pumps 210. If only a single charge pump 210 is present, capacitors therein may be drained and have insufficient time to recharge, particularly when operating in boost mode. Accordingly, some converters rely on two (or more) charge pumps 210, alternating between them. This situation is designated by buck left high 552, buck right high 554, buck left low 556, buck right low 558, boost left low 560, boost left high 562, boost right low 564, and boost right high 566. There are now two state changes that remain at or around Vbatt, namely from boost right low 564 to buck left high 552 and from boost left low 560 to buck right high 554. Thus, there are two transition states 568 and 570, that allow for delayed transitions to assist in settling and smooth transitions. [0045] While not shown, there may be one or more initialization states during reboots, power-ups, or similar events. Likewise, there may be a variety of signals that trigger transition states. [0046] It should be appreciated that there are some transitions that are well suited for transitioning synchronously with a clock edge, and there are other transitions that may make more sense to do asynchronously with clock edges, and there may also be occasions when it is desirable to exclude such transitions from the clock edge to avoid race conditions or the like. Figure 6 illustrates a DC-DC converter 600 that adds in circuitry to facilitate such asynchronous behavior. Many elements are the same as previously described and are not repeated. However, a combination logic circuit 602 is added between the state machines 206, 302, 404, and the switching module 604. The switching module 604 has a switch matrix 606 analogous to the switch matrix 208 and charge pumps 608 analogous to the charge pumps 210, as well as a decoder 610. The decoder 610 ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 10 receives synchronous transition signals from the state machine 206, 302, 404 and receives clock edge excluded asynchronous transition signals from the combination logic circuit 602. The combination logic circuit 602 receives a signal from the converter stabilization loop 224. Additional details of the converter stabilization loop 224 are also provided in Figure 6. Specifically, the V Feedback signal goes to a voltage loop circuit 612 and the I Feedback signal (if present) goes to a current loop circuit 614. Outputs from loop circuits 612, 614 are weighted by resistors 616, 618 and provided to the comparator 226. The comparator 226 provides a signal to a latch 620. The latch 620 holds the information from the comparator 226 until released by a logic circuit 602. The logic circuit 602 also receives a clock signal from the divider circuit 204 and triggers the latch 620 when the clock transition has passed. Additional details on this windowing function are provided below with reference to Figures 10-12. [0047] Figure 7 provides additional details about some of the circuitry in the state machine 206, 302, 404 and, particularly, how the pulse width may be modified to assist in making sure the transitions are smooth. Specifically, the pulse width may be forced to have a minimum width as well as a maximum width and/or have a one-shot generator that is tied to clock edges. Thus, Figure 7 shows a DC-DC converter 700 where the state machine 206, 302, 404 includes a state machine core circuit 702 that sends the synchronous and asynchronous signals. The state machine core circuit 702 receives signals from a min pulse width circuit 704 and a max pulse width circuit 706 as well as a one-shot generator 708. [0048] Note that there may be more than one DC-DC converter in a mobile device. When more than one converter operates, there may be instances when they both place demands on the battery at the same time. This concurrent draw on the battery may accelerate battery depletion or lead to other performance compromises. Exemplary aspects of the present disclosure may provide a system 800 with a synchronization circuit 802 within a digital core 804. The digital core 804 may also include state machines 806A, 806B that provide signals to switch matrices 808A, 808B (analogous to switch matrix 606) with some signals passing through combination logic circuits 810A, 810B. Output filters 212A, 212B may be coupled to the switch matrices 808A, 808B and have feedback loops with comparators 226A, 226B, respectively. The synchronization circuit 802 drives the state machines 806A, 806B such that transitions to boost high states are not done ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 11 concurrently. By preventing concurrent boost high states, the drain on the battery may be controlled such that the battery is not compromised. [0049] Figures 9A and 9B provide additional details in system 900 of how the comparator 226 may operate to prevent transitions in the vicinity of a clock edge. Specifically, the comparator 226 may receive the signal (or combined signal) from the loop circuits 612, 614 through the resistors 616, 618. The comparator 226 may compare this signal to a compare voltage (e.g., 1.8 V or the like). A series of delay elements 902(1)-902(M) may delay an output from the comparator 226 as the output is passed to the latch 620. The latch 620 also receives a control signal from a one-shot generator 622A, which may be part of the logic circuit 622 of Figure 6. The latch 620 controls the combination logic circuit 602 (not shown) and gates the signals from the state machine 206, 302, 404. Additional delay element 904 may be present between the latch 620 and the combination logic circuit 602 or between the combination logic circuit 602 and the decoder 610 of Figure 6. [0050] Figure 9B adds a hysteresis circuit 920 to the latch 922. The output from the latch 922 is coupled to a force pulse width and pulse stretch circuit 924 before being provided to the state machine 206, 302, 404 (instead of the combination logic circuit 602). The latch 922 and the circuit 924 may be controlled by a decoder 926 that reads the signals from the state machine 206, 302, 404. [0051] Use of the circuits set forth in Figures 9A and 9B helps shape the signals so that transitions do not occur at the clock edge. For example, the circuits may force the output of the comparator 226 high around the clock active edge, as seen in Figure 10. Specifically, if the output signal 1000 is already high at the clock edge 1002, the output signal remains high over an exclusion window 1004. The comparator 226 may transition asynchronously at the transition 1006 after the exclusion window 1004. If the output signal 1008 (bottom plot) is low before the exclusion window 1010, the output of the comparator 226 may be forced high 1009 during the exclusion window 1010. A certain minimum period of high may be enforced after the exclusion window 1010 ends, and the output signal 1008 may return to low at transition 1012. If the comparator 226 would normally transition to a low during the exclusion window, the transition is delayed until after the exclusion window. ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 12 [0052] Alternatively, the output of the comparator 226 may be forced low to ensure a maximum limit on the control duty cycle, as better seen in Figure 11. On the top plot, an output signal 1100 is shown with a force low transition 1102 to have a boost window 1104 before a force high transition 1106 and an asynchronous comparator transition 1108 after the exclusion window 1110. On the bottom plot without output signal 1112, the output from the comparator 226 is already low during the force low, so there is no need to transition until the force high 1114 transition with an asynchronous comparator transition 1116 after the exclusion window 1118. For the boost operation, it may be useful to force a minimum duration of boost operation before going back to buck. This minimum duration reduces chatter between buck and boost modes. For example, after the comparator 226 goes high for the boost mode, it will be forced to stay high until the next active clock edge. This will force a minimum of one clock period of operation in the boost mode when the comparator 226 goes back down after the exclusion window. If the comparator 226 does not go down until the next clock edge, it can be allowed to go asynchronously down in the next clock period (top plot of Figure 11). These different force-high, force-low, and delayed validation of the comparator transition can be implemented with digital combinational circuits. [0053] In the buck mode of operation, there is no need to enforce a minimal duration. As such, it may be appropriate to preserve the decision of the comparator 226 after the exclusion window has elapsed. If the decision would be lost during an exclusion window, this will result in the delay of the control signal, which in turn will increase the error and result in longer settings. Keeping the decision and taking action on it after the exclusion window has ended can be achieved using the latch 620 (Figure 6) during the exclusion window and using a combinational logic to force the control output during the exclusion window. In this regard, Figure 12 illustrates a comparator output signal 1200 that starts high (e.g., maximum pulse width) and is forced low at transition 1202 for a boost window 1204 prior to exclusion window 1206. After the exclusion window 1206, the comparator output signal 1200 is then left high so that the comparator state is retained after the force ends, and an asynchronous transition 1208 may occur after the exclusion window 1206. If the comparator output signal 1210 is low at the beginning of the exclusion window 1212 and then returns to a low at transition 1214. Thus, in the buck mode, the control line will transition to low asynchronously, and in the boost mode, the line will be forced ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 13 high for an entire clock period and then transition synchronously with the next clock edge if the comparator output goes low in this time interval or is allowed to go low asynchronously if the comparator does not go low until the next active clock edge. [0054] The signals of Figures 10-12 can be implemented using a state decoder that can sense the buck versus boost operation and the low/high state of the comparator output signal. There are multiple ways to distribute the latch, force, and min/max pulse width enforcement between different building blocks (although Figure 9B is illustrative). One option is to perform the latching of the comparator state directly in the comparator 226. In an alternate aspect, the latching can occur after the comparator 226. The forcing and duty enforcement action can be implemented in a combinational logic following the comparator-latch function. The action of the force and duty cycle min/max enforcement and latching of the comparator 226 are driven by the state-machine decoder circuit. In an alternate aspect, the state decoder circuit can be implemented together with the force and DC circuit in the same building block. Digital or analog implementations of the one-shot circuits and the different delayed timings can be used. A high-frequency clock that is synchronous with the actual switching clock of the converter can also be used to generate all these force functions. [0055] With reference to Figure 13, the concepts described above may be implemented in various types of user elements 1300, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user elements 1300 will generally include a control system 1302, a baseband processor 1304, transmit circuitry 1306, receive circuitry 1308, antenna switching circuitry 1310, multiple antennas 1312, and user interface circuitry 1314. In a non-limiting example, the control system 1302 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1302 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1308 receives radio frequency signals via the antennas 1312 and through the antenna switching circuitry 1310 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1308 cooperate to amplify and remove broadband interference from the received signal for ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 14 processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC). [0056] The baseband processor 1304 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1304 is generally implemented in one or more digital signal processors (DSPs) and ASICs. [0057] For transmission, the baseband processor 1304 receives digitized data, which may represent voice, data, or control information, from the control system 1302, which it encodes for transmission. The encoded data is output to the transmit circuitry 1306, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1312 through the antenna switching circuitry 1310 to the antennas 1312. The multiple antennas 1312 and the replicated transmit and receive circuitries 1306, 1308 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art. [0058] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 15 electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. [0059] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. ^{WT Ref. No. 2867-3336-WO}

Claims

Ref. No. P231294-WO-UTL 16 What is claimed is: 1. A power management integrated circuit (PMIC), comprising: a direct current-to-direct current (DC-DC) converter comprising: a state machine configured to smooth transitions between buck and boost modes by holding the DC-DC converter in a transition state for a predetermined amount of time when transitioning from a first buck mode to a first boost mode. 2. The PMIC of claim 1, wherein the DC-DC converter is integrated into an envelope tracking integrated circuit. 3. The PMIC of claim 1, wherein the DC-DC converter is integrated into an average power tracking circuit. 4. The PMIC of claim 1, further comprising a comparator configured to output a pulse to the state machine. 5. The PMIC of claim 4, wherein the comparator is configured to be delayed when a clock edge transition occurs. 6. The PMIC of claim 4, further comprising a voltage feedback loop circuit coupled to an output of the DC-DC converter and the comparator. 7. The PMIC of claim 6, further comprising a current feedback loop coupled to the comparator. 8. The PMIC of claim 4, further comprising a latch coupled to the comparator and configured to prevent race conditions. 9. The PMIC of claim 4, further comprising a delay circuit coupled to the comparator. ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 17 10. The PMIC of claim 4, further comprising a one-shot circuit coupled to the comparator. 11. A method for controlling power in a direct current-to-direct current (DC-DC) converter, comprising: passing a pulse from a comparator to a state machine; and smoothing transitions between buck and boost modes by using a transition state in the state machine. 12. The method of claim 11, further comprising delaying the pulse when a clock edge transition occurs. 13. The method of claim 11, further comprising providing a voltage feedback signal from an output of the DC-DC converter to the comparator. 14. The method of claim 13, further comprising providing a current feedback signal from the output to the comparator. 15. The method of claim 11, further comprising using a latch coupled to the comparator to prevent race conditions. 16. A mobile terminal comprising: a transceiver comprising a power management integrated circuit (PMIC) comprising: a direct current-to-direct current (DC-DC) converter comprising: a state machine configured to smooth transitions between buck and boost modes by holding the DC-DC converter in a transition state for a predetermined amount of time when transitioning from a first buck mode to a first boost mode. 17. The mobile terminal of claim 16, further comprising an envelope tracking integrated circuit, ETIC, wherein the ETIC includes the DC-DC converter. ^{WT Ref. No. 2867-3336-WO} Ref. No. P231294-WO-UTL 18 18. The mobile terminal of claim 16, further comprising an average power tracking circuit, wherein the average power tracking circuit includes the DC-DC converter. 19. The mobile terminal of claim 16, further comprising a comparator configured to output a pulse to the state machine. 20. The mobile terminal of claim 19, further comprising a delay circuit configured to delay the comparator when a clock edge transition occurs. ^{WT Ref. No. 2867-3336-WO}