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WO2025023903A1 - Logique évolutive et dispositif de mémoire basé sur des skyrmions magnétiques - Google Patents

Logique évolutive et dispositif de mémoire basé sur des skyrmions magnétiques Download PDF

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Publication number
WO2025023903A1
WO2025023903A1 PCT/TR2023/050739 TR2023050739W WO2025023903A1 WO 2025023903 A1 WO2025023903 A1 WO 2025023903A1 TR 2023050739 W TR2023050739 W TR 2023050739W WO 2025023903 A1 WO2025023903 A1 WO 2025023903A1
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Prior art keywords
logic
logic block
block
blocks
track
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Inventor
Arash Mousavi CHEGHABOURI
Mehmet Cangiz ONBASLI
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Koc Universitesi
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Koc Universitesi
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices

Definitions

  • the present disclosure generally relates to emerging memory devices that take advantage of magnetism.
  • Present disclosure more specifically concerns induced movement and interactions between magnetic skyrmions, nanoscale circular spins, and using skyrmions for performing non-volatile Boolean logic and memory operations.
  • magnetic skyrmions are experimentally verified statically stable solitons which can be used for carrying information. Their small size (20 nm in diameter) and the relatively small amount of current required to induce them make them quite advantageous and promising in the field of reversible computing. Another aspect of magnetic skyrmions is that they do not involve movement of individual particles, as they are regions of magnetization and as such what is required is the propagation of magnetization. For high-density and low-power logic and memory devices, electronic spins need to be used. Previous materials and device designs show spin injection, detection, and partial manipulation, but a complete spintronics/magnetic logic system is still not verified.
  • EP 3196944 Bl provides a magnetic element capable of generating and erasing the one skyrmion, which includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion.
  • a width Wm of the substantially rectangular magnet is such that 3‘A > Wm > A, where A denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2-A > Hm > A, and the magnet has a notch structure at an edge between the upstream electrode and the downstream electrode.
  • a similar concept is also disclosed in EP 3226307 Bl.
  • US 9,704,550 B2 proposes a scheme for generating and translating a skyrmion as a memory bit by a magnetic patch with a chiral configuration. Also, the magnetic element in which the skyrmion control unit brings the magnetic body into an unstable state by supplying thermal energy pulses to the magnetic body is provided. Furthermore, a skyrmion memory comprising the magnetic element is provided.
  • US 9,773,540 B2 discloses a method for generating a skyrmion, comprising: depositing a vertical metallic nanopillar electrode on a first side of a helimagnetic thin film, the helimagnetic thin film having a contact on a second side to provide a current drain; injecting a current through the vertical metallic nanopillar electrode to generate a rotating field; and applying a static upward magnetic field perpendicular to the helimagnetic thin film to maintain an FM phase background.
  • Teaching of US 10,497,800 B2 contains a scheme for a skyrmionic diode.
  • Said diode includes a magnetic body and a conductive body, the magnetic body having a skyrmion used as information carrier, the conductive body being disposed on or under the magnetic body.
  • the conductive body utilizes the modulation of the Dzyaloshinskii-Moriya Interaction strength using a geometric notch on a DMI-inducing material.
  • US 11,539,365 B2 provides a skyrmion logic gate, which comprises a first track configured for propagation of magnetic skyrmions and a second track configured for propagation of magnetic skyrmions.
  • a junction links the first and second tracks.
  • a continuous current flows through the logic gate, wherein skyrmions propagate due to the current.
  • a logic system proposed thereby is based on magnetic tracks with geometric notches that modulate the skyrmion motion in multi-track non-trivial geometries.
  • Primary object of the present invention is to provide a magnetic skyrmion based logic and memory device.
  • Another object of the present invention is to provide a magnetic skyrmion based logic and memory device that is able to produce universal and scalable logic.
  • a further object of the present invention is to provide a magnetic skyrmion based logic and memory device that provides a block-based logic paradigm that displays cascadability property.
  • a still further object of the present invention is to provide a magnetic skyrmion based logic and memory device wherein the entirety of data signals are magnetic skyrmions.
  • a still further object of the present invention is to provide a magnetic skyrmion based logic and memory device wherein actions of data storage and logic operations are enabled within the same block.
  • disclosed invention provides a magnetic skyrmion based logic and memory device.
  • Foremost feature of presently disclosed logic and memory device being that it enables cascadability in logic operations, said operations undertaken by logic and guiding blocks for magnetic skyrmions.
  • Present disclosure provides a logic inverter based on magnetic skyrmion operation.
  • Said magnetic skyrmion based logic inverter design due to the substrate thermal conductivity, enables functioning thereof with a direct current drive, a wide bandwidth, sub-micron footprint, zero or negligible external magnetic field, and in room -temperature thermal stability despite Joule heating.
  • Said logic inverter design also allows cascadability wherein multiple logic gates may accept, as input, outputs of other upstream logic gates, resulting in great scalability.
  • Disclosed invention also teaches the use of magnetic insulators for eliminating Joule heating in the proposed skyrmion based inverter logic gate design, and also lowers exchange stiffness, magnetic moment and other factors which according to various embodiments greatly reduce power consumption by more than four orders of magnitude.
  • Figure 1 demonstrates an inverter with inputs-outputs, modeling situations as well as a NOR gate cascading two inverter blocks according to the present disclosure.
  • Figure 2 demonstrates the black box abstract demonstration of a skyrmion logic block according to the present disclosure.
  • Figures 3a and 3b demonstrate the geometry, skyrmion flow and schematic demonstration of the inverter block according to the present disclosure.
  • Figures 4a and 4b demonstrate the geometry, skyrmion flow and schematic demonstration of the flipped inverter block according to the present disclosure.
  • Figures 5a and 5b demonstrate the geometry, skyrmion flow and schematic demonstration of the inverter-transfer block according to the present disclosure.
  • Figures 6a and 6b demonstrate the geometry, skyrmion flow and schematic demonstration of the junction up-right block according to the present disclosure.
  • Figures 7a and 7b demonstrate the geometry, skyrmion flow and schematic demonstration of the junction up-left block according to the present disclosure.
  • Figures 8a and 8b demonstrate the geometry, skyrmion flow and schematic demonstration of the duplicator block according to the present disclosure.
  • Figures 9a and 9b demonstrates the geometry, skyrmion flow and schematic demonstration of the transfer block according to the present disclosure.
  • Figures 10a and 10b demonstrate the geometry, skyrmion flow and schematic demonstration of the left-down deflector block according to the present disclosure.
  • Figures 11a and lib demonstrate the geometry, skyrmion flow and schematic demonstration of the bottom-left deflector block according to the present disclosure.
  • Figures 12a and 12b demonstrate the geometry, skyrmion flow and schematic demonstration of the logic one block according to the present disclosure.
  • Figures 13a and 13b demonstrate the geometry, skyrmion flow and schematic demonstration of the logic zero block according to the present disclosure.
  • Figure 14 demonstrates the 90-degree rotation of the inverter-transfer block according to at least one embodiment of the present disclosure.
  • Figures 15a, 15b, 15c and 15d demonstrate a NOR gate built using skyrmionics logic blocks, execution order and labels of individual blocks, geometry of the schematics, physical model after the execution of blocks 1 to 4 according to the present disclosure.
  • Present disclosure describes a type of logic gate acting as an inverter which uses magnetic skyrmion technology.
  • the design of this inverter is able to operate using direct current drive, has a wide bandwidth, and has a size in submicron scale. It is not associated with a strong external magnetic field, next to being thermally stable at room temperature even when subjected to Joule heating.
  • the inverter is also able to be cascaded, which means multiple logic gates can be connected to each other to create a more complex system. This allows for a highly scalable design.
  • a scalable logic and memory device which comprises individual blocks for guiding and spatially manipulating magnetic skyrmions, this being the essential element of the logic operations.
  • the foremost feature of said scalable logic and memory device comprising individual blocks is that the scalability arises from the cascadability of the logic gate design provided therein, making the device scalable to a great extent with the usage of different combinations for magnetic skyrmion logic gates.
  • An example thereof according to one embodiment may be the usage of the inverter gates to make AND, OR and NOT gates, and with the use thereof creating a Boolean universality.
  • said scalable logic and memory device comprising individual blocks can produce the entirety of Boolean operations, making the system universal in means of Boolean logic.
  • Above function accepts two inputs, and inverts one of said two inputs and outputs the result of the AND logic operation between the inverted input and the non-inverted input.
  • said logic and memory device comprises multiple logic and guiding blocks for magnetic skyrmions. This results in a block-based cascadable logic, which is providing the great scalability of the present invention. Said cascadability is also arising from the connection between, and sequential enabling of down-stream logic and guiding blocks such that desired Boolean logic functions are achieved.
  • Disclosed invention also has material parameters to be established.
  • Material parameters generally concern the substrate whereon the channels are realized, mainly those being conducive for Dzyaloshinskii-Moriya interaction.
  • it may be realized as a substance of magnetic character, such as a ferromagnet, or alternatively in some embodiments it may be realized as an anti-ferromagnetic material.
  • One example of such material parameters are of Cobalt on Platinum (Co/Pt) layers with thicknesses from 1 to 6 nanometers, serving as the substrate of said logic blocks.
  • the figures of this invention are provided for these substrate thickness values.
  • the blocks relating these values are of the size of 300 nm by 300 nm and the skyrmion sizes are with diameters ⁇ 25 nm. Different material parameters might change the optimum geometric dimensions, while the overall shapes and working principles are the same.
  • a magnetic skyrmion-based inverter logic block is proposed.
  • Said inverter logic block is configured to use a magnetic skyrmion in at least one vertical channel to halt the movement of one other magnetic skyrmion in at least one horizontal channel.
  • two different inverter logic block types are possible.
  • One embodiment may utilize a horizontal channel (horizontal track) in which said magnetic skyrmion is traveling towards the left, whereas another embodiment may utilize a horizontal channel in which magnetic skyrmion travels towards the right.
  • a logic inverter with an inverter-transfer capability is configured also to retrieve the magnetic skyrmion travelling in the vertical channel in addition to that which is travelling in the horizontal channel.
  • the geometry of a logic inverter according to the present disclosure can be realized in rectangular form, such as a rectangular plane that is 300 nm by 300 nm in dimensions. For concatenating multiple different gates, a deliberate placement is necessary for an automated, larger-scale system.
  • Figure 1 shows the summary of the cascadability of inverter gates. According to Figure la, what is shown is the geometry, truth table and circuit schematics equivalent of the inverter gate, whereas the magnetic configuration of each row of the said gate is shown in Figure 1 b, and the geometry, truth table and the equivalent circuit schematics of the NOR gate is shown in Figure 1 c. These magnetic configurations do not represent the end-of-cycle moment of the block, since at the clearance stage the middle part of the block will be cleared and the vertical magnetic domain will not exist. Geometric representation of the cascaded blocks, the circuit schematics and the truth table of the cascaded blocks are also demonstrated.
  • disclosed invention also provides a box model for individual blocks (10) in a novel skyrmion logic system that realizes a complete Boolean system.
  • blocks (10) that are in square form, comprising four input/output channels (12). Channels have the same width and are centrally aligned on the sides of the square form. Indices of the channels 0, 1, 2, and 3 respectively correspond to positions of top, right, bottom and left in the square block (10). For an inverter block, x input is at channel 2, y input is in channel 3 whereas z output is in channel 1. Note that not all the channels need be utilized in each block; for an inverter block channel 0 is null, and does not accept inputs or outputs.
  • the square form of the blocks (10) are realized in 300 nm by 300 nm dimensions. Each channel has a width of 50 nm.
  • Logic function executed in the interior (11) of a block (10) according to the present disclosure can be described by relations between values of the i/o channels (12) at the end of a work cycle based on their values at the beginning of the work cycle.
  • An exemplary inverter block (13) has the following state equation:
  • the output channel at the right side of the inverter gate is denoted by h.
  • a variant inverter block is also disclosed.
  • Said variant inverter also called a flipped inverter (14) is an inverter block where the flow of the skyrmion in the horizontal track is from right to left.
  • the state equation of the flipped inverter (14) is as given below:
  • the invertertransfer (15) logic block is the invertertransfer (15) logic block.
  • the vertical skyrmion in the inverter block is lost in the operation. The loss of the vertical skyrmion may not be desirable in some cases. Adding a channel at the top of the inverter block allows for the reuse of the lost vertical channel skyrmion.
  • the state equation of the inverter-transfer block (15) has the following state equation:
  • junction (16, 17) block Another type of logic block according to the present disclosure is the junction (16, 17) block.
  • the geometry of the junction block (16, 17) is similar to that of the inverter-transfer (15) logic block.
  • the key change in this block is the timing of the spin polarized current, i.e. the stages of the operation.
  • an up-right junction (16) and an up-left junction (17) are proposed with the associated respective state equations are as given below:
  • Duplicator (18) logic block is essential for an operational skyrmion logic system as it produces the fan-out operation.
  • a skyrmion is entered from the left channel of the duplicator and two skyrmions emerge from right and bottom channels.
  • the state equation of the duplicator block (18) is as given below:
  • Another type of block disclosed according to the present invention is the transfer (19) logic block. Transfer (19) block comprises essentially a simple track that allows a skyrmion to move from left to right therethrough.
  • logic one block Another type of block disclosed according to the present invention is the logic one block (22), which is configured to give an output of a skyrmion at the channel with index 1.
  • another type of block namely the logic zero block (23) gives an output of no skyrmion.
  • the latter block while in principle could be substituted with an empty block, is still conceived for sake of similarity to other logic blocks, and also for the fact that its value may be changed during runtime.
  • logic one (22) and zero (23) blocks are warranted as disclosed herein. State equations of logic one (22) and logic zero (23) blocks are as given below:
  • logic blocks are usable in various embodiments in multiple types of combinations such that arbitrary logic device units can be created.
  • arbitrary logic device units include a NOR gate, an XOR gate, an XNOR gate, a NOT gate, an AND gate, an OR gate, a NAND gate, a full adder, a half adder.
  • different types of magnetic materials may be used for constructing said logic blocks.
  • One particular embodiment may use a Cobalt-Platinum bilayer.
  • Internals of said logic blocks can have different dimensions with the intended functionality kept in mind.
  • An exemplary embodiment discloses a logic block dimension of 300 by 300 nanometres.
  • the minimum width of a horizontal magnetic skyrmion channel is set at 50 nanometres, whereas the maximum width is set to be 60 nanometres.
  • a minimum width of a vertical magnetic skyrmion channel is set at 20 nanometres, whereas the maximum width is set to be 50 nanometres.
  • Said horizontal channel can be configured to be utilized as the probing track, while said vertical channel can be utilized as the signal track.
  • said blocks can also be subject to rotation.
  • Blocks and their geometries are provided such that the black box view of said blocks display a 4-fold rotational symmetry, such that each block can be rotated 90 degrees and the channels match the neighboring block.
  • No embodiment is exclusively using rotated blocks: While some blocks may be rotated, others may be not, since only the inverter-transfer block is the block that utilizes all four channels comprised thereby.
  • this rotation also consequently changes the state equation of the block by permuting the channel indices.
  • This means that the channel io of a block becomes the channel is of a rotated block since (0-1) mod 4 3.
  • This property is essential to the emulation of all possible logic systems disclosed by the invention.
  • This rotation ability greatly reduces the redundancy of the system.
  • a block-propagation system is essential. Individual blocks are connected to bring together a larger geometry and this constitutes the overall physical model.
  • a skyrmion logic gate is constituted of an m by n matrix of blocks where m is the number of rows and n is the number of columns.
  • a NOR gate according to the present disclosure is a 1 by 2 matrix of blocks. If separate blocks are to be implemented for inputs of the NOR gate, the structure becomes a 2 by 3 matrix.
  • such a NOR gate comprises blocks with different execution orders, which means the electric current values in the tracks are adjusted such that the block with the specified execution order is enabled. Blocks are activated in required order via sending current pulses in tracks that are part of said blocks.
  • An exemplary case shows a matrix of three inverters producing an OR gate.
  • Such an OR gate comprises three inverter blocks concatenated horizontally with the rightmost block rotated 270 degrees. These blocks constitute an integrated geometry with four interconnected tracks, respectively the horizontal track, the ii vertical track, the Z?vertical track, and the output track. Since the work cycle of a combination of blocks finishes after the work cycle of every block has ended, a configured combination of pulses for the interconnected tracks can produce the effect of sequentially run blocks.
  • the first step is the calculation of the intended actions to be performed according to the logic system in terms of logic gates designed using the logic blocks.
  • a subsequent step is the building of said logic system structure as an object.
  • a truth table of the built structure as an object is obtained and compared to the intended truth table.
  • Next step is making a simulation object from the built logic system and obtaining the truth table of the simulated object, compared to the intended truth table.
  • a final step is the addition of specific inputs and producing a simulation, running said simulation and ensuring the simulation results match the simulation object results.
  • the universality of the inverter block with two input is the essential aspect of the core logic block of any logic system capable of producing arbitrary logic.
  • an arbitrary logic function can be made from inverter blocks.
  • Non-logic block such as junction, transfer, duplicator etc. are also essential parts of the disclosed system as they provide fan-in and fan-out functionalities for different inverter blocks.
  • a logic block comprising at least a first track suitable for propagating magnetic skyrmions, at least a second track suitable for propagating magnetic skyrmions, a junction joining said at least a first and a second tracks.
  • Said logic block is supplied with a sufficient amount of current such that at least two skyrmions propagate through respective channels, said at least a first track is a horizontal track, said at least a second track is a vertical track, said logic block is in square form and configured to accept at most three inputs and give at least one output.
  • said logic block in square form is of dimensions 300 by 300 nanometers.
  • said logic block further comprises a substrate configured to display Dzyaloshinskii-Moriya interaction, and/or a magnetic material conducive to skyrmion movement, such as a cobalt- platinum bilayer substrate.
  • said logic block is configured to perform a logic inversion and multiplication (logic AND) operation.
  • said logic block is configured to perform a duplication operation.
  • said logic block is configured to perform a transfer operation where an input is directly used as an output.
  • said logic block is configured to perform a bottom-left operation where a skyrmion on the bottom channel is deflected to the left channel.
  • said logic block is configured to perform a left-down operation where a skyrmion on the left channel is deflected to the bottom channel.
  • said logic block is configured to perform a logic one operation where an output is configured to be logic one regardless of input.
  • said logic block is configured to perform a logic zero operation where an output is configured to be logic zero regardless of input.
  • a logic and memory device comprising at least multiple logic blocks, each of which comprise at least two tracks suitable for propagation of magnetic skyrmions is proposed.
  • said at least multiple logic blocks are configured to control and guide magnetic skyrmions, said at least two tracks suitable for propagation of magnetic skyrmions are arranged such that one is a horizontal track whereas another is a vertical track, said at least multiple logic blocks are connectable such that at least one track of one logic block is structurally associated with at least one track of one other logic block, and said at least multiple logic blocks are transformably and rotatably arranged such that the horizontal tracks can be aligned with other horizontal tracks and vertical tracks, whereas vertical tracks can be aligned with other vertical tracks and horizontal tracks.
  • said at least multiple logic blocks are selected from a group including an inverter, a duplicator, a logic one, a logic zero, a left-down deflector, a bottom-left deflector, an inverter-transfer.
  • a computer- implemented method of simulation in a simulation environment for a logic system comprising individual logic blocks
  • said method comprising steps of calculating a set of intended actions to be performed according to the logic system in terms of logic gates designed using logic blocks; building of said logic system structure as an object in said environment using multiple instances of logic block objects; obtaining a truth table of the logic system structure built as an object and comparing to an intended truth table; making a simulation object from the built logic system and obtaining the truth table of the simulated object, compared to the intended truth table; making modifications, if necessary, to the object to update a truth table; adding predetermined specific inputs and generating a simulation, running said simulation, and; repeating previous steps until the simulation results match the simulation object results.

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
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Abstract

La présente invention divulgue un type de bloc logique utilisable pour guider des blocs pour des skyrmions magnétiques, une logique et un dispositif de mémoire comprenant lesdits blocs et un procédé de simulation pour ledit système logique comprenant lesdits blocs. L'invention est caractérisée par une évolutivité fournie par une logique en cascade basée sur un bloc, des signaux de données représentant des skyrmions entièrement magnétiques. Est également divulgué un dispositif, activant un stockage de données et des opérations logiques à l'intérieur du même bloc. La mise en cascade, la connexion, et l'activation séquentielle de blocs permettent d'obtenir n'importe quel ensemble de fonctions logiques booléennes souhaitées grâce auxquelles l'universalité booléenne est obtenue, favorisant un système capable de produire une logique arbitraire.
PCT/TR2023/050739 2023-07-27 2023-07-27 Logique évolutive et dispositif de mémoire basé sur des skyrmions magnétiques Pending WO2025023903A1 (fr)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867988B2 (en) * 2000-11-17 2005-03-15 Eastgate Investment Limited Magnetic logic elements
US9704550B2 (en) 2015-08-21 2017-07-11 Riken Magnetic element, skyrmion memory and arithmetic processing unit
US9773540B2 (en) 2015-07-17 2017-09-26 The Johns Hopkins University Skyrmion based universal memory operated by electric current
US10497800B2 (en) 2016-03-07 2019-12-03 Unist (Ulsan National Institute Of Science And Technology) Skyrmion diode and method of manufacturing the same
EP3196944B1 (fr) 2014-09-04 2021-05-05 Riken Element magnetique et memoire a skyrmions
EP3226307B1 (fr) 2014-11-27 2022-02-09 Riken Élément magnétique, mémoire à skyrmions, dispositif électronique à semi-conducteur comprenant une mémoire à skyrmions installée, dispositif d'enregistrement de données, dispositif de traitement de données, et dispositif de communication
US11539365B2 (en) 2019-06-27 2022-12-27 Board Of Regents, The University Of Texas System Reversible computing system and method based on conservative magnetic skyrmion logic

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867988B2 (en) * 2000-11-17 2005-03-15 Eastgate Investment Limited Magnetic logic elements
EP3196944B1 (fr) 2014-09-04 2021-05-05 Riken Element magnetique et memoire a skyrmions
EP3226307B1 (fr) 2014-11-27 2022-02-09 Riken Élément magnétique, mémoire à skyrmions, dispositif électronique à semi-conducteur comprenant une mémoire à skyrmions installée, dispositif d'enregistrement de données, dispositif de traitement de données, et dispositif de communication
US9773540B2 (en) 2015-07-17 2017-09-26 The Johns Hopkins University Skyrmion based universal memory operated by electric current
US9704550B2 (en) 2015-08-21 2017-07-11 Riken Magnetic element, skyrmion memory and arithmetic processing unit
US10497800B2 (en) 2016-03-07 2019-12-03 Unist (Ulsan National Institute Of Science And Technology) Skyrmion diode and method of manufacturing the same
US11539365B2 (en) 2019-06-27 2022-12-27 Board Of Regents, The University Of Texas System Reversible computing system and method based on conservative magnetic skyrmion logic

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
KAI YU MAK ET AL: "Transcription and logic operations of magnetic skyrmions in bilayer cross structures", JOURNAL OF PHYSICS: CONDENSED MATTER, INSTITUTE OF PHYSICS PUBLISHING, BRISTOL, GB, vol. 33, no. 40, 28 July 2021 (2021-07-28), pages 1 - 9, XP020369641, ISSN: 0953-8984, [retrieved on 20210728], DOI: 10.1088/1361-648X/AC117E *
MOUSAVI CHEGHABOURI ARASH ET AL: "Cascadable direct current driven skyrmion logic inverter gate", PHYSICAL REVIEW B, vol. 105, no. 5, 4 April 2022 (2022-04-04), pages 1 - 11, XP093119508, ISSN: 2469-9950, DOI: 10.1103/PhysRevB.105.054411 *
NIKONOV DMITRI E ET AL: "Review of Simulation Methods for Design of Spin Logic", IEEE NANOTECHNOLOGY MAGAZINE, IEEE, USA, vol. 17, no. 4, 19 July 2023 (2023-07-19), pages 37 - 42, XP011945166, ISSN: 1932-4510, [retrieved on 20230608], DOI: 10.1109/MNANO.2023.3278971 *
YAN ET AL., SKYRMION-BASED PROGRAMMABLE LOGIC DEVICE WITH COMPLETE BOOLEAN LOGIC FUNCTIONS
ZHANG SHILEI ET AL: "Topological computation based on direct magnetic logic communication", SCIENTIFIC REPORTS, vol. 5, no. 1, 25 October 2015 (2015-10-25), pages 1 - 11, XP055902332, DOI: 10.1038/srep15773 *

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