WO2025017863A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device (100) is provided with: a semiconductor layer (10) having a first main surface (50) and a second main surface (51); and a diamond layer (11) having a third main surface (52) and a fourth main surface (53). The diamond layer (11) is provided with: a first recess (30) formed in the third main surface (52); and a first bonding layer (13) embedded in the first recess (30). The second main surface (51) of the semiconductor layer (10) and the third main surface (52) of the diamond layer (11) are bonded via the first bonding layer (13).

Description

Semiconductor device and method for manufacturing the same

This disclosure relates to a semiconductor device and a method for manufacturing the same.

Semiconductor devices made from nitride semiconductors, such as field effect transistors (FETs), are known as semiconductor devices that operate at high power and high frequencies. However, nitride semiconductor devices have a problem in that the characteristics or reliability of the semiconductor device deteriorates due to an increase in the temperature inside the semiconductor device during high power operation.

In order to suppress temperature rise inside semiconductor devices, it is important to place materials or structures with high heat dissipation properties near heat-generating parts. Diamond boasts the highest thermal conductivity of any solid substance, making it an ideal heat dissipation material.

As a semiconductor device that is expected to have a high heat dissipation effect, a structure in which the entire substrate of the semiconductor device is replaced with diamond, in other words, diamond is used as a heat spreader, is known. In particular, the GaN on Diamond structure, which uses gallium nitride (GaN) as a nitride semiconductor, is widely known.

Since it is difficult to grow a nitride semiconductor directly on diamond, the above structure is formed by growing diamond on a nitride semiconductor via an intermediate layer, or by bonding a separately formed diamond substrate to a semiconductor substrate made of a nitride semiconductor. In the technology for bonding a diamond substrate to a semiconductor substrate, due to the difference in thermal expansion coefficient between the two, it is desirable to bond them at a relatively low temperature to suppress stress changes in each substrate. Therefore, for direct bonding of a semiconductor substrate and a diamond substrate, a method such as surface activated bonding is used, in which dangling bonds are formed at the bonding interface by irradiating Ar at room temperature in a high vacuum, and then pressure bonding is performed.

When directly bonding substrates together, bonding is performed at the atomic level, so in addition to flattening the bonding surfaces of the diamond substrate and the semiconductor substrate, they also need to be smoothed to a surface roughness of 1 nm or less. While it is possible to smooth and flatten single crystal diamond and polycrystalline diamond on diamond substrates, it is difficult to uniformly smooth and flatten the entire surface of large diamond substrates with an area of 2 inches or more with high precision. In particular, when bonding a large semiconductor substrate and a diamond substrate, the effects of stress are large, and peeling is likely to occur unless the adhesion between the substrates is high.

In order to mitigate the effects of substrate surface roughness and improve the bonding of dangling bonds made of amorphous materials, methods have been proposed that introduce an interface layer to increase adhesion between substrates (e.g., Patent Documents 1 and 2). By making the interface layer thicker, the amorphous layer expands, increasing the bonding strength and enabling uniform bonding within the substrate surface.

JP 2020-109796 A Special Publication No. 2016-509372

However, when an interface layer is introduced between the substrates, the influence of the amorphous layer, which has low thermal conductivity, becomes greater, and the effect of improving heat dissipation provided by the diamond substrate cannot be fully achieved. Therefore, a method of forming a bonding layer that can increase the bonding strength with the semiconductor substrate while maintaining the heat dissipation effect of the diamond substrate is desired.

The present disclosure has been made to solve the above problems, and aims to provide a semiconductor device and a manufacturing method thereof that can increase the bonding strength between the semiconductor layer and the diamond layer while ensuring the heat dissipation effect of the diamond layer.

The semiconductor device according to the present disclosure comprises a semiconductor layer having a first main surface and a second main surface, a diamond layer having a third main surface and a fourth main surface, a first recessed portion formed in the third main surface of the diamond layer, and a first bonding layer embedded in the first recessed portion, and the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer.

In the semiconductor device according to the present disclosure, the bonding layer is thicker in the recessed portion, and the bonding strength between the semiconductor layer and the diamond layer is increased in that portion, so that the effects of stress are mitigated overall, and high bonding strength is obtained. In addition, because the bonding layer introduced between the semiconductor layer and the diamond layer is localized, the heat dissipation effect of the diamond substrate is also fully obtained.

The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a cross-sectional view of a semiconductor device according to a first embodiment; 1 is a cross-sectional view of a semiconductor device according to a first embodiment; 1 is a top view of a semiconductor device according to a first embodiment; 2A to 2C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to the first embodiment; 2A to 2C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to the first embodiment; 2A to 2C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to the first embodiment; 2A to 2C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to the first embodiment; 5A to 5C are diagrams illustrating a second step of the manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a second step of the manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a second step of the manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a second step of the manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a second step of the manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a third step of the method for manufacturing the semiconductor device according to the first embodiment. 5A to 5C are diagrams illustrating a third step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 11A to 11C are diagrams illustrating a first step of a method for manufacturing a semiconductor device according to a second embodiment. 13A to 13C are diagrams illustrating a second step in the manufacturing method of the semiconductor device according to the second embodiment. 13A to 13C are diagrams illustrating a second step in the manufacturing method of the semiconductor device according to the second embodiment. 13A to 13C are diagrams illustrating a third step of the method for manufacturing a semiconductor device according to the second embodiment. 13A to 13C are diagrams illustrating a third step of the method for manufacturing a semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. 13A to 13C are diagrams illustrating a third step in the method for manufacturing a semiconductor device according to the third embodiment. 13A to 13C are diagrams illustrating a third step in the method for manufacturing a semiconductor device according to the third embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 13 is a top view of a semiconductor device according to a fourth embodiment. FIG. 13 is a top view of a semiconductor device according to a fourth embodiment.

The semiconductor device and the manufacturing method thereof according to the present disclosure will be described in detail with reference to the drawings. In the drawings, the scale of each component may differ from the actual components in order to facilitate understanding.

A. First embodiment
A-1. Configuration A description will be given of a semiconductor device 100 according to the embodiment 1. The semiconductor device 100 includes a semiconductor layer 10 and a diamond layer 11, as shown in FIG.

The semiconductor layer 10 has a first main surface 50 and an opposing second main surface 51. In FIG. 1, the upper surface of the semiconductor layer 10 is the first main surface 50, and the lower surface is the second main surface 51. The diamond layer 11 has a third main surface 52 and an opposing fourth main surface 53. In FIG. 1, the upper surface of the diamond layer 11 is the third main surface 52, and the lower surface is the fourth main surface 53. The semiconductor layer 10 is mounted on the diamond layer 11, and the third main surface 52 of the diamond layer 11 and the second main surface 51 of the semiconductor layer 10 are bonded.

A first recess 30 is formed in the third main surface 52 of the diamond layer 11. A first bonding layer 13 is densely embedded in the first recess 30. The surface of the first bonding layer 13 forms the same plane as the third main surface 52 of the diamond layer 11, and the first bonding layer 13 is bonded to the second main surface 51 of the semiconductor layer 10.

The shape of the first recess 30 is preferably an inverted cone, an inverted truncated cone, an inverted pyramid, or an inverted truncated pyramid in order to obtain high coating properties of the first bonding layer 13 on the first recess 30. The depth of the first recess 30 is preferably 10 nm or more and 500 nm or less, taking into account the influence of the thickness of the first bonding layer 13.

The material for the first bonding layer 13 can be any of the following: silicon-based thin film, silicon carbide-based thin film, silicon nitride-based thin film, silicon oxide-based thin film, gallium oxide-based thin film, aluminum oxide thin film, Ti-based thin film, Ta-based thin film, Cu-based thin film, Au-based thin film, and Pt-based thin film, or a combination of two or more of these.

2, a second bonding layer 14 may be provided between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 in order to increase the bonding strength between the semiconductor layer 10 and the diamond layer 11. The second bonding layer 14 is provided on the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, and bonds the second main surface 51 and the third main surface 52. If the second bonding layer 14 is thick, it may cause parasitic components to be generated and the heat dissipation performance to be reduced, so the thickness is preferably 10 nm or less. As will be described later, the bonding strength between the semiconductor layer 10 and the diamond layer 11 is improved by the first bonding layer 13, so that a sufficient bonding strength can be obtained even if the second bonding layer 14 has a thickness of 10 nm or less. In order to increase the bonding strength, the second bonding layer 14 is preferably made of the same material as the first bonding layer 13.

A semiconductor device is formed on the first main surface 50 of the semiconductor layer 10. FIG. 3 shows an example in which a high electron mobility transistor (HEMT) is formed on the first main surface 50. Note that FIGS. 1 and 2 correspond to a cross section taken along line A1-A2 in FIG. 3. The HEMT is composed of electrodes such as a source electrode 20, a gate electrode 21, and a drain electrode 22.

Examples of materials for the semiconductor layer 10 include GaN, AlGaN, InAlN, AlN, SiC, Si, GaAs, _{and Ga2O3} . The semiconductor layer 10 may have a single-layer structure made of one of these materials, or a laminate structure made of multiple materials. The thickness of the semiconductor layer 10 is preferably 10.0 μm or less, but may exceed 10.0 μm.

The diamond layer 11 may be a single crystal diamond, a mosaic diamond in which multiple single crystal diamonds are joined laterally, or a polycrystalline diamond. The diamond layer 11 is preferably fabricated by the CVD (Chemical Vapor Deposition) method. The thickness of the diamond layer 11 is preferably 10 μm or more and 700 μm or less.

The materials of the source electrode 20, gate electrode 21, and drain electrode 22 may be a single metal element or an alloy. As a single metal element, an element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo may be used. As an alloy, AlSi, AlCu, AuGe, AuGa, AuSn, or the like may be used. In addition, the materials of the source electrode 20, gate electrode 21, and drain electrode 22 may be a laminate of any of the above materials.

A-2. Manufacturing method Figures 4 to 14 are diagrams showing a manufacturing method of the semiconductor device 100 according to the first embodiment. The manufacturing method of the semiconductor device 100 according to the first embodiment will be described below with reference to Figures 4 to 14. The manufacturing method of the semiconductor device 100 comprises a "first step" of processing the semiconductor layer 10, a "second step" of processing the diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and the diamond layer 11.

Explain the first step.

First, as shown in FIG. 4, a support layer 16 made of Si, SiC, GaN, or the like is prepared, and a semiconductor layer 10 is formed on the support layer 16 to produce a first semiconductor substrate 1a made of the semiconductor layer 10 and the diamond layer 11.

Next, as shown in FIG. 5, a source electrode 20, a gate electrode 21, and a drain electrode 22 are formed on the first major surface 50 of the semiconductor layer 10.

Next, as shown in FIG. 6, a separately prepared support substrate 2 is bonded to the first main surface 50 of the semiconductor layer 10 via an adhesive layer 17 to produce a second semiconductor substrate 3a, which is the first semiconductor substrate 1a to which the support substrate 2 is bonded. The support substrate 2 may be a glass substrate, a sapphire substrate, a Si substrate, or the like.

Then, as shown in FIG. 7, the support layer 16 is completely removed from the second semiconductor substrate 3a to expose the second main surface 51 of the semiconductor layer 10. The second main surface 51 of the semiconductor layer 10 is processed by grinding or polishing to flatten and smooth the surface shape. The smoothed second main surface 51 is processed to have a surface roughness Sa≦1.0 nm.

The second step will be explained.

First, as shown in FIG. 8, a diamond substrate 4a that will become the diamond layer 11 is prepared. Then, as shown in FIG. 9, the third main surface 52 of the diamond layer 11 is ground and polished to flatten and smooth the surface shape of the third main surface 52. The smoothed third main surface 52 is processed to have a surface roughness Sa≦1.0 nm.

Next, as shown in FIG. 10, a first recess 30 is formed in the ground and polished third main surface 52. The first recess 30 can be formed by selectively etching the third main surface 52 using an etching mask made of a patterned resist or metal mask. The etching method used may be, for example, etching by a thermochemical reaction with nickel, or dry etching using a reactive etching gas.

Next, as shown in FIG. 11, a first bonding layer 13 is formed on the third main surface 52 of the diamond substrate 4a on which the first recess 30 is formed, and the first bonding layer 13 is embedded in the first recess 30. The first bonding layer 13 is formed by a method such as plasma CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition. The first bonding layer 13 is formed to a thickness equal to or greater than the depth of the first recess 30, so that the first recess 30 is completely embedded in the first bonding layer 13.

Then, as shown in FIG. 12, using the third main surface 52 of the diamond substrate 4a as a guide, the first bonding layer 13 is polished by CMP (Chemical Mechanical Polishing) to remove the first bonding layer 13 on the third main surface 52, and to adjust the height of the surface of the first bonding layer 13 embedded in the first recess 30 to match the height of the third main surface 52. This flattens the surface of the third main surface 52.

The third step will now be described. In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded.

First, as shown in FIG. 13, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. Room temperature surface activation bonding or the like is used when bonding the second semiconductor substrate 3a and the diamond substrate 4a. When using the configuration of FIG. 2, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. The second bonding layer 14 is preferably made of the same material as the first bonding layer 13 in order to increase adhesion with the first bonding layer 13.

Then, as shown in FIG. 14, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a. In this way, the semiconductor device 100 having the structure shown in FIG. 1 or FIG. 2 is completed.

A-3. Effects In the semiconductor device 100 according to the first embodiment, the diamond layer 11 and the semiconductor layer 10 are bonded via the first bonding layer 13 embedded in the first recess 30. This increases the bonding surface area and the bonding layer thickness, and increases the bonding strength between the semiconductor layer 10 and the diamond layer 11 in the first recess 30.

The first bonding layer 13 between the semiconductor layer 10 and the diamond layer 11 can correct surface roughness and assist in bonding dissimilar substrates together through amorphous components, but the presence of the first bonding layer 13 may lead to the generation of parasitic components and reduced heat dissipation performance. For this reason, it is desirable to reduce the influence of the first bonding layer 13 as much as possible. In the semiconductor device 100 according to the first embodiment, the first bonding layer 13 is formed locally, thereby suppressing the influence of the first bonding layer 13. Therefore, the generation of parasitic components is prevented and the heat dissipation effect of the diamond layer 11 is sufficiently obtained.

B. Second embodiment
B-1. Configuration A semiconductor device 100 according to the second embodiment will be described. Fig. 15 is a diagram showing the configuration of the semiconductor device 100 according to the second embodiment. In Fig. 15, elements that are the same as or correspond to those shown in Fig. 1 are given the same reference numerals. Therefore, detailed description thereof will be omitted.

In the semiconductor device 100 according to the second embodiment, the diamond layer 11 does not have the first recessed portion 30 and the first bonding layer 13 shown in the first embodiment (FIG. 1), and instead the semiconductor layer 10 has a second recessed portion 31 and a third bonding layer 15 as shown in FIG. 15. The second recessed portion 31 is formed in the second main surface 51 of the semiconductor layer 10, and the third bonding layer 15 is densely embedded in the second recessed portion 31. The surface of the third bonding layer 15 forms the same plane as the second main surface 51 of the semiconductor layer 10, and the third bonding layer 15 is bonded to the third main surface 52 of the diamond layer 11.

The shape of the second recess 31 is preferably an inverted cone, an inverted truncated cone, an inverted pyramid, or an inverted truncated pyramid in order to improve the coating properties of the third bonding layer 15 on the second recess 31. The depth of the second recess 31 is preferably 10 nm or more and 500 nm or less, taking into account the effect of the thickness of the third bonding layer 15.

The third bonding layer 15 can be made of any of the following: silicon-based thin film, silicon carbide-based thin film, silicon nitride-based thin film, silicon oxide-based thin film, gallium oxide-based thin film, aluminum oxide thin film, Ti-based thin film, Ta-based thin film, Cu-based thin film, Au-based thin film, and Pt-based thin film, or a combination of two or more of these.

As shown in FIG. 16, a second bonding layer 14 may be formed between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 in order to increase the bonding strength. The second bonding layer 14 is provided on the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, and bonds the second main surface 51 and the third main surface 52. If the second bonding layer 14 is thick, it may cause parasitic components to be generated and the heat dissipation performance to be reduced, so the thickness is preferably 10 nm or less. As will be described later, the bonding strength between the semiconductor layer 10 and the diamond layer 11 is improved by the third bonding layer 15, so that sufficient bonding strength can be obtained even if the second bonding layer 14 is 10 nm or less in thickness. In order to increase the bonding strength, the second bonding layer 14 is preferably made of the same material as the third bonding layer 15.

B-2. Manufacturing method Figures 17 to 27 are diagrams showing a manufacturing method for the semiconductor device 100 according to the second embodiment. The manufacturing method for the semiconductor device 100 according to the second embodiment will be described below with reference to Figures 17 to 27. The manufacturing method for the semiconductor device 100 according to the second embodiment also includes a "first step" of processing the semiconductor layer 10, a "second step" of processing the diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and the diamond layer 11.

Explain the first step.

First, as shown in FIG. 17, a support layer 16 made of Si, SiC, GaN, or the like is prepared, and a semiconductor layer 10 is formed on the support layer 16 to produce a first semiconductor substrate 1a made of the semiconductor layer 10 and the diamond layer 11.

Next, as shown in FIG. 18, a source electrode 20, a gate electrode 21, and a drain electrode 22 are formed on the first major surface 50 of the semiconductor layer 10.

Next, as shown in FIG. 19, a separately prepared support substrate 2 is bonded to the first main surface 50 of the semiconductor layer 10 via an adhesive layer 17 to produce a second semiconductor substrate 3a, which is the first semiconductor substrate 1a to which the support substrate 2 is bonded. The support substrate 2 may be a glass substrate, a sapphire substrate, a Si substrate, or the like.

Next, as shown in FIG. 20, the support layer 16 is removed from the second semiconductor substrate 3a to expose the second main surface 51 of the semiconductor layer 10. Then, as shown in FIG. 21, a second recess 31 is formed in the exposed second main surface 51. The second recess 31 can be formed by selectively etching the second main surface 51 using an etching mask made of a patterned resist or a metal mask. The etching method may be, for example, etching by a thermochemical reaction with nickel, or dry etching using a reactive etching gas.

Next, as shown in FIG. 22, a third bonding layer 15 is formed on the second main surface 51 of the semiconductor layer 10 in which the second recess 31 is formed, and the third bonding layer 15 is embedded in the second recess 31. The third bonding layer 15 is formed by a method such as plasma CVD, sputtering, or vacuum deposition. The third bonding layer 15 is formed to a thickness equal to or greater than the depth of the second recess 31, so that the second recess 31 is completely embedded with the third bonding layer 15.

23, the second main surface 51 of the semiconductor layer 10 is processed by grinding or polishing to flatten and smooth the surface shape. The smoothed second main surface 51 is processed to have a surface roughness Sa≦1.0 nm. In addition, the third bonding layer 15 on the second main surface 51 is removed, and the surface height of the third bonding layer 15 embedded in the second recess 31 is adjusted to the height of the second main surface 51.

The second step will be explained.

First, as shown in FIG. 24, a diamond substrate 4a that will become the diamond layer 11 is prepared. Then, as shown in FIG. 25, the third main surface 52 of the diamond layer 11 is ground and polished to flatten and smooth the surface shape of the third main surface 52. The smoothed third main surface 52 is processed to have a surface roughness Sa≦1.0 nm.

The third step will now be described. In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded.

First, as shown in FIG. 26, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. Room temperature surface activation bonding or the like is used when bonding the second semiconductor substrate 3a and the diamond substrate 4a. When using the configuration of FIG. 16, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. The second bonding layer 14 is preferably made of the same material as the third bonding layer 15 in order to increase adhesion with the third bonding layer 15.

Then, as shown in FIG. 27, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a. In this way, the semiconductor device 100 having the structure shown in FIG. 15 or 16 is completed.

B-3. Effects In the semiconductor device 100 according to the second embodiment, the semiconductor layer 10 and the diamond layer 11 are bonded via the third bonding layer 15 embedded in the second recess 31. This increases the bonding surface area and the bonding layer thickness, and increases the bonding strength between the semiconductor layer 10 and the diamond layer 11 in the second recess 31.

In addition, in the semiconductor device 100 according to the second embodiment, the third bonding layer 15 is formed locally, so that the influence of the third bonding layer 15 is suppressed. This prevents the generation of parasitic components, and the heat dissipation effect of the diamond layer 11 is sufficiently obtained.

C. Third embodiment
C-1. Configuration A semiconductor device 100 according to the third embodiment will be described. Fig. 28 is a diagram showing the configuration of the semiconductor device 100 according to the third embodiment. In Fig. 28, elements that are the same as or correspond to those shown in Fig. 1 or Fig. 15 are given the same reference numerals. Therefore, detailed description thereof will be omitted.

In the semiconductor device 100 according to the third embodiment, the diamond layer 11 has a first recess 30 and a first bonding layer 13 on the second main surface 51, as in the first embodiment (FIG. 1), and the semiconductor layer 10 has a second recess 31 and a third bonding layer 15 on the third main surface 52, as in the second embodiment (FIG. 15). The first recess 30 and the second recess 31 are formed at positions where they overlap each other, and the first bonding layer 13 in the first recess 30 and the third bonding layer 15 in the second recess 31 are bonded on the same plane. The first bonding layer 13 and the third bonding layer 15 are preferably formed of the same material.

As shown in FIG. 29, a second bonding layer 14 may be formed between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 to increase the bonding strength. The second bonding layer 14 is provided on the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, and bonds the second main surface 51 and the third main surface 52. If the second bonding layer 14 is thick, it may cause parasitic components to be generated and the heat dissipation performance to be reduced, so the thickness is preferably 10 nm or less. Since the bonding strength between the semiconductor layer 10 and the diamond layer 11 is improved by the first bonding layer 13 and the third bonding layer 15, sufficient bonding strength can be obtained even if the second bonding layer 14 is 10 nm or less in thickness. In order to increase the bonding strength, the second bonding layer 14 is preferably made of the same material as the first bonding layer 13 and the third bonding layer 15.

C-2. Manufacturing method Hereinafter, a manufacturing method for the semiconductor device 100 according to the third embodiment will be described. The manufacturing method for the semiconductor device 100 according to the third embodiment also includes a "first step" of processing the semiconductor layer 10, a "second step" of processing the diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and the diamond layer 11.

The first step in embodiment 3 is the same as the first step in embodiment 2 (Figures 17 to 23).

The second step in the third embodiment is the same as the second step in the first embodiment (Figures 8 to 12).

In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded.

First, as shown in FIG. 30, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. At this time, the first recessed portion 30 and the second recessed portion 31 are aligned. When bonding the second semiconductor substrate 3a and the diamond substrate 4a, room temperature surface activation bonding or the like is used. When using the configuration of FIG. 29, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. The second bonding layer 14 is preferably made of the same material as the first bonding layer 13 and the third bonding layer 15 in order to increase adhesion with the third bonding layer 15.

Then, as shown in FIG. 31, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a. In this way, the semiconductor device 100 having the structure shown in FIG. 28 or FIG. 29 is completed.

C-3. Effects In the semiconductor device 100 according to the third embodiment, the semiconductor layer 10 and the diamond layer 11 are bonded via the first bonding layer 13 embedded in the first recess 30 and the third bonding layer 15 embedded in the second recess 31. The first recess 30 and the first bonding layer 13, and the second recess 31 and the third bonding layer 15 are provided at positions where they overlap each other, and the first bonding layer 13 and the third bonding layer 15 are bonded together. This increases the bonding surface area and the bonding layer thickness, and increases the bonding strength between the semiconductor layer 10 and the diamond layer 11 in the first recess 30 and the second recess 31.

In addition, in the semiconductor device 100 according to the second embodiment, the first bonding layer 13 and the third bonding layer 15 are formed locally, so that the influence of the first bonding layer 13 and the third bonding layer 15 is suppressed. This prevents the generation of parasitic components, and the heat dissipation effect of the diamond layer 11 is sufficiently obtained.

D. Fourth embodiment
32 and 33 are a cross-sectional view and a top view of a semiconductor device 100 according to the fourth embodiment. Fig. 32 is a cross-sectional view taken along the line A1-A2 in Fig. 33.

The basic structure of the semiconductor device 100 according to the fourth embodiment is the same as that of the first to third embodiments, but as shown in Figures 32 and 33, one or both of the first recessed portion 30 and the second recessed portion 31 are formed at a position away from directly below the conductive region 54 of the semiconductor layer 10 (a region that becomes a current path when a semiconductor device such as a transistor operates).

The positions of the first recess 30 and the second recess 31 are preferably at least 50 μm away from the current-carrying region 54 in order to reduce the effect on heat generation when current is passed through the semiconductor device, and more preferably at least 100 μm away from the current-carrying region 54.

Also, as shown in FIG. 34, one or both of the first recessed portion 30 and the second recessed portion 31 may extend to surround the conductive region 54.

D-2. Manufacturing Method The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device 100 according to the first to third embodiments only in the arrangement of the first recessed portion 30 or the second recessed portion 31. Therefore, the semiconductor device 100 according to the fourth embodiment can be formed by a method similar to the manufacturing method of the semiconductor device 100 according to the first to third embodiments.

D-3. Effects In the semiconductor device 100 according to the fourth embodiment, the first recessed portion 30 or the second recessed portion 31 is provided at a position away from directly below the current-carrying region 54 of the semiconductor device, and therefore the influence of heat generation during current flow is reduced, and the influence of parasitic components due to dissimilar materials between the substrates, leak paths, and the like on the semiconductor device can be suppressed.

Furthermore, by arranging the first recessed portion 30 or the second recessed portion 31 so as to surround the current-carrying region 54, the effects of localized stress can be broadly alleviated, and peeling in the region necessary for device operation can be suppressed.

In addition, it is possible to freely combine each embodiment, and to modify or omit each embodiment as appropriate.

The above description is illustrative in all respects, and it is understood that countless variations not illustrated may be envisioned.

1a first semiconductor substrate, 2 support substrate, 3a second semiconductor substrate, 4a diamond substrate, 10 semiconductor layer, 11 diamond layer, 12 support layer, 13 first bonding layer, 14 second bonding layer, 15 third bonding layer, 16 support layer, 17 adhesive layer, 20 source electrode, 21 gate electrode, 22 drain electrode, 30 first recess, 31 second recess, 50 first main surface, 51 second main surface, 52 third main surface, 53 fourth main surface, 54 current carrying region, 100 semiconductor device.

Claims (22)

a semiconductor layer having a first major surface and a second major surface;
a diamond layer having a third major surface and a fourth major surface;
a first recess formed in the third major surface of the diamond layer;
a first bonding layer embedded in the first recess;
Equipped with
the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer.
Semiconductor device. a second bonding layer provided on an entire bonding surface between the second main surface of the semiconductor layer and the third main surface of the diamond layer, bonding the second main surface and the third main surface;
The semiconductor device according to claim 1 . a second recess portion formed in the second major surface of the semiconductor layer;
a third bonding layer embedded in the second recess;
Further equipped with
the second recessed portion and the third bonding layer are provided at positions overlapping with the first recessed portion and the first bonding layer,
the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer and the third bonding layer.
3. The semiconductor device according to claim 1 or 2. a semiconductor layer having a first major surface and a second major surface;
a diamond layer having a third major surface and a fourth major surface;
a second recess portion formed in the second major surface of the semiconductor layer;
a third bonding layer embedded in the second recess;
Equipped with
the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the third bonding layer.
Semiconductor device. a second bonding layer provided across an entire bonding surface between the second main surface of the semiconductor layer and the third main surface of the diamond layer, bonding the second main surface and the third main surface;
The semiconductor device according to claim 4. The first bonding layer is composed of at least one of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film.
The semiconductor device according to claim 1 . The second bonding layer is composed of at least one of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film.
The semiconductor device according to claim 2 or 5. The third bonding layer is composed of at least one of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film.
The semiconductor device according to claim 3 . The second bonding layer has a thickness of 10 nm or less.
The semiconductor device according to claim 2, claim 5 or claim 7. The first recessed portion is formed in a shape of an inverted cone, an inverted truncated cone, an inverted pyramid, or an inverted truncated pyramid.
The semiconductor device according to claim 1, 2, 3 or 6. The shape of the second recessed portion is any one of an inverted cone, an inverted truncated cone, an inverted pyramid, and an inverted truncated pyramid.
The semiconductor device according to claim 3, 4, 5 or 8. The depth of the first recess is 10 nm or more and 500 nm or less.
The semiconductor device according to claim 1, 2, 3, 6 or 10. The depth of the second recess is 10 nm or more and 500 nm or less.
The semiconductor device according to claim 3, 4, 5, 8 or 11. The first recessed portion is formed at a position 50 μm or more away from the current-carrying region of the semiconductor layer.
The semiconductor device according to claim 1, 2, 3, 6, 10 or 12. The second recessed portion is formed at a position 50 μm or more away from the current-carrying region of the semiconductor layer.
The semiconductor device according to claim 3, 4, 5, 8, 11 or 13. The first recessed portion extends so as to surround a periphery of a current-carrying region of the semiconductor layer.
The semiconductor device according to claim 1, 2, 3, 6, 10, 12 or 14. The second recessed portion extends so as to surround a periphery of a current-carrying region of the semiconductor layer.
The semiconductor device according to claim 3, 4, 5, 8, 11, 13 or 15. A step of forming a semiconductor layer having a first main surface and a second main surface on a support layer such that the second main surface is connected to the support layer, thereby fabricating a first semiconductor substrate including the support layer and the semiconductor layer; and
removing the support layer from the first semiconductor substrate and grinding and polishing the second main surface of the semiconductor layer;
A first step comprising:
providing a diamond layer having a third major surface and a fourth major surface, and grinding and polishing the third major surface to make it flat and smooth;
forming a first recessed portion in the third main surface;
forming a first bonding layer on the third main surface and embedding the first bonding layer in the first recess; and
a step of polishing the first bonding layer using the second main surface as a guide to remove the first bonding layer on the third main surface and aligning a height of a surface of the first bonding layer embedded in the first recessed portion to a height of the third main surface;
A second step comprising:
bonding the third major surface of the diamond layer to the second major surface of the semiconductor layer;
A third step comprising:
A method for manufacturing a semiconductor device comprising the steps of: The third step further comprises:
forming a second bonding layer on the third major surface of the diamond layer;
Including,
the third main surface of the diamond layer and the second main surface of the semiconductor layer are bonded via the second bonding layer;
The method for manufacturing a semiconductor device according to claim 18. The first step further comprises:
forming a second recessed portion in the second main surface;
forming a third bonding layer on the second main surface and embedding the third bonding layer in the second recess; and
a step of removing the third bonding layer on the second main surface by grinding and polishing the second main surface on which the third bonding layer is formed, and adjusting the height of a surface of the third bonding layer embedded in the second recessed portion to the height of the second main surface;
Including,
the second recessed portion and the third bonding layer are provided at positions that overlap the first recessed portion and the first bonding layer when the diamond layer and the semiconductor layer are bonded in the third step.
The method for manufacturing a semiconductor device according to claim 18 or 19. A step of forming a semiconductor layer having a first main surface and a second main surface on a support layer such that the second main surface is connected to the support layer, thereby fabricating a first semiconductor substrate including the support layer and the semiconductor layer;
removing the support layer from the first semiconductor substrate and forming a second recessed portion in the second main surface;
forming a third bonding layer on the second main surface and embedding the third bonding layer in the second recess; and
a step of removing the third bonding layer on the second main surface by grinding and polishing the second main surface on which the third bonding layer is formed, and adjusting the height of a surface of the third bonding layer embedded in the second recessed portion to the height of the second main surface;
A first step comprising:
providing a diamond layer having a third major surface and a fourth major surface, and grinding and polishing the third major surface to make it flat and smooth;
A second step comprising:
bonding the third major surface of the diamond layer to the second major surface of the semiconductor layer;
A third step comprising:
A method for manufacturing a semiconductor device comprising the steps of: The third step further comprises:
forming a second bonding layer on the third major surface of the diamond layer;
Including,
the third main surface of the diamond layer and the second main surface of the semiconductor layer are bonded via the second bonding layer;
The method for manufacturing a semiconductor device according to claim 21 .

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