WO2025013193A1 - Quantum device control system - Google Patents

Abstract

A quantum device control system for controlling a quantum operation in a quantum bit array in which a plurality of quantum bits are arranged one-dimensionally or two-dimensionally includes: a sequence control unit for controlling a sequence of quantum operations; a command memory for storing a command for controlling each quantum bit in the quantum bit array; and a parameter memory for storing a variable unique to each quantum bit in the quantum bit array. The sequence control unit acquires the command from the command memory, acquires a variable unique to each quantum bit from the parameter memory, and constructs a sequence of quantum operations, and the parameter memory can be rewritten according to characteristics of each quantum bit.

Description

Quantum Device Control System

The present invention relates to a quantum device control system.

The performance improvement achieved by miniaturizing semiconductor elements, which has supported the progress of computers for over half a century, is expected to reach its limit in the near future due to the comparison between process rules and the atomic distance of silicon. Quantum computers are an attempt to overcome this limit with new calculation principles and devices, and quantum devices and calculation methods using superconducting circuits, ion traps, photons, silicon quantum dots, etc. have been proposed. In addition, as a preliminary step to the future concept of running large-scale, practical applications on an error-tolerant general-purpose quantum computer system, progress is currently being made in proving the principle and exploring algorithms for a system called NISQ (Noisy Intermediate-Scale Quantum Device), which is based on the concept that the number of quantum bits is small, around 100, and error correction is not possible.

To realize a quantum computer system that uses quantum devices that operate on quantum effects that become evident at extremely low temperatures, such as the spin of a single electron in a silicon quantum dot, it is customary to choose a dilution refrigerator as the device to incorporate it into. In this case, the quantum device is fixed in thermal contact with the mixing chamber, which is the coldest part of the dilution refrigerator, and the quantum device is controlled by applying a control signal generated by the control device to the quantum device, thereby performing quantum calculations.

JP 2022-10223 A JP 2022-100226 A

It is known that elements that hold quantum information, such as silicon qubits in quantum devices, can change in characteristics due to changes in the environment, and even if the same control signal is applied to the same quantum device, different quantum calculations will be performed due to changes in characteristics. Patent Document 1 discloses a calibration method for adjusting the parameter values of a control signal to reduce one or more of quantum gate leakage, non-fidelity, etc., thereby making it possible to perform a desired quantum calculation by correcting changes in characteristics. However, it does not disclose a process for generating a control signal from the adjusted parameter values. Patent Document 2 discloses a process for generating a sequence (control signal) from parameters, but there is a problem in that the entire control sequence needs to be regenerated (compiled) from the parameters, resulting in a high processing load for generating the control signal.

The present invention has been made to solve the above problems, and the object of the present invention is to provide a quantum device control system that generates control signals while realizing, with a low processing load, changes in parameters required for calibration, which corrects changes in element characteristics.

A preferred aspect of the present invention is a quantum device control system for controlling quantum operations in a quantum bit array in which multiple quantum bits are arranged one-dimensionally or two-dimensionally, the system comprising a sequence control unit for controlling a sequence of quantum operations, a command memory for storing commands for controlling each quantum bit in the quantum bit array, and a parameter memory for storing variables specific to each quantum bit in the quantum bit array, the sequence control unit acquiring the commands from the command memory and acquiring the variables specific to each quantum bit from the parameter memory to construct a sequence of quantum operations, and the parameter memory being rewritable according to the characteristics of each quantum bit.

According to one aspect of the present invention, it is possible to provide a quantum device control system that generates control signals while realizing parameter changes required for calibration, which is the correction of changes in element characteristics, with a low processing load. Problems, configurations, and effects other than those described above will be made clear through the explanation of the following examples.

1 is a block diagram showing a configuration of a quantum device control system according to a first embodiment of the present invention. FIG. 1 is a diagram showing an example of a circuit configuration of a quantum dot array in which a plurality of quantum dots are arranged two-dimensionally. FIG. 4 is a diagram showing an example of a detailed configuration of a bias control switch. FIG. 4 is a diagram showing an example of a driving signal for a quantum dot array. FIG. 4 is a diagram showing an example of a configuration of data stored in a command memory; FIG. 4 is a diagram showing an example of a command format of command data. FIG. 4 is a diagram showing an example of the configuration of data stored in a parameter memory. FIG. 4 is a diagram showing an example of data stored in a command memory; FIG. 4 is a diagram showing an example of data stored in a parameter memory. FIG. 11 is a diagram showing an example of a calibration flowchart. FIG. 13 is a diagram showing an example of an input/output screen for calibration. FIG. 4 is a diagram showing an example of a command memory. FIG. 11 is a block diagram showing a configuration of a quantum device control system according to a second embodiment of the present invention. FIG. 4 is a diagram showing an example of the configuration of data stored in a sequence memory; FIG. 4 is a diagram showing an example of a configuration of data stored in a template memory; FIG. 4 is a diagram showing an example of the configuration of data stored in a parameter memory. FIG. 11 is a block diagram showing a configuration of a quantum device control system according to a third embodiment of the present invention. FIG. 13 is a block diagram showing a configuration of a quantum device control system according to a fourth embodiment of the present invention. FIG. 13 is a diagram showing an example of a flowchart of calibration according to a fourth embodiment of the present invention.

Below, examples of the present invention will be described in detail with reference to the drawings. Note that the following description is intended to explain one embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, a person skilled in the art could adopt an embodiment in which each or all of these elements are replaced with equivalents, and these embodiments are also within the scope of the present invention.

In the configurations of the embodiments described below, the same parts or parts having similar functions are designated by the same reference numerals in different drawings, and duplicate descriptions may be omitted.

When there are multiple elements with the same or similar functions, they may be described using the same reference numeral with different subscripts. However, when there is no need to distinguish between multiple elements, the subscripts may be omitted.

In this specification, the designations "first," "second," "third," and the like are used to identify components, and do not necessarily limit the number, order, or content. Furthermore, numbers for identifying components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, there is no prohibition on a component identified by a certain number also serving the function of a component identified by another number.

The position, size, shape, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, shape, range, etc., in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings, etc.

　Publications, patents, and patent applications cited in this specification are incorporated herein by reference.

In this specification, elements expressed in the singular include the plural unless the context clearly indicates otherwise.

A representative example of an embodiment is as follows. That is, in a quantum device control system for controlling quantum operations in a quantum bit array in which multiple quantum bits are arranged one-dimensionally or two-dimensionally, the system includes a sequence control unit for controlling the sequence of quantum operations, a command memory for storing commands for controlling each quantum bit in the quantum bit array, and a parameter memory for storing variables specific to each quantum bit in the quantum bit array, the sequence control unit obtains the commands from the command memory and obtains the variables specific to each quantum bit from the parameter memory to construct a sequence of quantum operations, and the parameter memory is rewritable according to the characteristics of each quantum bit.

FIG. 1 is a block diagram showing the configuration of a quantum device control system 1 according to a first embodiment of the present invention.

The quantum device control system 1 comprises a host PC (Personal Computer) 100, a control device 110, and a quantum device 120. In this embodiment, the quantum device 120 that executes quantum computation is systemized by combining the host PC 100 that manages the entire quantum computation sequence, and the control device 110 that generates control signals for the quantum device 120 based on commands received from the host PC 100 and acquires the computation results.

The quantum device 120 includes an element that holds quantum information. For example, this may be a quantum dot, a superconducting circuit, an ion trap structure, or a structure that holds photons. The element that holds quantum information may have a structure of a quantum bit array arranged in a one-dimensional or two-dimensional shape. In this embodiment, a quantum bit array in which multiple silicon quantum dots are connected in a two-dimensional shape is used as an example for explanation, but the present invention is not limited to this, and it is also possible to have the structure of the superconducting circuit described above or a quantum bit array arranged in a one-dimensional shape.

The host PC 100 is usually placed in a room temperature environment (e.g., 20°C). On the other hand, the quantum device 120 is placed in an extremely low temperature environment (e.g., -273°C) realized by the mixing chamber, which has the lowest temperature in the dilution refrigerator, to enable the operation of the quantum bit. The other components are placed between the room temperature environment and the extremely low temperature environment. In this case, the temperature gradient changes from high to low along the flow of the signal from the host PC 100 to the quantum device 120. For example, the semiconductor chip that constitutes the quantum device 120 is placed in an extremely low temperature environment, and the semiconductor chip that constitutes the control device 110 is placed in an environment that is lower than the room temperature environment (but not the extremely low temperature environment in which the quantum bit operates). However, if the cooling capacity of the mixing chamber is sufficiently high, the control device 110 and the quantum device 120 may be composed of the same semiconductor chip and the entire device may be placed in an extremely low temperature environment.

The host PC 100 is a general information processing device equipped with a microprocessor, memory, storage device, input device, output device, etc. (not shown), and is assumed to run a system control application that manages the overall control of the quantum operation sequence to be executed by the quantum device control system 1.

The system control application interprets the specified quantum operation sequence and supplies the commands and various control information required for the quantum operation to the control device 110 via the host interface 101, while acquiring the quantum operation results read from the quantum device 120. Here, the host interface 101 may be an interface based on standard communication specifications such as USB (trademark), SPI (trademark), I2C (trademark), RS-232C, PCI Express (trademark), Ethernet (trademark), etc., or may be an interface with a unique specification based on a general-purpose input/output port.

The control device 110 includes a host interface unit 111, a sequence control unit 112, a command memory 113, a parameter memory 114, a control signal generation unit 115, and a signal measurement unit 116.

The host interface unit 111 controls communication with the host PC 100 connected via the host interface 101. The host interface unit 111 also communicates various signals between the sequence control unit 112, the command memory 113, the parameter memory 114, and the signal measurement unit 116.

The sequence control unit 112 generates a signal for driving the control signal generation unit 115 by referring to the command memory 113 and parameter memory 114 in accordance with the control signal from the host interface unit 111, and transmits the signal to the control signal generation unit 115.

Command memory 113 stores commands that control quantum device 120. For example, if quantum device 120 includes a quantum bit array, command memory 113 stores commands that control each quantum bit in the quantum bit array.

Parameter memory 114 stores variables specific to quantum device 120. For example, if quantum device 120 includes a qubit array, parameter memory 114 stores variables specific to each qubit in the qubit array.

The control signal generating unit 115 is composed of, for example, a bias voltage generating unit consisting of multiple channel voltage sources that operate independently, a bias voltage switching control unit that selects the bias voltage applied to the bias voltage control lines provided for each quantum bit in the quantum device 120 and controls the switching of the selected state, an arithmetic radio frequency generating unit that generates a radio frequency signal that controls the spin rotation of a single electron confined within the quantum bit, and a timing control unit required for time control between various processes. The control signal generating unit 115 transmits to the quantum device 120 a quantum device control signal 117 generated by at least one of the timing control unit, bias voltage switching control unit, bias voltage generating unit, and arithmetic radio frequency generating unit. The quantum device control signal 117 is, for example, at least one of a bias voltage drive signal and an RF signal that drive the quantum bit array, and more specifically, a signal that is multiplied onto a bias voltage supply line 143 that transmits a voltage signal generated by a bias voltage generation unit, a bias voltage switching strobe 141 and a bias voltage control register setting value 142 that are generated by a bias voltage switching control unit, and a signal that is multiplied onto an RF signal line 132 that transmits a signal generated by a radio frequency generation unit for calculation.

The quantum device 120 includes a quantum operation unit control unit (not shown) and a quantum operation unit.

The quantum operation control unit temporarily stores at least a portion of the control information input from the control signal generation unit 115 via the quantum device control signal 117, and switches the application state of the quantum operation unit control signal, which includes a bias voltage control line and a high frequency signal for operation, and which serves as a direct control signal for each quantum bit of the quantum operation unit, based on the strobe signal included in the quantum device control signal 117. The quantum operation unit control signal is, for example, a signal multiplied by the quantum dot array applied bias voltage control line 131 or a signal multiplied by the RF signal line 132.

The quantum computing unit includes, for example, a quantum bit array in which multiple quantum bits are arranged one-dimensionally or two-dimensionally. The quantum computing unit executes quantum operations based on the application state of the quantum computing unit control signal, and outputs quantum computing unit output signal 121 including the quantum computing result. Here, the quantum computing result is, for example, the observed spin state of a single electron confined in a quantum bit, converted into a binary value that identifies 0 or 1 in a classical computer. The computing unit output signal 121 may be a binary value or an analog value.

The signal measurement unit 116 measures the quantum computation unit output signal 121 received from the quantum device 120 and transmits the measurement result to the host interface unit 111. The host PC 100 receives the measurement result via the host interface 101.

Figure 2 shows an example of the circuit configuration of a two-dimensionally arranged quantum dot array. A quantum bit is realized by confining a single electron within a potential barrier formed in a silicon channel of a MOS structure, and the array structure has multiple quantum dots arranged in a two-dimensional lattice via transfer gates that control the movement and interaction of electrons between quantum dots. Each quantum dot is assigned coordinates that specify its position in the X (horizontal) and Y (vertical) directions within the array.

The quantum dot array applied bias voltage control lines 131 include bias control line XQ for gate control of the quantum dot control gate MOS arranged in the X direction, bias control line YQW-YQE for gate control of the quantum dot control gate MOS arranged in the Y direction, bias control line XJN-XJS for gate control of the transfer gate MOS that connects the quantum dots in the X direction, and bias control line YJW-YJE for gate control of the transfer gate MOS that connects the quantum dots in the Y direction.

By applying a magnetic field to a quantum dot in which a single electron is trapped, and then irradiating it with a high frequency wave that coincides (resonates) with the precession of the electron spin, which is determined by the strength of the magnetic field, the electron spin rotates and a quantum operation can be performed. However, in a quantum dot array containing multiple quantum dots, a means is required to select or deselect the quantum dots that are the subject of the quantum operation. Specifically, for example, a method is envisaged in which a local magnetic field is generated by the current that flows by appropriately controlling the bias voltage of a bias voltage control line, and the strength of the magnetic field at each quantum dot position is locally modulated, resulting in a minute shift in the resonant frequency of the precession of the electron spin. In this case, a high frequency wave that coincides with the resonant frequency of the quantum dot in the selected state is input from the RF signal line 132, so that only the selected quantum dots selectively perform quantum operations.

FIG. 3 is a diagram showing an example of a detailed configuration of a typical bias control switch included in the bias voltage switching switch matrix 140 provided in the quantum operation unit control unit. Bias control switches XJN[i], XJS[i], YJW[k], and YJE[k] are connected to the quantum dot array applied bias voltage control line 131, which are independent for each control target. When each bias control switch detects the bias voltage switching timing indicated by the bias voltage switching strobe 141, it internally latches the setting value (binary, or a bitmap obtained by decoding the binary) related to its own switch from the bias voltage control register setting value 142. Next, by selecting one of at least some of the supply lines of the bias voltage supply line 143 specified by the setting value after latching, a bias voltage having a voltage value reflecting the setting value is output from the quantum dot array applied bias voltage control line 131.

FIG. 4 shows an example of a drive signal for a quantum dot array. Specifically, it shows an example of the bias voltage to be applied from the quantum dot array applied bias voltage control line 131 and the period during which high frequency should be input from the RF signal line 132 when executing a specific quantum operation (command) for one quantum dot in the quantum dot array.

Here, symbols such as VL, VL1s, VL1n, VL3w, and VL4e are bias voltage codes, and indicate the state in which the bias voltage identified by the code is applied to the bias voltage control line. Note that the RF signal is simply shown only for the period when high frequency is input, but normally it should be a waveform with an envelope designed to suppress as much as possible the loss of fidelity that occurs with the execution of commands.

Quantum computers, which are based on the extremely low temperature environment realized by a dilution refrigerator, not only have strict power consumption requirements for quantum devices, but also have unique constraints that differ from classical computers. Specifically, the wiring connecting the inside and outside of the dilution refrigerator not only transmits power and signals, but also serves as a medium for thermal conduction, meaning that only a minimum number of wiring can be laid, determined by the balance between the target temperature of the mixing chamber and the cooling capacity of the dilution refrigerator, and because these wiring runs over long distances, the transmission speed is inevitably limited.

In addition, quantum computers are subject to discontinuous changes in the characteristics of quantum devices due to temperature cycles, and continuous time fluctuations in the control output due to the circuit characteristics or implementation design of the control device that controls the quantum device. Due to the influence of these factors, the optimal control parameter values for achieving the desired quantum operation must be experimentally determined prior to the actual quantum operation, and may also change over time. This is an essential difference from classical computers, and requires a process known as calibration, in which optimal control parameter values are set as appropriate. In other words, even when controlling the same quantum bits placed in a quantum device, the control sequence must be changed due to changes in variation over time.

Next, we will explain the configuration of this embodiment, which generates a control signal while achieving parameter changes required for calibration with a low processing load.

FIG. 5 is a diagram showing an example of the configuration of data stored in the command memory 113. The command memory 113 is composed of registers to which an address is assigned for each predetermined bit. Command data is stored in the register at each address. The bit length of the command data can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, etc. The address number may be assigned so that it increases or decreases by 1 for every 8 bits of command data, or it may be assigned so that it increases or decreases by 1 for each bit length of the command data. FIG. 5 shows a case where addresses are assigned as integers in order starting from 0 for each bit length of the command data.

FIG. 6 shows an example of a command format 500 of command data.

Rate information specification field (501, RATE): This field specifies the rate information corresponding to the execution time of the command.

Operation information specification field (502, OPR): A field for specifying the operation content of the command. Although not particularly limited, examples of the operation content include operations related to each function corresponding to the primitive control signal generated by the control signal generation unit 115, i.e., voltage setting of the bias voltage generation unit consisting of a voltage source of multiple channels operating independently, setting of selection control information of the bias voltage applied to each bias voltage control line, setting of the waveform envelope of the high frequency signal for calculation, switching of the bias voltage application state, output gating of the high frequency signal for calculation, and generation of various strobe signals that indicate the timing of reading and storing the calculation results. In addition, examples of operation content that supports sequence control and calibration processing may include operations related to notification indicating that it is the final command of the quantum calculation sequence (command string), and initialization operation of the quantum bit or at least a part of the control signal to the quantum bit.

External parameter selection field (503, EXT): This field selects whether the control parameters required to execute the command are specified in the parameter specification field 504 within the command, or by referencing the parameter memory 114.

Parameter specification field (504, PARAM): This field specifies either the immediate value of the control parameter required to execute the command, or a reference (address number) to the control parameter stored in the parameter memory 114. Depending on the contents of the external parameter selection field 503, this field is set to either an immediate value or a reference.

FIG. 7 is a diagram showing an example of the configuration of data stored in the parameter memory 114. The parameter memory 114 is composed of registers to which an address is assigned for each predetermined number of bits. Parameter data is stored in the registers at each address. The bit length of the parameter data can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, etc. Address numbers may be assigned so that they increase or decrease by 1 for every 8 bits of parameter data, or they may be assigned so that they increase or decrease by 1 for each bit length of the parameter data. FIG. 7 shows a case where addresses are assigned as integers in order starting from 0 for each bit length of the parameter data.

When the sequence control unit 112 receives a command execution command from the host PC 100, it refers to the command memory 113 and the parameter memory 114 and starts executing the command. Specifically, when the sequence control unit 112 receives a command execution command from the host PC 100, it obtains command data 0 stored in address number 0 from the command memory 113 and executes the command stored in the command data 0. At that time, if the external parameter selection field 503 indicates that the control parameters required for the execution of the command are specified by immediate values in the command, the sequence control unit 112 uses the control parameters stored in the parameter specification field 504. If the external parameter selection field 503 indicates that the parameter memory 114 is to be referenced, the sequence control unit 112 obtains the parameter data stored in the address number specified in the parameter specification field 504 from the parameter memory 114 and uses the control parameters stored in the parameter data. After completing the execution of the command data with address number 0, the sequence control unit 112 increases the address number of the command data to be executed by a predetermined value and then proceeds to execute the address number.

In the above, the sequence control unit 112 is described as obtaining command data from address number 0 of the command memory 113 and executing them in order, but the present invention is not limited to this. For example, the control device 110 may be configured to have a start address register, the sequence control unit 112 obtains an address number from which execution starts from the start address register, and the sequence control unit 112 executes from the command data of the address number in the command memory 113. The host PC is configured to be able to rewrite the start address register via the host interface 101. By using it in combination with the operation information designation field 502 indicating that it is the final command of the quantum operation sequence (command string), it is possible to start command execution from the middle of the command memory 113 and end command execution in the middle of the command memory 113. This makes it possible to store multiple types of command sequences in the command memory in advance, and by starting command execution after setting the start address register, it is possible to selectively execute multiple types of command sequences without rewriting the command memory 113.

As mentioned above, in a quantum computer, even when controlling the same quantum bit placed in a quantum device, it is necessary to change the control sequence due to changes in variance over time. In this embodiment, the parameters in the control sequence that must be changed due to changes in variance over time are stored in a parameter memory.

For example, among the parameters of each function corresponding to the primitive control signal generated by the control signal generating unit 115, the voltage setting parameters of the bias voltage generating unit consisting of multiple channel voltage sources operating independently (voltage setting parameters of the bias voltage supply line 143) and the setting parameters of the waveform of the high frequency signal for calculation (amplitude, phase, frequency, duration such as full width at half maximum or half width at half maximum, envelope, etc.) may change due to changes in variation over time, and these parameters are configured to be stored in the parameter memory.

Parameters that do not change with time or are only slightly affected by the change in variance with time and do not require changes to the control sequence may be configured to be stored in the parameter memory, or may be configured to be stored directly in the parameter designation field 504 without referencing the parameter memory 114.

For example, among the parameters of each function corresponding to the primitive control signal generated by the control signal generating unit 115, the setting parameter (bias voltage control register setting value 142) for the selection control information of the bias voltage applied to each bias voltage control line and the timing parameter for switching the bias voltage application state are less affected by changes in variability over time. For this reason, they may be configured to be stored directly in the parameter designation field 504 without referencing the parameter memory 114.

FIG. 8A is a diagram showing an example of data stored in the command memory in this embodiment. FIG. 8B is a diagram showing an example of data stored in the parameter memory in this embodiment.

In address numbers 0 to 7 in FIG. 8A, the voltage setting parameters for the bias voltage supply line 143 are set. These parameters may change due to variations over time, and are configured to be stored in a parameter memory, with the command memory referencing address numbers 0 to 7 of the parameter memory.

In FIG. 8A, addresses 8 to 15 and 17 to 24 set the bias voltage control register setting value 142. Additionally, addresses 16 and 25 set the bias voltage switching strobe 141. These parameters are not affected by variations over time, so the setting values are stored directly in the PARAM of the command memory.

Next, the calibration procedure in this embodiment will be described. Calibration in this embodiment can be achieved by scanning variables specific to each quantum bit within a predetermined range and rewriting the data in the parameter memory 114 based on the measurement results of the signal measurement unit 116.

FIG. 9 is a diagram showing an example of a calibration flow chart in this embodiment. FIG. 9 shows an example of performing calibration of the voltage setting parameters (voltage of bias voltage supply line 143) of a bias voltage generating unit consisting of multiple channels of voltage sources that operate independently, among the parameters of each function corresponding to the primitive control signal generated by the control signal generating unit 115.

First, the quantum device control system 1 changes the setting value of the applied voltage on the predetermined bias voltage supply line 143 to a predetermined value (step 201). Specifically, for example, the host PC 100 sends a command to the control device 110 to change the voltage setting parameters of the bias voltage generation unit and change the setting value of the applied voltage on the predetermined bias voltage supply line 143 to a predetermined value. More specifically, the host PC 100 writes a command to the command memory 113 to change the setting value of the applied voltage on the predetermined bias voltage supply line 143 to a predetermined value, and then sends a command to the sequence control unit 112 to execute the sequence. The sequence control unit 112 executes the command written in the command memory 113 to send a command to the control signal generation unit 115, and the control signal generation unit 115 can change the voltage value on the predetermined bias voltage supply line 143 to a predetermined value in accordance with the command.

In another aspect of the present invention, the control signal generating unit 115 can be configured to be capable of communicating with the host interface unit 111, and the host PC 100 can be configured to send a command to the control signal generating unit 115 via the host interface unit 111 to change the voltage value on the specified bias voltage supply line 143 to a specified value. This can simplify the procedure for changing the voltage value on the specified bias voltage supply line 143.

Next, the quantum device control system 1 acquires data (step 202). Specifically, for example, the host PC 100 sends a command to the signal measurement unit 116 of the control device 110 to measure the quantum operation unit output signal 121. The signal measurement unit 116 measures the quantum operation unit output signal 121 in accordance with the command. The host PC 100 commands the signal measurement unit 116 to transmit the measurement result. The signal measurement unit 116 returns the measurement result to the host PC 100 in accordance with the command.

Next, the host PC 100 of the quantum device control system 1 determines whether to end the voltage scan (step 203). If the voltage scan is not to be ended (step 203; No), the set value of the output voltage is changed by a predetermined value and execution is repeated from step 201.

If the voltage scan is to be terminated (step 203; Yes), the host PC 100 determines the optimal setting value for the voltage output value based on the voltage setting value in step 201 and the data acquired in step 202 (step 204).

Finally, the determined optimal setting value for the voltage output value is written to a register in parameter memory 114 that stores the voltage setting parameters of the bias voltage generating unit (step 205). This completes the calibration of the voltage setting parameters of the bias voltage generating unit.

In the example of the command memory 113 and parameter memory 114 shown in Figures 8A and 8B, if we show an example of calibrating the VL1s voltage, calibration can be achieved by changing the VL1s voltage in step 201 and rewriting the parameter data at address number 0 in the parameter memory in step 205.

FIG. 10 is a diagram showing an example of an input/output screen 210 for calibration. The input/output screen 210 includes a button 211 and a display area 212. The input/output screen 210 is, for example, a part of a display screen displayed by the host PC 100.

When a user of quantum device control system 1 clicks button 211A, quantum device control system 1 starts the calibration flow. Once the calibration flow is started, the progress is displayed in display area 212A. Once acquisition of calibration data is complete, the calibration result is displayed in display area 212B. This displayed value is the value determined in step 204. When a user of quantum device control system 1 clicks button 211B, the value of the calibration result is written to the parameter memory. This corresponds to step 205.

In the above, it has been described that the calibration result values are written to the parameter memory when the user of the quantum device control system 1 clicks button 211B, but the present invention is not limited to this. For example, the quantum device control system 1 may not have button 211B, and may be configured to automatically write the values to the parameter memory in step 205 after the optimal setting values are determined in step 204. This allows for further automation of the calibration.

According to this embodiment, parameters specific to each quantum bit, which require a change in the control sequence due to a change in the variation over time, are stored in the parameter memory 114, and the data stored in the parameter memory 114 is rewritten by calibration. For example, a quantum device control system (e.g., control device 110) that controls quantum operations in a quantum bit array in which quantum bits are arranged one-dimensionally or two-dimensionally includes a sequence control unit 112 that controls the sequence of quantum operations, a command memory 113 that stores commands to control each quantum bit in the quantum bit array, and a parameter memory 114 that stores variables specific to each quantum bit in the quantum bit array, and the sequence control unit 112 obtains the commands from the command memory 113 and obtains the variables specific to each quantum bit from the parameter memory 114 to construct the quantum operation sequence, and the parameter memory 114 is rewritable according to the characteristics of each quantum bit. This makes it possible to provide a quantum device control system that generates control signals while realizing the change in parameters required for calibration, which is a correction for changes in element characteristics, with a low processing load.

Furthermore, a control signal generating unit 115 is provided which generates a control signal for the quantum bit array, and the sequence of quantum operations is a sequence of signals which drive the control signal generating unit 115, and the sequence control unit 112 generates signals which drive the control signal generating unit 115 and transmits them to the control signal generating unit 115. This makes it possible to control the control signal generating unit 115 in response to instructions from the sequence control unit 112.

The control signal generating unit 115 also generates at least one of a bias voltage drive signal or an RF signal that drives the quantum bit array. This allows the control signal generating unit 115 to generate at least a control signal for driving the quantum bit array, such as a bias voltage drive signal or an RF signal, in response to an instruction from the sequence control unit 112.

Furthermore, the variable specific to each quantum bit in the quantum bit array may be at least one of the parameters specifying the bias voltage drive signal or the parameters specifying the RF signal. This allows the parameters specifying the bias voltage drive signal and the parameters specifying the RF signal to be defined as variables specific to each quantum bit.

The parameter specifying the bias voltage drive signal may be a bias voltage, a bias voltage switching strobe, or a bias voltage control register setting value. This allows the bias voltage, the bias voltage switching strobe, or the bias voltage control register setting value to be output as the bias voltage drive signal.

The parameter specifying the RF signal may be at least one of the amplitude, phase, frequency, duration, or envelope of the RF signal. This makes it possible to output an RF signal with the amplitude, phase, frequency, duration, or envelope of the RF signal as a parameter.

The quantum device control system 1 also includes a signal measurement unit 116, which measures the signal output from the quantum bit array. The signal measurement unit 116 also scans variables specific to each quantum bit within a predetermined range, and rewrites the data in the parameter memory based on the measurement results of the signal measurement unit 116. This allows the data in the parameter memory 114 to be rewritten based on the measurement results of the signal output from the quantum bit array measured by the signal measurement unit 116, making it possible to calibrate voltage setting parameters, for example.

The quantum device control system 1 further comprises a host PC 100, a control device 110 including the sequence control unit 112, the command memory 113, the parameter memory 114, and the signal measurement unit 116, and a quantum device including the quantum bit array, and the signal measurement unit 116 measures the signal output from the quantum bit array based on a command from the host PC 100. This makes it possible to measure the signal output from the quantum bit array at a timing desired by the user.

In the second embodiment, the command memory 113 is configured to include a sequence memory 301 and a template memory 302. Note that in the second embodiment, differences from the previous embodiment will be mainly described, and the same components as those in the previous embodiment will be given the same reference numerals, and descriptions of these will be omitted.

11 is a diagram showing an example of the command memory 113 in the configuration of the first embodiment when the same control is performed on two adjacent quantum bits in the quantum bit array. Address numbers 0 to 7 in the command memory 113 shown in FIG. 11 are command data that refer to the parameter memory. Address numbers 8 to 25 are command data that control the first quantum bit in the quantum bit array. Address numbers 26 to 43 are command data that control the second quantum bit adjacent to the first quantum bit in the quantum bit array. FIG. 11 illustrates a case where the second quantum bit is adjacent to the first quantum bit in the X direction. As shown in FIG. 11, when the same control is performed on adjacent quantum bits, the control sequence executed by the quantum device control system 1 is a control sequence that differs only in the field required to identify the target quantum bit. In other words, when the same control is performed on two different quantum bits in a quantum bit array in which quantum bits are arranged in a one-dimensional or two-dimensional shape, the control sequences are generally the same, but slightly different control sequences are required due to differences in the wiring to be accessed and variations in the quantum bits.

FIG. 12 is a block diagram showing the configuration of a quantum device control system 1A according to a second embodiment of the present invention. In the quantum device control system 1A, the command memory 113 includes a sequence memory 301 and a template memory 302.

The host interface unit 111 communicates various signals between the sequence memory 301 and the template memory 302.

The sequence control unit 112 refers to the sequence memory 301, template memory 302, and parameter memory 114 in accordance with the control signal from the host interface unit 111, generates a signal for driving the control signal generation unit 115, and transmits it to the control signal generation unit 115.

13A is a diagram showing an example of the configuration of data stored in the sequence memory 301 according to the second embodiment of the present invention. The sequence memory 301 is composed of registers to which addresses are assigned for each predetermined bit. Sequence data is stored in the registers of each address. FIG. 13A illustrates a case in which addresses are assigned by integers starting from 0 for each bit length of the sequence data. Each sequence data stored in the sequence memory 301 may be configured to refer to either the template memory 302 or the parameter memory 114, or both. As will be described later, the data stored in the template memory 302 is composed of multiple template data sets identified by template numbers, and when the sequence data refers to the template memory 302, the template number to be referenced is specified. Also, the data stored in the parameter memory 114 is composed of multiple parameter data sets identified by parameter numbers, and when the sequence data refers to the parameter memory 114, the parameter number to be referenced is specified.

FIG. 13B is a diagram showing an example of the configuration of data stored in the template memory 302 according to the second embodiment of the present invention. The template memory 302 is composed of multiple template data sets identified by template numbers. In FIG. 13B, the template memory 302 is illustrated as being composed of two template data sets, template number 1 and template number 2. Each template data set stored in the template memory 302 is composed of, for example, a register to which an address is assigned for each predetermined bit. Template data is stored in the register at each address. In FIG. 13B, an integer number is assigned to addresses in order starting from 0 for each bit length of the template data. Each template data stored in the template memory 302 may be configured to refer to the parameter memory 114.

FIG. 13C is a diagram showing an example of the configuration of data stored in the parameter memory 114 according to the second embodiment of the present invention. The parameter memory 114 is composed of multiple parameter data sets identified by parameter numbers. Each parameter data set stored in the parameter memory 114 is composed of registers to which an address is assigned for each predetermined bit, for example. Parameter data is stored in the registers at each address. FIG. 13C shows a case in which addresses are assigned integers in order starting from 0 for each bit length of the parameter data.

The sequence memory 301 stores the outline sequence of the quantum computation executed by the quantum device control system 1A. The outline sequence is a sequence of the control sequence that is composed of fields other than the different fields for identifying the target quantum bit.

The template memory 302 can store commands that are common to each quantum bit in the quantum bit array. For example, when a quantum computation executed by the quantum device control system 1A is divided into multiple blocks, the template memory 302 stores, as a template, a control sequence for executing the divided small-scale quantum computation.

As a further concrete example, if the quantum computation performed by quantum device control system 1A is divided into an operation on one quantum bit and an operation on two adjacent quantum bits, template memory 302 stores a control sequence for performing an operation on one quantum bit as a first template, and stores a control sequence for performing an operation on two adjacent quantum bits as a second template.

In another aspect of the present invention, the template memory 302 may be configured to divide the quantum bits in the quantum device 120 into a plurality of sets, and store a control sequence for executing an operation on one quantum bit as a template for each divided set. For example, the quantum bits in the quantum device 120 may be divided into a plurality of sets based on the number of adjacent quantum bits, i.e., a set of quantum bits adjacent to one quantum bit, a set of quantum bits adjacent to two quantum bits, a set of quantum bits adjacent to three quantum bits, a set of quantum bits adjacent to four quantum bits, etc., and store a control sequence for executing an operation on one quantum bit for each divided set as a template. This makes it possible to provide a difference in the control sequence for each divided set.

Parameter memory 114 stores data that complements a portion of the data stored in sequence memory 301 or template memory 302. For example, parameter memory 114 stores variables specific to each quantum bit, and sequence memory 301 or template memory 302 configures sequence data or template data by referring to parameter memory 114.

Next, an example of the sequence memory 301, template memory 302, and parameter memory 114 shown in Figures 13A to 13C will be described in detail.

Address numbers 0 to 7 of the sequence memory 301 shown in FIG. 13A refer to parameter numbers 3 to 10 of the parameter memory 114, respectively. For example, address number 0 of the sequence memory 301 refers to parameter number 3 of the parameter memory 114, and the parameter data includes the voltage value of the bias voltage supply line 143 (VL1s) as a parameter.

Address numbers 8 and 9 of the sequence memory 301 both refer to template number 1 of the template memory, and also refer to parameter numbers 1 and 2 of the parameter memory 114, respectively. Template number 1 of the template memory stores a series of sequences for switching the bias voltage changeover switch matrix 140 and a command for driving the arithmetic radio frequency generating unit, but the number of the signal line to be switched and the parameters for driving the arithmetic radio frequency generating unit (such as the amplitude and phase of the radio frequency) differ depending on the quantum bit to be controlled and are therefore parameterized, and invalid data (dummy data) is stored in the corresponding bit of the template data, and the corresponding bit is configured to be cut out to the parameter memory 114.

Parameter memory parameter numbers 1 and 2 store the number of the signal line to be switched and the parameters for driving the calculation high frequency generating unit for each quantum bit to be controlled. For example, parameter memory parameter number 1 stores parameters for controlling the first quantum bit, and parameter memory parameter number 2 stores parameters for controlling the second quantum bit. For example, if the 4-bit bit area from the 10th bit to the 13th bit at address 0 in the template memory is parameterized, then parameter number 1 and address number 0 in the parameter memory mean writing the value 0 to the 4-bit bit area from the 10th bit to the 13th bit at address number 0 in the template data.

In the above, it has been described that the template memory 302 is complemented with the data in the parameter memory 114, but the present invention is not limited to this. For example, it is also possible to configure the parameter memory 114 to further refer to a second parameter memory (not shown), and to complement the parameter memory 114 data using the values in the second parameter memory, and further to complement the template memory 302 using those values. For example, the parameter memory 114 contains parameters for quantum operations (such as the amount of rotation of a rotation operator), and the second parameter memory contains a correspondence table between the parameters for quantum operations and the parameters of control signals (such as the application time of an RF signal). This makes it possible to increase the freedom of configuration of the quantum device control system 1A and the flexibility of parameter setting.

In another aspect of the present invention, the control device 110 can be configured to include a calculation unit (not shown), send data from the parameter memory 114 to the calculation unit, and supplement the template memory 302 with the results of calculations on that data. For example, the parameter memory 114 includes parameters for quantum calculations (such as the amount of rotation of a rotation operator), and the calculation unit calculates parameters for the control signal (such as the application time of an RF signal) from the parameters for the quantum calculation. This makes it possible to increase the freedom of configuration of the quantum device control system 1A and the flexibility of parameter setting.

As mentioned above, in a quantum bit array in which quantum bits are arranged in a one-dimensional or two-dimensional shape, when the same control is performed on two different quantum bits, the control sequence is generally the same, but due to differences in the wiring to be accessed and variations in the quantum bits, slightly different control sequences are required. In this embodiment, when the quantum computation performed by the quantum device control system 1A is divided into multiple blocks, the control sequence for executing the divided small-scale quantum computation is stored as a template in the template memory 302, and parameters specific to each quantum bit are configured to refer to the parameter memory 114. For example, in the quantum device control system 1A, the command memory includes a sequence memory 301 that stores an outline sequence and a template memory 302 that stores commands common to each quantum bit in the quantum bit array, and the sequence control unit 112 acquires the outline sequence from the sequence memory 301, and acquires commands common to each quantum bit from the template memory 302 among the outline sequences acquired from the sequence memory 301. This allows a portion of the memory that stores the control sequences required for operations on different quantum bits to be shared, making it possible to reduce the amount of memory provided to the control device 110 and also to reduce the amount of data sent from the host PC to the control device 110.

In addition, in this embodiment, variables specific to each quantum bit are stored in parameter memory 114. Therefore, similar to embodiment 1, parameters specific to each quantum bit that require a change in the control sequence due to changes in variation over time can be stored in parameter memory 114, and the data stored in parameter memory 114 can be rewritten by calibration, making it possible to provide a quantum device control system that generates control signals while realizing, with a low processing load, changes in parameters required for calibration, which corrects changes in element characteristics.

Furthermore, when the quantum computation executed by the quantum device control system 1A is divided into a plurality of blocks, the template memory 302 stores, as templates, control sequences for executing the divided small-scale quantum computations. This makes it possible to store, as templates, control sequences for the quantum computations of each of the divided blocks.

The above division is a division of the quantum computation executed by the quantum device control system 1A into an operation on one quantum bit and an operation on two adjacent quantum bits, and the template memory 302 stores a control sequence for executing an operation on one quantum bit as a first template, and stores a control sequence for executing an operation on two adjacent quantum bits as a second template. This makes it possible to perform quantum computation in the control sequence using a different template for each divided group.

In Example 3, the quantum device control system 1 is configured to include a signal measurement unit 401 outside the control device 110. Note that in Example 3, differences from the previous examples will be mainly described, and the same components as in the previous examples will be given the same reference numerals and their description will be omitted.

FIG. 14 is a block diagram showing the configuration of a quantum device control system 1B according to a third embodiment of the present invention. The quantum device control system 1B includes a host PC 100, a control device 110, a quantum device 120, and a signal measurement unit 401. The control device 110 also includes a host interface unit 111, a sequence control unit 112, a command memory 113, a parameter memory 114, and a control signal generation unit 115. The signal measurement unit 401 includes a measurement device such as an oscilloscope, a digitizer, or a spectrum analyzer. The signal measurement unit 401 may be placed in a room temperature environment, a lower temperature environment than room temperature, or an extremely low temperature environment.

The host PC 100 communicates with the signal measurement unit 401.

The signal measurement unit 401 receives the quantum operation unit output signal 121 from the quantum device 120. The signal measurement unit 401 measures the quantum operation unit output signal 121 received from the quantum device 120. The host PC 100 receives the measurement results from the signal measurement unit 401 via the host interface 101.

Thus, in this embodiment, the quantum device control system 1B comprises a host PC 100, a control device 110 comprising the sequence control unit 112, the command memory 113, and the parameter memory 114, a quantum device comprising the quantum bit array, and a signal measurement unit 401, and the signal measurement unit 116 measures a signal output from the quantum bit array based on a command from the host PC 100. Therefore, according to this embodiment, it is possible to configure the signal measurement unit 401 to include a high-performance measurement device, making it possible to improve the accuracy of calibration, for example. Furthermore, since a variety of measurement devices can be used as the signal measurement unit 401, it is possible to increase the flexibility of the configuration of the quantum device control system 1B.

In Example 4, the quantum device control system 1 is configured such that the control unit 601 controls the signal measurement unit 116. Note that in Example 4, differences from the previously described examples will be mainly described, and the same components as those in the previously described examples will be given the same reference numerals and their description will be omitted.

FIG. 15 is a block diagram showing the configuration of a quantum device control system 1C according to a fourth embodiment of the present invention.

The control device 110 includes a host interface unit 111, a control unit 601, a command memory 113, a parameter memory 114, a control signal generation unit 115, and a signal measurement unit 116.

The control unit 601 has a function equivalent to that of the sequence control unit 112 in the first embodiment. That is, in accordance with a control signal from the host interface unit 111, the control unit 601 generates a signal for driving the control signal generation unit 115 by referring to the command memory 113 and the parameter memory 114, and transmits the signal to the control signal generation unit 115.

The control unit 601 also communicates with the signal measurement unit 116.

The signal measurement unit 116 measures the quantum operation unit output signal 121 received from the quantum device 120 according to instructions from the control unit 601. The signal measurement unit 116 transmits the measurement result to the control unit 601 according to instructions from the control unit 601. The control unit 601 rewrites the value of a specified register area of the parameter memory 114 based on the measurement result received from the signal measurement unit 116.

An example of a calibration flow chart in this embodiment is the same as that shown in FIG. 9. However, it differs from the first embodiment in that the control unit 601 controls the signal measurement unit 116.

That is, in step 202, the host PC 100 sends a command to the control unit 601 to measure a signal. Based on the command received from the host PC 100, the control unit 601 sends a command to the signal measurement unit 116 to measure the quantum operation unit output signal 121. The signal measurement unit 116 measures the quantum operation unit output signal 121 in accordance with the command. The control unit 601 commands the signal measurement unit 116 to transmit the measurement result. In accordance with the command, the signal measurement unit 116 returns the measurement result to the control unit 601. The control unit 601 returns the measurement result to the host PC 100.

In another aspect of the present invention, it is also possible to configure the control unit 601 to control the calibration flow based on a calibration start command from the host PC 100.

FIG. 16 shows another example of a calibration flow chart in this embodiment.

The host PC 100 sends a command to the control unit 601 to start calibration (step 200). When the control unit 601 receives the command from the host PC 100, it starts the calibration flow.

The control unit 601 changes the voltage setting parameters of the bias voltage generation unit and controls the setting value of the applied voltage in the predetermined bias voltage supply line 143 to a predetermined value (step 201). Next, the control unit 601 sends a command to the signal measurement unit 116 to measure the quantum operation unit output signal 121, and receives the measurement result from the signal measurement unit 116 (step 202). The control unit 601 determines whether to end the voltage scan (step 203). If the voltage scan is not to be ended (step 203; No), the output voltage setting value is changed by a predetermined value and execution is performed again from step 201. If the voltage scan is to be ended (step 203; Yes), the control unit 601 determines the optimal setting value of the voltage output value based on the voltage setting value in step 201 and the data acquired in step 202 (step 204). The control unit 601 writes the determined optimal setting value of the voltage output value to a register in the parameter memory that stores the voltage setting parameters of the bias voltage generation unit (step 205). Finally, the control unit 601 sends a notification to the host PC 100 that the calibration is complete. This completes the calibration of the voltage setting parameters of the bias voltage generation unit.

Thus, in this embodiment, the quantum device control system 1C comprises a host PC 110, a control device 110 comprising a control unit 601, the command memory 113, the parameter memory 114, and a signal measurement unit 116, and a quantum device comprising the quantum bit array, the control unit 601 comprising the sequence control unit 112, and the signal measurement unit 116 measuring a signal output from the quantum bit array based on a command from the control unit 601. Therefore, according to this embodiment, by the control unit 601 controlling the signal measurement unit 116, it is possible to reduce the amount of communication between the host PC 100 and the control device 110 and also reduce the processing load on the host PC 100.

Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the sequence control unit 112, command memory 113, and parameter memory 114 may be provided in the host PC 100, and signals may be output to the control signal generation unit 115 of the control device 200. In this case, the control device 200 can be configured simply to achieve functions similar to those of the respective embodiments.

These embodiments and variations are within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents as described in the claims. The components described in the embodiments may be realized by specially designed hardware such as an ASIC (Application Specific Integrated Circuit), or by programmable hardware such as an FPGA (Field-Programmable Gate Array). In addition, at least some of the functions may be performed by software running on a host PC.

The above-mentioned embodiment makes it possible to realize a practical quantum computer, which consumes less energy, reduces carbon emissions, prevents global warming, and contributes to the realization of a sustainable society.

1: quantum device control system, 1A to 1C: quantum device control system, 100: host PC, 101: host interface, 110: control device, 111: host interface unit, 112: sequence control unit, 113: command memory, 114: parameter memory, 115: control signal generation unit, 116: signal measurement unit, 117: quantum device control signal, 120: quantum device, 121: quantum operation unit output signal, 131: quantum dot array applied bias voltage control line, 132: RF signal line, 140: bias voltage switching switch matrix, 1 41: Bias voltage switching strobe, 142: Bias voltage control register setting value, 143: Bias voltage supply line, 200-206: State, 210: Input/output screen, 211: Button, 212: Display area, 301: Sequence memory, 302: Template memory, 401: Signal measurement section, 500: Command format, 501: Rate information specification field (RATE), 502: Operation information specification field (OPR), 503: External parameter selection field (EXT), 504: Parameter specification field (PARAM), 601: Control section

Claims (14)

A quantum device control system for controlling quantum operations in a quantum bit array in which a plurality of quantum bits are arranged one-dimensionally or two-dimensionally,
A sequence control unit that controls a sequence of quantum operations;
a command memory for storing commands for controlling each quantum bit in the quantum bit array;
a parameter memory for storing variables specific to each quantum bit in the quantum bit array;
The sequence control unit acquires the command from the command memory and acquires a variable specific to each quantum bit from the parameter memory to construct the sequence of the quantum operation;
The parameter memory is rewritable according to the characteristics of each quantum bit.
A quantum device control system comprising: 2. The quantum device control system according to claim 1,
the command memory comprises a sequence memory for storing a general sequence; and a template memory for storing commands common to each quantum bit in the quantum bit array;
The sequence control unit acquires the outline sequence from the sequence memory,
the sequence control unit acquires, from the template memory, a command common to each of the quantum bits, from the outline sequence acquired from the sequence memory;
A quantum device control system comprising: 2. The quantum device control system according to claim 1,
a control signal generation unit that generates a control signal for the quantum bit array;
the sequence of quantum operations is a sequence of signals that drive the control signal generator;
The sequence control unit generates a signal for driving the control signal generation unit and transmits the signal to the control signal generation unit.
A quantum device control system comprising: 4. The quantum device control system according to claim 3,
The control signal generation unit generates at least one of a bias voltage drive signal and an RF signal that drives the quantum bit array.
A quantum device control system comprising: 5. The quantum device control system according to claim 4,
The variable specific to each quantum bit in the quantum bit array is at least one of a parameter specifying the bias voltage drive signal or a parameter specifying the RF signal.
A quantum device control system comprising: 6. The quantum device control system according to claim 5,
The parameter specifying the bias voltage drive signal is a bias voltage, a bias voltage switching strobe, or a bias voltage control register setting value.
A quantum device control system comprising: 6. The quantum device control system according to claim 5,
The parameter specifying the RF signal is at least one of the amplitude, phase, frequency, duration, and envelope of the RF signal;
A quantum device control system comprising: 3. The quantum device control system according to claim 2,
The template memory stores, as a template, a control sequence for executing the divided small-scale quantum computations when the quantum computation to be executed by the quantum device control system is divided into a plurality of blocks.
A quantum device control system comprising: 9. The quantum device control system according to claim 8,
The division is a division of a quantum computation executed by the quantum device control system into an operation for one quantum bit and an operation for two adjacent quantum bits;
The template memory stores a control sequence for executing an operation on one quantum bit as a first template, and stores a control sequence for executing an operation on two adjacent quantum bits as a second template.
A quantum device control system comprising: 2. The quantum device control system according to claim 1,
A signal measuring unit is provided,
The signal measurement unit measures a signal output from the quantum bit array.
A quantum device control system comprising: 11. The quantum device control system according to claim 10,
Scanning a variable specific to each quantum bit within a predetermined range;
rewriting data in the parameter memory based on a measurement result of the signal measurement unit;
A quantum device control system comprising: 11. The quantum device control system according to claim 10,
A host PC;
a control device including the sequence control unit, the command memory, the parameter memory, and the signal measurement unit;
a quantum device comprising the quantum bit array;
The signal measurement unit measures a signal output from the quantum bit array based on a command from a host PC.
A quantum device control system comprising: 11. The quantum device control system according to claim 10,
A host PC;
a control device including the sequence control unit, the command memory, and the parameter memory;
A quantum device comprising the quantum bit array;
A signal measuring unit,
The signal measurement unit measures a signal output from the quantum bit array based on a command from a host PC.
A quantum device control system comprising: 11. The quantum device control system according to claim 10,
A host PC;
a control device including a control unit, the command memory, the parameter memory, and a signal measurement unit;
a quantum device comprising the quantum bit array;
The control unit includes the sequence control unit,
The signal measurement unit measures a signal output from the quantum bit array based on a command from the control unit.
A quantum device control system comprising:

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