WO2025011762A1

WO2025011762A1 - Voltage amplifier

Info

Publication number: WO2025011762A1
Application number: PCT/EP2023/069352
Authority: WO
Inventors: Federico VECCHI; Filippo SCHEMBARI
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-07-12
Filing date: 2023-07-12
Publication date: 2025-01-16
Anticipated expiration: 2026-01-12

Abstract

In some examples, a voltage amplifier (100) comprises an input transistor (101) arranged to receive an input voltage signal at a first terminal of the input transistor (101), a cascode transistor (102) connected to the input transistor (101), wherein a third terminal of the cascode transistor (102) is connected to a second terminal of the input transistor (101), wherein the cascode transistor (102) is arranged to generate an amplified output signal, a load resistor (103) connected to a second terminal of the cascode transistor (102), wherein the load resistor (103) is arranged to receive the amplified output signal, a first current generator (104) connected to the second terminal of the cascode transistor (102), and a second current generator (105) connected to the third terminal of the cascode transistor.

Description

VOLTAGE AMPLIFIER

TECHNICAL FIELD

The present disclosure relates, in general, to a wide band amplifier for linear applications. Aspects of the disclosure relate to a broadband driver amplifier capable of operating at low supply voltage.

BACKGROUND

A typical transmitter used in optical communication is composed of an output stage, which amplifies the desired signal and exhibits the required output impedance/matching, a bias tee (usually off chip due to required component values), which is used to bias the optical modulator, and an optical modulator (typically an electro-absorption modulator (EAM) and/or an electroabsorption modulated laser (EML)).

The bias tee typically consists of three elements: an inductor used to bias the EAM/EML, a capacitor used to isolate the output DC voltage of the output stage from the bias voltage of the EAM/EML, and an optional inductor used to short/eliminate the voltage drop across the output resistor, thus reducing the required headroom and power consumption for a given output amplitude.

SUMMARY

An objective of the present disclosure is to provide a broadband driver amplifier capable of operating at a low supply voltage by leveraging on current bleeding, reducing the power consumption without the use of external components, and with negligible impact on gain/bandwidth/linearity of the amplifier.

The foregoing and other objectives are achieved by the features of the independent claims.

Further implementation forms are apparent from the dependent claims, the description and the Figures.

A first aspect of the present disclosure provides a voltage amplifier comprising an input transistor arranged to receive an input voltage signal at a first terminal of the input transistor, a cascode transistor connected to the input transistor, wherein a third terminal of the cascode transistor is connected to a second terminal of the input transistor, wherein the cascode transistor is arranged to generate an amplified output signal, a load resistor connected to a second terminal of the cascode transistor, wherein the load resistor is arranged to receive the amplified output signal, a first current generator connected to the second terminal of the cascode transistor, and a second current generator connected to the third terminal of the cascode transistor.

Accordingly, the output parasitic capacitance can be reduced, and the bandwidth of the voltage amplifier can be improved. The voltage amplifier according to the present invention is able to operate at a low supply voltage by leveraging on current bleeding, reducing the power consumption without using external components and with negligible impact on gain/bandwidth/linearity.

In an implementation of the first aspect, the voltage amplifier may further comprise a resistor connected between the third terminal of the cascode transistor and the second current generator.

The voltage amplifier may further comprise an inductor connected between the third terminal of the cascode transistor and the second terminal of the input transistor, wherein the second current generator is connected to the second terminal of the input transistor or to the third terminal of the cascode transistor.

The voltage amplifier may further comprise a first inductor and a second inductor connected, in series, between the third terminal of the cascode transistor and the second terminal of the input transistor, wherein the second current generator is connected between the first inductor and the second inductor.

The voltage amplifier may further comprise an operational amplifier, op-amp, arranged to compare a reference voltage and an output DC voltage of the voltage amplifier, and generate a feedback signal based thereon, wherein a sensing resistor is connected between an output terminal of the operational amplifier and an input terminal of the operational amplifier.

An output terminal of the operational amplifier may be connected to the first current generator or the second current generator to thereby regulate the output DC voltage of the voltage amplifier based on the feedback signal.

The third terminal of the input transistor may be connected to ground.

The voltage amplifier may further comprise a degeneration resistor connected between the third terminal of the input transistor and ground. The input transistor and/or the cascode transistor may comprise a bipolar junction transistor (BJT) or a field-effect transistor (FET).

A second aspect of the present disclosure provides a distributed amplifier comprising a plurality of unit cells, each of the plurality of unit cells comprising the voltage amplifier as described herein.

A third aspect of the present disclosure provides a method of improving bandwidth in a voltage amplifier, the method comprising providing an input transistor to receive an input voltage signal at a first terminal of the input transistor, connecting a cascode transistor to the input transistor, wherein a third terminal of the cascode transistor is connected to a second terminal of the input transistor, wherein the cascode transistor is arranged to generate an amplified output signal, connecting a load resistor to a second terminal of the cascode transistor, wherein the load resistor is arranged to receive the amplified output signal, connecting a first current generator to the second terminal of the cascode transistor, and connecting a second current generator to the third terminal of the cascode transistor.

The method may further comprise connecting a resistor between the third terminal of the cascode transistor and the second current generator.

The method may further comprise connecting an inductor between the third terminal of the cascode transistor and the second terminal of the input transistor, and connecting the second current generator to the second terminal of the input transistor or to the third terminal of the cascode transistor.

The method may further comprise comparing, using an operational amplifier, a reference voltage and an output DC voltage of the voltage amplifier, and generating a feedback signal based thereon.

The method may further comprise connecting an output of the operational amplifier to the first current generator or the second current generator to thereby regulate the output DC voltage of the voltage amplifier based on the feedback signal.

These and other aspects of the invention will be apparent from the embodiment s) described below. BRIEF DESCRIPTION OF THE DRAWINGS

In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure l is a schematic representation of a voltage amplifier according to an example;

Figure 2 is a schematic representation of a voltage amplifier according to another example;

Figure 3 is a schematic representation of a unit cell comprising a voltage amplifier according to an example;

Figure 4 is a schematic representation of a distributed amplifier comprising a unit cell according to an example;

Figures 5a, 5b are a schematic representation of a voltage amplifier according to another example; and

Figure 6 is a flow chart of a method of improving bandwidth in a voltage amplifier according to an example.

DETAILED DESCRIPTION

Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

A conventional low noise amplifier circuit supporting a wide range of gain often suffers from a low output voltage headroom due to a DC current flowing through load resistors (i.e., an excessive DC voltage drop). One of the currently used approaches to address this issue is to use current bleeding branches (for example, transistors) to allow a portion of the DC current to flow through the current bleeding branches. Consequently, the DC current flowing through the load resistors is reduced (that is, the DC voltage drop across the load resistors is minimised), thus ensuring an adequate output voltage headroom for the signal. However, in this approach, the current bleeding branches may load non-negligibly the output terminals of the circuit, therefore potentially impairing the circuit bandwidth. Other approaches either do not have a significant impact on the output headroom and/or do not offer much freedom in terms of reducing the required output headroom/ supply voltage.

The present invention addresses the above-described problem by employing two current bleeding branches to reduce the output parasitic load capacitance, therefore ensuring a wider circuit bandwidth.

Figure 1 is a schematic representation of a voltage amplifier 100 according to an example. The voltage amplifier 100 comprises an input transistor 101 arranged to receive an input voltage signal at a first terminal of the input transistor 101. In Figure 1, exemplarily depicted are an input 120 and an output 122, but the invention is not limited thereto.

The input transistor 101 may comprise a bipolar junction transistor (BJT) and/or a field-effect transistor (FET). The first terminal of the input transistor 101 may comprise a base terminal and/or a gate terminal. The voltage amplifier 100 also comprises a cascode transistor 102, connected to the input transistor 101. A third terminal of the cascode transistor 102 is connected to a second terminal of the input transistor 101. The cascode transistor 102 is arranged to generate an amplified output signal.

The cascode transistor 102 may comprise a bipolar junction transistor (BJT) and/or a fieldeffect transistor (FET). The input transistor 101 and the cascode transistor 102 may form a cascode amplifier. The third terminal of the cascode transistor 102 may comprise an emitter terminal and/or a source terminal, and the second terminal of the input transistor 101 may comprise a collector terminal and/or a drain terminal. That is, the emitter/source terminal of the cascode transistor 102 may be connected to the collector/drain terminal of the input transistor 101. The input transistor 101 may be arranged in a common emitter/source configuration, and the cascode transistor 102 may be arranged in a common base/gate configuration. A third terminal (e.g., emitter/source terminal) of the input transistor may be connected to ground.

The voltage amplifier 100 comprises a load resistor 103 connected to a second terminal of the cascode transistor 102. The load resistor 103 is arranged to receive the amplified output signal from the cascode transistor 102. The second terminal of the cascode transistor 102 may comprise a collector terminal and/or a drain terminal, depending on whether the cascode transistor 102 comprises a BJT or a FET.

The voltage amplifier 100 comprises a first current generator 104, connected to the second terminal of the cascode transistor 102 (for example, to a collector/drain terminal). The voltage amplifier 100 also comprises a second current generator 105 connected to the third terminal (for example, to an emitter/source terminal) of the cascode transistor 102. In other words, the second current generator 105 may be connected between the input transistor 101 and the cascode transistor 102.

As previously discussed, by splitting the total bleeding current into two separated current generators (first current generator 104 and the second current generator 105), the output parasitic load capacitance (COUT) can be reduced, thus ensuring a wider circuit bandwidth. In particular, since the second current generator 105 may be connected to the emitter terminal (i.e., a low impedance node) of the cascode transistor 102, the impact of the parasitic capacitance associated with the second current generator 105 (CCASC) is low, and thus the circuit bandwidth is only marginally impaired. The maximum value of the second current generator 105 may be limited only by 1/gm of the cascode transistor 102 and the linearity. Furthermore, since the current through the cascode transistor 102 is reduced by the effect of the second current generator 105, the cascode transistor 102 may conveniently be made smaller.

The voltage amplifier 100 may further comprise a resistor 106. The resistor 106 may be connected in series to the second current generator 105, for example, between the third terminal of the cascode transistor 102 and the second current generator 105. The resistor 106 can further isolate the parasitic capacitance associated with the second current generator 105 (CCASC) from the RF circuit, thereby providing an additional bandwidth benefit. In order not to impair the performance of the circuit, the value of the resistor 106 may be »l/gm of the cascode transistor 102.

The voltage amplifier 100 may further comprise a degeneration resistor 110. The degeneration resistor may be connected to the third terminal (e.g., emitter/source terminal) of the input transistor 101. The purpose of the degeneration resistor 110 may be to adjust the gain of the voltage amplifier 100, and to improve linearity.

Figure 2 is a schematic representation of a voltage amplifier according to another example. Figure 2 builds on the voltage amplifier 100 shown in Figure 1. Same elements in Figures 1 and 2 share the same reference signs and function likewise. The voltage amplifier 100 may further comprise an inductor 107 connected between the third terminal (e.g., emitter/source terminal) of the cascode transistor 102 and the second (e.g., collector/drain terminal) terminal of the input transistor 101. The second current generator 105 may be connected to the second terminal of the input transistor 101, or to the third terminal of the cascode transistor 102.

The use of the inductor 107 can further improve the bandwidth of the cascoded amplifier stage. As shown in Figure 2, the inductor 107 may comprise a first inductor 107a and a second inductor 107b, connected, in series, between the third terminal of the cascode transistor 102 and the second terminal of the input transistor 101. The second current generator 105 may be connected between the first inductor 107a and the second inductor 107b. In other words, the inductor 107 may be split into two or more inductors, and the bleeding current may be injected between the two. The same concept (as well as the concepts described above in relation to Figure 1) may also be applied to a differential amplifier.

Figure 3 is a schematic representation of a unit cell comprising a voltage amplifier according to an example. Figure 4 is a schematic representation of a distributed amplifier comprising a unit cell according to an example. Figures 3 and 4 build on the voltage amplifier 100 shown in Figures 1 and 2. Same elements in Figures 1 to 4 share the same reference signs and function likewise.

The proposed voltage amplifier 100 may be used as a unit cell (Figure 3) within a distributed amplifier (Figure 4). In the unit cell 300, the first current generator 104 may be downscaled by a factor of N, wherein N is the number of stages of the distributed amplifier 400. Similarly, the second current generator 105 may also be downscaled by a factor of N. Similar considerations may also apply to the input transistor 101 and the cascode transistor 102, downscaled by a factor of N. In contrast, the resistor 106 may be upscaled by the same factor N. As such, the output parasitic capacitance (COUT) may be absorbed into an output artificial transmission line (i.e. split into sub-units equal to COUT / N). AS before, the same concept may also be applied to a differential distributed amplifier. Figure 4 shows a distributed amplifier 400 comprising a plurality of unit cells 300. Advantageously, the distributed amplifier 400 offers an improved bandwidth.

Figures 5a, 5b are a schematic representation of a voltage amplifier according to another example. As with previous figures, the voltage amplifier of Figures 5a/5b builds on the voltage amplifier 100 shown in Figure 1. Same elements in Figures 1 and 5a/5b share the same reference signs and function likewise. Advantageously, the arrangement of Figure 5a/5b enables setting the output DC level of the amplifier. That is, the two current bleeding branches can be properly controlled to arbitrarily set the output common mode DC voltage of the amplifier.

The voltage amplifier 100 may further comprise an operational amplifier (op-amp) 108 and a sensing resistor 109. The operational amplifier 108 may be arranged to compare a reference voltage and an output DC voltage (for example, an output common-mode DC voltage of the voltage amplifier 100), and generate a feedback signal based thereon. The sensing resistor 109 may be connected between an output terminal 122 of the voltage amplifier 100 and an input terminal of the operational amplifier 108. The sensing resistor 109 may be used to isolate the sensed node from an input capacitance of the operational amplifier 108.

The output terminal of the operational amplifier 108 may be connected to the first current generator 104 (as shown in Figure 5a) to thereby act on the current bleeding branch comprising the first current generator 104, or to the second current generator 105 (as shown in Figure 5b) to thereby act on the current bleeding branch comprising the second current generator 105. In particular, the operational amplifier 108 may act on the current bleeding branch by regulating the output DC voltage of the voltage amplifier 100 based on the feedback signal. Figure 6 is a flow chart of a method of improving bandwidth in a voltage amplifier according to an example. In block 601, the method comprises providing an input transistor to receive an input voltage signal at a first terminal of the input transistor. In block 602, the method comprises connecting a cascode transistor to the input transistor, wherein a third terminal of the cascode transistor is connected to a second terminal of the input transistor, wherein the cascode transistor is arranged to generate an amplified output signal. In block 603, the method comprises connecting a load resistor to a second terminal of the cascode transistor, wherein the load resistor is arranged to receive the amplified output signal. In block 604, the method comprises connecting a first current generator to the second terminal of the cascode transistor. In block 605, the method comprises connecting a second current generator to the third terminal of the cascode transistor.

The method may further comprise connecting a resistor between the third terminal of the cascode transistor and the second current generator. The method may further comprise connecting an inductor between the third terminal of the cascode transistor and the second terminal of the input transistor, and connecting the second current generator to the second terminal of the input transistor or to the third terminal of the cascode transistor. The method may further comprise comparing, using an operational amplifier, a reference voltage and an output DC voltage of the voltage amplifier, and generating a feedback signal based thereon. The method may further comprise connecting an output of the operational amplifier to the first current generator or the second current generator to thereby regulate the output DC voltage of the voltage amplifier based on the feedback signal.

The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

1. A voltage amplifier (100) compri sing : an input transistor (101) arranged to receive an input voltage signal at a first terminal of the input transistor (101); a cascode transistor (102) connected to the input transistor (101), wherein a third terminal of the cascode transistor (102) is connected to a second terminal of the input transistor (101), wherein the cascode transistor (102) is arranged to generate an amplified output signal; a load resistor (103) connected to a second terminal of the cascode transistor (102), wherein the load resistor (103) is arranged to receive the amplified output signal; a first current generator (104) connected to the second terminal of the cascode transistor (102); and a second current generator (105) connected to the third terminal of the cascode transistor (102).

2. The voltage amplifier (100) of claim 1, further comprising a resistor (106) connected between the third terminal of the cascode transistor (102) and the second current generator (105).

3. The voltage amplifier (100) of claim 1 or 2, further comprising: an inductor (107) connected between the third terminal of the cascode transistor (102) and the second terminal of the input transistor (101), wherein the second current generator (105) is connected to the second terminal of the input transistor (101) or to the third terminal of the cascode transistor (102).

4. The voltage amplifier (100) of claim 1 or 2, further comprising a first inductor (107a) and a second inductor (107b) connected, in series, between the third terminal of the cascode transistor (102) and the second terminal of the input transistor (101), wherein the second current generator (105) is connected between the first inductor (107a) and the second inductor (107b).

5. The voltage amplifier (100) of any preceding claim, further comprising: an operational amplifier (108), op-amp, arranged to compare a reference voltage and an output DC voltage of the voltage amplifier (100), and generate a feedback signal based thereon, wherein a sensing resistor (109) is connected between an output terminal of the operational amplifier (108) and an input terminal of the operational amplifier (108).

6. The voltage amplifier (100) of claim 5, wherein an output terminal of the operational amplifier (108) is connected to the first current generator (104) or the second current generator (105) to thereby regulate the output DC voltage of the voltage amplifier (100) based on the feedback signal.

7. The voltage amplifier (100) of any preceding claim, wherein a third terminal of the input transistor (101) is connected to ground.

8. The voltage amplifier (100) of claim 7, further comprising a degeneration resistor (110) connected between the third terminal of the input transistor (101) and ground.

9. The voltage amplifier (100) of any preceding claim, wherein the input transistor (101) and/or the cascode transistor (102) comprise a bipolar junction transistor or a field-effect transistor.

10. A distributed amplifier (400) comprising a plurality of unit cells (300), each of the plurality of unit cells (300) comprising the voltage amplifier (100) of any one of claims 1 to 7.

11. A method of improving bandwidth in a voltage amplifier, the method comprising: providing an input transistor to receive an input voltage signal at a first terminal of the input transistor (601); connecting a cascode transistor to the input transistor, wherein a third terminal of the cascode transistor is connected to a second terminal of the input transistor, wherein the cascode transistor is arranged to generate an amplified output signal (602); connecting a load resistor to a second terminal of the cascode transistor, wherein the load resistor is arranged to receive the amplified output signal (603); connecting a first current generator to the second terminal of the cascode transistor (604); and connecting a second current generator to the third terminal of the cascode transistor (605).

12. The method of claim 11, further comprising connecting a resistor between the third terminal of the cascode transistor and the second current generator.

13. The method of claim 11 or 12, further comprising connecting an inductor between the third terminal of the cascode transistor and the second terminal of the input transistor, and connecting the second current generator to the second terminal of the input transistor or to the third terminal of the cascode transistor.

14. The method of claim 11, 12 or 13, further comprising comparing, using an operational amplifier, a reference voltage and an output DC voltage of the voltage amplifier, and generating a feedback signal based thereon.

15. The method of claim 14, further comprising connecting an output of the operational amplifier to the first current generator or the second current generator to thereby regulate the output DC voltage of the voltage amplifier based on the feedback signal.