WO2025001527A1 - Data detection method and apparatus - Google Patents

Abstract

Provided in the present application are a data detection method and apparatus. The data detection apparatus comprises: a rate de-matching module, a soft merging module, a decoding verification module, a processor and a first memory, wherein a program is stored in the first memory, and when the program is executed by the processor, at least one of the following steps is implemented: controlling whether to input at least one of a synchronization signal block index and a log-likelihood probability of a first synchronization signal block into the rate de-matching module by means of software or a hardware circuit; controlling whether to perform secondary de-scrambling processing and duplication rate de-matching processing on the log-likelihood probability of the first synchronization signal block by means of the rate de-matching module, so as to obtain a log-likelihood probability of a second synchronization signal block, or to perform secondary de-scrambling processing and duplication rate de-matching processing on the log-likelihood probability of the first synchronization signal block by means of the software, so as to obtain the log-likelihood probability of the second synchronization signal block; and controlling whether to input a system frame number index into the soft merging module by means of the software or the hardware circuit.

Description

Data detection method and device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to patent application No. 202310779715.0 filed with the China Patent Office on June 28, 2023, the entire contents of which are incorporated herein by reference.

Technical Field

The embodiments of the present application relate to but are not limited to the field of communication technology.

Background Art

In the ^5th Generation Mobile Communication Technology (5G), the Physical Broadcast Channel (PBCH) contains two parts: the PBCH demodulation reference signal (DMRS) and the PBCH data. After successfully detecting the Primary Synchronization Signal (PSS) and the Secondary Synchronization Signal (SSS), the User Equipment (UE) obtains the Cell Identity (Cell ID), Orthogonal Frequency Division Multiplexing (OFDM) symbol boundary synchronization and coarse frequency synchronization. Afterwards, the PBCH DMRS is blindly detected to obtain at least one candidate synchronization signal block index (SSB index), and then the PBCH data is detected to obtain the master information block (MIB) message, thereby obtaining the system frame number and half-frame indication to complete the wireless frame timing and half-frame timing. At the same time, the time slot and symbol of the current PSS and SSS are determined by the candidate SSB index and the synchronization signal block burst set (SSB burst set) pattern used by the current frequency band to complete the time slot timing.

The PBCH data detection process is also the PBCH decoding process. The PBCH decoding process includes de-scrambling, de-repetition rate matching, de-sub-block interleaving, de-system frame number (SFN, System Frame Number) mask, polarization code (Polar code) decoding and cyclic redundancy check (CRC, Cyclic Redundancy Check) processes to support PBCH blind detection. The measurement also includes: SFN mask generation, log-likelihood-ratio (LLR) soft merging and other processes.

In the Long Term Evolution (LTE) system, the transmission time interval (TTI) of PBCH is 40 milliseconds (ms), the SSB burst set period is fixed at 10ms, and a maximum of 4 bursts can be combined in one TTI. In the 5G system, the TTI of PBCH is 80ms, and the SSB burst set period is variable. During the initial cell selection, the SSB burst set period defaults to 20ms, but during cell switching and cell reselection, the SSB burst set period can be any of 5ms, 10ms, 20ms, 40ms, 80ms, and 160ms. Different SSB burst set periods in the same TTI can be soft-merged for LLR to improve the signal-to-noise ratio.

For 5G systems, the PBCH decoding process has many steps and there are situations where the SSB burst set has multiple periods, which greatly complicates the blind detection process and reduces its flexibility.

Summary of the invention

The embodiments of the present application provide a data detection method and device.

In the first aspect, an embodiment of the present application provides a data detection device, comprising: at least one rate-dematching module, each of which is connected to at least one soft-merging module, each of which is connected to a decoding and verification module, as well as at least one processor and a first memory; wherein the rate-dematching module is configured to perform a de-secondary scrambling process and a de-repetition rate matching process on the log-likelihood probability of the input first synchronization signal block according to the synchronization signal block index to obtain the log-likelihood probability of the second synchronization signal block; the soft-merging module is configured to perform a de-sub-block interleaving process and a de-system frame number on the log-likelihood probability of the second synchronization signal block according to the system frame number index The mask processing and the log-likelihood probability soft merging processing are performed to obtain the log-likelihood probability of the third synchronization signal block; the decoding verification module is configured to perform decoding processing and cyclic redundancy code check processing on the log-likelihood probability of the third synchronization signal block to obtain decoded data and a verification result; wherein the rate matching module, the soft merging module and the decoding verification module are implemented by hardware circuits; wherein at least one program is stored on the first memory, and when the at least one program is executed by the at least one processor, at least one of the following steps is implemented: controlling whether the synchronization signal block index is input into the rate matching module through software or hardware circuits; controlling whether the synchronization signal block index is input into the rate matching module through software whether the first synchronization signal block log-likelihood probability is input into the rate dematching module by software or hardware circuit; whether the rate dematching module performs secondary descrambling and repetition rate dematching on the first synchronization signal log-likelihood probability to obtain the second synchronization signal block log-likelihood probability, or whether the software performs secondary descrambling and repetition rate dematching on the first synchronization signal log-likelihood probability to obtain the second synchronization signal block log-likelihood probability; whether the software or hardware circuit is used to input the system frame number index into the soft merging module.

In the second aspect, an embodiment of the present application provides a data detection method, including: using at least one de-rate matching module to implement de-secondary scrambling and de-repetition rate matching processing of the input first synchronization signal block log-likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block log-likelihood probability; wherein different de-rate matching modules correspond to different synchronization signal block indexes; using at least one soft merging module connected to the same de-rate matching module to implement de-sub-block interleaving processing, de-system frame number mask processing and log-likelihood probability soft merging processing of the second synchronization signal block log-likelihood probability according to the system frame number index to obtain the third synchronization signal block log-likelihood probability; wherein different soft merging modules connected to the same de-rate matching module correspond to different system frame number indexes; decoding and cyclic redundancy checking of the log-likelihood probability of the third synchronization signal block are performed by a decoding check module connected to the soft merging module. The residual code check processing obtains the decoded data and the check result; wherein, the rate matching module, the soft merging module and the decoding check module are implemented by hardware circuits; the data detection method also includes at least one of the following steps: controlling whether the synchronization signal block index is input into the rate matching module through software or hardware circuits; controlling whether the log-likelihood probability of the first synchronization signal block is input into the rate matching module through software or hardware circuits; controlling whether the log-likelihood probability of the first synchronization signal is de-scrambled and de-repeated through the rate matching module to obtain the log-likelihood probability of the second synchronization signal block, or whether the log-likelihood probability of the first synchronization signal is de-scrambled and de-repeated through software to obtain the log-likelihood probability of the second synchronization signal block; controlling whether the system frame number index is input into the soft merging module through software or hardware circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a block diagram of a data detection device provided by an embodiment of the present application;

FIG2 is a block diagram of a data detection device in an embodiment of the present application, taking the data detection device including a rate matching solution module and a soft merging module as an example;

FIG3 is a block diagram of another data detection device in the embodiment of the present application, taking the data detection device including a rate matching solution module and a soft merging module as an example;

FIG. 4 is a flow chart of a data detection method provided in another embodiment of the present application.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the technical solution of the present application, the data detection method and device provided by the present application are described in detail below in conjunction with the accompanying drawings.

Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.

In the absence of conflict, the embodiments of the present application and the features therein may be combined with each other.

As used herein, the term "and/or" includes any and all combinations of at least one of the associated listed items.

The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and/or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and/or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component and/or its group is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

The data detection device and data detection method of the embodiments of the present application are proposed based on the problems existing in the PBCH decoding process, but the data detection device and data detection method of the embodiments of the present application are not only applicable to PBCH decoding, but also applicable to the decoding of other data.

The data detection device and data detection method of the embodiment of the present application can be applied to a mobile terminal, a computer terminal or other similar computing devices. For example, it can be applied to a communication device in a wireless communication system, and the communication device can be at least one of a user equipment, a base station, etc.

FIG1 is a block diagram of a data detection device according to an embodiment of the present application.

In the first aspect, referring to FIG1 , an embodiment of the present application provides a data detection device, which can be set in a mobile terminal, a computer terminal or other similar computing devices. For example, it can be included in a communication device in a wireless communication system, and the communication device can be at least one of a user equipment, a base station, etc. The data detection device may include: at least one rate matching module, each rate matching module is connected to at least one soft merging module, each soft merging module is connected to a decoding verification module, and at least one processor and a first memory.

Among them, the rate de-matching module is configured to perform secondary de-scrambling and repetition rate de-matching processing on the input first SSB LLR according to the SSB index to obtain the second SSB LLR; the soft merging module is configured to perform sub-block de-interleaving, SFN mask de-masking and LLR soft merging processing on the second SSB LLR according to the SFN index to obtain the third SSB LLR; the decoding and verification module is configured to perform decoding and CRC processing on the third SSB LLR to obtain decoded data and verification results.

Among them, the rate matching module, the soft combining module and the decoding and verification module are implemented by hardware circuits.

Among them, at least one program is stored in the first memory. When the at least one program is executed by at least one processor, at least one of the following steps is implemented: controlling whether the SSB index is input into the rate matching module through software or hardware circuit; controlling whether the first SSB LLR is input into the rate matching module through software or hardware circuit; controlling whether the rate matching module performs secondary descrambling and repetitive rate matching on the first SSB LLR to obtain a second SSB LLR, or performs secondary descrambling and repetitive rate matching on the first SSB LLR through software to obtain a second SSB LLR; controlling whether the software also performs secondary descrambling and repetitive rate matching on the first SSB LLR to obtain a second SSB LLR. It is the hardware circuit that inputs the SFN index into the soft combining module.

In some exemplary embodiments, different rate matching modules correspond to different SSB indexes. That is, in the same data detection process, the SSB indexes input into the rate matching module are different, that is, the process of blind detection using different SSB indexes.

In some exemplary embodiments, different soft merging modules connected to the same rate matching module correspond to different decoding channels, and different soft merging modules connected to the same rate matching module correspond to different SFN indexes. That is, when the same SSB index is used for data detection, the SFN indexes input to different soft merging modules connected to the same rate matching module are different, that is, the process of blind detection using different SFN indexes.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: determining whether the verification result is successful, and if the verification result is successful, ending the PBCH decoding process of the current TTI and continuing the PBCH decoding process of the next TTI.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when the verification result is a verification failure, determine whether all SFN indexes have been traversed. If not all SFN indexes have been traversed, notify the soft merging module to perform de-sub-block interleaving, de-SFN masking and LLR soft merging on the second SSB LLR according to the SFN index that has not been traversed to obtain a third SSB LLR.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when all SFN indexes have been traversed, determining whether all SSB indexes have been traversed; when all SSB indexes have not been traversed, notifying the rate matching module to perform secondary descrambling and repetitive rate matching processing on the input first SSB LLR according to the SSB index that has not been traversed to obtain a second SSB LLR.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when all SFN indexes and all SSB indexes have been traversed, the decoding process of the next SSB burst set cycle is performed.

The data detection device of the embodiment of the present application can be arranged in a mobile terminal, a computer terminal terminal or similar computing device.

The data detection device of the embodiment of the present application can perform PBCH decoding during the initial cell selection, or cell switching or reselection process. The initial cell selection is when the terminal is turned on or enters a service area from an out-of-service area, the terminal contacts the base station and selects a suitable cell to reside in, and extracts system messages; cell switching and reselection both involve changes in the service cell. The difference is that cell switching is a change in the service cell when the terminal is in a call state, while cell reselection is a change in the service cell when the terminal is in an idle state.

During the initial cell selection, the SSB burst set period is 20ms, the TTI is 4 times the SSB burst set period, and the number of SSB LLRs transmitted in one TTI is 4 times the number of SSB LLRs transmitted in one SSB burst set period.

However, during cell switching and reselection, the SSB burst set period can be any one of 5ms, 10ms, 20ms, 40ms, 80ms, and 160ms. The number of SSB LLRs transmitted in one TTI is 16, 8, 4, 2, 1, and 1 times the number of SSB LLRs transmitted in one SSB burst set period, respectively. The corresponding number of SFN indexes is 16, 8, 4, 4, 4, and 4, respectively.

Different SSB burst set periods within the same TTI can be soft-merged for LLR to improve the signal-to-noise ratio, while when the SSB burst set period is 80ms and 160ms, there is no need to perform SFN mask removal and LLR soft merging. Taking the SSB burst set period of 20ms and TTI of 80ms as an example, the first SSB LLR within different SSB burst set periods is de-scrambled, repetition rate matched, sub-block interleaved according to the same SSB index, and de-SFN masked according to the same SFN index, and then added together to form the LLR soft merging process.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: when the SSB index is input into the rate-dematching module through the hardware circuit, the first SSB LLR is input into the rate-dematching module through the software or the hardware circuit, the rate-dematching module is controlled to perform a secondary descrambling process and a de-repeated rate matching process on the first SSB LLR to obtain a second SSB LLR, and the SFN index is input into the soft merging module through the hardware circuit, the rate-dematching module is controlled to be in an enabled state, the first SSB LLR is received through the rate-dematching module, and the secondary descrambling process and the de-repeated rate matching process are performed on the first SSB LLR through the rate-dematching module. The rate matching process obtains the second SSB LLR. After obtaining the second SSB LLR corresponding to an SSB index, the rate matching module is notified to send a start indication to the soft merging module. The soft merging module performs sub-block interleaving, SFN masking and LLR soft merging on the second SSB LLR according to the SFN index to obtain a third SSB LLR. Every time the soft merging module obtains a third SSB LLR, the third SSB LLR is sent to the decoding and verification module for decoding and CRC processing to obtain decoded data and verification results.

In some exemplary embodiments, as shown in FIGS. 2 and 3 , the rate dematching module includes: a secondary scrambling code generating unit, configured to generate a secondary scrambling code according to an SSB index; a secondary descrambling unit, configured to perform secondary descrambling processing on the first SSB LLR according to the secondary scrambling code to obtain a fourth SSB LLR; and a derepetition rate matching unit, configured to perform derepetition rate matching processing on the fourth SSB LLR to obtain a second SSB LLR.

In some exemplary embodiments, the data detection device further includes: at least one of a first multiplexer (such as Mux1 in FIG. 2 ) and a second multiplexer (such as Mux2 in FIG. 2 ).

Among them, the output end of the first multiplexer is connected to the input end of the secondary scrambling code generation unit, one of the input ends of the first multiplexer is connected to the SSB index input through the software, that is, it is connected to the processor, the SSB index output by the front-end hardware circuit is input to the processor, and the processor inputs the SSB index into the secondary scrambling code generation unit, and the other input end of the first multiplexer is connected to the SSB index input through the hardware circuit, that is, the SSB index output by the front-end hardware circuit is directly input into the secondary scrambling code generation unit.

Among them, the output end of the second multiplexer is connected to the input end of the secondary descrambling unit, one of the input ends of the second multiplexer is connected to the first SSB LLR input through the software, that is, it is connected to the processor, the first SSB LLR output by the front-end hardware circuit is input to the processor, and the processor inputs the first SSB LLR into the secondary descrambling unit, and the other input end of the second multiplexer is connected to the first SSB LLR input through the hardware circuit, that is, the first SSB LLR output by the front-end hardware circuit is directly input to the secondary descrambling unit.

When at least one program is executed by at least one processor, the following method is used to control whether the SSB index is input into the rate matching module through software or hardware circuit: controlling the first multiplexer to select whether the SSB index is input into the rate matching module through software or hardware circuit In the secondary scrambling code generation unit.

When at least one program is executed by at least one processor, the following method is used to control whether the first SSB LLR is input into the rate dematching module through software or hardware circuit: control the second multiplexer to select whether the first SSB LLR is input into the secondary descrambling unit through software or hardware circuit.

In some exemplary embodiments, as shown in FIG. 2 , the rate de-matching module further includes: a second memory configured to store a second SSB LLR; and a third multiplexer (such as Mux3 in FIG. 2 ).

Among them, the output end of the third multiplexer is connected to the input end of the second memory, one of the input ends of the third multiplexer is connected to the de-repetition rate matching unit, and the other input end of the third multiplexer is connected to the second SSB LLR input through software, that is, connected to the processor, the second SSB LLR output by the de-repetition rate matching unit is input to the processor, and the processor inputs the second SSB LLR into the other input end of the third multiplexer.

When at least one program is executed by at least one processor, the following steps are also implemented: controlling the third multiplexer to select whether to store the second SSB LLR in the second memory through the de-repetition rate matching unit, or to write the second SSB LLR to the second memory through software.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when the second SSB LLR is written to the second memory by software, the rate dematching module is enabled and the soft merging module is disabled; after the rate dematching module performs secondary descrambling and repetitive rate matching processing on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the rate dematching module is disabled and the second SSB LLR is written to the second memory; the soft merging module is enabled.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are further implemented: when the third multiplexer is controlled to select to write the second SSB LLR to the second memory through software, the secondary scrambling code generation unit, the secondary descrambling unit, and the de-repetition rate matching unit are controlled to be in an enabled state, and the soft merging module is controlled to be in a disabled state; after the de-repetition rate matching unit performs de-repetition rate matching processing on the fourth SSB LLR to obtain the second SSB LLR, the secondary scrambling code generation unit, the secondary descrambling unit, and the de-repetition rate matching unit are controlled to be in a disabled state, and the de-repetition rate matching unit is controlled to be in a disabled state. The matching unit stops writing the second SSB LLR into the second memory, reads the second SSB LLR output by the de-repetition rate matching unit, and writes the second SSB LLR into the second memory; and controls the soft merging module to be in an enabled state.

In some exemplary embodiments, as shown in Figure 3, the rate dematching module also includes: a third memory configured to store the first SSB LLR.

The output end of the second multiplexer is connected to the input end of the third memory, the output end of the third memory is connected to the input end of the secondary descrambling unit, one of the input ends of the second multiplexer is connected to the first SSB LLR input through the software, that is, it is connected to the processor, the first SSB LLR output by the front-end hardware circuit is input to the processor, and the processor inputs the first SSB LLR into the third memory, and the other input end of the second multiplexer is connected to the first SSB LLR input through the hardware circuit, that is, the first SSB LLR output by the front-end hardware circuit is directly input into the third memory.

In some exemplary embodiments, the soft merging module includes: an SFN mask generation unit, configured to generate an SFN mask according to an SFN index; a de-sub-block interleaving unit, configured to perform de-sub-block interleaving processing on the second SSB LLR to obtain a fifth SSB LLR; a de-SFN mask unit, configured to perform de-SFN mask processing on the fifth SSB LLR according to the SFN mask to obtain a sixth SSB LLR; an LLR soft merging unit, configured to perform LLR soft merging processing on the sixth SSB LLR and the SSB LLR stored in a fourth memory to obtain a third SSB LLR; or, output the sixth SSB LLR as the third SSB LLR; the LLR soft merging unit is also configured to: store the third SSB LLR in a fourth memory; a fourth memory, configured to store a third synchronization signal block; a fourth multiplexer (such as Mux4 in Figures 2 and 3) and a fifth multiplexer (such as Mux5 in Figures 2 and 3).

The output end of the fourth multiplexer is connected to the input end of the LLR soft combining unit, one of the input ends of the fourth multiplexer is connected to data 0, and the other input end of the fourth multiplexer is connected to the output end of the SFN mask removal unit.

The output end of the fifth multiplexer is connected to the input end of the LLR soft combining unit, one of the input ends of the fifth multiplexer is connected to data 0, and the other input end of the fifth multiplexer is connected to the output end of the fourth memory.

When the at least one program is executed by the at least one processor, the following steps are also implemented: controlling the fourth multiplexer to select data 0 or the sixth SSB output by the SFN mask decryption unit The LLR is input to the LLR soft merging unit; the fifth multiplexer is controlled to select data 0 or the SSB LLR stored in the fourth memory to be input to the LLR soft merging unit; and the de-sub-block interleaving unit, the de-SFN mask unit, and the SFN mask generation unit are used to control whether the second SSB LLR is de-sub-block interleaved and the system frame number mask is de-masked, or whether the second SSB LLR is de-sub-block interleaved and the SFN mask is de-masked by software.

In some exemplary embodiments, the data 0 connected to one of the input terminals of the fourth multiplexer and the data 0 connected to one of the input terminals of the fifth multiplexer can both be generated by hardware circuits.

In some exemplary embodiments, when the fourth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the sixth SSB LLR output by the SFN mask de-masking unit is bypassed, and when the fifth multiplexer is controlled to select the SSB LLR stored in the fourth memory to be input into the LLR soft merging unit, the sixth SSB LLR output by the SFN mask de-masking unit in the previous SSB burst set cycle or the third SSB LLR of the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft merging unit, and then the sixth SSB LLR output by the SFN mask de-masking unit in the previous SSB burst set cycle or the third SSB LLR of the previous SSB burst set cycle is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the sixth SSB LLR output by the SFN mask de-masking unit in the previous SSB burst set cycle or the third SSB LLR of the previous SSB burst set cycle.

When the fourth multiplexer is controlled to select the sixth SSB LLR output by the SFN mask de-masking unit to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle is input into the LLR soft merging unit, when the fifth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and then the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle.

When the fourth multiplexer is controlled to select the sixth SSB LLR output by the SFN mask decryption unit to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask decryption unit in the current SSB burst set cycle is input into the LLR soft merging unit, When the fifth multiplexer selects to input the SSB LLR stored in the fourth memory into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft merging unit, and then the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle or the third SSB LLR in the previous SSB burst set cycle and the sixth SSB LLR output by the SFN mask decryption unit in the current SSB burst set cycle are subjected to LLR soft merging processing, and the soft merging result is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the result of adding the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle or the third SSB LLR in the previous SSB burst set cycle and the sixth SSB LLR output by the SFN mask decryption unit in the current SSB burst set cycle.

When the fourth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the sixth SSB LLR output by the SFN mask de-masking unit is bypassed; when the fifth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and the soft merging result is 0.

In some exemplary embodiments, the LLR soft combining process may be an addition.

As described above, different soft merging requirements can be achieved by controlling the fourth multiplexer and the fifth multiplexer controller to select different data channels. For example, when the BBS burst set period is 80ms and 160ms; or, when the BBS burst set period is any one of 5ms, 10ms, 20ms, and 40ms, and the current is the first BBS burst set period of TTI, LLR soft merging cannot be performed, then the fifth multiplexer controller can be controlled to input data 0 into the LLR soft merging unit.

When the BBS burst set period is any one of 5ms, 10ms, 20ms, and 40ms, and the current period is not the first BBS burst set period of TTI, LLR soft merging is performed. Then, the sixth SSB LLR output by the SFN mask de-masking unit in the previous SSB burst set period stored in the fourth memory can be input into the LLR soft merging unit by controlling the fifth multiplexing controller.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: controlling whether the generation of the SFN mask, the de-sub-block interleaving processing, and the de-SFN mask processing are implemented by software or by hardware circuits.

When the generation of SFN mask, de-sub-block interleaving and de-SFN mask processing are implemented by software, the de-rate matching module is controlled to be in an enabled state. After the de-repetition rate matching unit stops writing the second SSB LLR to the second memory, the de-rate matching module is controlled to be in a non-enabled state, and the second SSB LLR stored in the second memory is read; an SFN mask is generated, and the second SSB LLR is de-sub-block interleaving is performed on the second SSB LLR according to the generated SFN mask, and the sixth SSB LLR is obtained by de-SFN mask processing; the sixth SSB LLR is written to the fourth memory.

In this case, the LLR soft merging unit is further configured to: read the third SSB LLR of the previous BBS burst set cycle and the sixth SSB LLR of the current BBS burst set cycle stored in the fourth memory, perform LLR soft merging processing to obtain the third SSB LLR of the current BBS burst set cycle, and store the third SSB LLR of the current BBS burst set cycle in the fourth memory.

In some exemplary embodiments, it also includes: a sixth multiplexer (such as Mux6 as shown in Figures 2 and 3); the output end of the sixth multiplexer is connected to the input end of the SFN mask generation unit, one of the input ends of the sixth multiplexer is connected to the SFN index input through software, that is, connected to the processor, and the processor reads the SFN index from other hardware modules and inputs it, and the other input end of the sixth multiplexer is connected to the SFN index input through the hardware circuit.

When at least one program is executed by at least one processor, the following steps are also implemented: controlling the sixth multiplexer to choose whether to input the SFN index through software or through hardware circuit.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when the second SSB LLR is subjected to de-subblock interleaving and de-SFN masking by software, before the de-rate matching module performs de-secondary scrambling and de-repetitive rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is enabled; after the de-rate matching module performs de-secondary scrambling and de-repetitive rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is disabled; the second SSB LLR is read; the second SSB LLR is subjected to de-subblock interleaving and de-SFN masking to obtain the sixth SSB LLR; the sixth SSB LLR is converted into Write to the fourth memory.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are implemented: when the verification result is a verification failure, the second SSB LLR stored in the second memory is read to perform data analysis and error detection, and the third SSB LLR stored in the fourth memory is read to perform data analysis and error detection.

In some exemplary embodiments, the number of the second memories may be one or more.

In some exemplary embodiments, the number of the third memory may be one or more.

In some exemplary embodiments, the number of the fourth memory may be one or more.

In some exemplary embodiments, different second memories may be selected by switching through a multiplexer.

In some exemplary embodiments, different third memories may be selected by switching through a multiplexer.

In some exemplary embodiments, different fourth memories may be selected by switching through a multiplexer.

In some exemplary embodiments, the decoding and verification module includes: a Polar code decoding unit and a CRC unit.

Among them, the Polar code decoding unit is configured to decode the third SSB LLR to obtain decoded data.

The CRC unit is configured to perform CRC processing on the decoded data to obtain a check result.

In some exemplary embodiments, the processor is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the first memory or the second memory or the third memory or the fourth memory is a device with data storage capabilities, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH).

The data detection device provided in the embodiment of the present application realizes the detection of PBCH data by combining software and hardware circuits, thereby improving flexibility. The detection of PBCH data is realized by at least one rate matching module and at least one soft combining module. Greatly simplifies the data detection process.

FIG. 4 is a flow chart of a data detection method provided in another embodiment of the present application.

In a second aspect, referring to FIG. 4 , another embodiment of the present application provides a data detection method, which can be applied to a mobile terminal, a computer terminal, or other similar computing devices, for example, a communication device in a wireless communication system, and the communication device can be at least one of a user equipment, a base station, etc. The data detection method may include steps 400 to 402.

In step 400, at least one rate dematching module is used to perform secondary descrambling and repetition rate matching processing on the input first SSB LLR according to the SSB index to obtain a second SSB LLR; wherein different rate dematching modules correspond to different SSB indices.

In some exemplary embodiments, different rate matching modules correspond to different decoding channels, and different rate matching modules correspond to different SSB indexes. That is, in the same data detection process, the SSB index input into the rate matching module is different, that is, the process of blind detection using different SSB indexes.

In some exemplary embodiments, different soft merging modules connected to the same rate matching module correspond to different decoding channels, and different soft merging modules connected to the same rate matching module correspond to different SFN indexes. That is, when the same SSB index is used for data detection, the SFN indexes input to different soft merging modules connected to the same rate matching module are different, that is, the process of blind detection using different SFN indexes.

In some exemplary embodiments, performing de-secondary scrambling and de-repetition rate matching on an input first SSB LLR according to an SSB index to obtain a second SSB LLR through a de-rate matching module includes: generating a secondary scrambling code according to the SSB index through a secondary scrambling code generating unit; performing de-secondary scrambling on the first SSB LLR according to the secondary scrambling code through a de-secondary scrambling unit to obtain a fourth SSB LLR; and performing de-repetition rate matching on the fourth SSB LLR through a de-repetition rate matching unit to obtain a second SSB LLR.

In some exemplary embodiments, the first multiplexer can be controlled to select whether to input the SSB index into the secondary scrambling code generation unit through software or hardware circuit.

In some exemplary embodiments, whether the first SSB LLR is input to the de-scrambling unit through software or hardware circuit can be selected by controlling the second multiplexer.

In some exemplary embodiments, after performing de-repetition rate matching processing on the fourth SSB LLR through a de-repetition rate matching unit to obtain a second SSB LLR, the method further includes: controlling a third multiplexer to select whether to store the second SSB LLR in a second memory through the de-repetition rate matching unit, or to write the second SSB LLR into the second memory through software.

In some exemplary embodiments, when the second SSB LLR is written to the second memory by software, the rate dematching module is enabled and the soft merging module is disabled; after the rate dematching module performs secondary descrambling and repetitive rate matching processing on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the rate dematching module is disabled and the second SSB LLR is written to the second memory; the soft merging module is enabled.

In some exemplary embodiments, when controlling the third multiplexer to select to write the second SSB LLR into the second memory through software, the secondary scrambling code generation unit, the secondary descrambling unit, and the derepetition rate matching unit are controlled to be in an enabled state, and the soft merging module is controlled to be in a disabled state; after the derepetition rate matching unit performs derepetition rate matching processing on the fourth SSB LLR to obtain the second SSB LLR, the secondary scrambling code generation unit, the secondary descrambling unit, and the derepetition rate matching unit are controlled to be in a disabled state, the derepetition rate matching unit is controlled to stop writing the second SSB LLR into the second memory, the second SSB LLR output by the derepetition rate matching unit is read, and the second SSB LLR is written into the second memory; the soft merging module is controlled to be in an enabled state.

In some exemplary embodiments, when the second SSB LLR is subjected to de-sub-block interleaving and de-SFN masking by software, before the de-rate matching module performs de-secondary scrambling and de-repetitive rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is enabled; after the de-rate matching module performs de-secondary scrambling and de-repetitive rate matching on the input first SSB LLR according to the SSB index to obtain the second SSB LLR, the de-rate matching module is disabled; the second SSB LLR is read; the second SSB LLR is de-sub-block interleaving and de-SFN masking are performed on the second SSB LLR to obtain a sixth SSB LLR; and the sixth SSB LLR is written into the fourth memory.

In step 401, at least one soft-closer connected to the same rate matching module is used. The module implements de-sub-block interleaving, de-SFN masking and LLR soft merging processing on the second SSB LLR according to the SFN index to obtain a third SSB LLR; wherein different soft merging modules connected to the same de-rate matching module correspond to different SFN indices.

In some exemplary embodiments, performing de-sub-block interleaving, de-SFN masking and LLR soft merging on the second SSB LLR according to the SFN index to obtain the third SSB LLR through the soft merging module includes: generating an SFN mask according to the SFN index through the SFN mask generating unit; performing de-sub-block interleaving on the second SSB LLR through the de-sub-block interleaving unit to obtain a fifth SSB LLR; performing de-SFN masking on the fifth SSB LLR according to the SFN mask through the de-SFN mask unit to obtain a sixth SSB LLR; performing LLR soft merging on the sixth SSB LLR and the SSB LLR stored in the fourth memory through the LLR soft merging unit to obtain a third SSB LLR; or, outputting the sixth SSB LLR as the third SSB LLR; storing the third SSB LLR in the fourth memory through the LLR soft merging unit; and storing the third synchronization signal block through the fourth memory.

In some exemplary embodiments, the fourth multiplexer is controlled to select data 0 or the sixth SSB LLR output by the SFN mask de-coding unit to be input into the LLR soft merging unit; the fifth multiplexer is controlled to select data 0 or the SSB LLR stored in the fourth memory to be input into the LLR soft merging unit; and the de-sub-block interleaving unit, the de-SFN mask unit, and the SFN mask generating unit are used to control whether the second SSB LLR is de-sub-block interleaved and the system frame number mask is de-coded, or whether the second SSB LLR is de-sub-block interleaved and the SFN mask is de-coded by software.

In some exemplary embodiments, when the fourth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the sixth SSB LLR output by the SFN mask decryption unit is bypassed, and when the fifth multiplexer is controlled to select the SSB LLR stored in the fourth memory to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle or the third SSB LLR in the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft merging unit, and then the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle or the third SSB LLR in the previous SSB burst set cycle is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle or the third SSB LLR in the previous SSB burst set cycle. 3rd SSB LLR.

When the fourth multiplexer is controlled to select the sixth SSB LLR output by the SFN mask de-masking unit to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle is input into the LLR soft merging unit, when the fifth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and then the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the sixth SSB LLR output by the SFN mask de-masking unit in this SSB burst set cycle.

When the fourth multiplexer is controlled to select the sixth SSB LLR output by the SFN mask decryption unit to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask decryption unit in the current SSB burst set cycle is input into the LLR soft merging unit, when the fifth multiplexer is controlled to select the SSB LLR stored in the fourth memory to be input into the LLR soft merging unit, that is, the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle stored in the fourth memory is input into the LLR soft merging unit, and then the sixth SSB LLR output by the SFN mask decryption unit in the previous SSB burst set cycle is input into the LLR soft merging unit. The soft merging result of the sixth SSB LLR outputted by the SFN mask de-masking unit in the current SSB burst set cycle after LLR soft merging processing is input into the Polar code decoding unit for decoding processing, that is, the soft merging result is the result of adding the sixth SSB LLR outputted by the SFN mask de-masking unit in the previous SSB burst set cycle or the third SSB LLR of the previous SSB burst set cycle and the sixth SSB LLR outputted by the SFN mask de-masking unit in the current SSB burst set cycle.

When the fourth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the sixth SSB LLR output by the SFN mask de-masking unit is bypassed; when the fifth multiplexer is controlled to select data 0 to be input into the LLR soft merging unit, the SSB LLR stored in the fourth memory is bypassed, and the soft merging result is 0.

In some exemplary embodiments, the LLR soft combining process may be an addition.

As described above, different soft merging requirements can be achieved by controlling the fourth multiplexer and the fifth multiplexer controller to select different data channels. For example, when the BBS burst set period is 80ms and 160ms; or when the BBS burst set period is 5ms, 10ms, If the time interval is any one of 20ms and 40ms and the current period is the first BBS burst set period of TTI, LLR soft merging cannot be performed. Then, the fifth multiplexer controller can be controlled to input data 0 into the LLR soft merging unit.

When the BBS burst set period is any one of 5ms, 10ms, 20ms, and 40ms, and the current period is not the first BBS burst set period of TTI, LLR soft merging is performed. Then, the sixth SSB LLR output by the SFN mask de-masking unit in the previous SSB burst set period stored in the fourth memory can be input into the LLR soft merging unit by controlling the fifth multiplexing controller.

In some exemplary embodiments, the method further includes: controlling whether the generation of the SFN mask, de-subblock interleaving, and de-SFN mask processing are implemented by software or by hardware circuits.

When the generation of SFN mask, de-sub-block interleaving and de-SFN mask processing are implemented by software, the de-rate matching module is controlled to be in an enabled state. After the de-repetition rate matching unit stops writing the second SSB LLR to the second memory, the de-rate matching module is controlled to be in a non-enabled state, and the second SSB LLR stored in the second memory is read; an SFN mask is generated, and the second SSB LLR is de-sub-block interleaving is performed on the second SSB LLR according to the generated SFN mask, and the sixth SSB LLR is obtained by de-SFN mask processing; the sixth SSB LLR is written to the fourth memory.

In this case, the LLR soft merging unit is further configured to: read the third SSB LLR of the previous BBS burst set cycle and the sixth SSB LLR of the current BBS burst set cycle stored in the fourth memory, perform LLR soft merging processing to obtain the third SSB LLR of the current BBS burst set cycle, and store the third SSB LLR of the current BBS burst set cycle in the fourth memory.

In some exemplary embodiments, the method further includes: controlling a sixth multiplexer to select whether to input the SFN index through software or through a hardware circuit.

In step 402, the third SSB LLR is decoded and CRC processed by a decoding and verification module connected to the soft merging module to obtain decoded data and verification results.

In some exemplary embodiments, the decoding and CRC processing of the third SSB LLR by the decoding and verification module connected to the soft combining module to obtain the decoded data and the verification result includes: decoding and processing the third SSB LLR by the Polar code decoding unit The decoded data is obtained; and a CRC unit is used to perform CRC processing on the decoded data to obtain a verification result.

In some exemplary embodiments, the rate-decoding module, the soft-merging module and the decoding and checking module are implemented using hardware circuits.

In some exemplary embodiments, the data detection method also includes at least one of the following steps: controlling whether the SSB index is input into the rate dematching module through software or hardware circuit; controlling whether the first SSB LLR is input into the rate dematching module through software or hardware circuit; controlling whether the rate dematching module performs secondary descrambling and repetitive rate matching processing on the first SSB LLR to obtain the second SSB LLR, or performs secondary descrambling and repetitive rate matching processing on the first SSB LLR through software to obtain the second SSB LLR; controlling whether the software or hardware circuit is used to input the SFN index into the soft merging module.

In some exemplary embodiments, when the SSB index is input into the rate-dematching module through a hardware circuit, the first SSB LLR is input into the rate-dematching module through software or hardware circuit, the rate-dematching module is controlled to perform secondary scrambling and repetitive rate matching on the first SSB LLR to obtain a second SSB LLR, and the SFN index is input into the soft merging module through a hardware circuit, the rate-dematching module is controlled to be in an enabled state, the first SSB LLR is received through the rate-dematching module, and the first SSB LLR is processed through the rate-dematching module. The LLR performs de-secondary scrambling and de-repetition rate matching processing to obtain the second SSB LLR. After obtaining the second SSB LLR corresponding to an SSB index, the de-rate matching module is notified to send a start indication to the soft merging module. The soft merging module performs de-sub-block interleaving, de-SFN masking and LLR soft merging processing on the second SSB LLR according to the SFN index to obtain the third SSB LLR. Every time the soft merging module obtains a third SSB LLR, the third SSB LLR is sent to the decoding and verification module for decoding and CRC processing to obtain the decoded data and verification results.

In some exemplary embodiments, after the third SSB LLR is decoded and cyclic redundancy code checked by a decoding check module connected to the soft merging module to obtain decoded data and a check result, the method further includes: determining whether the check result is successful, and if the check result is successful, terminating the PBCH decoding process of the current TTI and continuing the PBCH decoding process of the next TTI.

In some exemplary embodiments, when the verification result is a verification failure, it is determined whether all SFN indexes have been traversed. If not all SFN indexes have been traversed, the soft merging module is notified to perform sub-block deinterleaving, SFN masking and LLR soft merging on the second SSB LLR according to the SFN index that has not been traversed to obtain the third SSB LLR.

In some exemplary embodiments, when all SFN indexes have been traversed, it is determined whether all SSB indexes have been traversed. When all SSB indexes have not been traversed, the rate dematching module is notified to perform secondary descrambling and repetitive rate matching processing on the input first SSB LLR according to the SSB index that has not been traversed to obtain the second SSB LLR.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when all SFN indexes and all SSB indexes have been traversed, the PBCH decoding process of the current TTI is terminated, and the PBCH decoding process of the next TTI is continued.

In some exemplary embodiments, when at least one program is executed by at least one processor, the following steps are also implemented: when all SFN indexes and all SSB indexes have been traversed, the decoding process of the next SSB burst set cycle is performed.

The data detection method of the embodiment of the present application can be applied in a mobile terminal, a computer terminal or similar computing devices.

The data detection method of the embodiment of the present application can perform PBCH decoding during the initial cell selection, or cell switching or reselection process. The initial cell selection is when the terminal is turned on or enters a service area from an out-of-service area, the terminal contacts the base station and selects a suitable cell to reside in, and extracts system messages; cell switching and reselection both involve changes in the service cell. The difference is that cell switching is a change in the service cell when the terminal is in a call state, while cell reselection is a change in the service cell when the terminal is in an idle state.

During the initial cell selection, the SSB burst set period is 20ms, the TTI is 4 times the SSB burst set period, and the number of SSB LLRs transmitted in one TTI is 4 times the number of SSB LLRs transmitted in one SSB burst set period.

However, during cell switching and reselection, the SSB burst set period can be any one of 5ms, 10ms, 20ms, 40ms, 80ms, and 160ms. The SSB transmitted within a TTI The number of LLRs is 16, 8, 4, 2, 1, and 1 times the number of SSB LLRs transmitted in one SSB burst set period, and the corresponding numbers of SFN indexes are 16, 8, 4, 4, 4, and 4, respectively.

Different SSB burst set periods within the same TTI can be soft-merged for LLR to improve the signal-to-noise ratio, while when the SSB burst set period is 80ms and 160ms, there is no need to perform SFN mask removal and LLR soft merging. Taking the SSB burst set period of 20ms and TTI of 80ms as an example, the first SSB LLR within different SSB burst set periods is de-scrambled, repetition rate matched, and sub-block interleaved according to the same SSB index and the same SFN index, and then de-SFN masked according to the same SFN index, and then added together, which is the LLR soft merging process.

The implementation process of the above data detection method is the same as the implementation process of the data detection device in the aforementioned embodiment, and will not be repeated here.

It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules/units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally include computer-readable instructions, data structures, program modules, or other media such as carrier waves or Other data in a modulated data signal such as other transport mechanisms, and may include any information delivery media.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and/or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims (11)

A data detection device, comprising: At least one rate matching module, each of which is connected to at least one soft combining module, each of which is connected to a decoding and checking module, and at least one processor and a first memory; The de-rate matching module is configured to perform a de-secondary scrambling process and a de-repetition rate matching process on the input first synchronization signal block log-likelihood probability according to the synchronization signal block index to obtain a second synchronization signal block log-likelihood probability; The soft merging module is configured to perform sub-block deinterleaving, system frame number demasking and log-likelihood probability soft merging processing on the log-likelihood probability of the second synchronization signal block according to the system frame number index to obtain the log-likelihood probability of the third synchronization signal block; The decoding and verification module is configured to perform decoding processing and cyclic redundancy code verification processing on the log-likelihood probability of the third synchronization signal block to obtain decoded data and a verification result; Wherein, the rate matching module, the soft combining module and the decoding verification module are implemented by hardware circuits; The first memory stores at least one program, and when the at least one program is executed by the at least one processor, at least one of the following steps is implemented: Controlling whether the synchronization signal block index is input into the de-rate matching module through software or hardware circuit; Controlling whether the first synchronization signal block log-likelihood probability is input into the de-rate matching module through software or hardware circuit; Controlling whether to perform a de-secondary scrambling process and a de-repetition rate matching process on the first synchronization signal log-likelihood probability through the de-rate matching module to obtain the log-likelihood probability of the second synchronization signal block, or to perform a de-secondary scrambling process and a de-repetition rate matching process on the first synchronization signal log-likelihood probability through software to obtain the log-likelihood probability of the second synchronization signal block; Control whether the system frame number index is input into the soft merging module through software or hardware circuit. The data detection device according to claim 1, wherein the solution rate matches Modules include: A secondary scrambling code generating unit, configured to generate a secondary scrambling code according to the synchronization signal block index; a de-scrambling unit configured to perform a de-scrambling process on the log-likelihood probability of the first synchronization signal block according to the secondary scrambling code to obtain a log-likelihood probability of a fourth synchronization signal block; a de-repetition rate matching unit, configured to perform a de-repetition rate matching process on the log-likelihood probability of the fourth synchronization signal block to obtain the log-likelihood probability of the second synchronization signal block; The data detection device further includes: at least one of a first multiplexer and a second multiplexer; Wherein, the output end of the first multiplexer is connected to the input end of the secondary scrambling code generating unit, one of the input ends of the first multiplexer is connected to the synchronization signal block index input through software, and the other input end of the first multiplexer is connected to the synchronization signal block index input through a hardware circuit; Wherein, the output end of the second multiplexer is connected to the input end of the de-scrambling unit, one of the input ends of the second multiplexer is connected to the log-likelihood probability of the first synchronization signal block input through software, and the other input end of the second multiplexer is connected to the log-likelihood probability of the first synchronization signal block input through a hardware circuit; When the at least one program is executed by the at least one processor, the control of inputting the synchronization signal block index into the de-rate matching module through software or hardware circuit is implemented in the following manner: controlling the first multiplexer to select whether to input the synchronization signal block index into the secondary scrambling code generation unit through software or hardware circuit; When the at least one program is executed by the at least one processor, the control of whether to input the log-likelihood probability of the first synchronization signal block into the de-rate matching module through software or hardware circuit is implemented in the following manner: controlling the second multiplexer to select whether to input the log-likelihood probability of the first synchronization signal block into the de-secondary scrambling unit through software or hardware circuit. The data detection device according to claim 2, wherein the rate matching module further comprises: include: A second memory configured to store the second synchronization signal block log-likelihood probability; A third multiplexer; The output end of the third multiplexer is connected to the input end of the second memory, one of the input ends of the third multiplexer is connected to the de-repetition rate matching unit, and the other input end of the third multiplexer is connected to the log-likelihood probability of the second synchronization signal block input by software; When the at least one program is executed by the at least one processor, the following steps are also implemented: Control the third multiplexer to select whether to store the second synchronization signal block log-likelihood probability into the second memory through the de-repetition rate matching unit, or to write the second synchronization signal block log-likelihood probability into the second memory through software. According to the data detection device of claim 3, when the at least one program is executed by the at least one processor, the following steps are further implemented: When the log-likelihood probability of the second synchronization signal block is written into the second memory by software, the rate solution matching module is enabled and the soft combining module is disabled; After the rate dematching module performs a de-secondary scrambling process and a de-repetition rate matching process on the input first synchronization signal block log-likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block log-likelihood probability, the rate dematching module is placed in a disabled state, and the second synchronization signal block log-likelihood probability is written into the second memory; The soft merging module is enabled. According to the data detection device according to claim 2, the rate matching module further comprises: A third memory is configured to store the log-likelihood probability of the first synchronization signal block. The data detection device according to claim 1, wherein the soft merging module comprises: a system frame number mask generating unit, configured to generate a system frame number mask according to the system frame number index; a de-sub-block interleaving unit, configured to perform a de-sub-block interleaving process on the second synchronization signal block log-likelihood probability to obtain a fifth synchronization signal block log-likelihood probability; a system frame number demasking unit, configured to perform a system frame number demasking process on the log-likelihood probability of the fifth synchronization signal block according to the system frame number mask to obtain the log-likelihood probability of the sixth synchronization signal block; A log-likelihood probability soft merging unit is configured to perform a log-likelihood probability soft merging process on the sixth synchronization signal block log-likelihood probability and the synchronization signal block log-likelihood probability stored in the fourth memory to obtain the third synchronization signal block log-likelihood probability; or, output the sixth synchronization signal block log-likelihood probability as the third synchronization signal block log-likelihood probability; the log-likelihood probability soft merging unit is further configured to: store the third synchronization signal block log-likelihood probability in the fourth memory; The fourth memory is configured to store the third synchronization signal block; a fourth multiplexer and a fifth multiplexer; The output end of the fourth multiplexer is connected to the input end of the log-likelihood probability soft combining unit, one of the input ends of the fourth multiplexer is connected to data 0, and the other input end of the fourth multiplexer is connected to the output end of the de-system frame number mask unit; The output end of the fifth multiplexer is connected to the input end of the log-likelihood probability soft combining unit, one of the input ends of the fifth multiplexer is connected to data 0, and the other input end of the fifth multiplexer is connected to the output end of the fourth memory; When the at least one program is executed by the at least one processor, the following steps are also implemented: Controlling the fourth multiplexer to select data 0 or the sixth synchronization signal block log-likelihood probability output by the de-system frame number mask unit to be input into the log-likelihood probability soft-merging unit; Controlling the fifth multiplexer to select data 0 or the log-likelihood probability of the synchronization signal block stored in the fourth memory to be input into the log-likelihood probability soft merging unit; Control whether to perform sub-block interleaving and system frame number masking on the log-likelihood probability of the second synchronization signal block through the de-sub-block interleaving unit, the de-system frame number masking unit, and the system frame number masking generating unit, or to perform de-sub-block interleaving and system frame number masking on the second synchronization signal block through software The signal block log-likelihood probability is de-sub-block interleaved and the system frame number masked. The data detection device according to claim 6, further comprising: a sixth multiplexer; The output end of the sixth multiplexer is connected to the input end of the system frame number mask generating unit, one of the input ends of the sixth multiplexer is connected to the system frame number index input through software, and the other input end of the sixth multiplexer is connected to the system frame number index input through a hardware circuit; When the at least one program is executed by the at least one processor, the following steps are also implemented: The sixth multiplexer is controlled to select whether to input the system frame number index through software or through a hardware circuit. According to the data detection device of claim 6, when the at least one program is executed by the at least one processor, the following steps are further implemented: In the case where the sub-block interleaving process and the system frame number mask process are performed on the log-likelihood probability of the second synchronization signal block by software, before the rate-decoding module performs the secondary scrambling process and the repetition rate matching process on the input first synchronization signal block log-likelihood probability according to the synchronization signal block index to obtain the log-likelihood probability of the second synchronization signal block, the rate-decoding module is enabled; After the rate dematching module performs a de-secondary scrambling process and a de-repetition rate matching process on the input first synchronization signal block log likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block log likelihood probability, the rate dematching module is placed in a disabled state; Reading the log-likelihood probability of the second synchronization signal block; Performing sub-block deinterleaving and system frame number demasking processing on the log-likelihood probability of the second synchronization signal block to obtain the log-likelihood probability of the sixth synchronization signal block; The log-likelihood probability of the sixth synchronization signal block is written into the fourth memory. The data detection device according to any one of claims 1 to 8, wherein different de-rate matching modules correspond to different synchronization signal block indexes. The data detection device according to any one of claims 1 to 8, wherein different soft merging modules connected to the same derate matching module correspond to different systems. The frame number index. A data detection method, comprising: At least one de-rate matching module is used to perform de-secondary scrambling and de-repetition rate matching processing on the input first synchronization signal block logarithmic likelihood probability according to the synchronization signal block index to obtain the second synchronization signal block logarithmic likelihood probability; wherein different de-rate matching modules correspond to different synchronization signal block indexes; The log-likelihood probability of the third synchronization signal block is obtained by performing de-subblock interleaving, de-system frame number masking and log-likelihood probability soft merging processing on the log-likelihood probability of the second synchronization signal block according to the system frame number index through at least one soft merging module connected to the same de-rate matching module; wherein different soft merging modules connected to the same de-rate matching module correspond to different system frame number indexes; Performing decoding processing and cyclic redundancy code check processing on the log-likelihood probability of the third synchronization signal block through a decoding check module connected to the soft combining module to obtain decoded data and a check result; Wherein, the rate matching module, the soft combining module and the decoding verification module are implemented by hardware circuits; The data detection method further comprises at least one of the following steps: Controlling whether the synchronization signal block index is input into the de-rate matching module through software or hardware circuit; Controlling whether the first synchronization signal block log-likelihood probability is input into the de-rate matching module through software or hardware circuit; Controlling whether to perform a de-secondary scrambling process and a de-repetition rate matching process on the first synchronization signal log-likelihood probability through the de-rate matching module to obtain the log-likelihood probability of the second synchronization signal block, or to perform a de-secondary scrambling process and a de-repetition rate matching process on the first synchronization signal log-likelihood probability through software to obtain the log-likelihood probability of the second synchronization signal block; Control whether the system frame number index is input into the soft merging module through software or hardware circuit.