WO2025001399A1 - Method and apparatus for data check, and device, medium and product - Google Patents

Abstract

The embodiments of the present disclosure relate to a method and apparatus for a data check, and a device, a medium and a product. The method comprises: acquiring N groups of data from a memory, wherein each group of data among the N groups of data comprises a check bit, N being a positive integer greater than or equal to 2. The method further comprises: performing aggregation on the N groups of data to obtain aggregated data, and performing error correction code (ECC) encoding on the aggregated data to obtain encoded data, wherein the aggregated data comprises an aggregated check bit, and the aggregated check bit is an aggregation of the check bits of the N groups of data. The method further comprises: decomposing the encoded data into N groups of encoded data, among which each group of data comprises a check bit, and respectively writing the N groups of encoded data into the memory. Therefore, a plurality of single groups of data, which are read from a memory in unit, are aggregated to obtain a larger encoding unit, such that a memory ECC function with stronger error detection and error correction capabilities can be supported under the same hardware condition.

Description

Method, device, equipment, medium and product for data verification

This application claims priority to Chinese patent application with application number 202310792806.8 filed with the Chinese Patent Office on June 29, 2023 and invention name “A method for data error correction”, and Chinese patent application with application number 202311126669.0 filed with the Chinese Patent Office on August 31, 2023 and invention name “Method, device, equipment, medium and product for data verification”, the entire contents of which are incorporated into this application by reference.

Technical Field

Embodiments of the present application relate to the field of memory technology, and more specifically to methods, devices, equipment, media, and products for verifying data in a memory.

Background Art

In the application fields that require a lot of computing, such as artificial intelligence (AI), the demand for high performance and the integration of central processing unit (CPU) and graphics processing unit (GPU) computing power has led to the rapid development of high-performance computing (HPC) systems with computing power above E-level (supporting 1018 floating-point operations per second). Such high-computing systems have high requirements for memory bandwidth, which in turn promotes the widespread application of high-bandwidth memory (HBM) in HPC systems.

HBM is a high-performance dynamic random access memory based on 3D stacking technology. HBM technology achieves large-capacity and high-bit-width memory arrays by stacking multiple Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM or DDR for short) particles in three-dimensional space. HBM supports multi-channel parallel reading of memory, which significantly improves the reading speed.

Summary of the invention

An embodiment of the present application provides a data verification solution.

In a first aspect, a method for data verification is provided. The method includes: obtaining N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; aggregating the N groups of data to obtain aggregated data, the aggregated data includes an aggregated check bit, and the aggregated check bit is an aggregation of the check bits of the N groups of data; error correction code (ECC) encoding the aggregated data to obtain coded data; decomposing the coded data into N groups of coded data, each group of data in the N groups of coded data includes a check bit; and writing the N groups of coded data into the memory respectively. Thus, multiple groups of data read from the memory unit can be aggregated to obtain a larger coding unit for ECC coding. Therefore, under the same hardware conditions such as redundancy ratio, this method can support memory ECC functions with stronger error detection and correction capabilities compared to traditional technologies, and meet higher error correction and error detection requirements.

In some embodiments of the first aspect, obtaining N groups of data from the memory includes: reading data from N channels or N memory bank groups of the memory, wherein the data of each channel or each memory bank is a group of data. Thus, the data as the coding unit can be aggregated from the spatial dimension to obtain a larger coding unit.

In some embodiments of the first aspect, acquiring N groups of data from the memory includes: reading data from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and the time slice is the duration of a burst transmission of reading data from the memory. Thus, it is possible to aggregate as encoded data from the time and space dimensions to obtain a larger encoding unit.

In some embodiments of the first aspect, performing ECC encoding on the aggregated data includes: determining a method for obtaining N groups of data from a memory according to a preset encoding method; and performing ECC encoding on the aggregated data according to the preset encoding method. Thus, a flexible, configurable, and customizable ECC error detection and correction function is provided, which can provide a variety of ECC encoding and decoding methods that meet different needs of users under the same hardware environment.

In some embodiments of the first aspect, performing ECC encoding on the aggregated data according to a preset encoding method includes: presetting the encoding method according to a user input, the input including an ECC performance requirement for a memory, thereby automatically providing an optimal encoding method under hardware conditions based on the ECC performance requirement.

In some embodiments of the first aspect, the method further comprises: in response to the encoding method being updated, acquiring data from the memory according to the updated encoding method to update the check bit of the acquired data. Thus, the relevant configuration can be dynamically updated without restarting in response to demand changes, thereby avoiding business interruption caused by updating the configuration.

In some embodiments of the first aspect, the encoding method includes Reed-Solomon (RS) encoding. RS encoding can detect and correct multi-bit errors, significantly improving the error detection and correction capabilities of the generated ECC code.

In some embodiments of the first aspect, the method further comprises: determining a corresponding decoding method according to the encoding method; and when reading data from the memory for use, generating error-corrected data bits for the data based on the check bits of the read data according to the decoding method. Thus, it can be used in combination with the ECC encoding process of aggregating multiple groups of data, so that under the same hardware conditions, an ECC function with stronger error detection and correction capabilities and performance can be achieved compared with traditional methods.

In some embodiments of the first aspect, the method further includes: determining the number of bits that are different between the corrected data bits and the read data bits; if the number of bits satisfies a threshold condition, generating a prompt indicating that there may be an error in the corrected data bits. Thus, a more cautious error correction result can be provided, and the decision of whether to use risky data can be handed over to an upper-layer application, thereby ensuring the continuous operation of the business as much as possible while taking into account the risk of miscorrection.

In a second aspect, a device for data verification is provided, the device comprising: an acquisition module, configured to acquire N groups of data from a memory, each group of the N groups of data comprising a check bit, wherein N is a positive integer greater than or equal to 2; an aggregation module, configured to aggregate the N groups of data to obtain aggregated data, the aggregated data comprising an aggregated check bit, the aggregated check bit being an aggregation of the check bits of the N groups of data; an encoding module, configured to perform error correction code ECC encoding on the aggregated data to obtain encoded data; a decomposition module, configured to decompose the encoded data into N groups of encoded data, each group of the N groups of encoded data comprising a check bit; and a writing module, writing the N groups of encoded data into the memory respectively.

In some embodiments of the second aspect, the acquisition module includes a first reading module, which is configured to read data from N channels or N memory bank groups of the memory, wherein the data of each channel or each memory bank is a group of data.

In some embodiments of the second aspect, the acquisition module includes a second read module, which is configured to read data from M channels or M storage memory groups of the memory in L time slices, where N=L*M, and the time slice is the duration of a burst transmission of reading data from the memory.

In some embodiments of the second aspect, the encoding module includes: a determination module, configured to determine a method for obtaining N groups of data from a memory according to a preset encoding method; and an ECC encoding module, configured to perform ECC encoding on the aggregated data according to a preset encoding method.

In some embodiments of the second aspect, the ECC encoding module includes: pre-setting the encoding method according to user input, where the input includes ECC performance requirements for the memory.

In some embodiments of the second aspect, the apparatus further comprises an updating module, wherein the updating module is configured to: in response to the encoding method being updated, obtain data from the memory according to the updated encoding method to update a check bit of the obtained data.

In some embodiments of the second aspect, the encoding scheme includes Reed-Solomon encoding.

In some embodiments of the second aspect, the device also includes: a decoding method determination module, configured to determine a corresponding decoding method according to an encoding method; and an error correction module, configured to generate error-corrected data bits for the data based on the check bits of the read data according to the decoding method when reading data from the memory for use.

In some embodiments of the second aspect, the device also includes: a difference bit number determination module, which determines the number of different bits between the error-corrected data bits and the data bits of the read data; a prompt module, which is configured to generate a prompt when the different number of bits meets a threshold condition, and the prompt indicates that there may be an error in the error-corrected data bits.

In a third aspect, an electronic device is provided, including a processor and a memory, wherein computer instructions are stored in the memory, and when the computer instructions are executed by the processor, the electronic device performs actions according to the method in the first aspect or any embodiment thereof.

In a fourth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions, which, when executed by an electronic device, enable the electronic device to perform the operation of the method according to the first aspect or any of its embodiments.

In a fifth aspect, a computer program product is provided. The computer program product is tangibly stored on a computer-readable medium and includes computer-executable instructions, which, when executed, implement the operations of the method according to the first aspect or any of its embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features, advantages and aspects of the embodiments of the present application will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

FIG1 is a schematic diagram showing an example environment in which various embodiments of the present application can be implemented;

FIG2 shows a flow chart of an example method for data verification according to some embodiments of the present application;

FIG3 shows a schematic diagram of a non-limiting example of reading data for aggregation according to some embodiments of the present application;

FIG4 is a schematic diagram showing a non-limiting example of aggregating multiple groups of data for ECC encoding according to some embodiments of the present application;

FIG5 is a schematic diagram showing a non-limiting example of decomposing and writing ECC-encoded aggregate data into a memory according to some embodiments of the present application;

FIG6 shows a flow chart of an example method for performing error detection and correction on data according to some embodiments of the present application;

FIG7 shows a flowchart of an example method for data verification according to some embodiments of the present application;

FIG8 shows a schematic block diagram of a message transmission device according to some embodiments of the present application; and

FIG. 9 shows a schematic block diagram of an example device that can be used to implement embodiments of the present application.

DETAILED DESCRIPTION

The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

In the description of the embodiments of the present application, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

HBM is based on 3D stacking technology, which can provide multi-channel parallel reading of memory. In application fields that require HPC, HBM is widely used due to the high demand for memory bandwidth in high-computing systems. The structure of HBM determines that it has no separate redundant particles, and the redundancy ratio is also lower than that of general DDR. Due to the limited redundancy ratio and other reasons, the ECC algorithm that conventional HBM can support is relatively simple and has limited error detection and correction capabilities. For example, for 128 bits of data, 8-bit Hamming code ECC can detect and correct one bit error. If you want to detect two-bit errors, you need 9-bit Hamming code ECC.

Some HBM providers provide 16 redundant bits for ECC check bits for 128-bit data. This redundancy ratio can support 8-bit basic Hamming code check bits and 8-bit parity check bits, where each parity check bit is calculated for 16 bits of 128-bit data. This method can achieve single-grain error correction, but its error correction requires multiple trial calculations, resulting in a large delay. In addition, to implement this method, the redundancy ratio of the memory needs to be increased to 8:1, which increases the cost of the hardware. Moreover, Hamming code-based ECC cannot correct multi-bit errors. If more than two bits of errors occur, missed detection or miscorrection will still occur, that is, it cannot achieve the ability to correct multi-bit errors required to cope with hard failures.

On the other hand, with the development of memory technology, the amount of charge stored in a unit decreases, and the probability that instantaneous errors may lead to multi-bit errors is increased. In addition, during the design and manufacturing process of the memory, the probability of multi-bit errors may also be increased. At the same time, the HPC field where HBM is often used has high requirements for data reliability and latency. Therefore, the capabilities and performance of traditional simple encoding methods for HBM may not meet application requirements. In addition, more and more dedicated chips encapsulate CPUs and HBM and other memories in a system on chip (System On Chip, SoC). The high failure rate of the memory may directly lead to the return of the entire SoC, making the after-sales cost and service risk very high. Therefore, there is a challenge in how to improve the ECC error correction and error detection capabilities and performance for HBM and other memories under the constraints of limited hardware redundancy ratio and certain latency requirements.

In order to solve the above problems and other problems, an embodiment of the present disclosure provides a data verification scheme. The scheme aggregates multiple groups of data read from the memory unit (for example, from dimensions such as space and time) to obtain a larger coding unit for ECC encoding. Thus, under the same hardware conditions such as redundancy ratio, the scheme can support ECC-related functions for memory with stronger error detection and correction capabilities than traditional technologies, thereby significantly improving the reliability of ECC error detection and correction of the memory and reducing uncorrectable errors, meeting higher error correction and error detection requirements. It should be understood that although HBM may be used as an example in the description of this article, the scheme according to the embodiment of the present application is also applicable to various other memory forms, such as DDR, mobile DDR, and storage class memory (SCM).

First, refer to Figure 1, which shows a schematic diagram of an example environment 100 in which multiple embodiments of the present application can be implemented. Example environment 100 includes a computing device 110. Computing device 110 includes a processor 120 and a memory 130. Processor 120 may include a CPU, a GPU, various types of dedicated computing units (such as, AI chips, etc.), various controllers, or a suitable combination of the foregoing items. Processor 120 can perform various processing actions according to computer program instructions stored in or loaded into memory 130.

The memory 130 may be a random access memory (RAM), such as a dynamic random access memory (DRAM), which may support fast random read and write from the processor 120, thereby directly supporting The processor 120 can quickly read or write data to a random address in the memory 130. Thus, when the processor 120 performs a process, it can read data required for the execution (such as instructions and/or calculation parameters) from the memory 130 and write data (such as the output of the calculation) to the memory 130.

The computing device 110 also includes (multiple) memory controllers 140 as part of the processor 120. The memory controller 140 is a component of the computing device 110 used to control and manage data transmission between a computing unit such as a CPU/GPU and the memory 130. The processor 120 reads and writes data from the memory 130 via the memory controller 140. Each memory controller 140 can be implemented as a separate chip, or integrated into another larger chip, such as a controller built into a CPU or a north bridge.

In some embodiments of the present disclosure, data may be transmitted between the processor 120 and the memory 130 in a burst transmission manner. The burst transmission has a certain burst length. During the duration of a burst transmission (hereinafter also referred to as a data cycle), the memory controller 140 may continuously read/write a number of consecutive storage units equal to the burst length according to a specified starting address without continuously providing addresses. As a non-limiting example, in the case where a unit burst length is capable of reading 64 bits of data from the memory 130 via a single channel, during a data cycle with a burst length equal to 2, the processor 120 may be capable of reading 128 bits of data from the storage area via a single channel.

In some embodiments, there are multiple parallel communication channels between the memory 130 and the memory controller 140, so that the processor 120 can read/write data simultaneously via the multiple channels in parallel. For example, the memory 130 may include multiple bank groups, each of which can be read and written independently, so that data can be read/written from multiple bank groups at the same time. For example, the memory 130 may be an HBM based on 3D stacking technology, in which multiple bank groups are stacked together in a three-dimensional manner.

In some such embodiments, there may be multiple memory controllers 140, each of which controls data transmission for a portion of the memory bank groups, and can read data from the multiple memory bank groups in parallel via multiple channels. In some such embodiments, the memory 130 also supports virtual channels. Virtual channel technology can split each physical channel into multiple virtual channels, so that the number of single data that can be transmitted in parallel between the processor 120 and the memory 130 is greater than the number of physical channels. The embodiments of the present application are not limited to the specific number of memory controllers, memory bank groups, or channels/virtual channels.

In an embodiment of the present application, the memory 130 supports an error-correcting code (ECC) check function. In this case, for a group of data bits to be written to the memory 130, the processor 120 can, for example, use the memory controller 140 to calculate the corresponding ECC. When the group of data bits is written to the memory 130, the calculated ECC is also written to the memory 130 as a check bit. Later, when the group of data bits is read back for use by the processor 120, the corresponding check bit is also read together.

The memory controller 140 then recalculates the ECC for the read data bits and compares it with the ECC in the read check bits. If the two do not match, the memory controller 140 can determine that there is an error in the read data bits. In this case, the memory controller 140 can perform further error correction decoding on the data bits to determine which one or more bits are incorrect. Then, the erroneous bits are corrected. For binary data bits, this correction can mean that the erroneous bits are flipped. The correction of the data enables the processor 120 to correctly perform subsequent tasks, thereby ensuring the normal operation of the computing device 110.

To achieve this function, optionally, the memory 130 may include a data portion 150 specifically storing actual data bits and a check portion 160 storing check bits. The processor 120 may write the check bits of the data bits into the check portion 160 based on the corresponding read and write specifications. It should be understood that the data portion 150 and the check portion 160 are shown only as examples. In some embodiments, there may be no separate particles storing check bits in the memory 130. The memory 130 may also store data bits and corresponding check bits in other appropriate structures.

In addition, the processor 120 includes a paired ECC encoding circuit and decoding circuit (not shown), for example, in the memory controller 140 or in another part thereof. A pair of encoding circuits can implement the encoding and decoding functions of a specific ECC algorithm, for example, a Hamming code algorithm, and a Reed-Solomon encoding algorithm. The encoding circuit can be used to calculate the ECC of the data bit. The decoding circuit can decode the calculated ECC to determine the error bit in the corresponding data bit and correct it. In some embodiments, the memory controller 140 may include multiple pairs of encoding circuits and decoding circuits, and switch between different circuits according to the system settings to perform the ECC function using different algorithms.

The data unit targeted by ECC encoding is called a codeword. Each codeword includes actual data bits and redundant check bits including ECC. To achieve a certain error correction capability, the number of check bits needs to meet certain conditions, which are usually limited to the achievable hardware redundancy ratio between the capacity of the data part 150 and the check part 160. Take the ECC function of the basic Hamming code with a hardware redundancy ratio of 16:1 as an example. For a codeword including 128 data bits, a maximum of 8 additional check bits can support the detection and correction of one bit of error. If it is necessary to ensure reliable detection of two-bit errors, the redundancy ratio needs to be increased. If two-bit errors are to be detected and one-bit errors are to be corrected, 128-bit data requires 9 bits of ECC. In this case, a higher hardware redundancy ratio can be provided, that is, the capacity of the check part 160 is increased while the capacity of the data part 150 remains unchanged. This approach will reduce the cost of hardware. Without increasing the hardware cost, the size of the coding unit needs to be increased. For example, the processor 120 can increase the size of the coding unit according to the method of an embodiment of the present application, as will be described in detail later.

It should be understood that the architecture and functions in the example environment 100 are described for exemplary purposes only, and do not imply any limitation on the scope of the present application. In addition, other devices, systems or components not shown may also exist in the example environment 100. In addition, the embodiments of the present application may also be applied to other environments with different and/or other functions. For example, in some high-performance computing systems, the processor 120 and the memory 130 may be packaged in the same SoC. For example, the read, write and data verification actions for the memory 130 may also be performed by the base die. The following will generally describe the embodiments of the present application in the context of the computing device 110 using the processor 120 to perform actions.

Now refer to Figure 2, which shows a flow chart of an example method 200 for data verification according to some embodiments of the present application. The example method 200 can be performed, for example, by the computing device 110 as shown in Figure 1. It should be understood that the method 200 can also include additional actions not shown, and the scope of the present application is not limited in this respect. The method 200 is described in detail below in conjunction with the example environment 100 of Figure 1.

At 210, N groups of data are obtained from the memory, each of which includes a check bit. Wherein N is an integer greater than or equal to 2. For example, the computing device 110 can read N groups of data from the memory 130 to the processor 120 via the memory controller 140, wherein each of the N groups of data includes actual data bits and a check bit. The check bit can be used to store the ECC check code of the group of data bits. At this time, the check bit can be empty or may need to be updated.

In some embodiments, the processor 120 may read N groups of data in parallel from N memory bank groups or N channels of the memory 130. In some embodiments, the N channels may be virtual channels. The N groups of data read in parallel may be aggregated for encoding as described below, and compared with ECC encoding of a single group of data obtained from each channel, this reading method can obtain more numbers of encoding units without increasing latency.

In some embodiments, the processor 120 can read N groups of data from M channels or M storage banks of the memory in L time slices, where L and M are integers, and N=L*M. Each of the L time slices is the duration of a burst transmission of data read from the memory. As known to those skilled in the art, the burst transmission has a certain burst length. When the hardware capability and the burst length are determined, the duration of a burst transmission can be used as a unit time for configuration. An example of reading data from multiple channels and/or multiple time slices for ECC encoding will be described in more detail below in conjunction with FIG. 3.

2. At 220, the N groups of data are aggregated to obtain aggregated data, the aggregated data including an aggregated check bit, the aggregated check bit being an aggregation of the check bits of the N groups of data. For example, the processor 120 may aggregate the N groups of data obtained at 210 to obtain aggregated data, including an aggregated check bit of the check bits of the N groups of data.

In some embodiments, the processor 120 may concatenate the data bits of the N groups of data and the check bits of the N groups of data to obtain aggregated data. It should be understood that such aggregation may be a logical aggregation, as long as the processor 120 is able to know which bits in the aggregated data are data bits and which bits are check bits.

At 230, the aggregated data is ECC-encoded to obtain encoded data. For example, the processor 120 may perform ECC encoding on the aggregated data obtained at 220 to obtain encoded data. In some embodiments, the ECC encoding may be Hamming code encoding and its various variants. For example, the processor 120 may calculate a Hamming code for the aggregated data, calculate a parity bit for each of a plurality of segments of the aggregated data, and use both as part of the check bits of the encoded data. In some embodiments, the ECC encoding may be RS encoding with a stronger error correction and detection capability. An example of ECC encoding of aggregated N groups of data will be described in more detail below in conjunction with FIG. 4.

2. At 240, the coded data is decomposed into N groups of coded data, each of which includes a check bit. For example, the processor 120 may decompose the coded data obtained at 230 into N groups of coded data, each of which includes a check bit. Similarly, this decomposition may be a logical decomposition, as long as the processor 120 can correctly process (e.g., transmit) the N groups of coded data in groups.

At 250, the N groups of coded data are written to the memory separately. For example, the processor 120 may write the N groups of coded data decomposed at 240 to the memory 130 separately. The processor 120 may write data to the memory 130 in a manner corresponding to the manner in which the data is read from the memory 130 at 210. In some embodiments, in some embodiments, the processor 120 may write the N groups of data to N memory bank groups or N channels (or virtual channels) in parallel. In some embodiments, the processor 120 may write the N groups of data to M channels or M memory bank groups in L time slices, where L and M are integers, and N=L*M. An example of decomposing coded data will be described in more detail below in conjunction with FIG. 5.

Using method 200, multiple single groups of data read from the memory unit are aggregated from dimensions such as space and time, and a larger coding unit can be obtained for ECC encoding. Therefore, under the same hardware conditions, method 200 can support memory ECC functions with stronger error detection and correction capabilities (such as RS encoding with stronger capabilities than Hamming code) compared to traditional methods, thereby significantly improving the reliability of memory ECC error detection and correction functions and reducing the occurrence of uncorrectable errors (UCE). In addition, method 200 can also meet the increased demand by aggregating data without changing hardware characteristics such as hardware redundancy ratio after the error correction and error detection requirements of memory ECC increase.

Referring now to FIG. 3 , a schematic diagram 300 of a non-limiting example of reading data for aggregation according to some embodiments of the present application is shown. A processor 310 is shown in the schematic diagram 300 , which communicates with an HBM 320 supporting multiple channels. The processor 310 and the HBM 320 may be example implementations of the processor 120 and the memory 130 in FIG. 1 , respectively, and the actions described in FIG. 3 may be example implementations of the action 210 in the method 200 of FIG. 2 .

In the schematic diagram 300, the processor 310 reads data in parallel via a plurality of controllers 330-1 to 330-I (individually or collectively referred to as controller 330). For the purpose of illustration, controller 330-1 is taken as an example, which is capable of controlling the data transmission of channels 340-1 and 340-2. In each data cycle of a burst transmission, controller 330-1 can read a group of unit data from each channel of channels 340-1 and 340-2 into its own buffer. The duration of a data cycle depends on the burst length of the burst transmission and the hardware conditions of the relevant components. Therefore, the group of unit data can be regarded as data read in a unit time slice.

As shown, in the first time slice, the controller 330-1 can read data 311 from the channel 340-1 and read data 312 from the channel 340-2. In the second time slice, the controller 330-1 can read data 313 from the channel 340-1 and read data 314 from the channel 340-2. Each group of data in the data 311 to 314 includes an additional check bit of the actual data bit. It should be understood that, depending on the scenario, the check bit at this time can be a null value reserved for later writing to HBM 320.

Traditionally, the controller 330-1 can calculate the check bit separately for each data as a codeword, then for the example codeword of 128+8 bits, the Hamming code encoding for detecting and correcting single bit errors can be used. However, in the example of Figure 3, the controller 330-1 can aggregate the data 311 to 314 into a longer codeword for ECC encoding. Thus, in this example, the longer codeword includes 32 check bits, so that 4 RS8 redundant encodings can be supported. RS encoding is widely used in DDR4 and DDR5. It is a symbol-based algorithm that can be used to correct errors in one or more symbols, each symbol can be 8 bits, for example.

According to the Reed-Solomon theory, using RS8 redundant coding based on finite field algorithm to calculate the 32-bit check bits can correct the errors of two random RS symbols at most, that is, it can correct 16-bit errors, which can cover the failure modes involving more errors. In this way, the error detection and correction capabilities of the memory can be significantly improved, and the occurrence of UCE can be reduced.

In this non-limiting example, the processor 310 aggregates data based on the data read in parallel by each controller 330. It should be understood that this is for illustration purposes only. In some embodiments, the computing device (e.g., computing device 110) can determine the manner of obtaining N groups of data for aggregation from the memory according to a preset encoding manner. For example, the number of channels that should be used to read data in parallel and/or the data read in how many time slices should be aggregated can be preset.

In some embodiments, the computing device may set the configuration information of the encoding method according to the parameter values (e.g., the number of channels and the number of time slices) input by the user. In some such embodiments, the input includes ECC performance requirements for the memory. For example, the correctable rate, the expected error correction delay, and the expected missed detection rate. The computing device can then adapt the configuration parameters of the encoding method based on these performance requirements and the hardware conditions of the memory 130.

Reference is now made to FIG. 4 , which illustrates a schematic diagram 400 of a non-limiting example of aggregating multiple sets of data for ECC encoding according to some embodiments of the present application, wherein multiple sets of data 411 to 414 are shown read at multiple time slices and/or from multiple channels. The actions described in FIG. 4 may be example implementations of actions 220 and 230 in the method 200 of FIG. 2 , and the multiple sets of data 411 to 414 may be examples of data 311 to 314 read from the HBM 320 in the example of FIG. 3 . For purposes of illustration, FIG. 4 will continue to be described below in the context of the processor 310 in FIG. 3 performing the actions.

As shown in FIG. 4 , each group of data in data 411 to 414 includes a group of data bits and a group of check bits, such as data bit 425 and check bit 435 of data 411. In some embodiments, the check bit can be empty at this time. In some embodiments, the check bit can be a placeholder added by the processor according to the hardware redundancy ratio of the memory.

Instead of calculating the value of the check bit separately for each set of data, the processor 310 can aggregate the data 411 to 414 before performing the calculation. In the example of FIG. 4 , to aggregate the data, the processor 310 concatenates the data bits of the data 411 to 414 together to form an aggregate 445 of data bits, and concatenates the check bits of the data 411 to 414 together to form an aggregate 455 of check bits. In turn, the aggregate 445 of data bits and the aggregate 455 of check bits are aggregated (in this example, concatenated) to form final aggregate data 465. Aggregate data 455 includes aggregate data bits 475 and aggregate check bits 485.

Then, the processor 310 can perform ECC encoding on the aggregate data 465 to obtain encoded data. Specifically, the processor 310 can calculate the value of the check bit of the aggregate data 465 according to a preset ECC encoding method, and put it into the aggregate check bit 485. In some embodiments, the processor 310 can perform ECC encoding on the aggregate data 465 according to a preset encoding method. For example, the processor 310 can configure its ECC encoding circuit according to the parameters in the encoding settings to perform ECC encoding on the aggregate data. In some embodiments, the encoding method can be RS encoding with specific parameters, which specify various properties of the RS encoding algorithm and codewords. In some embodiments, the processor 310 may include multiple ECC encoding circuits. According to the preset encoding method, the processor 310 can switch to The corresponding encoding circuit is configured according to the set parameters to perform ECC encoding on the aggregate data.

Now refer to FIG. 5 , which shows a schematic diagram 500 of a non-limiting example of decomposing and writing ECC-encoded aggregate data to a memory according to some embodiments of the present application. The actions described in FIG. 5 may be an example implementation of actions 240 and 250 in the method 200 of FIG. 2 , and the aggregate data 565 may be an example of the aggregate data 465 in the example of FIG. 4 . For ease of explanation, FIG. 5 will continue to be described below in the context of the processor 310 in FIG. 3 performing actions.

After performing ECC encoding on the aggregate data 565, the processor 310 also needs to write each data bit and check bit of the encoded aggregate data 565 to the corresponding address. Therefore, the processor 310 can perform the reverse process of the above-mentioned aggregation process, and rewrite the encoded data (for example, via the controller 330) to the HBM 320 in an analogous manner to reading N groups of data from the HBM.

As shown in FIG5 , the aggregated data 565 may be aggregated from multiple sets of data (e.g., data 411 to 414 in FIG4 ), and its data bits 575 include multiple parts from the multiple sets of data, such as part 545. In addition, the number of bits of the check bits 585 of the aggregated data 565 is also equal to the aggregation of the multiple sets of check bits of the multiple sets of data. After the processor has ECC-encoded the aggregated data 565 as a long codeword, the check bits 585 include the ECC values calculated for the data bits 575. The check bits 575 may be considered to include multiple parts corresponding to the check bits of each set of data in the multiple sets of data, such as 555.

On this basis, the processor 310 can decompose the data bits 575 into multiple groups of data bits again, and decompose the check bits 585 into multiple groups of check bits. The processor 310 can then combine each group of data bits in the multiple groups of data bits with the corresponding check bits to re-obtain multiple groups of data, in this example, data 511 to 514. Each group of data in the data 511 to 514 has the same structure as the multiple groups of data previously obtained by the processor 310 and includes a portion of the calculated check bits 585.

In this way, the processor 310 can rewrite N groups of data into the HBM 320 according to the corresponding read and write specifications in an analogous manner to the previous reading of multiple groups of data. Taking FIG. 3 as an example, as shown in the figure, the controller 330-1 of the processor 310 can write data 511 to 514 into the HBM 320 in two time slices in parallel via the channel 340-1 and the channel 340-2.

It should be understood that the data structures of the aggregation and decomposition described in Fig. 4 and Fig. 5 are only logical examples. Various implementation variations that meet such logical structures also fall into the scope of the present application, as long as the processor can correctly operate and transmit the corresponding bits of data. It should also be understood that the number of controllers, time slices, and channels shown in Fig. 3 to Fig. 5 are only examples, which can be determined based on input parameters and/or performance requirements for coding configuration as described above, and the coding configuration can be changed. The example of the ECC coding configuration being changed will be described in more detail in conjunction with Fig. 7 hereinafter.

After ECC encoding the data in the memory, when the processor 120 subsequently needs to obtain the ECC-encoded data for use (for example, by an application process running on the processor 120, etc.), it can use the check bits of the encoded data to detect whether an error has occurred in the actual data bits of the encoded data when being written and correct the error. Now refer to Figure 6, which shows a flowchart of an example method 600 for error detection and error correction of data according to some embodiments of the present application. The example method 600 can be performed, for example, by a computing device 110 as shown in Figure 1. It should be understood that the method 600 can also include additional actions not shown, and some actions in the method 600 can be omitted, and the scope of the present application is not limited in this respect. The method 600 is described in detail below in conjunction with the example environment 100 of Figure 1.

At 610, for example, according to the instructions of the application program, the processor 120 can read the corresponding amount of encoded data from the memory 130 into its cache line, such as the cache line of the controller 140. The encoded data includes data bits to be used by the program and corresponding check bits. When these data bits are previously written, the check bits can be generated by the processor 120 based on the method of the embodiment of the present application (for example, the method described with respect to Figures 2 to 5).

According to the currently configured ECC encoding mode, the processor 120 can determine the corresponding decoding mode. For example, when the computing device 110 is started, the processor 120 can configure the corresponding ECC encoding and decoding path according to the current ECC encoding configuration information. The processor 120 can then read the amount of encoded data suitable for the current decoding mode to perform decoding according to the decoding mode. For example, the processor 120 can read multiple groups of encoded data from (multiple) channels and/or (multiple) time slices in a manner similar to the above-mentioned acquisition of multiple groups of data to combine into codewords suitable for the current decoding mode.

The processor 120 may perform error detection on the encoded data read, and if necessary, attempt to generate error-corrected data bits for the data based on the read check bits. Specifically, at 615, the processor 120 may generate check bits for the data bits of the encoded data read based on the current decoding method. Then, at 620, the processor 120 may compare the check bits generated at 615 with the check bits of the encoded data read at 610 to determine whether the two sets of check bits match.

If the two sets of check bits match, the processor 120 can determine that the data bits of the encoded data read are consistent with when the data bits were written, that is, there are no errors in the data bits. In this case, the method 600 can proceed to 625, where the detected data is provided to the application process for further use. Then, the method 600 can return to 610, where the processor 120 can read the next batch of data of the decoding unit size and its check bits.

If the two sets of check bits do not match, the processor 120 may determine that there are errors in the data bits. In this case, the processor 120 needs to attempt to perform error correction on the data bits to correct the erroneous bits. Therefore, the method 600 proceeds to 630, where the processor 120 may decode the read check bits according to the currently active ECC decoding path (e.g., the RS decoding circuit path). Such a decoding process is intended to determine the location of the erroneous bit in the corresponding data bit for correction.

Different ECC algorithms with different parameters have different error correction capabilities. In some cases, the situation that the error of data cannot be corrected may occur, that is, there is UCE in the data. If the processor 120 finds UCE at 635, the method 600 proceeds to 640, where the processor 120 can trigger the UCE interrupt. If no UCE is found, the method 600 proceeds to 645, where the processor 120 can generate the result of error correction. That is, the processor 120 can correct the error in the detected data bit based on the result of decoding the check bit to generate the data bit through error correction. For a binary erroneous data bit in the data bit, this can mean the flipping of the value.

As mentioned above, a specific ECC decoding method has a certain error detection and correction capability. When the errors in the data bits detected by it exceed its capability, in addition to ECC, miscorrection may also occur. That is, using the current decoding method to perform ECC decoding on the check code can obtain a certain result, but in fact there may be errors in the result.

In some cases, method 600 may further detect the reliability of the corrected data. At 650, processor 120 may determine whether to perform a reliability test on the corrected data. For example, processor 120 may turn this function on or off according to a pre-set configuration, thereby implementing two different error correction modes. If it is determined that the reliability test is not to be performed, method 600 proceeds to 655, where processor 120 may provide the corrected data to the application process for further use. At 655, processor 120 may also record a relevant error correction log. Then, method 600 may return to 610.

If it is determined to perform reliability testing, the method 600 proceeds to 660, where the processor 120 can determine the difference between the error-corrected data bits generated at 645 and the read data bits. In some embodiments, the processor 120 can determine the number of bits that are different between the error-corrected data bits and the data bits of the read data. In some embodiments, the processor 120 can also determine the distribution of these different bits in the data bits. Then, at 665, the processor 120 can determine whether the difference meets a threshold condition.

In some embodiments, the processor 120 may determine that the number of bits that differ between the error-corrected data bits and the data bits of the read data exceeds a threshold. The threshold is associated with the maximum number of bits that can be corrected in a group of data bits by the ECC encoding and decoding method used. For example, if an ECC method that can detect at most one bit of data generates a correction result that corrects two bits, then the result meets the threshold condition, that is, the correction result may include an error.

In some embodiments, the threshold condition is also related to the distribution of the error bits. For example, if the ECC method can reliably detect errors of j consecutive bits, but if the error bits are discontinuous, it can only reliably detect fewer k bits of errors. If the error-corrected data bits correct the errors of i discontinuous bits, the processor 120 can still determine that the result meets the threshold condition.

If the difference does not meet the threshold condition, the method proceeds to 655. If the difference meets the threshold condition, the method proceeds to 670, where the processor 120 can generate a hint indicating that there may be an error in the corrected data bit. Then, at 675, the processor 120 can provide the corrected data with the hint (e.g., as an additional mark) to the application process for use. The processor 120 can also record the relevant error correction log for tracking and analysis. Then, the method 600 can return to 610.

In this way, more cautious error correction results can be provided to upper-level applications, and the decision of whether to use risky data can be handed over to upper-level applications, so as to ensure the continuous operation of the business while taking into account the risk of miscorrection. For example, when the data is an image to be displayed by an application, errors involving several pixels may not affect the display. Therefore, the application can choose to use the data. As another example, when the application has high requirements for data correctness, it can discard the corrected data that is marked as possibly erroneous. In other embodiments of the present application, for example, in a security server where the correctness of the data is very important, in order to ensure the reliability of the data as much as possible, after determining that there may be errors in the corrected data bits, instead of generating a prompt at 670, the processor 120 can trigger an interrupt.

Method 600 can be used in combination with the ECC encoding process described above according to FIGS. 2 to 5 , so as to achieve an ECC function with stronger error detection and correction performance than the conventional method under the same hardware conditions. In addition, the above process of detecting and prompting the reliability of the error-corrected data can also be used separately with other ECC decoding processes to provide the related benefits described above.

As described above, the computing device 110 can read data and perform ECC functions on the data according to a preset encoding method. In addition, these encoding methods can be updated due to changes in ECC-related requirements for the computing device 110. In some embodiments, the update of the encoding method can occur during system operation, and the update does not require the system to be restarted for it to take effect.

Now, the setting and updating of the encoding method will be described with reference to FIG. 7. FIG. 7 shows a flowchart of an example method 700 for data verification according to some embodiments of the present application, wherein the ECC encoding configuration for data verification is updated during system operation. The example method 700 may be executed, for example, by the computing device 110 shown in FIG. 1. It should be understood that the method 700 may also include additional actions not shown, and some actions in the method 700 may be omitted, and the scope of the present application is not limited in this respect. The method 700 is described in detail below in conjunction with the example environment 100 of FIG. 1. FA 700.

The method 700 begins with the system on the computing device 110 starting at 710. Here, the computing device 110 can configure the components that perform ECC encoding and decoding based on the preset encoding method to initialize the ECC error correction and error detection functions. For example, the computing device 110 can be configured based on a configuration file that stores relevant parameters of the encoding method. The values of these relevant parameters can be default values that are not changed or restored, or can be values previously entered by a user.

In some embodiments, the configuration parameters may include the number of channels that should be used to read data in parallel and/or the number of time slices over which the data read should be aggregated. For example, the computing device 110 may configure its ECC encoding function to encode based on N groups of data read in parallel from M channels or M groups of memory banks aggregated over L time slices, as described above with respect to method 200.

In some embodiments, for example, as part of the processor 120, the computing device 110 may include multiple ECC encoding circuits and corresponding decoding circuits, such as a circuit implementing a Hamming code algorithm and a circuit implementing a RS algorithm. According to the encoding algorithm specified in the configuration file, the computing device 110 may enable and configure the corresponding circuit and perform ECC-related functions.

It should be understood that in addition to the above configurations affecting the encoding method, the computing device 110 may also perform other ECC-related configurations. For example, according to requirements such as the missed detection rate for ECC decoding, the computing device 110 may include a function of enabling or disabling reliability detection of error-corrected data after it is generated, as described in detail above with respect to method 600.

At 720, the processor 120 of the computing device 110 begins to run various system and application processes, and continuously communicates with the memory 130 to read and write data, etc. During this period, the configured ECC-related functions are utilized. The processor 120 (for example, in its internal buffer) can perform ECC encoding on the data to be written to the memory 130, and write the data bits of the data and the calculated check bits to the memory 130 according to the corresponding read and write specifications. And, when reading the encoded data for use, the processor 120 can use the configured ECC-related functions to read in the data bits and corresponding check bits of the data for decoding, thereby performing ECC error correction and error detection on the data.

The computing device 110 can perform ECC encoding on the aggregated long codeword and correspondingly perform ECC decoding based on the configured ECC error correction and error detection functions according to the method actions described above with respect to Figures 2 to 6, which will not be repeated here. Depending on the implementation, the process can be performed by the memory controller 140 or another component of the processor. Although not shown in Figure 7, if UCE is found during the decoding process, the computing device 110 performs relevant error handling actions, such as triggering an interrupt.

During system operation, at 730, the computing device 110 may receive an update indication for the ECC encoding method, for example, via a user interface. The update indication may include update information for one or more parameters, such as the number of channels for reading the data to be aggregated in parallel, the number of time slices for reading the data to be aggregated, and the encoding algorithm. In response to receiving the update indication, at 740, the computing device 110 may configure the relevant components according to the update to switch to a new encoding method. For example, the computing device 110 may switch the encoding circuit to another encoding circuit, and correspondingly switch the decoding circuit to a decoding circuit paired with another encoding circuit. After switching to the new encoding method, the processor 120 of the computing device 110 may perform subsequent ECC encoding and decoding actions according to the new encoding method.

When the update of the encoding method occurs during system operation, after the update, there may be data encoded with check bits in the method before the update in the memory 130. If the processor 120 reads this data for error detection and error correction, it will use the updated decoding method to perform these actions. This will produce wrong results or no results. To solve this problem, at 750, the computing device 110 can cause the processor 120 to update the check bits of the encoded data in the memory 130 with the updated encoding method.

To this end, the processor 120 can read the encoded data from the memory 130 into its buffer according to the updated encoding method to update the check bit of the data. According to the ECC encoding process as described above, the processor 120 can use the number of channels and the number of time slices indicated in the updated configuration to read and aggregate the long codeword for ECC encoding, and use the updated encoding method to calculate the check bit of the long codeword. Then, the processor 120 can write the data bits and check bits of the long codeword back to the corresponding addresses, thereby keeping the data bits unchanged and overwriting the previous check bits. The processor 120 can continue to read and aggregate the next long codeword to update the check bit until the required update is completed.

Method 700 provides customizable ECC error detection and correction functions that are flexible and configurable in multiple dimensions such as space, time, and encoding algorithms. In this way, multiple ECC encoding and decoding methods that meet different needs of users can be provided under the same hardware environment. In addition, the relevant configuration can be dynamically updated without restarting in response to changes in demand, thereby avoiding business interruptions caused by updating ECC-related function configurations. The method can be used for operational configuration optimization of data centers, etc. Multiple ECC-related function configurations can be adopted and tested for a period of time to clarify the most important memory failure modes and determine the best configuration parameters.

As described above, given the hardware constraints of the memory system (e.g., the redundancy ratio of data bits and check bits that it can support, etc.), the user can configure the ECC related functions according to the requirements of memory error detection and correction in its application scenario. In some embodiments, the user can directly input parameter values to configure the parameters according to the requirements.

For example, in the case where the processor 120 includes multiple pairs of encoding and decoding circuits, for a scenario where 1-bit error correction is required, the user can configure the encoding algorithm to be a Hamming code encoding algorithm for cost considerations. The RS encoding algorithm with stronger power is encoded on the basis of the aggregated long codeword to achieve error correction capability for multiple consecutive symbols. As another non-limiting example, the user can enter a configuration value to specify RS8 encoding based on the aggregation of two time slices of data read in parallel from two channels. However, if less time delay is to be achieved without changing the encoding algorithm, the user can modify the configuration to aggregate the data of one time slice read in parallel from four channels for RS8 encoding.

In other embodiments, instead of directly inputting parameter values, user input may include ECC performance requirements for memory 130. The computing device 110 may automatically adapt the parameters of the encoding method that can meet the performance requirements and meet the hardware and other constraints according to these ECC performance requirements and the hardware constraints of the memory 130, and use these parameters to set or update the ECC related function configuration. In some embodiments, these performance requirements may include the expected delay caused by ECC error correction, and the expected reliability indicators of the corresponding data using the generated verification data, such as the expected missed detection rate or the false correction rate. In some embodiments, the hardware constraints of the memory 130 may include the redundancy ratio between the capacity used to store the original data and the capacity used to store the verification data in the memory 130.

In some embodiments, the computing device 110 may provide preset multiple parameter combinations, and corresponding requirements to these multiple parameter combination mapping rules. In this way, the computing device 110 may provide corresponding parameter combinations based on the mapping rules to configure ECC related functions. In some embodiments, the computing device 110 may implement a configuration planning function. This function takes performance requirements and constraints as input, and outputs the optimal configuration parameters for extreme reliability that meet various constraints, such as the number of channels and time slices on which the aggregated data is based, and the ECC encoding algorithm to be used. The optimal configuration parameters can then be used to configure ECC related functions.

Fig. 8 shows a schematic block diagram of a data verification device 800 according to some embodiments of the present application. The device 800 may be implemented as or included in the computing device 110 of Fig. 1. The device 800 may include multiple modules to perform corresponding actions in, for example, method 200, method 600, and method 700.

As shown in the figure, the device 800 includes the following modules: an acquisition module 810, configured to acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; an aggregation module 820, configured to aggregate the N groups of data to obtain aggregated data, the aggregated data includes an aggregated check bit, and the aggregated check bit is an aggregation of the check bits of the N groups of data; an encoding module 830, configured to perform error correction code ECC encoding on the aggregated data to obtain encoded data; a decomposition module 840, configured to decompose the encoded data into N groups of encoded data, each group of encoded data in the N groups of encoded data includes a check bit; and a writing module 850, configured to write the N groups of encoded data into the memory respectively.

In some embodiments, the acquisition module 810 includes a first reading module, which is configured to read data from N channels or N memory bank groups of the memory, wherein the data of each channel or each memory bank is a group of data.

In some embodiments, the acquisition module 810 includes a second read module, which is configured to read data from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and the time slice is the duration of a burst transmission of reading data from the memory.

In some embodiments, the encoding module 830 includes: a determination module configured to determine a method for obtaining N groups of data from a memory according to a preset encoding method; and an ECC encoding module configured to perform ECC encoding on the aggregated data according to a preset encoding method.

In some embodiments, the ECC encoding module includes: presetting the encoding method according to user input, where the input includes ECC performance requirements for the memory.

In some embodiments, the apparatus 800 further includes an updating module, wherein the updating module is configured to: in response to the encoding method being updated, obtain data from the memory according to the updated encoding method to update the check bit of the obtained data.

In some embodiments, the encoding scheme includes Reed-Solomon encoding.

In some embodiments, the device 800 also includes: a decoding method determination module, configured to determine a corresponding decoding method according to an encoding method; and an error correction module, configured to generate error-corrected data bits for the data based on the check bits of the read data according to the decoding method when reading data from the memory for use.

In some embodiments, the device 800 also includes: a difference bit number determination module, which determines the number of different bits between the corrected data bits and the data bits of the read data; a prompt module, which is configured to generate a prompt when the different number of bits meets a threshold condition, and the prompt indicates that there may be errors in the corrected data bits.

FIG9 shows a schematic block diagram of an example device 900 that can be used to implement an embodiment of the present application. The device 900 can be used to implement the functions of the computing device 110 shown in FIG1 . As shown in the figure, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 903 and/or a read-only memory (ROM) 902 or computer program instructions loaded from a storage unit 908 into the RAM 903 and/or the ROM 902. Various programs and data required for the operation of the device 900 can also be stored in the RAM 903 and/or the ROM 902. As a non-limiting example, the computing unit 901 and the RAM 903 can respectively implement 1 shows the functions of the processor 120 and the memory 130. The computing unit 901 and the RAM 903 and/or the ROM 902 are connected to each other via a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.

A number of components in the device 900 are connected to the I/O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The computing unit 901 may be a variety of general and/or special processing components with processing and computing capabilities. It may implement the functions of the processor 120 in FIG. 1 . Some examples of the computing unit 901 include, but are not limited to, a CPU, a GPU, various dedicated AI computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as methods 200, 600, and 700. For example, in some embodiments, methods 200, 600, and 700 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 900 via RAM and/or ROM and/or a communication unit 909. When the computer program is loaded into the RAM and/or ROM and executed by the computing unit 901, one or more steps of the methods 200, 600, or 700 described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to execute the method 200 , 600 , or 700 in any other appropriate manner (eg, by means of firmware).

In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, and a tape, etc.), or an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the application. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

Although the subject matter has been described in language specific to structural features and/or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims (13)

A method for data verification, comprising: Acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; aggregate the N groups of data to obtain aggregated data, the aggregated data includes an aggregated check bit, and the aggregated check bit is an aggregation of the check bits of the N groups of data; Performing error correction code (ECC) encoding on the aggregated data to obtain encoded data; Decomposing the coded data into N groups of coded data, each group of the N groups of coded data including a check bit; and The N groups of encoded data are written into the memory respectively. The method according to claim 1, wherein acquiring N sets of data from the memory comprises: Data are read from N channels or N memory bank groups of the memory, wherein data of each channel or each memory bank group constitutes a group of data. The method according to claim 1, characterized in that acquiring N sets of data from the memory comprises: Data is read from M channels or M memory bank groups of the memory in L time slices, where N=L*M, and the time slice is the duration of one burst transmission of reading data from the memory. The method according to claim 1, characterized in that performing error correction code (ECC) encoding on the aggregated data comprises: Determining a method for acquiring the N groups of data from the memory according to a preset encoding method; and The aggregated data is ECC-encoded according to the preset encoding method. The method according to claim 4, characterized in that performing ECC encoding on the aggregated data according to the preset encoding method comprises: The encoding mode is preset according to a user input, wherein the input includes an ECC performance requirement for the memory. The method according to claim 4, further comprising: In response to the encoding method being updated, data is retrieved from the memory according to the updated encoding method to update a check bit of the retrieved data. The method according to claim 4 is characterized in that the encoding method includes Reed-Solomon encoding. The method according to claim 4, further comprising: Determine a corresponding decoding method according to the encoding method; and When data is read from the memory for use, error-corrected data bits for the data are generated based on the parity bits of the read data according to the decoding method. The method according to claim 8, further comprising: determining the number of bits that differ between the error-corrected data bits and the read data bits of the data; If the number of bits satisfies a threshold condition, an indication is generated indicating that there is likely an error in the error-corrected data bits. A device for data verification, comprising: An acquisition module is configured to acquire N groups of data from a memory, each group of data in the N groups of data includes a check bit, wherein N is a positive integer greater than or equal to 2; an aggregation module, configured to aggregate the N groups of data to obtain aggregated data, wherein the aggregated data includes an aggregated check bit, and the aggregated check bit is an aggregation of check bits of the N groups of data; An encoding module, configured to perform error correction code (ECC) encoding on the aggregated data to obtain encoded data; a decomposition module configured to decompose the coded data into N groups of coded data, each group of coded data in the N groups of coded data including a check bit; and The N groups of data are written into the memory respectively, wherein N is a positive integer greater than or equal to 2. An electronic device, characterized in that it comprises a processor and a memory, wherein the memory stores computer instructions, and when the computer instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 9. A computer storage medium, characterized in that the computer-readable storage medium stores instructions, and when the instructions are executed by an electronic device, the electronic device executes the method according to any one of claims 1 to 9. A computer program product, characterized in that the computer program product comprises instructions, and when the instructions are executed by an electronic device, the electronic device executes the method according to any one of claims 1 to 9.