WO2025090074A1

WO2025090074A1 - Reference clock generation using machine learning compensation

Info

Publication number: WO2025090074A1
Application number: PCT/US2023/077640
Authority: WO
Inventors: Mohamed A. Abdelmoneum; Timo Sakari HUUSARI; Narayan Srinivasa; Sarah Shahraini; Brent R. Carlton
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2025-05-01
Anticipated expiration: 2026-04-24

Abstract

Embodiments herein relate to a system which predicts the frequency or phase offset of a primary clock signal relative to a stable reference such as an atomic clock based on the frequency or phase offsets, respectively, of secondary clock signals relative to the frequency or phase, respectively, of the primary clock signal. The system can include a neural network which is trained to learn a correspondence between the offset of the primary clock signal relative to the stable reference and the offsets of the secondary clock signals relative to the primary clock signal. The training can include varying environmental conditions such as temperature, vibration, pressure, humidity or magnetic field. Once trained, the neural network can be used to provide a stable output clock signal based on the primary clock signal and its predicted offset.

Description

REFERENCE CLOCK GENERATION USING MACHINE LEARNING COMPENSATION

GOVERNMENT RIGHTS

This invention was made with government support under HR0011-23-9-0028 awarded by DARPA. The government has certain rights in the invention.

FIELD

The present application generally relates to the field of clock generators and, more particularly, to circuits and techniques to provide a stable clock signal.

BACKGROUND

A clock generator is an electronic oscillator that produces a clock signal on an integrated circuit or chip. The clock signal can be provided to synchronize the operation of different circuits on the chip. In some cases, other clocks are derived from a reference clock and distributed on a chip. Generally, a clock signal can be distributed to one or more chips. A clock generator can include a quartz crystal resonator or a Microelectromechanical Systems (MEMS) resonator, for instance, which vibrates at a specific resonant frequency when excited by a signal from a driver. However, various challenges are presented in maintaining a stable frequency and phase of the clock signal in different conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 depicts an example plot of a changing frequency (f) of a clock signal over time (t), in accordance with various embodiments.

FIG. 2 depicts an example system 200 including a neural network 220 which is trained using a primary oscillator 211, a set of secondary' oscillators 212-214 and one or more environmental sensors 215 to predict an offset in the frequency of a clock signal of the primary oscillator, in accordance with various embodiments.

FIG. 3 depicts a flowchart of an example process for training a neural network, consistent with FIG. 2, in accordance with various embodiments.

FIG. 4 depicts an example plot of changes in the frequency of clock signals of the different oscillators of FIG. 2 as a function of an environmental condition (EC), in accordance with various embodiments. FIG. 5 depicts an example nonlinear autoregressive network with exogenous inputs (NARX) model 500 for training a neural network, consistent with FIG. 2. in accordance with various embodiments.

FIG. 6A depicts an example system in which the trained neural network of FIG. 2 is used to predict the frequency and/or phase offset of a primary clock signal, in accordance with various embodiments.

FIG. 6B illustrates an example phase-locked loop (PLL) 630 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments.

FIG. 6C illustrates an example digital-to-time converter 640 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments.

FIG. 6D illustrates an example Direct Digital Synthesis (DDS) circuit 650 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments.

FIG. 7 depicts a flowchart of an example process for using a trained neural network to predict the frequency offset of a clock signal, consistent with FIG. 6A, in accordance with various embodiments.

FIG. 8 depicts an example configuration of an oscillator 800, consistent with the primary and secondary oscillators of FIG. 2, in accordance with various embodiments.

FIG. 9 depicts example environmental sensors of the set of environmental sensors 215 of FIG. 2, in accordance with various embodiments.

FIG. 10 depicts an example system 1000 which provides an output clock signal based on a primary clock signal, secondary clock signals and environmental conditions, consistent with FIG. 2, in accordance with various embodiments.

FIG. 11 depicts an example implementation of a circuit 1100 which represents one of the secondary’ oscillators of FIG. 10, in accordance with various embodiments.

FIG. 12 depicts an example implementation of a circuit 1200 which represents one of the secondary oscillators of FIG. 10, and which has multiple resonators, in accordance with various embodiments.

FIG. 13 depicts an example implementation of a circuit 1300 which represents the primary oscillator of FIG. 10. in accordance with various embodiments.

FIG. 14 illustrates an example of components that may be present in a computing system 1450 for implementing the techniques (e.g., operations, processes, methods, and methodologies) described herein.

DETAILED DESCRIPTION As mentioned at the outset, various challenges are presented in maintaining a stable frequency and phase of a clock signal of an oscillator circuit.

A clock signal which is output from a reference clock can be used for various purposes in a computing device. For example, in one approach, the reference clock can be used for navigation in a mobile device when Global Positioning System (GPS) signals are not present. Other example applications include network synchronization in server platforms, high speed transactions and security. In these cases, the reference clock should be highly accurate with no more than a very small drift. The drift is a change in the frequency of the clock signal relative to a reference level, which may be the resonant frequency of a resonating material of the clock.

One approach to providing a highly accurate clock signal involves a high-stability clock on the mam board of the computing device. However, such clocks are expensive, depending on the stability specifications and have disadvantages in terms of size, power cons umpti on and j itter.

Another approach is to use a chip-scale atomic clock. This is a compact, low-power atomic clock fabricated using techniques of microelectromechanical systems (MEMS) and incorporating a low-power semiconductor laser as the light source. Atomic clocks rely on the stability of the frequency of an electron spin transition between two energy levels. A cry stal oscillator is locked using a phase-locked loop (PLL) to a stable microwave frequency that is divided down to the crystal oscillator frequency as part of a feedback loop. However, these are also expensive, and can have a high power consumption, e.g., more than 20 W.

The solutions provided herein address the above and other disadvantages. In one aspect, in a computing device, an array of secondary oscillators is used to improve the accuracy of a primary oscillator. The respective secondary clock signals of the secondary oscillators can be evaluated to determine a frequency offset or drift relative to a primary clock signal of the primary oscillator under varying environmental conditions, such as temperature, vibration, pressure, humidity or magnetic field. An offset of the primary clock signal relative to a ground truth reference such as an atomic clock can also be determined. These frequency offsets and the environmental conditions can be used in a machine learning process such as in training a neural network. Once the neural network is trained, the computing device can be deployed in the field, where the atomic clock is not available. The environmental conditions can be continually monitored by sensors, and the offsets of the secondary clock signals relative to the primary clock signal can be determined and input to the neural network to obtain an optimum compensation value for the primary clock signal.

In one approach, the oscillators are micromechanical oscillators. The oscillators can be generally uncorrelated in terms of their response to different environmental conditions. The solution described improves the overall system precision compared to an approach which uses an averaging factor such as the inverse of the square root of the number of clocks. The solution can use machine learning (ML) to combine data from the individual oscillators, which may be thermally stable, age resistant and uncorrelated, to produce a precise clock output. In one approach, a recurrent neural network is trained using data collected to predict the timing errors between the uncorrelated clock signals relative to a master stable atomic clock in a laboratory environment. The trained model can leam to weigh the timing information from the individual oscillators, with a goal to minimize the timing error compared to the atomic clock across a wide range of thermal and aging conditions. The trained model can form an inference engine to predict, in real time, the aging and stability of the micromechanical oscillators without the need for an atomic clock. The solution can be implemented using a software-defined timing engine to compute a compensation for the primary clock signal which results in a highly precise clock timing output.

The solutions provide a number of advantages. For example, micromechanical oscillators have a low power consumption. A total power consumption may be less than, e.g.. 150 mW. The oscillators also have a small form factor. For example, individual packaged oscillators may have a size of 800 pmm x 800 pmm x 130 pmm, resulting in a total solution size of less than 10 mm x 10 mm x 300 pm. Moreover, the solution is very cost-effective. The solution can provide precision navigation for a mobile device in a GPS- denied environment as well as advantages in server platforms such as high speed transactions and improved security, as well as in many other applications.

These and other features will be further apparent in view of the following discussion.

FIG. 1 depicts an example plot 100 of a changing frequency (f) of a clock signal over time (t), in accordance with various embodiments. The frequency of a clock signal can change based on factors such as aging of the resonator and changing environmental conditions such as changing temperature, vibration, pressure, humidity or magnetic field. The temperature of the oscillator can change due to changes in ambient temperature and the temperature of other components of the computing device. Even when the temperature is regulated, the temperature can change within the regulated range and due to inaccuracies in the temperature-regulation system.

The computing device can also be subject to a varying vibration based on factors such as movement of a mobile computing device. For a non-mobile computing device such as a server, changing vibrations can be introduced by other components of the computing device, other nearby computing devices or equipment in a facility in which the server is located.

The pressure or humidity can be an ambient pressure or humidity in the environment in which the computing device is located. In some cases, a resonator can be hermetically sealed to reduce the effects of changes in pressure or humidity.

The magnetic field can vary due to the presence of electrical components or conductive paths near the resonators and a changing current in these electrical components or conductive paths.

The frequency of a clock signal can vary' higher or low er than a reference level, f ref. The reference level can be a nominal or baseline frequency that the resonator would run at under specified conditions such as specified environmental conditions. The plot 100 shows that the frequency is below the reference level by a drift or offset frequency, Afx, at a time tx. The solutions described herein can estimate the drift of the oscillator and provide a corresponding compensation to bring the frequency back to f ref. A similar approach can be used to correct a drift in the phase of the clock signal.

FIG. 2 depicts an example system 200 including a neural network 220 which is trained using a primary' oscillator 211, a set of secondary' oscillators 212-214 and one or more environmental sensors 215 to predict an offset in the frequency of a clock signal of the primary oscillator, in accordance with various embodiments. A number of oscillators are provided in a package 210 of a computing device, in one example approach. The computing device can be a mobile device or a server, for example. The oscillators include a primary' oscillator (Primary Osc) 211, a first secondary oscillator (SecOsc[l]) 212, asecond secondary oscillator (SecOsc[2]j 213 and a third secondary oscillator (SecOsc[3]) 214. Three secondary oscillators are depicted as an example. In general, tw o or more secondary oscillators can be provided. The accuracy of the solution is improved when a larger number of secondary oscillators are used and, in particular, when the secondary' oscillators are relatively uncorrelated in their frequency and phase response to different environmental conditions. One or more environmental conditions can be measured by environmental sensors (EnvSensors) 215. See also FIG. 9.

The primary oscillator outputs a primary clock signal on paths 230 and 231. The secondary oscillators 212, 213 and 214 output respective clock signals on paths 232, 233 and 234, respectively. The subtraction circuits 239, 240 and 241 indicate that the frequency of the primary clock signal is subtracted from the frequencies of the secondary clock signals on the paths 232, 233 and 234, respectively, to provide offset frequencies on paths 242, 243 and 244, respectively, to input nodes 221, 222 and 223 in an input layer LI of the neural network 220. The environmental sensors output data regarding environmental conditions on a path 235 to an input node 224 of the neural network.

A neural network can include a number of processing units, also referred to as nodes or cells, arranged in multiple layers. Each processing unit is represented by a circle, and the arrows between circles represent input paths between the processing units. In this example, the layers include an input layer LI, a hidden layer L2 and an output layer L3. The initial data for the neural network is input at the input layer. The hidden layers are intermediate layers (between the input and output layers) where all the computations are performed. The output layer provides a result based on the given inputs.

The nodes are connected by arrows which denotes input paths. In this example, each node in L2 receives three data inputs, one from each node in LI. Each input to a processing unit is a digital data unit. The number of processing units per layer can vary. Typically, the hidden layers have the same number of processing units when multiple hidden layers are present.

In this example, the outputs of the nodes 221-224 are input to each of nodes 225- 227. and the output of the nodes 225-227 are input to the node 228. The output of the node 228 is a predicted or estimated offset for the primary clock signal. A goal of the training of the neural network is to minimize the difference between the predicted offset and a target offset, where the target offset is a difference between the frequency of the primary clock signal and the frequency of a reference clock signal such as an atomic clock signal from an atomic clock 250. for instance. In one approach, a subtraction circuit 252 is used to obtain the target offset by subtracting the frequency of the primary clock signal on the path 230 from the frequency of the atomic clock signal on the path 251. The neural network can be trained by adjusting the weights of the nodes to minimize the difference between the predicted offset and a target offset, in an example implementation.

The neural network can optionally receive environmental conditions from one or more sensors associated with each oscillator as well as a system-wide device temperature. For example, these environmental conditions could include temperatures of the respective oscillators.

The components of the system can include an intelligent software engine that uses machine learning to estimate the drift error relative to a stable atomic clock using relative drift among an a finite set of uncorrelated mechanical oscillators as sensory inputs with a theoretical accuracy of less than 1 psec. of time drift over a week.

The oscillators can include micromechanical resonator arrays implemented as hermetic vacuum-packaged chiplets in combination with advanced packaging techniques to achieve a small size and power consumption.

In the different oscillators, different single crystalline materials can be used in a thin film form. This simultaneously results in high-quality piezoelectric layers on a silicon substrate and suspends the resonators so that they can be ovenized (e g., a local heating element is provided for each resonator) with very low power. High quality films translate to very' low loss and high quality factors (Q) and low rates of aging due to significantly reduced intrinsic defect fluctuations during high frequency operations.

Integrating the temperature sensors in a resonator body and using multiple modes to make the resonator itself as the temperature sensor with 1 m °C temperature sensitivity, for instance, results in a sub 22 m °C temperature control. Moreover, in combination with sub 100 mTorr hermetic vacuum packaging, the micro-oven gain is greater than 7xlO^A-14 per °C.

Moreover, additional features can be provided to improve the estimation accuracy for the machine learning model. These features include using fine resolution fractional PLLs for temperature compensation of the resonator which will have a different aging profile than that of the same array compensated using the micro-even approach. Heating from ovenization accelerates aging while the fractional-N PLL compensation does not involve any heating and hence will have a slower aging profile. An additional feature involves customizing the thermal response of the resonator arrays to operate at different temperature ranges using the turnover temperature as the basis for controlling these ranges.

See also FIG. 12.

The solution can also benefit from the design of mechanical suspensions that simultaneously attain high quality factors, high isolation from thermal fluctuations and stress changes, and vibration rejection, in addition to active vibration compensation to achieve good vibration isolation such as better than 10^A-l 3 per g.

FIG. 3 depicts a flowchart of an example process for training a neural network, consistent with FIG. 2, in accordance with various embodiments. Block 300 includes vary ing one or more environmental conditions, such as temperature, vibration, pressure, humidity or magnetic field. The environmental conditions can be varied one at a time or multiple conditions can be varied concurrently. Different rates of change can be used as well. Training data sets can be developed which cover a wide range of scenarios. For example, the temperature can be varied higher and lower in cycles while vibrating the package or platform on which the oscillators are mounted. In other cases, there can be large changes in temperature with no changes in vibration, and so on. The responses of the individual clocks in terms of frequency and phase can be gathered along with measurements of the environmental conditions or parameters. The testing can occur over a time frame such as several days, for example.

Block 301 includes detennining an offset (target offset) of a frequency of a primary clock signal relative to a reference frequency, e.g., of an atomic clock. This can involve using the subtraction circuit 252 of FIG. 2, for example. Block 302 includes determining offsets of respective frequencies of secondary clock signals relative to the frequency of the primary clock signal. This can involve using the subtraction circuits 239-241 of FIG. 2, for example. Block 303 includes training a model to have an output corresponding to the target offset, where inputs of the model include the offsets of the respective secondary clock signals and the one or more environmental conditions. The model can be based on a neural network, in one approach.

FIG. 4 depicts an example plot of changes in the frequency of clock signals of the different oscillators of FIG. 2 as a function of an environmental condition (EC), in accordance with various embodiments. The different oscillators will respond differently to the changes in the environmental conditions when the oscillators are of different types. For example, the different oscillators can have different resonating materials and/or different resonating mode shapes. Example resonating materials include quartz, lithium nitrate, lithium tantalite or aluminum nitride. Example resonating mode shapes include flexural mode (bending mode), extensional mode, lamb mode and lame mode. Various types of MEMS resonators which may be used include clamped-clamped resonator, cantilever resonator, fixed-fixed beam resonator, square plate resonator, disc resonator, ring resonator and comb drive resonator.

By providing different types of oscillators, their responses to the changes in the environmental conditions will be relatively uncorrelated. This helps improve the accuracy of the training of the neural network. For example, the plots show an environmental condition at three different levels, EC_a, EC_b and EC_c, and a frequency which varies from a reference level, f_ref. A plot 410 represents the reference level of f ref. Plots 400, 401. 402 and 403 represent the frequencies of PrimaryOsc. SecOsc[l], SecOsc[2] and SecOsc[3], respectively. At EC a, the frequencies of PrimaryOsc, SecOscfl], SecOsc[2] and SecOsc[3] are fpa, fl a, f2a and f3a, respectively. At EC_b, the frequencies of PrimaryOsc, SecOscfl], SecOsc[2] and SecOsc[3] are fpb, fib, f2b and f3b, respectively. At EC_c, the frequencies of PrimaryOsc, SecOscfl], SecOsc[2] and SecOsc[3] are fpc, flc, f2c and flc, respectively. The frequencies of PrimaryOsc, SecOsc[l] and SecOscR] therefore increase as EC increases, while the frequency of SecOsc[3] decreases as EC increases. Additionally, the frequency of SecOsc[2] increases more than the frequency of SecOsc[l], and the frequency of SecOscf 1 ] increases more than the frequency of PrimaryOsc. The different oscillators thus are relatively uncorrelated in their response to the change in EC.

The target offset of block 301 of FIG. 3 can be determined as f ref. - fpa, f ref. - fpb or f ref. - fpc at EC_a, EC_b and EC_C, respectively. Regarding block 302 of FIG. 3, at EC_a, the offset of the secondary clock signals relative to the primary clock signals can be determined as fla - fpa, 12a - fpa and f3a - fpa for SecOscf l], SecOsc[2] and SecOsc[3], respectively. At EC_b, the offset of the secondary' clock signals relative to the primary clock signals can be determined as fib - fpb, f2b - fpb and f3b - fpb for SecOscfl], SecOsc[2] and SecOsc[3], respectively. At EC_c, the offset of the secondary clock signals relative to the primary clock signals can be determined as flc - fpc, f2c - fpc and 1 c - fpc for SecOsc[l], SecOsc[2] and SecOsc[3], respectively. The offsets can be determined similarly for each different environmental condition.

The plots provide data which allows the target offset of the primary clock signal to be predicted based on the relative offsets of the secondary’ clock signals. For example, if the offsets are fla - fpa, f2a - fpa and f3a - fpa for SecOsc[l], SecOsc[2] and SecOsc[3], respectively, and EC=EC_a, it can be predicted that the target offset is f ref. - fpa for PrimaryOsc. The primary clock signal can then be compensated to reduce its frequency by the target offset to result in the stable desired frequency of f ref. for PrimaryOsc, in one approach. The prediction becomes more accurate as more secondary’ clock signals are used and as the secondary clock signals are more uncorrelated relative to one another in their response to the changing environmental conditions.

FIG. 5 depicts an example nonlinear autoregressive network with exogenous inputs (NARX) model 500 for training a neural network, consistent with FIG. 2, in accordance with various embodiments. This is one example approach for training a neural network. A NARX model can leam to predict one time series given past values of the same time series, a feedback input, and another time series called the external (or exogenous) time series. The model includes a hidden layer 510 and an output layer 520. An input node 501 is to input x(t) into a 2: 1 delay function 511, and an input node 502 is to input y(t) into a 2: 1 delay function 512. 1:2 represents the input delay for x(t) and the feedback delay for y(t). X(t) is an input of a current step and can represent the inputs such as frequency offsets or environmental conditions. Y(t) is the output of the previous step and can represent the target offset of the primary' clock signal. As mentioned, a goal of training the model in one approach is to minimize the target offset. The training can involve determining optimum values of the weights in the model, such as wl, w2 and w3. Nodes 513 and 514 represent weights wl and w2 which are multiplied by x(t) and y(t), respectively. At a node 515, bl is a constant. A summation node 516 provides the sum x(t)*wl + y(t)*w2 + bl to a function 517, which is non-linear in this example. The function 517 translates its input to a corresponding output z(t).

The output z(t) is input to a node 521 which represents a weight w3. At a node 522, b2 is a constant. A summation node 523 provides the sum z(t)*w3 + b2 to a function 524, which is linear in this example. The function 524 translates its input to a corresponding output y(t) at the output node 530. The process is repeated in an iterative manner until the model is sufficiently trained, e.g.. to be able to predict the target offset with a desired degree of accuracy.

A study' using the NARX model involved predicting clock drifts for a nonlinear Temperature-Compensated Cry stal Oscillator (TCXO) compared to an Ovenized Crystal Oscillator (OCXO). This study involved collecting the change in frequency versus a 10 MHz nominal frequency over a period of eight hours while tracking the package temperature, followed by four hours of power down. Ten data sets were collected, where nine data sets were used to train a NARX model to estimate the drift of the tenth data set when run with respect to temperature and time compared to the OCXO reference. The estimated error is between -3 mHz and -4 mHz of drift frequency, or 0.7 parts per billion (ppb). The study demonstrates that neural networks can accurately estimate clock drifts of TCXOs when trained on drifts calculated with respect to a reference clock (i.e., OCXO) limited by the training reference accuracy. Hence, using an atomic clock reference would allow estimating the primary oscillator error with a precision close to that of the atomic reference.

These studies show the concept of using multiple uncorrelated clocks to generate a stable clock with time error approaching that of the reference. Additional performance can be gained by leveraging the strong points at specific temporal intervals of each of the uncorrelated clocks instead of just relying on a single most stable clock. Generally, the proposed machine learning approach provides many more degrees of freedom in the design space than what would be present when developing just one clock that is challenged by fundamental physics. It also enables a path to future system improvements as improvements in individual components occur over time.

FIG. 6 A depicts an example system in which the trained neural network of FIG. 2 is used to predict the frequency and/or phase offset of a primary clock signal, in accordance with various embodiments. Once the neural network is trained, a computing device which includes the package 210 of oscillators and environmental sensors can be deployed in the field, to the end user. In this case, there is no further access to an atomic clock. Based on the inputs, the output of the neural network 220 is a predicted offset of the primary clock signal. The predicted offset can be provided to a correction circuit 610 which determines correction parameters to provide to a frequency synthesizer 620. The frequency synthesizer receives the primary clock signal on the path 230 and applies the correction parameters to provide a corrected output clock signal. This is a stable clock signal which does not vary significantly with varying environmental conditions. This clock signal can be distributed to other circuits in the computing device or to other computing devices for various uses such as discussed previously.

The output clock signal has a frequency based on the frequency of the primary clock signal and the predicted offset. In one possible approach, the output clock signal has a frequency equal to the sum of the frequency of the primary clock signal and the predicted offset. In another approach, the output clock signal is obtained by up converting, e.g., multiplying, or down converting, e.g., dividing, the frequency of the primary clock signal while incorporating a correction to frequency based on the predicted offset.

The frequency synthesizer can be implemented in various ways. In one approach, the frequency synthesizer receives the input primary clock signal and generates a clock of desired frequency determined by a frequency-controlled word (FCW) from the correction circuit. The frequency synthesizer can be implemented using a phase-locked loop (PLL), which uses a voltage-controlled oscillator in a feedback loop to generate the output. In another approach, the frequency synthesizer is implemented as a digital-to-time converter (DTC), where clock edges of the primary’ clock signal can be delayed by a predefined amount to generate a different frequency output. A 48-bit FCW can be used, for instance. A PLL-based approach has the benefit of frequency multiplication and is more energy efficient at lower frequencies, while the DTC-based approach provides a benefit for frequencies higher than 500 MHz. The power consumption is expected to be relatively small. In another approach, the frequency synthesizer is implemented as a direct digital synthesizer which receives correction coefficients from the correction circuit and regenerates the input primary’ clock signal with an adjusted frequency, either higher or lower than the frequency of the primary clock signal, based on the correction coefficients.

FIG. 6B illustrates an example phase-locked loop (PLL) 630 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments. The PLL receives the primary clock signal at a phase detector 631. A feedback clock signal (divclk) is also received at the phase detector. Based on a phase difference between the two input signals, the phase detector provides an output signal (a phase error) for use by a loop filter 632. The loop filter provides a corresponding output signal to control an oscillator 633, which in turn provides the output clock signal. For example, the phase detector, loop filter and oscillator can be digitally-implemented, in which case the signals they provide are digital codes or code words.

In one possible implementation, a digital phase detector can comprise an exclusive- OR (XOR) logic gate. When the two signals being compared are completely in-phase, the XOR gate's output will have a constant level of zero. When the two signals differ in phase, the XOR gate's output will be high for a portion of each cycle which is proportional to the difference in phase. The output of the XOR gate thus changes duty cycle in proportion to the phase difference. The output can be applied to a low-pass fdter to obtain an analog voltage that is proportional to the phase difference between the two signals. The phase difference can then be converted to a code word using an analog-to-digital converter. The input clock signals can be square waves in one approach.

In other possible implementations, a digital phase detector can be based on a sample and hold circuit, a charge pump, or a logic circuit comprising flip-flops. In another approach, the phase detector has an analog implementation.

The loop filter converts the signal representing the phase difference to a signal for the oscillator 633. For example, in an all-digital implementation of the PLL, a digital loop filter can convert a code word representing the phase difference to a code word representing an output frequency, or a change in an output frequency, for the digitally-controlled oscillator. The digital loop filter may be a proportional-integral filter which includes a proportional gain summed with an output of an integrator. The path between the loop filter and the oscillator may be a digital bus, in this case, and the oscillator may be a synthesized digitally-controlled oscillator.

Alternatively, in a hybrid digital implementation, the path between the loop filter and the oscillator may be coupled to a digital to analog converter (DAC) which, in turn is coupled to an analog oscillator. The DAC translates the code provided by the loop filter to an analog signal for controlling the oscillator.

In either case, the oscillator adjusts the output clock signal based on the signal received from the filter, such that the loop filter controls the frequency and phase of the oscillator. The output clock signal is also provided on a feedback path to a fractional-N divider 634. The output clock signal is divided in frequency by the fractional divider to provide the divided clock signal, divclk. In one approach, the division is by an integer N for some cycles and by an integer N+l for other cycles. With the fractional division, the frequency of divclk, on average, can match a corrected version of the frequency of the primary clock signal. Thus, in one approach, the division ratio is adjusted based on the offset of the primary clock signal. Other components of the PLL could also be adjusted based on the offset such as the phase detector, loop filter and oscillator.

Due to the frequency division, the frequency of the output clock signals is a multiple of the frequency of the primary clock signal.

FIG. 6C illustrates an example digital-to-time converter 640 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments. A digital-to-time converter (DTC), also referred to as a digital delay generator, converts a number to a time delay. A DTC can be used, e.g., in reducing or down converting the frequency of a primary clock signal.

In this example implementation, a gate controller 646 receives coefficients such as first and second digital values dl and d2, respectively. These values control a delay to be provided by the DTC. The first and second digital values can be converted to time instants of a rising edge and a falling edge, respectively, of an output signal of the DTC. The gate controller 646 generates a gate enable signal 647 based on the first and second digital values so that the gate enable signal has a first enable period enl and a second enable period en2 for each pair of the first and second digital values.

A gate 641 is configured to conditionally pass the primary clock signal 642 to a l:n divider in response to the gate enable signal. The gate 641 thus provides a gated signal 643. The frequency divider 644 generates a frequency divided signal 645 which may be used as the output signal of the DTC 640. Alternatively, the frequency divided signal may be further processed to obtain the output signal of the DTC 640.

The input of the frequency divider may be edge-triggered and the frequency divider may toggle between a first logic state and a second logic state each time an edge of a particular polarity (rising or falling edge) is applied to its input. For example, the frequency divider 644 may react to rising edges, only, and ignore any falling edges (or vice versa).

The gate controller 646 may be configured such that a single pulse of the primary clock signal is passed during each enable period. In an alternative implementation the gate controller may be configured such that a predefined number of pulses of the primary clock signal is passed during each enable period. In this case, the frequency divider 644 may divide by a divide factor larger than two. The multiple clock pulses corresponding to each of the first digital value and second digital value may be used for calibration of the DTC.

FIG. 6D illustrates an example Direct Digital Synthesis (DDS) circuit 650 of the frequency synthesizer 620 of FIG. 6A, in accordance with various embodiments. A DDS can create an output clock from a single, fixed-frequency reference clock. The DDS can be used to increase or decrease the frequency of the primary clock signal, for example. The output clock can be an analog waveform formed by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. The DDS includes a phase accumulator 651, a phase-to-amplitude converter 653, such as a sine look-up table and a digital-to-analog converter (DAC) 654. The DDS produces can output a sine wave at a given frequency, for example, where the frequency depends on the primary clock frequency and a tuning word, which is a binary number programmed into a frequency register. The binary number provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude — corresponding to the sine of that phase angle — to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed- frequency sine wave, a constant value is added to the phase accumulator with each clock cycle. The constant value is the phase increment, which is determined by the binary number. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform.

FIG. 7 depicts a flowchart of an example process for using a trained neural network to predict the frequency offset of a clock signal, consistent with FIG. 6A, in accordance with various embodiments. Block 701 includes receiving digital data indicating respective offsets of frequencies of respective secondary clock signals from a plurality of secondary oscillators, wherein the respective offsets are relative to the frequency of a primary clock signal. Block 702 includes receiving environmental data from one or more sensors. Block

703 includes inputting the offsets and the environmental data to a neural network. Block

704 includes determining, as an output of the neural network, an offset of the frequency of the primary clock signal relative to a respective baseline frequency, e.g., from an atomic clock. Block 705 includes providing an output clock based on the primary clock signal and the determined offset of the frequency of the primary’ clock signal. The process can be repeated in successive iterations.

The process can be a processor-implemented method, in one approach.

FIG. 8 depicts an example configuration of an oscillator 800, consistent with the primary and secondary oscillators of FIG. 2, in accordance with various embodiments. The oscillator includes a resonator die 810 and a silicon die 820. The resonator die includes a temperature sensor 811 and a resonator 812. Example resonating materials include quartz, lithium nitrate, lithium tantalite or aluminum nitride. The resonator vibrates at a specific resonant frequency when excited by a signal from a driver/shaper 821. The driver/shaper provides an uncompensated reference signal to a reference sampling frac-N PLL 822. The PLL is responsive to a frequency word from a look up table (LUT) 823 to provide an output signal to a divider 824. The divider in turn provides a compensated output signal. A temperature sensor driver 825 can be used to receive temperature data from the temperature sensor. Based on the sensed temperature, the temperature sensor driver selects a frequency word from the LUT for use by the PLL.

A resonator typically has a resonant frequency at a specific design temperature, also referred to as a turnover temperature. If the temperature is higher or lower than the specific design temperature, the resonant frequency tends to drop off.

FIG. 9 depicts example individual environmental sensors of the set of environmental sensors 215 of FIG. 2, in accordance with various embodiments. The environmental sensors can include a temperature sensor 901, a vibration sensor 902. a pressure sensor 903, a humidity sensor 904 and a magnetic field sensor 905. An example temperature sensor is the LM75A from Texas Instruments, Inc. in Dallas, Texas. An example vibration sensor is the ADXL362 from Analog Devices, Inc. in Wilmington, Massachusetts. An example ambient pressure sensor which can also measure temperature is the BMP280 from Bosch Sensortec GmbH in Reutlingen, Germany. An example humidity sensor is the Si701x from Silicon Labs in Austin, Texas. An example magnetic field sensor is the A133x series of Hall-effect magnetic sensors from Allegro Microsystems in Manchester, New Hampshire. The sensors may communicate with a processor over a bus, for example, such as an Inter- Integrated Circuit (I2C) bus.

FIG. 10 depicts an example system 1000 which provides an output clock signal based on a primary clock signal, secondary clock signals and environmental conditions, consistent with FIG. 2, in accordance with various embodiments. The system includes the primary oscillator 211 and the secondary oscillators 212-214 of FIG. 2. The system may be on one or more boards or dies, for example. Each oscillator provides its clock signal to a respective counter. For example, the primary clock signal from PrimaryOsc is provided to a counter 1011 and the secondary' clock signals from SecOsc[l], SecOsc[2] and SecOsc[3] are provided to counters 1012, 1013 and 1014, respectively. Optionally, each oscillator modifies its clock signal in a similar way such as by dividing down the frequency by the same amount, before providing it to a counter.

Each counter provides a count based on the frequency of the respective clock signal to multiplexers 1020 and 1021. The dashed line paths represent a count of the primary' clock signal. The multiplexer 1020 passes pairs of counts, in turn, to a time-to-digital-counter (TDC) 1022. Each pair includes the count of the primary clock signal and a count of one of the secondary clock signals. The TDC 1022 determines an offset or error of the two counts and provides it as a frequency offset or error to a processor 1030 as digital data. Each offset may represent the frequency offset of the secondary clock signal relative to the primary clock signal, for instance.

In one approach, the frequency error detection circuit comprises a first multiplexer 1020 coupled to the respective frequency counters, wherein the multiplexer is to pass a frequency count of the primary clock signal and a frequency count of one of the secondary clock signals at a time.

The multiplexer 1021 passes pairs of counts, in turn, to a phase-detection circuit 1023. The phase-detection circuit determines an offset or error of the two counts and provides it as a phase offset or error to the processor 1030 as digital data. Each offset represents the phase offset of the secondary clock signal relative to the pnmary clock signal. The counters, multiplexers, TDC and phase-detection circuit are part of a frequency and phase error detection circuit 1025, which is coupled to the oscillators and to the processor

The processor 1030 may receive a reference clock from the atomic clock 250 in the training phase of a neural network. The processor may also receive data representing one or more environmental conditions from the set of environmental sensors 215. The processor may be configured to execute instructions 1041 stored in a memory 1040 to provide the functions described herein. Generally, the processor may provide data management and algorithms. The memory may store measurements.

The primary clock signal from the primary oscillator 211 can also be provided to a divider 1050 to provide a divided-down version of the primary⁷ clock signal to the processor. Based on the various inputs it receives, the processor can implement a neural network or other model which predicts an offset of the primary clock signal and provides instructions to a frequency synthesis circuit 1060 for providing a corresponding output clock signal. A divider 1061 may be separate from, or included with, the frequency synthesis circuit. The frequency synthesis circuit can receive the primary clock signal as an input from the primary oscillator 211 and provide a corresponding output clock signal such as by using one of the implementations described in connection with FIGs. 6B-6D.

As mentioned, the different oscillators can have different types of resonators so that their response to different environmental conditions is relatively uncorrelated. Each resonator can include a localized heater driver and a temperature sensor for frequency compensation. Additionally, a circuit 1003 represents a global temperature sensor 1001 and driver 1002 which can be used to keep the die temperature fixed to ensure than an oscillator driver does not introduce errors due to temperature drift.

The frequency error between each secondary resonator and the primary resonator is quantized by a counter and time-to-digital converter (TDC) which will be used as the real time features to be processed by the machine learning engine running on the processor 1030. The processor can also include a hardware accelerator to implement the neural network model. The oscillator drivers can be low jitter oscillator drivers that are associated with different uncorrelated resonator chiplets. To mitigate the increase in the number of inputoutput circuits as well as power consumption from having a dedicated driver for each resonator within each resonator chiplet, multiple resonators with non-harmonic frequency relationship can be connected across each driver, and the desired oscillator mode can be selected by energy injection to a specific frequency generated by an on-die oscillator. The set of resonators can be considered to be a single resonator with multiple oscillation modes which can be manually selected.

Regarding the frequency and phase error detection circuit 1025. accurate detection of the frequency error can be implemented using digital counters, in one possible approach. However, there is a trade-off between latency and accuracy. For example, 1 ppm error in frequency would require at least 106 cycles to detect any change in counter output. For a 100 MHz clock, the counter provides an output after 10 ms. The TDCs are used to improve the resolution. Since there is a trade-off between range and resolution in TDCs, a combination of coarse and fine TDCs may be used to meet a desired specification. State- of-the-art TDCs can reach ~lps resolution in <lmW. This can improve the latency by a factor of 104. Resolution can be improved further by leveraging advanced technology nodes and consuming more power. This mechanism can detect the relative frequency or phase error between two clock sources. Absolute detection of frequency would require a reference clock source.

Regarding temperature sensing and compensation, a micromechanical oscillator that implements a fractional PLL can be used to compensate the mechanical resonator frequency using a resistor-based temperature sensor on the resonator chiplet. This approach enabled compensating a thin film piezoelectric-on-silicon (TPoS) mechanical resonator from about 2000 ppm down to 30 ppm across a temperature range from -40 °C to 125 °C. A temperature sensor with 1 m°C accuracy will ensure the control of the oven temperature to less than 22 m°C and hence the > 2481 oven gain required to attain the df/dT of 7xlO^A-14 across the product temperature specification range. Resistor-based temperature sensors can be embedded in the resonator structures, with dual mode resonator structures used as thermal sensors. Moreover, both resistive-based sensors and bandgap-based thermal sensors can be used to monitor the temperature of the complementary metal-oxide-semiconductor (CMOS) chip. For all thennal sensors, both on the resonator chiplets as well on the CMOS chiplet, highly digital detection circuits using tunable delay lines can be used to accommodate many sensors for each resonator array with a small area and power consumption. Sensing circuitry can be used having a ~lmK temperature resolution while dissipating <100uW powder, for example.

Another possible feature of the system 1000 is oven control compensation. This compensation can provide better than 22 m C control of the micro-oven using a fine grain DAC that controls the heater current relative to the reading of the thermal sensor for that specific resonator. The thermal sensor can be calibrated to ensure ~ 1 m°C sensitivity and the micro-oven can be calibrated to ensure an error less than 22 m°C to achieve frequency stability target and power goals. In one approach, the solution does not ovenize the CMOS chip to reduce the overall power, but instead relies on the calibration step to dial in the change in the oscillator frequency resulting from the change in the driver transconductance as the temperature of the CMOS chip changes.

Another possible feature of the system 1000 is active vibration compensation. The resonance frequency can be tuned in response to a measured acceleration by controlling the load capacitor (C1.C2) connected at each node of the resonator. To achieve a finer granularity' in how' the oscillator driver can adjust the frequency, a delta-sigma modulator can be used which dynamically switches on/off the unit capacitor to maintain the desired average value. For example, an M-bit delta-sigma modulator can effectively reduce the capacitance value by a factor of 2-M leading to ppb frequency tuning granularity’ required to meet the target high stability.

Another possible feature of the system 1000 involves the processor 1030 (e.g., a microprocessor) and a machine learning accelerator to improve the performance and power consumption of the neural netw ork.

FIG. 11 depicts an example implementation of a circuit 1100 which represents one of the secondary’ oscillators of FIG. 10, in accordance with various embodiments. The circuit includes a resonator 1101 coupled to a negative resistance -R 1125 which creates an oscillation in the resonator. The circuit 1100 may include a temperature sensor 1110 coupled to a resistor R2 to sense a temperature at a point which is close to the resonator, and an associated heater driver 1120 to drive a heater in the form of a resistor R1 (a resistive heating element) to maintain the sensed temperature within a specified range of temperatures. An output of the circuit 1100 passes through a delay component 1130 to an output path 1131.

The heater driver can work to stabilize the resonator temperature versus the environmental temperature. To achieve this, the resonator can be kept at a relatively high temperature which is higher than the range of operation of an associated integrated circuit or computing device. For example, if the range of operation is -40 to 80 °C, then the resonator can be kept at a target temperature of, e.g., 90 °C +/- 5 °C. A target temperature range is thus 85-95 °C. Moreover, the resonator is designed to have a specific frequency at a specific temperature called the turnover temperature. The turnover temperature may be the same as the target temperature, in one approach. The resonator temperature is continually sensed and the heater is used to keep it at the turnover temperature, plus or minus a margin. Although, as mentioned, the temperature can vary⁷ at least within the target temperature range and potentially outside the target temperature range as well. A smaller effect is that operating the resonator at an elevated temperature increases its drift gradually over time.

FIG. 12 depicts an example implementation of a circuit 1200 which represents one of the secondary⁷ oscillators of FIG. 10, and which has multiple resonators, in accordance with various embodiments. The circuit includes a set of resonators 1201, 1202 and 1203 coupled to a negative resistance -R 1225 which creates an oscillation in the resonators. In one approach, the resonators may have a non-harmonic frequency relationship. In another approach, the resonators have different turnover temperatures. One of the resonators is selected for use with switches, not shown. The circuit 1200 may include a temperature sensor 1210 coupled to a resistor R2 to sense a temperature at a point which is close to the resonator, and an associated heater driver 1220 to drive a heater in the form of a resistor Rl. An output of the circuit 1200 passes through a delay component 1230 to an output path 1231.

FIG. 13 depicts an example implementation of a circuit 1300 which represents the primary oscillator of FIG. 10, in accordance w ith various embodiments. The circuit includes a resonator 1301 coupled to a negative resistance -R 1325 which creates an oscillation in the resonator. The circuit 1300 may include a temperature sensor 1310 coupled to a resistor R2 to sense a temperature at a point which is close to the resonator, and an associated heater driver 1320 to drive a heater in the form of a resistor Rl. An output of the circuit 1300 passes through a delay component 1330 to an output path 1331. Additionally, a capacitor Cl is in parallel with the resonator 1301 and the negative resistance. The capacitor is adjustable based on a signal received from the processor 1030 on a path 1341 to adjust the resonant frequency of the resonator 1301. An output path 1340 is coupled to the divider 1050.

FIG. 14 illustrates an example of components that may be present in a computing system 1450 for implementing the techniques (e.g., operations, processes, methods, and methodologies) described herein. The voltage regulator 1400 may provide a voltage Vout to one or more of the components of the computing system 1450. An oscillator system 1490 may correspond to the systems 200, 600 and 1000 discussed herein. The memory circuitry 1454 may store instructions and the processor circuitry⁷ 1452 may execute the instructions to perform the functions described herein.

The computing system 1450 may include any combinations of the hardware or logical components referenced herein. The components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or a combination thereof adapted in the computing system 1450, or as components otherwise incorporated within a chassis of a larger system. For one embodiment, at least one processor 1452 may⁷ be packaged together with computational logic 1482 and configured to practice aspects of various example embodiments described herein to form a System in Package (SiP) or a System on Chip (SoC).

The system 1450 includes processor circuitry in the form of one or more processors 1452. The processor circuitry 1452 includes circuitry such as, but not limited to one or more processor cores and one or more of cache memory⁷, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface circuit, real time clock (RTC). timer-counters including interval and watchdog timers, general purpose I/O, memory card controllers such as secure digital/multi-media card (SD/MMC) or similar, interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports. In some implementations, the processor circuitry 1452 may include one or more hardware accelerators (e.g., same or similar to acceleration circuitry 1464), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), or the like. The one or more accelerators may include, for example, computer vision and/or deep learning accelerators. In some implementations, the processor circuitry 1452 may include on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory. such as DRAM, SRAM, EPROM, EEPROM, Flash memory', solid-state memory, and/or any other type of memory device technology, such as those discussed herein

The processor circuitry 1452 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acom RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFIC), one or more microprocessors or controllers, a multi-core processor, a multithreaded processor, an ultra-low-voltage processor, an embedded processor, or any other known processing elements, or any suitable combination thereof. The processors (or cores) 1452 may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the platform 1450. The processors (or cores) 1452 is configured to operate application software to provide a specific service to a user of the platform 1450. In some embodiments, the processor(s) 1452 may be a special-purpose processor(s)/controller(s) configured (or configurable) to operate according to the various embodiments herein.

As examples, the processor(s) 1452 may include an Intel® Architecture Core™ based processor such as an i3, an i5, an i7, an i9 based processor; an Intel® microcontrollerbased processor such as a Quark™, an Atom™, or other MCU-based processor; Pentium® processor(s), Xeon® processor(s), or another such processor available from Intel® Corporation, Santa Clara, California. However, any number other processors may be used, such as one or more of Advanced Micro Devices (AMD) Zen® Architecture such as Ryzen® or EPYC® processor(s), Accelerated Processing Units (APUs), MxGPUs, Epyc® processor(s), or the like; A5-A12 and/or S1-S4 processor(s) from Apple® Inc., Snapdragon™ or Centriq™ processor(s) from Qualcomm® Technologies, Inc., Texas Instruments, Inc.® Open Multimedia Applications Platform (OMAP)™ processor(s); a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; an ARM-based design licensed from ARM Holdings, Ltd., such as the ARM Cortex- A, Cortex-R, and Cortex-M family of processors; the ThunderX2® provided by Cavium™, Inc.; or the like. In some implementations, the processor(s) 1452 may be a part of a system on a chip (SoC), System-in-Package (SiP), a multi-chip package (MCP), and/or the like, in which the processor(s) 1452 and other components are formed into a single integrated circuit, or a single package, such as the Edison™ or Galileo™ SoC boards from Intel® Corporation. Other examples of the processor(s) 1452 are mentioned elsewhere in the present disclosure.

The system 1450 may include or be coupled to acceleration circuitry 1464, which may be embodied by one or more AI/ML accelerators, a neural compute stick, neuromorphic hardware, an FPGA, an arrangement of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs such as complex (CPLDs) or high complexity PLDs (HCPLDs), and/or other forms of specialized processors or circuitry designed to accomplish one or more specialized tasks. These tasks may include AI/ML processing (e.g., including training, inferencing, and classification operations), visual data processing, network data processing, object detection, rule analysis, or the like. In FPGA-based implementations, the acceleration circuitry 1464 may comprise logic blocks or logic fabric and other interconnected resources that may be programmed (configured) to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such implementations, the acceleration circuitry 1464 may also include memory cells (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuses, etc.) used to store logic blocks, logic fabric, data, etc. in LUTs and the like.

In some implementations, the processor circuitry 1452 and/or acceleration circuitry 1464 may include hardware elements specifically tailored for machine learning and/or artificial intelligence (Al) functionality'. In these implementations, the processor circuitry 1452 and/or acceleration circuitry' 1464 may be, or may include, an Al engine chip that can run many different kinds of Al instruction sets once loaded with the appropriate weightings and training code. Additionally or alternatively, the processor circuitry' 1452 and/or acceleration circuitry 1464 may be. or may include, Al accelerator(s), which may be one or more of the aforementioned hardware accelerators designed for hardware acceleration of Al applications. As examples, these processor(s) or accelerators may be a cluster of artificial intelligence (Al) GPUs, tensor processing units (TPUs) developed by Google® Inc., Real Al Processors (RAPs™) provided by AlphalCs®, Nervana™ Neural Network Processors (NNPs) provided by Intel® Corp., Intel® Movidius™ Myriad™ X Vision Processing Unit (VPU), NVIDIA® PX™ based GPUs, the NM500 chip provided by General Vision®, Hardware 3 provided by Tesla®, Inc., an Epiphany™ based processor provided by Adapteva®, or the like. In some embodiments, the processor circuitry 1452 and/or acceleration circuitry 1464 and/or hardware accelerator circuitry may be implemented as Al accelerating co-processor(s), such as the Hexagon 685 DSP provided by Qualcomm®, the PowerVR 2NX Neural Net Accelerator (NNA) provided by Imagination Technologies Limited®, the Neural Engine core within the Apple® Al l or A12 Bionic SoC, the Neural Processing Unit (NPU) within the HiSilicon Kirin 1470 provided by Huawei®, and/or the like. In some hardware-based implementations, individual subsystems of system 1450 may be operated by the respective Al accelerating co-processor(s), Al GPUs, TPUs, or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., that are configured with appropriate logic blocks, bit stream(s), etc. to perform their respective functions.

The system 1450 also includes system memory⁷ 1454. Any number of memory devices may be used to provide for a given amount of system memory. As examples, the memory 1454 may be, or include, volatile memory such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS® Dy namic Random Access Memory⁷ (RDRAM®), and/or any other desired type of volatile memory device. Additionally or alternatively, the memory 1454 may be, or include, non-volatile memory⁷ such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable (EEPROM), flash memory, nonvolatile RAM, ferroelectric RAM, phase-change memory⁷ (PCM), flash memory, and/or any other desired type of non-volatile memory⁷ device. Access to the memory 1454 is controlled by a memory controller. The individual memory devices may be of any number of different package types such as single die package (SDP), dual die package (DDP) or quad die package (Q17P). Any number of other memory⁷ implementations may be used, such as dual inline memory⁷ modules (DIMMs) of different varieties including but not limited to microDIMMs or MiniDIMMs.

Storage circuitry 1458 provides persistent storage of information such as data, applications, operating systems and so forth. In an example, the storage 1458 may be implemented via a solid-state disk drive (SSDD) and/or high-speed electrically⁷ erasable memory (commonly referred to as “flash memory ”). Other devices that may be used for the storage 1458 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and the like, and USB flash drives. In an example, the memory device may be or may include memory’ devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory', nanowire memory’, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory’, magnetoresistive random access memory’ (MRAM) memory that incorporates memristor technology', phase change RAM (PRAM), resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a Domain Wall (DW) and Spin Orbit Transfer (SOT) based device, a thyristor based memory device, a hard disk drive (HDD), micro HDD, of a combination thereof, and/or any other memory. The memory circuitry 1454 and/or storage circuitry 1458 may also incorporate three-dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®.

The memory circuitry 1454 and/or storage circuitry 1458 is/are configured to store computational logic 1483 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. The computational logic 1483 may be employed to store working copies and/or permanent copies of programming instructions, or data to create the programming instructions, for the operation of various components of system 1450 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), an operating system of system 1450, one or more applications, and/or for carrying out the embodiments discussed herein. The computational logic 1483 may’ be stored or loaded into memory circuitry' 1454 as instructions 1482, or data to create the instructions 1482, which are then accessed for execution by the processor circuitry 1452 to carry out the functions described herein. The processor circuitry 1452 and/or the acceleration circuitry 1464 accesses the memory circuitry 1454 and/or the storage circuitry 1458 over the interconnect (IX) 1456. The instructions 1482 direct the processor circuitry’ 1452 to perform a specific sequence or flow of actions, for example, as described with respect to flowchart(s) and block diagram(s) of operations and functionality depicted previously. The various elements may be implemented by assembler instructions supported by processor circuitry' 1452 or high-level languages that may be compiled into instructions 1488, or data to create the instructions 1488, to be executed by the processor circuitry' 1452. The permanent copy of the programming instructions may be placed into persistent storage devices of storage circuitry' 1458 in the factor}' or in the field through, for example, a distribution medium (not shown), through a communication interface (e.g.. from a distribution server (not shown)), over-the-air (OTA), or any combination thereof.

The IX 1456 couples the processor 1452 to communication circuitry 1466 for communications yvith other devices, such as a remote server (not shown) and the like. The communication circuitry 1466 is a hardw are element, or collection of hardware elements, used to communicate over one or more networks 1463 and/or with other devices. In one example, communication circuitry 1466 is, or includes, transceiver circuitry configured to enable wireless communications using any number of frequencies and protocols such as, for example, the Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and/or variants thereof). IEEE 802.23.4. Bluetooth® and/or Bluetooth® low energy (BLE), ZigBee®, LoRaWAN™ (Long Range Wide Area Network), a cellular protocol such as 3GPP LTE and/or Fifth Generation (5G)/New Radio (NR), and/or the like. Additionally or alternatively, communication circuitry' 1466 is, or includes, one or more network interface controllers (NICs) to enable wired communication using, for example, an Ethernet connection, Controller Area Network (CAN), Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway® or PROFINET, among many others.

The IX 1456 also couples the processor 1452 to interface circuit® 1470 that is used to connect system 1450 with one or more external devices 1472. The external devices 1472 may include, for example, sensors, actuators, positioning circuit® (e.g., global navigation satellite system (GNSS)/Global Positioning System (GPS) circuit®), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuit (IC) and/or the like), and/or other like devices.

In some optional examples, various input/output (I/O) devices may be present within or connected to, the system 1450, which are referred to as input circuit® 1486 and output circuit® 1484. The input circuit® 1486 and output circuit® 1484 include one or more user interfaces designed to enable user interaction with the platform 1450 and/or peripheral component interfaces designed to enable peripheral component interaction with the platform 1450. Input circuit® 1486 may include any physical or virtual means for accepting an input including, inter alia, one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphones, scanner, headset, and/or the like. The output circuit® 1484 may be included to show information or otherwise convey information, such as sensor readings, actuator position(s), or other like information. Data and/or graphics may be displayed on one or more user interface components of the output circuitry 1484. Output circuitry 1484 may include any number and/or combinations of audio or visual display, including, inter alia, one or more simple visual outputs/indicators (e.g., binary' status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., Liquid Crystal Displays (LCD), LED displays, quantum dot displays, projectors, etc.), with the output of characters, graphics, multimedia objects, and the like being generated or produced from the operation of the platform 1450. The output circuitry 1484 may also include speakers and/or other audio emitting devices, printer(s), and/or the like. Additionally or alternatively, sensor(s) may be used as the input circuitry 1484 (e.g.. an image capture device, motion capture device, or the like) and one or more actuators may be used as the output device circuitry 1484 (e.g., an actuator to provide haptic feedback or the like). Peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a USB port, an audio jack, a power supply interface, etc. In some embodiments, a display or console hardware, in the context of the present system, may be used to provide output and receive input of an edge computing system; to manage components or services of an edge computing system; identify a state of an edge computing component or service; or to conduct any other number of management or administration functions or service use cases.

The components of the system 1450 may communicate over the IX 1456. The IX 1456 may include any number of technologies, including ISA, extended ISA, I2C, SPI, point-to-point interfaces, power management bus (PMBus), PCI, PCIe, PCIx, Intel® UPI, Intel® Accelerator Link, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, UPI, Intel® OPA IX, RapidlO™ system IXs, CCIX, Gen-Z Consortium IXs, a HyperTransport interconnect. NVLink provided by NVIDIA®, a Time-Trigger Protocol (TTP) system, a FlexRay system, PROFIBUS, and/or any number of other IX technologies. The IX 1456 may be a proprietary bus, for example, used in a SoC based system.

The number, capability, and/or capacity of the elements of system 1450 may vary, depending on whether computing system 1450 is used as a stationary computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smartphone, tablet computing device, laptop computer, game console. loT device, etc.). In various implementations, the computing device system 1450 may comprise one or more components of a data center, a desktop computer, a workstation, a laptop, a smartphone, a tablet, a digital camera, a smart appliance, a smart home hub, a network appliance, and/or any other device/system that processes data.

The techniques described herein can be performed partially or wholly by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions to implement any other processes discussed herein). Instructions associated with the flowchart (and/or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.

The storage medium can be a tangible, non-transitory machine readable medium such as read only memory (ROM), random access memory (RAM), flash memoiy devices, floppy and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memoiy (CD ROMS), Digital Versatile Disks (DVDs)), among others.

The storage medium may be included, e.g., in a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet, a game console, a set top box, an embedded system, a TV (television), or a personal desktop computer.

Some non-limiting examples of various embodiments are presented below.

Example 1 includes an apparatus, comprising: a primary oscillator configured to output a primary' clock signal; a plurality of secondary oscillators, wherein each secondary' oscillator is configured to output a respective secondary clock signal; one or more sensors configured to provide data regarding one or more environmental conditions; and a processor coupled to the primary oscillator, the plurality of secondary oscillators and the one or more sensors, wherein the processor is configured to provide an output clock signal based on the primary clock signal, the respective secondary clock signals and the data from the one or more sensors.

Example 2 includes the apparatus of Example 1, further comprising a frequency error detection circuit coupled to the processor, the primary' oscillator and the plurality' of secondary oscillators, wherein: the frequency error detection circuit is to determine offsets of frequencies of the respective secondary clock signals relative to a frequency of the primary clock signal; and the processor is to determine a predicted offset of the frequency of the primary clock signal based on the offsets of the frequencies of the respective secondary clock signals, and provide the output clock signal based on the predicted offset.

Example 3 includes the apparatus of Example 2, wherein the frequency error detection circuit comprises respective frequency counters coupled to the primary oscillator and the plurality of secondary oscillators.

Example 4 includes the apparatus of Example 3, wherein the frequency error detection circuit comprises a time-to-digital converter coupled to the respective frequency counters.

Example 5 includes the apparatus of Example 3 or 4, wherein the frequency error detection circuit comprises a phase-detection circuit coupled to the respective frequency counters.

Example 6 includes the apparatus of any one of Examples 3-5, wherein the frequency error detection circuit comprises a first multiplexer coupled to the respective frequency counters, and the multiplexer is to pass a frequency count of the primary clock signal and a frequency count of one of the secondary clock signals at a time to the processor.

Example 7 includes the apparatus of any one of Examples 1-6, further comprising a frequency synthesizer coupled to the primary oscillator and the processor, wherein the frequency synthesizer is to provide the output clock signal.

Example 8 includes the apparatus of Example 7, wherein the frequency synthesizer comprises at least one of a direct digital synthesizer, a fractional-N phase-locked loop or a digital-to-time converter.

Example 9 includes the apparatus of any one of Examples 2-8, wherein to determine the predicted offset of the frequency of the primary clock signal, the processor is to implement a neural network having input nodes for the offsets of the frequencies of the respective secondary clock signals and for the one or more environmental conditions, and an output node for the predicted offset.

Example 10 includes the apparatus of any one of Examples 1-9, wherein the plurality of secondary oscillators comprise at least one of different resonating materials or different resonating mode shapes.

Example 11 includes the apparatus of any one of Examples 1-10, further comprising at least one of an integrated circuit, a System on Chip, a System in Package or a computing device in which the primary oscillator, plurality of secondary’ oscillators, one or more sensors and processor are provided, wherein the computing device comprises at least one of a processor circuitry, a memory circuitry, a storage circuitry, an acceleration circuitry, a communication circuitry, an input circuitry, an output circuitry, an interface circuitry or an external device.

Example 12 includes an apparatus, comprising: a memoiy to store instructions; and a processor coupled to the memoiy, wherein the processor is to execute the instructions to: receive digital data indicating respective offsets of frequencies of respective secondary clock signals from a plurality of secondary oscillators, wherein the respective offsets are relative to the frequency of a primary clock signal from a primary oscillator; receive environmental data from one or more sensors; input the offsets and the environmental data to a neural network; determine, as an output of the neural network, an offset of the frequency of the primary clock signal relative to a respective baseline frequency; and provide an output clock signal based on the primary clock signal and the determined offset of the frequency of the primary' clock signal.

Example 13 includes the apparatus of Example 12, wherein the digital data indicating the respective offsets of the frequencies of respective secondary clock signals are received from frequency counters coupled to the plurality⁷ of secondary oscillators and to the primary oscillator.

Example 14 includes the apparatus of Example 12 or 13, wherein the one or more sensors comprises at least one of a temperature sensor, a vibration sensor, a pressure sensor, a humidity sensor or a magnetic field sensor.

Example 15 includes the apparatus of any one of Examples 12-14, wherein the plurality of secondary oscillators comprise different resonating materials.

Example 16 includes the apparatus of any one of Examples 12-15, wherein the plurality of secondary oscillators comprise different resonating mode shapes.

Example 17 includes a processor-implemented method for training a model, comprising: varying one or more environmental conditions; determining a target offset during the varying of the one or more environmental conditions, wherein the target offset is an offset of a frequency of a primary clock signal of a primary oscillator relative to a reference frequency; determining offsets in respective secondary clock signals from a plurality⁷ of secondary oscillators during the vary ing of the one or more environmental conditions, wherein the offsets in the respective secondary clock signals are relative to the frequency of the primary clock signal; and training a model to have an output corresponding to the target offset, where inputs of the model include the offsets of the respective secondary clock signals and the one or more environmental conditions.

Example 18 includes the processor-implemented method of Example 17, wherein the model comprises a neural network, and the training of the model comprises setting weights of nodes of the neural network.

Example 19 includes the processor-implemented method of Example 17 or 18, wherein the reference frequency is from an atomic clock.

Example 20 includes the processor-implemented method of any one of Examples 17-19, wherein the plurality⁷ of secondary oscillators comprise at least one of different resonating materials or different resonating mode shapes.

Example 21 includes a non-transitory machine-readable storage including machine- readable instructions that, when executed, cause a processor or other circuit or computing device to implement the processor-implemented of any one of Examples 17-20.

Example 22 includes a computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the processor- implemented of any one of Examples 17-20.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subj ect matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

The terms “substantially,” “close,” “approximately,” “near,” and “about.” generally refer to being within +/- 10% of a target value. Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like obj ects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, the phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

As used herein, the term “circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, “computer- implemented method” may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

The terms “coupled,” “communicatively coupled,” along with derivatives thereof are used herein. The term “coupled” may mean two or more elements are in direct physical or electrical contact with one another, may mean that two or more elements indirectly contact each other but still cooperate or interact with each other, and/or may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact with one another. The term “communicatively coupled” may mean that two or more elements may be in contact with one another by a means of communication including through a wire or other interconnect connection, through a wireless communication channel or link, and/or the like.

Reference in the specification to "an embodiment," "one embodiment," "some embodiments." or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might." or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional elements. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS What is claimed is:

1. An apparatus, comprising: a primary oscillator configured to output a primary clock signal; a plurality of secondary oscillators, wherein each secondary oscillator is configured to output a respective secondary' clock signal; one or more sensors configured to provide data regarding one or more environmental conditions: and a processor coupled to the primary oscillator, the plurality of secondary' oscillators and the one or more sensors, wherein the processor is configured to provide an output clock signal based on the primary clock signal, the respective secondary clock signals and the data from the one or more sensors.

2. The apparatus of claim 1, further comprising a frequency error detection circuit coupled to the processor, the primary oscillator and the plurality of secondary oscillators, wherein: the frequency error detection circuit is to determine offsets of frequencies of the respective secondary clock signals relative to a frequency of the primary clock signal; and the processor is to determine a predicted offset of the frequency of the primary clock signal based on the offsets of the frequencies of the respective secondary' clock signals, and provide the output clock signal based on the predicted offset.

3. The apparatus of claim 2, wherein the frequency error detection circuit comprises respective frequency⁷ counters coupled to the primary oscillator and the plurality of secondary⁷ oscillators.

4. The apparatus of claim 3, wherein the frequency error detection circuit comprises a time-to-digital converter coupled to the respective frequency counters.

5. The apparatus of claim 3 or 4, wherein the frequency error detection circuit comprises a phase-detection circuit coupled to the respective frequency counters.

6. The apparatus of any one of claims 3-5, wherein the frequency error detection circuit comprises a first multiplexer coupled to the respective frequency counters, and the multiplexer is to pass a frequency count of the primary clock signal and a frequency count of one of the secondary⁷ clock signals at a time to the processor.

7. The apparatus of any one of claims 1-6, further comprising a frequencysynthesizer coupled to the primary oscillator and the processor, wherein the frequency synthesizer is to provide the output clock signal.

8. The apparatus of claim 7, wherein the frequency synthesizer comprises at least one of a direct digital synthesizer, a fractional-N phase-locked loop or a digital-to-time converter.

9. The apparatus of any one of claims 2-8, wherein to determine the predicted offset of the frequency of the primary clock signal, the processor is to implement a neural network having input nodes for the offsets of the frequencies of the respective secondary clock signals and for the one or more environmental conditions, and an output node for the predicted offset.

10. The apparatus of any one of claims 1-9, wherein the plurality of secondary oscillators comprise at least one of different resonating materials or different resonating mode shapes.

11. The apparatus of any one of claims 1-10, further comprising at least one of an integrated circuit, a System on Chip, a System in Package or a computing device in which the primary oscillator, plurality of secondary oscillators, one or more sensors and processor are provided, wherein the computing device comprises at least one of a processor circuitry, a memory circuitry-, a storage circuitry-, an acceleration circuitry-, a communication circuitry-, an input circuitry, an output circuitry, an interface circuitry or an external device.

12. An apparatus, comprising: a memory to store instructions; and a processor coupled to the memory-, wherein the processor is to execute the instructions to: receive digital data indicating respective offsets of frequencies of respective secondary clock signals from a plurality of secondary oscillators, wherein the respective offsets are relative to the frequency of a primary clock signal from a primary oscillator; receive environmental data from one or more sensors; input the offsets and the environmental data to a neural network; determine, as an output of the neural network, an offset of the frequency of the primary- clock signal relative to a respective baseline frequency; and provide an output clock signal based on the primary' clock signal and the determined offset of the frequency of the primary clock signal.

13. The apparatus of claim 12, wherein the digital data indicating the respective offsets of the frequencies of respective secondary clock signals are received from frequency counters coupled to the plurality⁷ of secondary⁷ oscillators and to the primary' oscillator.

14. The apparatus of claim 12 or 13, wherein the one or more sensors comprises at least one of a temperature sensor, a vibration sensor, a pressure sensor, a humidity sensor or a magnetic field sensor.

15. The apparatus of any one of claims 12-14, wherein the plurality⁷ of secondary oscillators comprise different resonating materials.

16. The apparatus of any one of claims 12-15, wherein the plurality of secondary oscillators comprise different resonating mode shapes.

17. A processor-implemented method for training a model, comprising: vary ing one or more environmental conditions; determining a target offset during the varying of the one or more environmental conditions, wherein the target offset is an offset of a frequency of a primary clock signal of a primary oscillator relative to a reference frequency; determining offsets in respective secondary⁷ clock signals from a plurality' of secondary oscillators during the varying of the one or more environmental conditions, wherein the offsets in the respective secondary clock signals are relative to the frequency of the primary clock signal; and training a model to have an output corresponding to the target offset, where inputs of the model include the offsets of the respective secondary' clock signals and the one or more environmental conditions.

18. The processor-implemented method of claim 17, wherein the model comprises a neural network, and the training of the model comprises setting weights of nodes of the neural network.

19. The processor-implemented method of claim 17 or 18, wherein the reference frequency is from an atomic clock.

20. The processor-implemented method of any one of claims 17-19, wherein the plurality⁷ of secondary' oscillators comprise at least one of different resonating materials or different resonating mode shapes.

21. A non-transitory machine-readable storage including machine-readable instructions that, when executed, cause a processor or other circuit or computing device to implement the processor-implemented of any one of claims 17-20.

22. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to cany⁷ out the processor-implemented of any one of claims 17-20.