WO2025089795A1 - Data processing device and data driving device - Google Patents

Abstract

An embodiment discloses a data processing device comprising: a first data conversion unit that converts image data and control data; and a transmission unit that transmits the converted image data and control data, wherein the first data conversion unit comprises: a first packer that converts the image data into a first data packet; a second packer that converts the control data into a second data packet; a first encoder that encodes the first data packet according to a first rule; and a second encoder that encodes the second data packet according to a second rule that is different from the first rule.

Description

Data processing unit and data driving unit

The present embodiment relates to a technique for driving a display device.

The display panel is composed of a number of pixels arranged in a matrix form. Each pixel can have a color such as R (red), G (green), or B (blue), and displays an image on the display panel by emitting light in grayscale according to the image data.

Image data is transmitted from a data processing device such as a timing controller to a data driving device such as a source driver. Image data is transmitted as a digital value, and the data driving device converts the image data into an analog voltage to drive each pixel.

Since image data individually or independently indicates the grayscale value of each pixel, the amount of image data increases as the number of pixels arranged on the display panel increases. Also, as the frame rate increases, the amount of image data that must be transmitted per unit time increases.

Recently, as display panels have become more high-resolution, the number of pixels placed on the display panel and the frame rate are both increasing, and in order to process the increased amount of image data due to higher resolution, data communication in display devices is becoming faster.

One embodiment may provide a data processing device and a data driving device that encode and decode setup data, control data, and image data in different manners, respectively.

One embodiment can provide a data processing device and a data driving device that encode image data so that the maximum run length becomes constant.

One embodiment can provide a data processing device and a data driving device that encode control data to ensure transmission signal quality.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A data processing device according to one embodiment of the present invention comprises: a first data conversion unit which converts image data and control data; and a transmission unit which transmits the converted image data and control data, wherein the first data conversion unit comprises: a first packer which converts the image data into a first data packet; a second packer which converts the control data into a second data packet; a first encoder which encodes the first data packet with a first rule; and a second encoder which encodes the second data packet with a second rule which is different from the first rule.

The number of bits of the second data packet may be less than the number of bits of the first data packet.

The number of bits of the encoded second data packet and the number of bits of the encoded first data packet may be the same.

The above control data may include first control data and second control data, and the first control data may include a control value applied per line or pixel of the display panel, and the second control data may include a control value applied per frame.

The above data driving device can divide each frame time into an active period and a blank period, transmit the image data and the first control data in the active period, and transmit the second control data in the blank period.

The second data conversion unit may include a third packer for converting the configuration data into a third data packet; and a third encoder for encoding the third data packet with a third rule different from the first rule and the second rule.

The above transmission circuit can transmit the converted image data, control data, and setting data in a set order.

The first encoder may include a data comparison unit that compares a most significant bit (MSB) of an adjacent 1-1 data packet among a plurality of first data packets with a least significant bit (LSB) of a 1-2 data packet; a code conversion unit that inverts the least significant bit of the 1-2 data packet when the most significant bit of the 1-1 data packet and the least significant bit of the 1-2 data packet have the same value; and a bit generation unit that generates an indicator packet in which conversion information of the least significant bit of the 1-2 data packet is stored.

The method may further include a data group generation unit that generates a plurality of data groups by inserting the indicator packet into the plurality of first data packets.

Each of the above multiple data groups may have the same number of packets, and the number of bits of the indicator packet may be the same as the number of data packets in the data group.

The second encoder can map each unit bit constituting the control data into a plurality of redundancy bits having the same value as the unit bit and a transition bit having a different value from the unit bit.

A data driving device according to one embodiment of the present invention comprises: a receiving circuit which receives first to third data packets; a third data conversion unit which converts the first data packet and the second data packet; and a fourth data conversion unit which converts the third data packet, wherein the third data conversion unit comprises: a first decoder which decodes the first data packet with a first rule; a second decoder which decodes the second data packet with a second rule different from the first rule; a first unpacker which converts the first data packet into image data; and a second unpacker which converts the second data packet into control data, wherein the fourth data conversion unit comprises: a third decoder which decodes the third data packet with a third rule different from the first and second rules; and a third unpacker which converts the third data packet into setting data.

According to an embodiment, transmission of control data according to video timing, such as horizontal lines or vertical blanks, may be supported.

According to an embodiment, two or more data coding techniques with clock embedding applied can be applied. Control data has the advantage of ensuring transmission signal quality, thereby omitting data checkers such as CRC and Checksum. Image data has the advantage of securing a regular run-length and easily enabling clock embedding.

In some embodiments, EMI can be reduced by scrambling image data.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Figure 1 is a configuration diagram of a display device according to one embodiment of the present invention.

FIG. 2 is a diagram showing main communication and auxiliary communication between a data processing device and a data driving device according to one embodiment of the present invention.

Figure 3 is a configuration diagram of a data processing device according to one embodiment of the present invention.

FIG. 4 is a configuration diagram of a scrambler according to one embodiment of the present invention.

Figure 5 is a configuration diagram of a first encoder according to one embodiment of the present invention.

Figure 6 is a configuration diagram of a second encoder according to one embodiment of the present invention.

Figure 7 is a configuration diagram of a data processing device according to another embodiment of the present invention.

FIG. 8 is a diagram showing a sequence of a transmission signal according to one embodiment of the present invention.

Figure 9 is a configuration diagram of blank data and line data according to one embodiment of the present invention.

FIG. 10 is a diagram showing bits of a plurality of packets according to one embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of a data packet of a first horizontal line according to one embodiment of the present invention.

FIG. 12 is a diagram showing a data packet including dummy data according to one embodiment of the present invention.

FIG. 13 is a diagram showing an image data structure according to one embodiment of the present invention.

Figure 14 is a flowchart showing an image data encoding step according to one embodiment of the present invention.

FIG. 15 is a diagram illustrating a method for encoding image data according to one embodiment of the present invention.

FIG. 16 is a diagram showing a decoding process according to one embodiment of the present invention.

FIG. 17 is a diagram showing a process of encoding control data according to one embodiment of the present invention.

FIG. 18 is a diagram showing a process of encoding control data according to another embodiment of the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated in the drawings. The same reference numerals throughout the specification refer to substantially the same components. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The following embodiments may be partially or wholly combined or combined with each other, and may be technically capable of various interconnections and operations. Each embodiment may be implemented independently of each other, or may be implemented together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 1 is a configuration diagram of a display device according to one embodiment.

Referring to FIG. 1, the display device (100) may include a data processing device (110), a data driving device (120), a display panel (130), and a gate driving device (140).

The data processing device (110) can receive image data from another device. The other device is a device that generates image data and may be a host.

The data processing device (110) can process image data received from another device to be suitable for the data driving device (120) and transmit the processed image data to the data driving device (120). The data processing device (110) can perform digital gamma correction processing on the grayscale value of each pixel included in the image data, or can perform compensation processing to suit the characteristics of each pixel.

The data driving device (120) can receive image data from the data processing device (110), generate a data voltage (VD) according to the grayscale value of a pixel included in the image data, and supply the data voltage (VD) to the pixel (P).

A plurality of pixels (P) may be arranged on the display panel (130). In addition, each pixel (P) may be connected to a data driving device (120) through a data line (DL) and to a gate driving device (140) through a gate line (GL).

The display panel (130) may be a panel of a flat panel display device such as a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display (OLED), or a non-organic light emitting display (Non-Organic Light Emitting Display).

A transistor may be arranged in each pixel (P), and a gate terminal of the transistor may be connected to a gate line (GL), and a source terminal may be connected to a data line (DL). When a gate driving device (140) supplies a scan signal (SCN) to the gate line (GL), the transistor is turned on and the data line (DL) is connected to the pixel (P). After the data line (DL) is connected to the pixel (P), a data voltage (VD) supplied by the data driving device (120) is transmitted to the pixel (P).

To synchronize the timing of the gate driving device (140) and the data driving device (120), the data processing device (110) can transmit a timing control signal to the gate driving device (140) and the data driving device (120).

The data processing device (110) can transmit a gate control signal to the gate driving device (140). The gate control signal can include the aforementioned timing control signal. The gate driving device (140) can generate a scan signal (SCN) according to the gate control signal and supply the scan signal (SCN) to the pixel (P) through the gate line (GL).

At least two types of communication lines (CLM, CLA) may be arranged between the data processing device (110) and the data driving device (120). The data processing device (110) may transmit a first communication signal (MDT) through the first communication line (CLM) and transmit or receive a second communication signal (LCK) through the second communication line (CLA).

Hereinafter, for convenience of explanation, the first communication line (CLM) may be defined as a main communication line, and the second communication line (CLA) may be defined as an auxiliary communication line. In addition, the first communication signal (MDT) may be defined as a main communication signal, and the second communication signal (LCK) may be defined as an auxiliary communication signal.

The data processing device (110) can transmit image data and a timing control signal to the data driving device (120) through a main communication signal (MDT), and the data driving device (120) can transmit status information to the data processing device (110) through an auxiliary communication signal (LCK).

FIG. 2 is a diagram showing main communication and auxiliary communication between a data processing device and a data driving device according to one embodiment.

Referring to FIG. 2, the data driving device (120) may be composed of a plurality of data driving integrated circuits (120a, 120b, 120c, 120d).

The data processing device (110) can communicate with a plurality of data-driven integrated circuits (120a, 120b, 120c, 120d) via main communication lines (CLM). The data processing device (110) can be connected one-to-one with each data-driven integrated circuit (120a, 120b, 120c, 120d). For example, the data processing device (110) can be connected one-to-one with a first data-driven integrated circuit (120a) and one-to-one with a second data-driven integrated circuit (120b).

Each main communication line (CLM) can be composed of m (m is a natural number) electrically isolated lines. In addition, the m lines can be paired in pairs, and each pair can enable LVDS (Low Voltage Differential Signaling) communication.

The main communication signal (see MDT of Fig. 1) transmitted and received between this communication connection structure and the data processing device (110) and the plurality of data drive integrated circuits (120a, 120b, 120c, 120d) can be defined as the main communication.

A data processing device (110) and a plurality of data driving integrated circuits (120a, 120b, 120c, 120d) can transmit and receive information through auxiliary communication in addition to main communication.

Auxiliary communications between multiple data-driven integrated circuits (120a, 120b, 120c, 120d) can be connected in a cascade form. For example, a first data-driven integrated circuit (120a) arranged at the beginning of the cascade can transmit a first auxiliary communication signal (LCKa) to a second data-driven integrated circuit (120b) via a first auxiliary communication line (CLAa).

The second data driving integrated circuit (120b) can generate a second auxiliary communication signal (LCKb) by combining a status signal generated internally and a first auxiliary communication signal (LCKa) and transmit it to the fourth data driving integrated circuit (120c) through the second auxiliary communication line (CLAb).

The fourth data driving integrated circuit (120c) can generate a fourth auxiliary communication signal (LCKc) by combining an internally generated status signal and a second auxiliary communication signal (LCKb) and transmit it to the fourth data driving integrated circuit (120d) through the fourth auxiliary communication line (CLAc).

The fourth data driving integrated circuit (120d) arranged at the end of the cascade can generate a fourth auxiliary communication signal (LCKd) by combining an internally generated status signal and a fourth auxiliary communication signal (LCKc) and transmit it to the data processing device (110) through the fourth auxiliary communication line (CLAd). Here, the fourth data driving integrated circuit (120d) arranged at the end of the cascade transmits the auxiliary communication signal to the data processing device (110) through auxiliary communication.

The data processing device (110) can check the status of the data driving integrated circuits (120a, 120b, 120c, 120d) based on an auxiliary communication signal received from the fourth data driving integrated circuit (120d) located at the end of the cascade.

The data processing device (110) can transmit an auxiliary communication feedback signal for an auxiliary communication signal to the first data driving integrated circuit (120a) arranged at the beginning of the cascade through an auxiliary communication feedback line (CLAF). For example, the data processing device (110) can generate an auxiliary communication feedback signal in the same form as an auxiliary communication signal received from the fourth data driving integrated circuit (120d) and transmit the auxiliary communication feedback signal to the first data driving integrated circuit (120a). However, the embodiments of the present invention are not limited thereto. For example, the auxiliary communication feedback line (CLAF) can be omitted, and a driving voltage (VCC) and a pull-up resistor can be connected to the receiving unit of the first data driving integrated circuit (120a). For example, a plurality of data-driven integrated circuits (120a, 120b, 120c, 120d) may be connected to a data processing device (110) in a multi-drop manner.

FIG. 3 is a configuration diagram of a data processing device and a data driving device according to one embodiment. FIG. 4 is a configuration diagram of a scrambler according to one embodiment of the present invention.

Referring to FIG. 3, the data processing device (110) may include a first main communication circuit (410) and a first auxiliary communication circuit (420), and the data driving device (120) may include a second main communication circuit (610) and a second auxiliary communication circuit (620). The first main communication circuit (410) may communicate with the second main communication circuit (610), and the first auxiliary communication circuit (420) may communicate with the second auxiliary communication circuit (620).

The first main communication circuit (410) can transmit a main communication signal (MDT) to the data driving device (120) through the main communication line (CLM). The first main communication circuit (410) can transmit image data and first control data in the active section and transmit second control data in the blank section through the main communication line (CLM).

The data driving device (120) can drive pixels of the display panel according to image data. The first control data can include a control value applied per line or per pixel of the display panel, and the second control data can include a control value applied in a longer cycle than per line or per pixel or a control value applied per frame.

The first main communication circuit (410) can transmit setup data at a first data rate through the main communication line (CLM). Thereafter, the first main communication circuit (410) can transmit image data, first control data, and second control data at a second data rate higher than the first data rate through the main communication line (CLM). A mode for performing communication at the first data rate can be defined as a low-speed communication mode, and a mode for performing communication at the second data rate can be defined as a high-speed communication mode.

The first main communication circuit (410) can receive image data, control data, and setting data, and can convert and output the received image data, control data, and setting data according to different rules. The first main communication circuit (410) can include a first data conversion unit (411) that converts image data and control data, and a second data conversion unit (412) that converts setting data. The first data conversion unit (411) and the second data conversion unit (412) can be defined as a first data conversion circuit and a second data conversion circuit, respectively.

The first data conversion unit (411) can receive image data and control data, and convert and output the received image data and control data according to different rules. The first data conversion unit (411) can include a first packer (413A), a second packer (413B), a scrambler (414), a first encoder (415A), and a second encoder (415B).

The first packer (413A) can receive image data from a data processing circuit (10). The data processing circuit may be an external host or an AP (Application Processor), but embodiments of the present invention are not limited thereto. For example, the data processing circuit may be a part of a data processing device (110) that receives data from a host.

The first packer (413A) and the second packer (413B) are each connected to the data processing circuit (10) through separate lines and can receive data independently. The data processing circuit (10) can transmit data to the first packer (413A) and/or the second packer (413B) according to a predetermined time line. However, the embodiments of the present invention are not limited thereto. The first packer (413A) and the second packer (413B) are each connected to the data processing circuit (10) through a single line and can receive data according to a predetermined time line.

The first packer (413A) receives image data in a continuous bit stream format from the data processing circuit (10) and generates an image packet having a preset number of bits, and the second packer (413B) receives first control data and/or second control data from the data processing circuit (10) and generates a control packet having a preset number of bits. The image packet may be referred to as a first data packet, an image data packet, an image packet data, etc., and the control packet may be referred to as a second data packet, a control data packet, a control packet data, etc.

The video packets packaged by the first packer (413A) and the control packets packaged by the second packer (413B) may have different numbers of bits. For example, one video packet may be packaged with 12 bits, while one control packet may be packaged with 3 or 4 bits. However, embodiments of the present invention are not limited thereto. For example, the bits of the video packets and the control packets may be packaged with the same number of bits.

The scrambler (414) can scramble data of a video packet. Scrambling is a process of mixing each bit of data to be transmitted, and can prevent the same bit from being arranged consecutively K times or more (K is a natural number greater than or equal to 2) in the transmission stream of data. Scrambling is performed according to a previously agreed upon rule, and according to the previously agreed upon rule, the data driving device (120) can restore the stream in which each bit is mixed back to the original data.

Referring to FIG. 4, the scrambler (414) may include a 12-bit linear feedback shift register (LFSR) configured as a polynomial of G(x) = X ¹² + X ⁶ + X ⁴ + X ¹ + 1, a logic circuit (414B), and an arithmetic circuit (414C). After power is turned on, the initial seed value of the linear feedback shift register (414A) is 12'hFFF, and the linear feedback shift registers (LFSRs) of the scrambler (414) and the descrambler (614) may be initialized to the seed value by SCR_RST. Afterwards, when SCR_EN is input to the logic circuit (414B) as "H", the linear feedback shift register (414A) is processed, and the value of the linear feedback shift register (414A) and the image data are subjected to an exclusive OR (XOR) operation by the operation circuit (414C) to output scrambled data. Control signals such as SCR_RST and SCR_EN can be set to the control data of the display mode.

The scrambler (414) may scramble only the image data and may not apply scrambling to the first control data or the second control data. However, the present invention is not limited thereto. For example, the scrambler (414) may scramble blank data to more effectively reduce EMI.

Fig. 5 is a configuration diagram of a first encoder according to one embodiment of the present invention. Fig. 6 is a configuration diagram of a second encoder according to one embodiment of the present invention. Fig. 7 is a configuration diagram of a data processing device according to another embodiment of the present invention.

Referring to FIG. 5, the first encoder (415A) may include a data comparison unit (521), a bit generation unit (522), a code conversion unit (523), and a data group generation unit (524).

The data comparison unit (521) can compare the most significant bit (MSB) of the neighboring first video packet with the least significant bit (LSB) of the second video packet. The first video packet may be a previous video data packet transmitted to the encoder immediately before, and the second video packet may be a current video data packet, but the embodiments of the present invention are not limited thereto. For example, the data comparison unit (521) may simultaneously input a plurality of video data packets stored in a frame memory and compare bits of packet boundaries. The first video packet may be referred to as the 1-1 data packet, and the second video packet may be referred to as the 1-2 data packet.

The data comparison unit (521) can output an inverted signal if the most significant bit of the neighboring first image packet and the least significant bit of the second image packet are the same, and can output a non-inverted signal if the most significant bit of the first image packet and the least significant bit of the second image packet are different. The fact that the bits are the same may mean that the bit values have the same value of 0 or 1. In addition, the fact that the bits are different may mean that the bit values have different values of 0 or 1.

The data comparison unit (521) can perform an exclusive OR (XOR) operation. The data comparison unit (521) can output an inverted signal 0 when the most significant bit of the first image packet and the least significant bit of the second image packet are both 0 or both 1.

The data comparison unit (521) can output a non-inverted signal 1 when the most significant bit of the first image packet is 1 and the least significant bit of the second image packet is 0, or when the most significant bit of the first image packet is 0 and the least significant bit of the second image packet is 1.

The bit generation unit (522) can generate an indicator packet and receive an inverted signal or a non-inverted signal output from the data comparison unit (521) to map conversion information of the corresponding bit to the indicator packet. The conversion information can be an inverted signal or a non-inverted signal output from the data comparison unit (521). For example, if the conversion information is input as 1, the decoder does not invert the corresponding bit, and if the conversion information is input as 0, the decoder can invert the corresponding bit.

The code conversion unit (523) can invert or non-invert the least significant bit of the video packet according to the inverted signal or the non-inverted signal. However, the embodiments of the present invention are not limited thereto. For example, the most significant bit of the first video packet and the least significant bit of the second video packet may be compared, and if the bits are the same, the most significant bit of the first video packet may be inverted. According to an embodiment, two neighboring video packets may be compared, and if the neighboring bits at the packet boundary have the same value, one of the neighboring bits may be inverted to generate a clock edge.

According to an embodiment, the least significant bit of a video packet may have a different value from the most significant bit of an adjacent video packet. Since the bits at the boundary of each video packet have different values, a clock edge may be generated at the boundary of the packet. Accordingly, the set maximum run length may be secured.

For example, if the set maximum run length is 3UI, and the bit of the first video packet is [0100] and the bit of the second video packet is [0000], the two video packets may exceed the maximum run length of 3UI since 0 is consecutive 6 times. However, according to the embodiment, since the least significant bit of the second video packet is inverted from 0 to 1, the bit of the second video packet may be encoded as [1000]. Accordingly, the bits change at the boundary between the first video packet and the second video packet, generating a clock edge, so that the maximum run length can be satisfied.

The data group generation unit (524) can generate a data group having N packets by inserting one indicator packet into N-1 (N is a natural number) video packets. According to an embodiment, one data group can have N packets, and each packet can have N bits. That is, one data group can have the same number of packets and bits. Therefore, effective clock recovery can be enabled in the receiver (200).

Referring to FIG. 6, the second encoder (415B) may include a first bit generation unit (531) that generates a plurality of redundancy bits identical to the unit bit for each unit bit of an input control packet, and a second bit generation unit (532) that generates an inversion bit of the unit bit. The first bit generation unit (531) may generate a plurality of redundancy data having the same value as the value of the unit bit.

For example, if the value of the unit bit is 1, the first bit generation unit (531) can generate three redundancy bits whose bit values are 1. For example, if the unit bit is 0, the first bit generation unit (531) can generate three bits whose values are 0. In the encoded redundancy bits, the middle bit can be a valid bit having information. However, the number of bits generated by the first bit generation unit (531) is not limited thereto. For example, the first bit generation unit (531) can also generate two redundancy bits.

The second bit generation unit (532) can insert a unit bit and an inverted transition bit. For example, if the unit bit is 1, the second bit generation unit (532) can generate a transition bit having a value of 0. For example, if the bit value of the unit bit is 0, the second bit generation unit (532) can generate a transition bit having a bit value of 1.

Accordingly, if the bit of the control packet is [110] consisting of three unit bits, the bit encoded by the second encoder (415B) may be [111011100001], and if the bit of the control packet is [1101], the encoded bit may be [110110001110]. When the data driving device samples each bit for data and clock recovery, a bit error may occur, but according to the embodiment, since a sampling margin can be secured by the redundancy bit, the bit error can be reduced. Therefore, a configuration for detecting an error, such as a CRC or checksum for checking for an error, can be omitted.

The coding technique of the second encoding can be defined as TC (Transition code) coding, but is not limited thereto and may be defined by other names.

Referring again to FIG. 3, the second data conversion unit (412) may include a third packer (413C) and a third encoder (415C). The third packer (413C) may receive setting data from the data processing circuit (10) and generate a setting packet according to a predetermined number of bits. The setting packet may be referred to as a third data packet, a setting data packet, a setting packet data, etc.

The setting data is data transmitted at a low speed and may include setting values of a data driving device (120) required before high-speed communication. For example, the setting data may include setting values of a circuit that performs high-speed communication in the data driving device (120).

The third encoder (415C) can encode the setup packet packaged by the third packer (413C) in a predetermined manner. The third encoder (415C) can encode the setup packet with a DC balanced code. For example, the third encoder (415C) can encode the setup packet with a Manchester code or an 8B10B code, but embodiments of the present invention are not limited thereto.

The first data output circuit (416) can receive data packets from the first encoder (415A), the second encoder (415B), and the third encoder (415C), respectively, and transmit data appropriate to the mode to the serializer (417). For example, the first data output circuit (416) can transmit setting data to the serializer (417) in the setting mode, and can transmit image data and control data to the serializer (417) in the display mode.

Data transmitted in parallel from the first data output circuit (416) can be converted serially by the serializer (417). The serializer (417) can transmit the serially converted transmission data to the data driving device (120). At this time, a series of data transmitted serially can form a transmission stream and can be in the form of a main communication signal (MDT) in terms of signal. The first data output circuit (416) and the serializer (417) can constitute a transmission unit. The transmission unit can be called a transmission circuit or a transmission logic, etc.

According to an embodiment, even the setting data transmitted at a low speed can be transmitted using a high-speed serializer (417). Therefore, a separate low-speed serializer can be omitted. At this time, the transmission data can be varied so that it can be transmitted at a low speed substantially even when the serializer (417) is driven at a high speed. For example, when transmitting bit [10], the bit is increased to [1111111111000000000] and transmitted, so that it is transmitted at a high speed, but the actual data transmission speed can be adjusted to be driven at a low speed.

However, embodiments of the present invention are not limited thereto. For example, the setting data transmitted from the third encoder (415C) in the first data output circuit (416) may be synchronized to a high-speed frequency based on the second data rate or the frequency of the image packet and transmitted to the serializer (417). The serializer (417) may serialize the received setting data and transmit it at the second data rate.

For example, it can be assumed that the setting data output from the third encoder (415C) is 12 bits, the output of the first data output circuit (416) is 12 bits, and the second data rate is 12 times faster than the first data rate. At this time, the first data output circuit (416) can transmit the 1 clock output data of the third encoder (415C) to the serializer (417) for 12 clocks as a high-speed packet clock. At this time, the data of 1 clock as a high-speed packet clock is transmitted by increasing 1 bit of the setting data output from the third encoder (415C) to the same 12 bits, and can output 1 bit per clock. According to this configuration, high-speed transmission is possible in the transmitter without configuring a separate low-speed serializer, and the transmission speed on the first communication line (CLM) can be transmitted at the second data rate.

For example, the setting data encoded by the second data conversion unit (412) may be transmitted to the main communication line (CLM) by a separately provided low-speed serializer.

The main communication line (CLM) can be composed of m (m is a natural number) electrically insulated lines. In addition, the m lines can be paired by two, and each pair can enable LVDS (Low Voltage Differential Signaling) communication. When the main communication line (CLM) includes two or more pairs, the serializer (417) can distribute transmission data to each pair and transmit it.

Transmission data is composed of bits, and multiple bits can constitute one symbol. One symbol can be composed of 6 bits, 8 bits, or 10 bits. In addition, multiple symbols can constitute one image data. The image data can sequentially include information corresponding to sub-pixels such as R (Red), G (Green), and B (Blue). The data driving device (120) can align data received serially in bit units into byte units or pixel units.

The main communication signal may be an embedded clock signal. Since the main communication signal has an embedded clock, the data drive device (120) may require clock training in the initial section of the communication.

The data processing device (110) includes a first auxiliary communication circuit (420), and the first auxiliary communication circuit (420) may include a first auxiliary control circuit (421) and a first auxiliary signal processing circuit (422).

The first auxiliary signal processing circuit (422) can receive an auxiliary communication signal (LCK) from an auxiliary communication line (CLA) or transmit an auxiliary communication signal (LCK) to the auxiliary communication line (CLA).

The first auxiliary control circuit (421) can check an auxiliary communication signal (LCK) received from an auxiliary communication line (CLA), and if the auxiliary communication signal (LCK) indicates an abnormality in the data driving device (120), can transmit an auxiliary communication feedback signal of the same form as the auxiliary communication signal (LCK) to the auxiliary communication line (CLA).

The data drive device (120) may include a second main communication circuit (610) and a second auxiliary communication circuit (620).

The second main communication circuit (610) can receive a main communication signal (MDT) through the main communication line (CLM). The second main communication circuit (610) can receive image data and first control data in the active section and can receive second control data in the blank section through the main communication line (CLM). The data driving circuit (20) can drive pixels of the display panel according to the image data and control data.

The second main communication circuit (610) can receive setup data at a first data rate through the main communication line (CLM). In addition, the second main communication circuit (610) can receive image data, first control data, and second control data at a second data rate higher than the first data rate through the main communication line (CLM).

The second main communication circuit (610) may include a deserializer (617), a second data output circuit (616), a third data conversion unit (611), and a fourth data conversion unit (612). The deserializer (617) and the second data output circuit (616) may constitute a receiving unit or receiving circuit.

The deserializer (617) can parallelize the main communication signal (MDT) received serially through the main communication line (CLM) into byte units or symbol units.

The second data output circuit (616) can transmit parallel data converted by the deserializer (617) to the third data conversion unit (611) and the fourth data conversion unit (612) according to the mode. For example, in the case of the setting mode, the setting data can be transmitted to the third decoder (615C), and in the case of the display mode, the image data can be transmitted to the first decoder (615A) or the control data can be transmitted to the second decoder (615B).

The third data conversion unit (611) may include a first decoder (615A), a second decoder (615B), a descrambler (614), a first unpacker (613A), and a second unpacker (613B).

The first decoder (615A) can decode image data, and the second decoder (615B) can decode control data. The first decoder (615A) can perform decoding in the reverse order in which the first encoder (415A) encoded the image data. The second decoder (615B) can perform decoding in the reverse order in which the second encoder (415B) encoded the control data. For example, the second decoder (615B) can extract only the second bit out of four bits from each control packet and delete the remaining bits. For example, if the bits of the control packet are [111011100001], only the second bit out of four bits can be extracted and decoded into [110].

The descrambler (614) can restore scrambled data to its original state according to a pre-agreed rule. The descrambler (614) can restore scrambled data by being synchronized with the scrambler (414).

The first unpacker (613A) can align image data on a pixel-by-pixel basis and transmit image data for each pixel to the data driving circuit (20). The second unpacker (613B) can restore control data to its original form and transmit it to the data driving circuit (20).

The fourth data conversion unit (612) may include a third decoder (615C) and a third unpacker (613C). The third decoder (615C) may restore setting data encoded with a Manchester code. The third unpacker (613C) may receive setting data and transmit setting values included in the setting data to a data driving circuit.

The second auxiliary communication circuit (620) may include a second auxiliary control circuit (621) and a second auxiliary signal processing circuit (622).

The second auxiliary control circuit (621) can check for an abnormal state of the main communication signal (MDT), an abnormal state of the main communication circuit, and/or an abnormal state of another configuration, and generate a status signal.

The second auxiliary signal processing circuit (622) can generate an auxiliary communication signal (LCK) using a status signal or a feedback signal and transmit the auxiliary communication signal (LCK) to an auxiliary communication line (CLA).

The data driving device (120) according to the embodiment may include a main control circuit (430). The main control circuit (430) may receive a control signal from the data processing circuit (10) and control the first data conversion unit (411), the second data conversion unit (412), the first data output circuit (416), etc. However, the embodiments of the present invention are not limited thereto. For example, as shown in FIG. 7, when the role of each block is terminated without configuring a separate main control circuit of the data driving device (120), the data driving device (120) may be configured to transmit a signal to a block to perform the function next according to the logic so as to perform the function. In the case of an interface without a low-speed driving setting mode, the configuration of the second data conversion unit (412) in the data driving device (120) may be omitted.

FIG. 8 is a diagram showing a sequence of main signals according to one embodiment. FIG. 9 is a diagram showing a configuration of blank data and line data according to one embodiment of the present invention. FIG. 10 is a diagram showing bits of a plurality of packets according to one embodiment of the present invention.

Referring to FIGS. 8 to 10, the driving voltage (VCC) initially has a low-level voltage and may change its waveform to a high-level voltage at a certain point in time. The point in time when the driving voltage (VCC) changes to a high-level voltage may be the driving point of the display driving device.

After the driving time, the data processing device (110) and the data driving device (120) can operate in the setting mode (CFG mode, T101). After the operation in the setting mode (T101) is completed, the data processing device (110) and the data driving device (120) can operate in the display mode (T102).

In the setup mode (T101), the data processing device (110) can continuously transmit a preamble packet (P710) and a setup packet (P720) through the main communication signal (MDT).

The data processing device (110) can change the voltage of the auxiliary communication feedback signal from a low level to a high level while sending the preamble packet (P710). Through this voltage change, the data processing device (110) can notify the data driving devices (120) that the preamble packet (P710) is being transmitted.

The data driving device (120) can train a low-speed communication clock for receiving a setup packet (P720) using a preamble packet (P710) composed of a clock training pattern. The data driving device (120) can perform phase locking to the preamble pattern within the T _{CFG_LOCK} time during which training is completed.

The data processing device (110) can transmit a preamble packet (P710) and a setup packet (P720) at a relatively low first data rate. The clock for low-speed communication becomes the first data rate, and the data driving device (120) can train the clock for low-speed communication using the preamble packet (P710).

When the clock for low-speed communication is trained, the data driving device (120) can inform the data processing device (110) of the clock training status through an auxiliary communication signal. For example, when the clock for low-speed communication is trained, the data driving device (120) can change the voltage of the auxiliary communication signal from a low level to a high level. After confirming that the data driving device (120) has trained the clock for low-speed communication through the auxiliary communication signal, the data processing device (110) can transmit a setup packet (P720).

A setup packet (P720) may consist of a start bit (CFGS, P721), a header (P722), body data (P723), and an end bit (CFGE, P724). It may further include checksum data as needed.

The header (P722) may include parameter values such as data type, mode, recipient's identification number (ID: identification), data length, and recipient's setting register address. The body data (P723) may include setting information transmitted and received via the message.

The start bit (P721) and the end bit (P724) may be composed of different data bits. For example, if the start bit (P721) is a data bit corresponding to binary "0", the end bit (P724) may be composed of a data bit corresponding to binary "1".

The data driving device (120) may determine that the setting mode (T101) is terminated and enter the display mode (T102) when the first communication signal (MDT) is maintained at a voltage level that can be recognized as a binary number “0” or “1” after recognizing the end bit (P724) through the first communication signal (MDT). However, the embodiments of the present invention are not limited thereto. Even when the voltage level is not a level that can be recognized as a binary number “0” or “1” but a high or low level, the setting mode may be determined to be terminated.

After the setup mode (T101) is terminated, the data processing device (110) and the data driving device (120) can enter the display mode (T102). The display mode (T102) can be composed of a clock training period (T103) and a frame period (T104). When the high-speed communication clock (P730) is trained in the clock training period (T103), the frame period (T104) appears repeatedly thereafter.

In the clock training section (T103), the data processing device (110) can transmit a clock training pattern (P730) to the data driving device (120) at a second data rate. The data driving device (120) can train a high-speed communication clock corresponding to the second data rate to the clock training pattern (P730). Here, the second data rate can have a higher frequency than the first data rate.

If the data driving device (120) fails to train the clock for high-speed communication in the clock training section (T103), the data driving device (120) can transmit a clock training failure signal through an auxiliary communication signal. For example, the data driving device (120) can notify the data processing device (110) of the clock training failure by lowering the voltage of the auxiliary communication signal from a high level to a low level.

If clock training for a clock for high-speed communication fails, the data processing device (110) may additionally transmit an additional clock training pattern or return to the setup mode (T101).

When clock training for the clock for high-speed communication is completed, the data processing unit (110) and the data driving unit (120) can enter the frame period (T104).

The frame section (T104) may include an active section (T106) and a blank section (T105). The active section (T106) may be a section in which image data and control data are transmitted in units of lines, and the blank section (T105) may be a section in which image data in units of lines is not transmitted. The blank section (T105) may be divided into a horizontal blank section and a vertical blank section. For convenience of explanation, the blank section (T105) is described below as a vertical blank section.

In the blank period (T105), the data processing device (110) can transmit a frame control packet (P740) in line units. The frame control packet (P740) can include a control start packet (CS, P741), a frame start packet (FPS, P742), and a frame data packet (FC data, P743).

The control start packet (P741) can indicate the start of a control packet. The frame start packet (P742) can indicate the start of transmission of frame data. Accordingly, it is possible to distinguish whether the data to be transmitted after the control start signal is frame data or line data.

Referring to Fig. 10, the bits of the control start packet (P741) may be [110011110000] from MSB to LSB, and the bits of the frame start packet (P742) may be [001111001100], but are not limited thereto and various other patterns are possible. TC coding or scrambling may not be applied to the control start packet (P741) and the frame start packet (P742).

The frame data packet (P743) may include setting values that change on a frame basis or do not change frequently. The frame clock training pattern may include a pattern signal that can train a clock for high-speed communication. According to an embodiment, the frame control packet (P740) and the frame clock training pattern may not be scrambled. However, the embodiments of the present invention are not limited thereto. For example, the frame control packet (P740) may not be scrambled, and the frame clock training pattern (P744), which is blank data, may be scrambled to reduce EMI.

In the blank period (T105), the data processing device (110) may enter the active period (T106) after transmitting blank data packets for all lines. According to an embodiment, the blank data may include information on dummy data included in the image data. For example, by adding a dummy control signal that can recognize a dummy line, the data processing device (110) may distinguish whether the corresponding pixel data is valid pixel data or dummy data generated to satisfy 12 bits. That is, in the vertical blank, a frame control packet (P740), a dummy control packet, and clock training may be transmitted in combination.

In the active section (T106), the data processing device (110) can transmit a line control packet (P750), a video packet (P760), and a line clock training pattern (P754) for each line.

The line control packet (P750) may be composed of a control start packet (P751), a line start packet (P752), and a line data packet (P753). The control start packet (P751) may indicate the start of the line control packet (P750), and the line start packet (P752) may indicate the start of transmission of line data. For example, the bit of the start packet may be [110011110000], and the bit of the line start packet (P752) may be [110000111100], but is not limited thereto, and various other patterns are possible. Scrambling may not be applied to the control start packet (P751) and the line start packet (P752).

The line data packet (P753) may include setting values that may be changed on a line-by-line basis or may be changed at any time. For example, the line data packet (P753) may include a polarity value indicating the polarity of each pixel, a value indicating whether the scrambler (414) is reset, and control information regarding whether the corresponding image data is valid data or dummy data.

The image packet (P760) may include grayscale values of pixels arranged in one line. The line clock training pattern (P754) may include a pattern signal capable of training a clock for high-speed communication.

In the active section (T106), the data processing device (110) can enter the blank section (T105) again after transmitting a line control packet (P750) for all lines.

Fig. 11 is a diagram showing a configuration of a data packet of a first horizontal line according to one embodiment of the present invention. Fig. 12 is a diagram showing a data packet including dummy data according to one embodiment of the present invention.

Referring to FIG. 11, a data packet of a first horizontal line may include a line control packet (P750), a plurality of data groups including grayscale values of pixels arranged in one line, and a clock training pattern.

One data group can be composed of a total of N packets, including one indicator packet and N-1 image packets (Packet 1 to Packet (n-1)). FIG. 11 illustrates an example in which one data group is composed of 12 packets. An image packet can be defined as effective data as RGB image data, but embodiments of the present invention are not limited thereto. As shown in FIG. 12, when RGB data is insufficient in the last data group of 1-Line, a packet can be generated by mapping a dummy bit. As described above, information on whether the image data of the corresponding line is effective image data or dummy data can be stored in the blank data or line data.

FIG. 13 is a diagram showing an image data structure according to one embodiment of the present invention. FIG. 14 is a flowchart showing an image data encoding step according to one embodiment of the present invention. FIG. 15 is a diagram showing an image data encoding method according to one embodiment of the present invention.

Referring to FIG. 13, an indicator packet (IDP) can have N bits (HD1, I1 to I(n-1), and HD2). The least significant bit (LSB) and the most significant bit (MSB) of the indicator packet (IDP) can be a clock bit (CK) or a dummy bit. Conversion information (BI) of each video packet can be mapped between the least significant bit (LSB) and the most significant bit (MSB) of the indicator packet. In an embodiment, the least significant bit can be the bit closest to the previous packet within each packet, and the most significant bit can be the bit closest to the next packet within each packet, but embodiments of the present invention are not limited thereto.

The least significant bit (LSB) of the indicator packet can be mapped to a different value from the most significant bit (B(n-1)) of the previous video packet. For example, if the last bit (B(n-1)) of the previous data group is 0, the least significant bit (LSB) of the indicator packet can be 1. For example, if the last bit (B(n-1)) of the previous data group is 1, the least significant bit (LSB) of the indicator packet can be 0. Therefore, a clock edge can be generated at the boundary between the previous data group and the current data group.

The most significant bit (MSB) of the indicator packet can be matched by inverting the value of the least significant bit (B0) of the first video packet (Packet 1) in the current data group. For example, if the least significant bit (B0) of the first video packet (Packet 1) in the current data group is 1, the most significant bit (MSB) of the indicator packet can be mapped to 0. For example, if the least significant bit (B0) of the first video packet (Packet 1) in the current data group is 0, the most significant bit (MSB) of the indicator packet can be mapped to 1. Therefore, since the clock edge occurs at the boundary between the indicator packet and the adjacent first video packet (Packet 1), the maximum run length can be satisfied.

Referring to FIGS. 5, 14, and 15, the comparing step may perform an exclusive OR (XOR) operation on the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the second image packet.

The data comparison unit (521) can output an inversion signal 0 when both the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the current image packet are 0 or 1.

The data comparison unit (521) can output a non-inverted signal 1 when the most significant bit (MSB) of the first image packet and the least significant bit (LSB) of the second image packet have different bit values.

For example, if the most significant bit (MSB) of the first image packet (Packet 1) is 1 and the least significant bit (LSB) of the second image packet is 1, the data comparison unit (521) can output an inversion signal 0 that inverts the least significant bit (LSB) of the second image packet because the bit values are the same.

The code conversion unit (523) can invert the least significant bit (LSB) of the second video packet and convert it to 0 (~B0) because the inversion signal 0 is output. The bit generation unit (522) can map the conversion information 0 to the I1 position of the indicator packet.

Thereafter, the data comparison unit (521) can compare the most significant bit (MSB) of the second video packet and the least significant bit (LSB) of the third video packet, and output an inverted signal if the bit values are the same. For example, the data comparison unit (521) can output a non-inverted signal 1 if the most significant bit (MSB) of the second video packet (Packet 2) is 1 and the least significant bit (LSB) of the third video packet (Packet 2) is 0 because the bit values are different. The third video packet can be referred to as the 1-3 data packet.

The code conversion unit (523) can keep (B0) the least significant bit (LSB) of the third image packet (Packet 3) as is without inverting it according to the non-inverted signal 1. The bit generation unit (522) can map the conversion information 1 to the I2 position of the indicator packet.

Likewise, the data comparison unit (521) can sequentially compare the most significant bit (MSB) of the previous video packet and the least significant bit (LSB) of the current video packet to output an inverted signal or a non-inverted signal.

The code conversion unit (523) can invert or non-invert the bit value of the least significant bit (LSB) of the current video packet according to the inverted or non-inverted signal. The bit generation unit (522) can sequentially map the conversion information (BI) to the corresponding bit position.

The least significant bit (LSB) of an indicator packet (IDP) can be mapped to 1 by reversing the bit value 0 of the most significant bit (MSB) of the previous video packet, and the most significant bit (MSB) of the indicator packet (IDP) can be mapped to 0 by reversing the bit value 1 of the least significant bit (LSB) of the first video packet (Packet 1) of the current data group.

The conversion information (BI) of the least significant bit (LSB) of the second to eleventh video packets (Packet 2 to Packet 11) can be sequentially mapped between the least significant bit (LSB) and the most significant bit (MSB) of the indicator packet (IDP).

According to an embodiment, the most significant bit (MSB) of the indicator packet is mapped to a different value from the least significant bit (LSB) of the first video packet (Packet 1), so that the least significant bit (LSB) of the first video packet (Packet 1) located closest to the indicator packet may not be encoded. In the data group, the least significant bits (LSBs) of the remaining 10 video packets excluding the first video packet (Packet 1) may be inverted or maintained by an XOR operation.

The data group may be composed of a total of 12 packets, for example, including one indicator packet and 11 video packets. The indicator packet and the video packet may each be composed of 12 bits. Therefore, the total number of bits in the data group may be 144 bits. However, the specification of the present invention is not limited thereto. For example, the data group may be composed of eight packets, including one indicator packet and seven video packets. If each packet is composed of 8 bits, the total number of bits in the data group may be 64 bits. According to an embodiment, since the number of packets and the number of bits in the packet are the same, the maximum run length can be maintained constant.

FIG. 16 is a diagram showing a decoding process according to one embodiment of the present invention.

Referring to FIG. 16, the decoder can separate the indicator packet and the video packet of the data group, and store the indicator packet and the video packet respectively. The decoder can invert or not invert the least significant bit of the video packet according to the conversion information (BI) of the indicator packet. The conversion information (BI) can be an indicator bit mapped to a bit position.

Since the bit information at position I1 in the conversion information (BI) is 0, the decoder can invert the least significant bit (LSB) of the second video packet (Packet 2) to 1.

Since the bit information at position I2 in the conversion information (BI) is 1, the decoder can keep the least significant bit (LSB) of the third video packet (Packet 3) as 0 by not inverting it.

Since the bit information at position I3 in the conversion information (BI) is 0, the least significant bit (LSB) of the fourth video packet (Packet 4) can be inverted to 0.

Since the bit information at position I10 in the conversion information (BI) is 1, the least significant bit (LSB) of the 11th video packet (Packet 11) can be kept as 0 by not inverting it.

The restored data information can be restored identically to the original data. According to an embodiment, there is an advantage in that separate memory for decoding is not required because decoding is performed using the conversion information stored in the indicator packet.

FIG. 17 is a diagram showing a process of encoding control data according to one embodiment of the present invention. FIG. 18 is a diagram showing a process of encoding control data according to another embodiment of the present invention.

Referring to FIG. 17, a control packet can be composed of three bits. The second encoder can map each bit of the input control packet to four bits. For example, if one control packet is composed of three unit bits, such as D0, D1, and D2, the second encoder can map the same three bits as the first unit bit D0 to redundancy bits (B0, B1, B2) and map D0 and the inverted bit (~D0) to the transition bit (B3). Similarly, the second unit bit D1 and the third unit bit D2 can be mapped to three redundancy bits (B4, B5, B6, B8, B9, B10) and one inverted transition bit (B7, B11).

For example, if the bit of the control packet is [101], the encoded bit can be [111000011110]. When packaged by the second packer, the number of bits of the control packet is less than the number of bits of the video packet, but after encoding, the number of bits per packet can all be the same as 12. Therefore, the control packet composed of 3 bits can be mapped to 12 bits by the second encoder to satisfy the 12-bit format. Therefore, all data transmitted from the data driving device can satisfy the 12-bit format.

Among the three redundancy bits in the encoded bits, the middle bit (B1, B5, B9) may be a valid bit having information. When sampling each bit, a bit error may occur, but according to the embodiment, since a sampling margin can be secured by the redundancy bit, the bit error can be reduced. Therefore, a configuration for detecting errors, such as CRC and checksum, for checking errors can be omitted.

Referring to FIG. 18, a control packet may be composed of four unit bits. The second encoder may map each bit of the input control packet to three bits. For example, if the control packet is composed of four bits in total, such as D0, D1, D2, and D3, the second encoder may map the same two bits for the first bit D0 to redundancy bits (B0, B1) and map one inverted bit to a transition bit (B2). Similarly, the second bit D1, the third bit D2, and the fourth bit D3 may be mapped to two non-inverted redundancy bits and one inverted transition bit.

For example, if the bit of the control packet is [1010], the encoded bit can be [110001110001]. Therefore, the control packet consisting of 4 bits can be mapped to 12 bits by the second encoder to satisfy the 12-bit format.

Since the contents of the specification described above in terms of the problem to be solved, the means for solving the problem, and the effect do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the contents of the specification.

Although the embodiments have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain it, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative and not restrictive in all respects.

Claims (12)

A first data conversion unit that converts image data and control data; and Includes a transmission unit that transmits the converted image data and control data, The above first data conversion unit, A first packer for converting the above image data into a first data packet; A second packer for converting the above control data into a second data packet; a first encoder for encoding the first data packet according to a first rule; and A data processing device comprising a second encoder for encoding the second data packet using a second rule different from the first rule. In the first paragraph, A data processing device, wherein the number of bits of the second data packet is less than the number of bits of the first data packet. In the second paragraph, A data processing device, wherein the number of bits of the encoded second data packet and the number of bits of the encoded first data packet are the same. In the first paragraph, The above control data includes first control data and second control data, A data processing device wherein the first control data includes a control value applied per line or pixel of the display panel, and the second control data includes a control value applied per frame. In the fourth paragraph, The above transmission unit, A data processing device that divides each frame time into an active period and a blank period, transmits the image data and the first control data in the active period, and transmits the second control data in the blank period. In the first paragraph, A third packer that converts the configuration data into a third data packet; and A data processing device comprising a second data conversion unit including a third encoder that encodes the third data packet using a third rule different from the first and second rules. In Article 6, The above transmission unit is a data processing device that transmits the converted image data, control data, and setting data in a set order. In the first paragraph, The above first encoder, A data comparison unit that compares the most significant bit (MSB) of an adjacent 1-1 data packet and the least significant bit (LSB) of the 1-2 data packet among a plurality of 1-1 data packets; A code conversion unit that inverts the least significant bit of the 1-2 data packet when the most significant bit of the 1-1 data packet and the least significant bit of the 1-2 data packet have the same value; and A data processing device including a bit generation unit for generating an indicator packet in which conversion information of the least significant bit of the first-second data packet is stored. In Article 8, A data processing device further comprising a data group generating unit that generates a plurality of data groups by inserting the indicator packet into the plurality of first data packets. In Article 9, Each of the above multiple data groups has the same number of packets, A data processing device, wherein the number of bits of the above indicator packet is equal to the number of data packets in the above data group. In the first paragraph, A data processing device in which the second encoder maps each unit bit constituting the control data into a plurality of redundancy bits having the same value as the unit bit and a transition bit having a different value from the unit bit. A receiving circuit for receiving the first data packet to the third data packet; A third data conversion unit that converts the first data packet and the second data packet; Including a fourth data conversion unit that converts the third data packet, The third data conversion unit above, A first decoder for decoding the first data packet according to a first rule; A second decoder for decoding the second data packet using a second rule different from the first rule; A first unpacker that converts the first data packet into image data; and Including a second unpacker that converts the second data packet into control data, The above fourth data conversion unit, a third decoder that decodes the third data packet using a third rule different from the first and second rules; and A data drive device comprising a third unpacker that converts the third data packet into setup data.

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