WO2025087574A1 - Method for a computing device with memristor and adc, and computing device - Google Patents

Abstract

The invention relates to a method with a computing device which comprises a circuit, wherein the circuit has an ohmic resistor (3), wherein the computing device comprises an analogue-digital converter (24) which can convert an output signal, generated by the circuit, into a digital value, the method comprising the following steps: the smallest possible and the largest possible output signal of the circuit are determined, the analogue-digital converter is adapted to the smallest possible and largest possible output value. The invention also relates to a computing device having a circuit which has an ohmic resistor (3), wherein the computing device comprises an analogue-digital converter (24) which can convert an output signal, generated by the circuit, into a digital value, wherein the analogue-digital converter (24) is adapted to the smallest possible and largest possible output signal of the circuit or can be adapted to the smallest possible and largest possible output signal of the circuit.

Description

Method for a computing device with memristor and ADC and computing device

Description

The invention relates to a method for a computing device having an ohmic resistor for performing a computing operation and an analog-to-digital converter (ADC) for digitizing the result of the computing operation. The invention relates to an electronic computing device having an ohmic resistor for performing a computing operation and an analog-to-digital converter for digitizing the result of the computing operation.

An analog electrical input signal can be applied to a circuit of the electronic computing device, which includes at least one ohmic resistor, for example with the aid of a digital-to-analog converter (DAC). The input signal can be an electrical voltage. Depending on the conductance of the ohmic resistor, an analog electrical output signal can be output by the circuit. Conductance refers to the inverse of the ohmic resistor. The output signal can be an electrical current. The output signal is a measure of the result of a performed arithmetic operation. The result of such arithmetic operation can be digitized using the analog-to-digital converter.

The ohmic resistor can be a memristor. The conductance of the memristor can depend on the electrical charge flowing through it. The conductance can also depend on the direction of the electrical current and can increase or decrease depending on the direction. The conductance of the memristor can therefore be adjusted and, consequently, programmed. Programming the memristor can be performed, for example, using a digital-to-analog converter. The digital-to-analog converter (DAC) can convert a digital value into an analog value or an analog signal.

An analog-to-digital converter can convert an analog signal into a digital value. One characteristic of an analog-to-digital converter is its linearity. In an analog-to-digital converter, the term "linearity" refers to the converter's ability to establish a linear relationship between its input signal and the digital output value. A linear conversion means that a change in the input value causes a proportional change in the digital output value. An ideal analog-to-digital converter would have a constant step between the digital values. However, in practice, small deviations can occur. The linearity of an analog-to-digital converter refers to the accuracy with which the analog-to-digital converter maintains the relationship between the analog input signal and the digital output value.

There are analog-to-digital converters with adjustable linearity. An analog-to-digital converter with adjustable linearity allows you to adjust the degree of linearity to achieve the desired accuracy and deviation.

An ADC with adjustable linearity typically has a control that allows for linearity adjustment. This can be a hardware- or software-based configuration option. By adjusting the linearity, the ADC can be tuned to different requirements or environments.

Adjustable linearity can be useful for correcting system-inherent nonlinearities or optimizing the signal-to-noise ratio (SNR). Fine-tuning linearity can improve the accuracy and reliability of the ADC to achieve a more precise digital representation of the input signal.

The present invention is based on the object of creating a powerful electronic computing device.

A method for solving the problem may comprise the features of the first claim. An electronic computing device may comprise the features of the dependent claim for solving the problem. Advantageous embodiments emerge from the dependent claims.

The method may include a computing device with a circuit. The circuit may have an ohmic resistor, such as a memristor. The computing device may include an analog-to-digital converter that can convert an output signal generated by the circuit into a digital value. The smallest and largest possible output signals of the circuit can be determined. The analog-to-digital converter can be adapted to the smallest and largest possible output values. To determine the smallest possible output signal, a minimum possible input signal can be applied to the circuit. The resulting output signal of the circuit is then determined. The output signal determined in this way is then the minimum possible output signal, i.e., the smallest possible output signal. A maximum possible input signal can be applied to the circuit. The resulting output signal of the circuit is determined. The output signal determined in this way is the maximum possible output signal, i.e., the largest possible output signal.

A signal can be an electrical voltage. A first signal can be an electrical voltage that differs from the electrical voltage of a second signal. The electrical voltages are then of different magnitudes. A signal can be an electrical current. A first signal can be an electrical current that differs from the electrical current of a second signal. The electrical currents of the two signals are then of different magnitudes.

For example, an electrical voltage can be provided as the input signal. An electrical current can be provided as the output signal.

For example, if the input signal is an electrical voltage, the minimum possible voltage may be the smallest voltage at which the circuit can be operated. The maximum possible voltage may be the largest voltage at which the circuit can be operated.

The input signal can be generated, for example, by a digital-to-analog converter. The minimum voltage that can be generated by the digital-to-analog converter can be the minimum possible input signal. The maximum voltage that can be generated by the digital-to-analog converter can be the maximum possible input signal.

The circuit with an ohmic resistor can also include a transistor. The circuit can be configured such that a voltage applied, for example, by a digital-to-analog converter is multiplied by the transistor by a value of the ohmic resistor. The output of the digital-to-analog converter can be connected to the gate terminal of the transistor. The ohmic resistor can be connected to the source terminal of the transistor. The result of the multiplication can be read out via the drain terminal of the transistor. Such a circuit is an example of a circuit that can be used to calculate, i.e., to perform a calculation operation.

The circuit can have at least two ohmic resistors. The circuit can be configured so that a voltage can be applied to each ohmic resistor as an input signal. The circuit can be configured so that, depending on the conductance of the first ohmic resistor, a first electrical current is generated when a first voltage is applied to the first ohmic resistor. The circuit can be configured so that, depending on the conductance of the second ohmic resistor, a second electrical current is generated when a second voltage is applied to the second ohmic resistor. The same can apply to other ohmic resistors in the circuit. In general, then, an xth electrical current depends on a conductance of an xth ohmic resistor when an xth voltage is applied to the xth ohmic resistor. The magnitude of the resulting electrical currents depends on the conductances of the ohmic resistors and the applied electrical voltages. The circuit can be configured so that the resulting currents are summed. The output signal can be the sum of these currents.

In such a circuit, the largest possible output signal can be determined by applying the maximum possible input signal to all ohmic resistors simultaneously. In such a circuit, the smallest possible output signal can be determined by applying the minimum possible input signal to each ohmic resistor.

The computing device can include an analog-to-digital converter with adjustable linearity. The adjustment of the analog-to-digital converter can consist of adjusting the linearity depending on the determined maximum and minimum output signals. For example, in the case of a flash ADC, its reference voltages can be adjusted. A flash ADC can be operated with a lowest and an highest reference voltage, for example, 0 V and 20 mV, in order to process signals between 0 V and 20 mV. Furthermore, the flash ADC can be operated with a predetermined number of additional intermediate reference voltages, for example, two additional reference voltages provided by voltage dividers. Using comparators, the flash ADC can compare an input signal with its reference voltages. to determine a digital result. Such an ADC can therefore resolve in 5 mV steps.

For example, the maximum possible signal was determined to be 16 mV. The upper reference voltage can be reduced from 20 mV to 16 mV. The ADC can now operate in 4 mV steps, thus improving resolution.

This type of adjustment can also be performed with other ADCs, such as a SAR ADC.

This also applies when the signals to be digitized are in the form of electrical currents. For example, a SAR ADC can process currents between 0 mA and 20 mA. For example, the smallest possible signal was determined to be 4 mV. For example, the largest possible signal was determined to be 20 mV. The lower limit of the SAR ADC can now be adjusted to 4 mA to improve resolution. This can be done by adjusting the corresponding lowest reference voltage of the SAR ADC accordingly.

Once the linearity has been adjusted and a signal has subsequently been digitized by the ADC, a lower and an upper limit for the same ADC can be determined again and the linearity can be adjusted in order to be able to measure with even better resolution.

The computing device can be configured so that a constant current can flow for digitizing the output signal, which current can be composed of the current of the output signal and a current coming from the analog-to-digital converter. The current coming from the analog-to-digital converter can flow through a first transistor. The source terminal of the transistor can be connected to the input of the analog-to-digital converter. The transistor can be a PMOSFET. A reference voltage or a bias voltage can be applied to the gate terminal of the transistor. This advantageously allows the output signal to be read out with very low impedance. The output signal can thus be advantageously mapped at the input of the analog-to-digital converter.

The constant current can be selected to be equal to the largest possible output signal. For example, if the largest possible output signal is 500 pA, the quiescent current will be 500 pA. The constant current can flow through a second transistor to increase the size of the constant current. large current. This second transistor can also be a PMOSFET.

The circuit may include a reference voltage source, an operational amplifier, a memristor, and a transistor. The inputs of the operational amplifier may be connected to the reference voltage source and the transistor in such a way that the operational amplifier can amplify a voltage difference between a voltage provided by the transistor and a voltage provided by the reference voltage source. The output of the operational amplifier may be connected to the transistor in such a way that the electrical resistance of the transistor can be controlled, i.e., adjusted, by the operational amplifier. The memristor may be connected to the transistor in such a way that the voltage provided by the transistor drops across the memristor. A circuit constructed in this way can operate with particular precision.

The voltage provided by the circuit's reference voltage source can be adjustable. The reference voltage source can be a digital-to-analog converter. The circuit's transistor can be a field-effect transistor. The drain terminal of the field-effect transistor can be electrically connected to an input of the operational amplifier. One terminal of the memristor can be electrically connected to the drain terminal of the field-effect transistor. The output of the operational amplifier can be electrically connected to the gate terminal of the field-effect transistor. The field-effect transistor can be an NMOS transistor. The drain terminal of the field-effect transistor can be connected to the inverting input of the operational amplifier. The second terminal of the memristor can be connected to ground or connected to ground by a switch.

Another memristor and another transistor may be present in the circuit. The output of the operational amplifier may be electrically connected to the gate terminal of the other transistor. The drain terminal of the other transistor may be connected to one input of the operational amplifier. A first electrical terminal of the other memristor may be electrically connected to the drain terminal of the other transistor.

Another reference voltage source, another operational amplifier, another memristor and another transistor can be present in the circuit. Inputs of the further operational amplifier can be connected to the further reference voltage source and the further transistor in such a way that the further operational amplifier can amplify a voltage difference between a voltage provided by the further transistor and a voltage provided by the further reference voltage source. The output of the further operational amplifier can be connected to the further transistor in such a way that the electrical resistance of the further transistor can be controlled by the further operational amplifier. A first terminal of the further memristor can be connected to the further transistor in such a way that the voltage provided by the further transistor drops across the further memristor. A readout device can be provided with which a current flowing through the transistor and the further transistor can be read out. The readout device can be a readout device that comprises the analog-to-digital converter.

The readout device can be configured to measure and thus read out the current flowing from the source terminal to the drain terminal of the transistors.

The invention is explained in more detail below using figures as examples.

They show:

Figure 1 : Circuit;

Figure 2: Circuit with column-wise expansion;

Figure 3: Circuit with line-by-line extension;

Figure 4: Circuit with reset device;

Figure 5: Reading device;

Figure 6: Resolution ADO;

Figure 7: Signal range of the external DAC;

Figure 8: Resolution by adjusting the linearity of the ADC from Figure 7.

- Eingang des Operationsverstärkers 2 ist über eine elektrische Leiterbahn mit einem ersten Anschluss des Memristors 3 verbunden, und zwar insbesondere dann, wenn der Transistor 4 ein NMOS Transistor ist. Der invertierende Eingang wird durch

dargestellt. Der nichtinvertierende Eingang wird durch „+“ dargestellt. Der Ausgang des Operationsverstärkers 2 ist über eine elektrische Leiterbahn mit dem Gate-Anschluss des Transistors 4 verbunden. Der Drain-Anschluss des Transistors 4 ist über eine elektrische Leiterbahn mit dem - Eingang des Operationsverstärkers 2 und daher auch mit einem ersten elektrischen Anschluss des Memristors 3 verbunden. Der Source-Anschluss des Transistors 4 ist mit der Ausleseeinrichtung 5 verbunden. Der zweite elektrische Anschluss des Memristors 3 ist über eine elektrische Leiterbahn mit Erde 6 verbunden. Figure 1 shows an embodiment of a circuit comprising a digital-to-analog converter 1, an operational amplifier 2, a memristor 3, a transistor 4 and a readout device 5. The readout device 5 comprises an analog-to-digital converter, by means of which the output signal of the circuit can be digitized. The transistor 4 is preferably a MOSFET. The transistor 4 is particularly preferably an NMOS transistor. The output of the digital-to-analog converter 1 is connected via an electrical conductor to the one first "+" input of the operational amplifier 2, in particular when the transistor 4 is an NMOS transistor. The other second

- The input of the operational amplifier 2 is connected via an electrical conductor to a first terminal of the memristor 3, especially when the transistor 4 is an NMOS transistor. The inverting input is

The non-inverting input is represented by "+". The output of operational amplifier 2 is connected to the gate terminal of transistor 4 via an electrical conductor. The drain terminal of transistor 4 is connected to the - input of operational amplifier 2 via an electrical conductor and therefore also to a first electrical terminal of memristor 3. The source terminal of transistor 4 is connected to readout device 5. The second electrical terminal of memristor 3 is connected to ground 6 via an electrical conductor.

- Eingang des Operationsverstärkers 2 während des Betriebs mit einer elektrischen Spannung. Der Operationsverstärker verstärkt die Differenz zwischen den beiden Eingangsspannungen und versorgt so den Gate-Anschluss des Transistors 4 mit einer elektrischen Spannung. Über die am Gate-Anschluss des Transistors 4 anliegende Spannung wird der elektrische Widerstand des Transistors 4 geregelt und damit auch die Spannung, die über den Memristor abfällt und die am

- Eingang des Operationsverstärkers 2 während des Betriebs anliegt. Durch diese Rückkopplung wird erreicht, dass die Spannungsdifferenz zwischen den beiden Eingängen des Operationsverstärkers auf null geregelt wird. Die Ausgangsspannung des Digital-Analogwandlers ist dann gleich der Spannung, die am Memristor 3 abfällt. Es kann das dadurch entstandene elektrische Signal am Drain-Anschluss des Transistors 4 über eine Leiterbahn 7 ausgelesen werden. Durch den in der Figur 1 gezeigten Schaltkreis kann die Spannung, die am Memristor 3 abfällt, sehr genau eingestellt werden. Durch die Verwendung einer Source-Folge- Transistorschaltung als aktives Element kann der Strom am Memristor 3 leicht erfasst werden. Der Schaltkreis kann für sogenannte „tile operation“ wie Vektormultiplikation in der Speicherberechnung verwendet werden. Der Schaltkreis kann Teil einer Matrixstruktur sein, ohne dafür einen großen Verdrahtungsaufwand betreiben zu müssen. A digital signal can be transmitted to the digital-to-analog converter 1 via d0 to d1. The digital-to-analog converter 1 converts the digital signal into an analog voltage signal. This analog voltage signal supplies the "+" input of the operational amplifier 2 with an electrical voltage during operation. The drain terminal of transistor 4 supplies the other

- Input of operational amplifier 2 during operation with an electrical voltage. The operational amplifier amplifies the difference between the two input voltages and thus supplies the gate terminal of transistor 4 with an electrical voltage. The voltage applied to the gate terminal of transistor 4 regulates the electrical resistance of transistor 4 and thus also the voltage that drops across the memristor and that is present at the

- input of operational amplifier 2 during operation. This feedback ensures that the voltage difference between the two inputs of the operational amplifier is regulated to zero. The output voltage of the digital-to-analog converter is then equal to the voltage drop across memristor 3. The resulting electrical signal can be read out at the drain terminal of transistor 4 via a conductor track 7. The circuit shown in Figure 1 allows the voltage drop across memristor 3 to be adjusted very precisely. By using a source-follower transistor circuit as the active element, the current across memristor 3 can be easily detected. The circuit can be used for so-called "tile operations" such as vector multiplication in memory calculations. The circuit can be part of a matrix structure without requiring extensive wiring.

Figure 2 illustrates that column-by-column expansion is possible without major wiring effort. As in Figure 1, the circuit comprises a digital-to-analog converter 1 and an operational amplifier 2. In contrast to the circuit in Figure 1, two memristors and two transistors are present. As in the case of Figure 1, the output of the digital-to-analog converter 1 is connected via an electrical conductor to the first "+" input of the operational amplifier 2. The other second - input of the operational amplifier 2 is electrically connected to a first terminal of the two memristors 3. The output of the operational amplifier 2 is electrically connected to each gate terminal of the two transistors 4. Each drain terminal of the two transistors 4 is electrically connected to the - input of the operational amplifier 2 and to the corresponding first electrical terminal of each memristor 3. The source terminal of each transistor 4 is connected to a readout device 5. The second electrical terminal of each memristor 3 is grounded.

In order to keep the wiring effort to a minimum, the digital-to-analog converter 1 and the operational amplifier 2 can be arranged one behind the other, as shown in Figure 2. The memristors 3 can be arranged in a first level above the digital-to-analog converter 1 and the operational amplifier 2, as shown in Figure 2. The transistors 4 can be arranged in a second level, as shown in Figure 2, above the memristors 3. The transistors 4 can be arranged laterally offset from the memristors 3, as shown in Figure 2. Such an arrangement enables a column-wise arrangement of additional memristors 3 and additional transistors 4 with little wiring effort. Further columns can be added, each adding a memristor 3 and a transistor 4.

Each column may comprise a readout device 5 to further process the generated signal in digital form. The readout devices 5 may be another, third level, which can be located, for example, above the transistors 4, as shown in Figure 2. However, the third level can also be located, for example, at the lower edge of the circuit, for example, below the digital-to-analog converter 1 and the operational amplifier 2.

With such a circuit, multiplications can be performed and read out in parallel.

Figure 3 shows that rows for addition tasks can be added to the columns in Figure 2 without requiring a great deal of wiring. Each row is constructed as shown in Figure 2. The transistors 4 in a column, i.e. the transistors 4 arranged one below the other, are each connected to only one readout device 5. Only one readout device 5 can be present for each column. The electrical currents flowing through two transistors 4 arranged one below the other are added together and read out. The current flowing through a transistor is the result of a multiplication resulting from the voltage of a digital-to-analog converter 1 and a value of a memristor 3.

With this matrix structure, column-wise arithmetic operations such as vector multiplication and/or vector addition can be performed in an energy-efficient manner.

Figure 4 shows a circuit which includes a reset device with which the memristor 3 can be reset. The second output of the memristor 3 is connected to the drain terminal of another transistor 8. If the switch 9 is closed, as shown in Figure 4, the transistor 8 is switched to low resistance via the conductor track 10. The electrical current then flows through the memristor 3 and the transistor 8 via the then closed switch 11 to ground 6. The switches 12, 13, 14, 15 and 16 are then open, as shown in Figure 4. The switches 17, 18 and 19 are then closed, as shown in Figure 4. The circuit shown in Figure 4 then operates in the same way as the circuit shown in Figure 1. To reset memristor 3, switches 12, 13, 14, 15, and 16 are closed. Switches 17, 18, and 19 are opened. Switches 12 to 19 are opened and closed via conductor tracks 20.

By closing the switch 13, the source terminal of the transistor 4 is connected to the ground 21. By closing the switch 16, the gate terminal of the transistor 4 is connected to the conductor track 22. This Transistor 4 is switched to low resistance. By opening switch 19, the source

The gate terminal of transistor 4 is disconnected from the power source. Opening switch 18 disconnects the gate terminal of transistor 4 from the output of operational amplifier 2. Opening switch 17 disconnects the drain terminal of transistor 4 from the output of operational amplifier 2.

By opening switch 11, the source terminal of the additional transistor 8 is separated from ground 6. By closing switch 12, the source terminal of the additional transistor 8 is connected to a current source 23. By opening switch 9, the gate terminal of the additional transistor 8 is separated from the conductor track 10. This removes the low-resistance circuit of the additional transistor 8. By closing switch 14, the gate

- Connection of the further transistor 8 is connected to the output of the operational amplifier 2. By closing the switch 15, the drain connection of the further transistor 8 is connected to one input of the operational amplifier 2.

A current can now flow in the reverse direction through memristor 3. This resets memristor 3. Proper operation of the circuit can be better ensured by such a reset.

As in the case of Figure 1, a matrix structure is still possible without requiring a great deal of wiring effort.

Figure 5 shows an example of a readout device 5. The readout device 5 comprises an analog-to-digital converter 24. The analog-to-digital converter 24 can have a track-and-hold circuit that can be located between a transistor 27 and the analog-to-digital converter 24. The readout device can have current sources 25 that can be binary weighted (due to the SAR algorithm). The analog-to-digital converter 24 can have a comparator 26. First, for example, the MSB (“most significant bit”) can be determined by switching a first switch 25 with the aid of the comparator 26. Using a suitably selected second switch 25, a next bit can then be determined with the aid of the comparator, etc. The readout device 5 can have the transistor 27. The readout device 5 can have a current source 28. The current source 28 can be connected to ground 29.

For the digitization of the output signal, a constant large current can flow towards earth 29, which consists of the current of the output signal and a The current coming from the analog-to-digital converter 24 can be composed of a current source 28. The current source 28 can comprise a transistor for setting a constant current. The current source 28 can be a variable current source in order to be able to set the constant current. The current coming from the analog-to-digital converter 24 can flow through the first transistor 27 of the readout device 5. The drain terminal of the first transistor 27 can be connected to the input of the analog-to-digital converter 24. The first transistor 27 can be a PMOSFET. A reference voltage V _ref can be applied to the gate terminal of the transistor 27.

The output signal is fed into the readout device 5 via the electrical conductor 7 and digitized.

Figure 6 shows an example of the resolution IRES with which a DAC can resolve a current signal S. In the example shown, the ADC can resolve a signal S with 16 steps. The range that can be resolved lies between the current strength 0 and the current strength I _RE F.

Figure 7 shows that the external DAC can only generate currents within the loAc-ext range. The linearity of the ADC is now adjusted to this loAc-ext range, as shown in Figure 8. This makes it possible to improve the resolution for the signals S that can be generated by the external DAC. The linearity adjustment is achieved by increasing the smallest reference current of the ADC to IREF-IO and/or decreasing the largest reference current of the ADC to IREF-N.

Claims

Claims 1. Method with a computing device which comprises a circuit, the circuit having an ohmic resistor (3), the computing device comprising an analog-digital converter (24) which can convert an output signal generated by the circuit into a digital value, with the steps: the smallest possible and the largest possible output signal of the circuit is determined, the analog-digital converter is adapted to the smallest possible and the largest possible output value. 2. Method according to the preceding claim, characterized in that the ohmic resistor is a memristor (3). 3. Method according to one of the preceding claims, characterized in that an electrical voltage is provided as the input signal for the circuit and a smallest possible voltage is applied to the circuit to determine the smallest possible output value and a largest possible voltage is applied to the circuit to determine the largest possible output value. 4. Method according to the preceding claim, characterized in that the input signal is generated by a digital-to-analog converter (1) and that the smallest possible voltage is the smallest voltage that can be generated by the digital-to-analog converter (1) and that the largest possible voltage is the largest voltage that can be generated by the digital-to-analog converter (1). 5. Method according to one of the preceding claims, characterized in that the linearity of the analog-digital converter (24) is adapted to the smallest possible and the largest possible output value. 6. A computing device for a method according to any one of the preceding claims, comprising a circuit having an ohmic resistor (3), the computing device comprising an analog-to-digital converter (24) capable of converting an output signal generated by the circuit into a digital value, wherein the analog-to-digital converter (24) is adapted to the smallest possible and the largest possible output signal of the circuit or is adaptable to the smallest possible and the largest possible output signal of the circuit. 7. A computing device according to the preceding claim, characterized in that the linearity of the analog-digital converter (24) is adjustable. 8. A computing device according to one of the two preceding claims, characterized in that the analog-digital converter (24) is part of a readout device (5) which is arranged so that a constant current can flow which is composed of the current of the output signal and a current coming from the analog-digital converter. 9. A computing device according to one of the three preceding claims, characterized in that the circuit comprises a transistor and the circuit is arranged such that a voltage applied to the circuit by a digital-to-analog converter (24) of the computing device is multiplied by the transistor by a value of the ohmic resistance. 10. A computing device according to one of the four preceding claims, characterized in that the circuit comprises a reference voltage source (1), an operational amplifier (2), a memristor (3) and a transistor (4), wherein the inputs (+, -) of the operational amplifier (2) are connected to the reference voltage source (1) and the transistor (4) in such a way that the operational amplifier (2) can amplify a voltage difference between a voltage provided by the transistor (4) and a voltage provided by the reference voltage source (1), wherein the output of the operational amplifier (2) is connected to the transistor (4) in such a way that the electrical resistance of the transistor (4) can be controlled by the operational amplifier (2), wherein the memristor (3) is connected to the transistor (4) in such a way that the voltage provided by the transistor (4) drops across the memristor (3). 11. A computing device according to the preceding claim, characterized in that the voltage that can be provided by the reference voltage source (1) is adjustable. 12. A computing device according to the preceding claim, characterized in that the reference voltage source (1) is a digital-to-analog converter. 13. A computing device according to one of the preceding claims, characterized in that the transistor (4) is a field-effect transistor (4), wherein the drain terminal of the field-effect transistor (4) is electrically conductively connected to an input of the operational amplifier (2) and a terminal of the memristor (3) is electrically conductively connected to the drain terminal of the field-effect transistor (4) and the output of the operational amplifier (2) is electrically conductively connected to the gate terminal of the field-effect transistor (4). 14. A computing device according to the preceding claim, characterized in that the field-effect transistor (4) is an NMOS. 15. A computing device according to the preceding claim, characterized in that the drain terminal of the field-effect transistor (4) is connected to the inverting input of the operational amplifier (2). 16. A computing device according to any one of the preceding claims, characterized in that the second terminal of the memristor (3) is connected to earth (6) or can be connected to earth (6) by a switch (11). 17. A computing device according to one of the preceding claims, characterized in that a further memristor (3) and a further transistor (4) are present, wherein the output of the operational amplifier (2) is electrically connected to the gate terminal of the further transistor (4), the drain terminal of the further transistor (4) is connected to one input of the operational amplifier (2) and a first electrical terminal of the further memristor (3) is electrically connected to the drain terminal of the further transistor (4). 18. A computing device according to one of the preceding claims, characterized in that a further reference voltage source (1), a further operational amplifier (2), a further memristor (3) and a further transistor (4) are present, wherein the inputs (+, -) of the further operational amplifier (2) are connected to the further reference voltage source (1) and the further transistor (4) in such a way that the further Operational amplifier (2) can amplify a voltage difference between a voltage provided by the further transistor (4) and a voltage provided by the further reference voltage source (1), wherein the output of the further operational amplifier (2) is connected to the further transistor (4) in such a way that the electrical resistance of the further transistor (4) can be controlled by the further operational amplifier (2), wherein a first terminal of the further memristor (3) is connected to the further transistor (4) in such a way that the voltage provided by the further transistor (4) drops across the further memristor (3), wherein a readout device (5) is provided with which a current flowing through the transistor (4) and the further transistor (4) can be read out. 19. A computing device according to the preceding claim, characterized in that the transistor is a field-effect transistor and the readout device is arranged such that the current flowing from the source terminal to the drain terminal of the transistors (4) is measured and thus read out. 20. A computing device according to one of the preceding claims, characterized in that two memristors (3) of the circuit are arranged in a first level, two transistors (4) are arranged in another level above the first level, and the transistors (4) are arranged laterally offset from the memristors (3).