WO2025087005A1 - Interconnect system, device and network - Google Patents

Abstract

The present application relates to the technical field of computers, and discloses an interconnect system, device and network. In the present application, the interconnect device is connected to a plurality of hosts by means of its own PCIE interfaces so as to form a host cluster of a mesh topology or a host cluster of a crossbar topology. The PCIE interfaces of the interconnect device are configured to be in an EP mode, and therefore, a data path from any host connected to the interconnect device to a network interface of the interconnect device, a data path from the network interface of the interconnect device to a host connected to any PCIE interface of the interconnect device, and a data path between hosts connected to different PCIE interfaces of the interconnect device can be realized by means of the interconnect device, without increasing hardware costs, and different hosts do not need to be connected by means of a network interface card and a network.

Description

An interconnection system, device and network

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to a Chinese patent application filed with the China Patent Office on October 27, 2023, with application number 2023114130298 and application name “An Interconnected System, Device and Network”, all contents of which are incorporated by reference in this application.

Technical Field

The embodiments of the present application relate to the field of computer technology, and more specifically, to an interconnected system, device, and network.

Background Art

Currently, the interconnection between different host servers is mostly achieved through network cards and network cables, and different host servers cannot be directly connected through a hardware network card.

Therefore, how to use a hardware device to achieve direct connection between different host servers is a problem that those skilled in the art need to solve.

Summary of the invention

In view of this, the purpose of this application is to provide an interconnection system, device and network to achieve direct connection between different host servers using a hardware device. The solution is as follows:

The present application provides an interconnection system, comprising: an interconnection device and multiple hosts;

The interconnection devices include: network interface, logic interconnection module and multiple PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interfaces;

The network interface is set to connect to the master device;

Any PCIE interface is configured as EP (End Point) mode and connected to a host to form a host cluster with a mesh topology or a host cluster with a crossbar topology;

The logic interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by a master control device to a host connected to any PCIE interface; and forward data sent by a host connected to any PCIE interface to the master control device.

Optionally, the interconnection device further includes: a configuration device;

Accordingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface.

Optionally, the configuration device is configured to: obtain configuration data of the slave device core based on the configuration message, and configure the configuration data in the slave device core.

Optionally, the network interface is built with a first register configured to record a network protocol supported by the master control device;

Correspondingly, the logic interconnection module is also configured to: encapsulate data sent by a host connected to any PCIE interface using a network protocol supported by the main control device, and forward the encapsulated data to the main control device.

Optionally, the network interface is further configured to: update the network protocol recorded in the first register according to the protocol update information sent by the main control device.

Optionally, any PCIE interface is configured in RP mode and connected to an accelerator card;

The logical interconnection module is configured to: forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the acceleration card connected to any PCIE interface; and forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the main control device.

Optionally, the interconnection device further includes: an enabling device;

Accordingly, the enabling device is configured to enable the network interface and any one PCIE interface and then disable other PCIE interfaces.

Optionally, the enabling device is further configured to: disable the network interface and other PCIE interfaces when enabling any two PCIE interfaces.

Optionally, the logical interconnection module is further configured to: encapsulate the network protocol message sent by the master control device into a PCIE message, and forward the PCIE message to any PCIE interface.

Optionally, the logical interconnect module is further configured to discard data with missing forwarding addresses.

Optionally, the interconnection device further includes: a DMA (Direct Memory Access) management device and a DMA controller;

Accordingly, the DMA management device is configured to: query the memory free information of any host connected to the PCIE interface; and write the data to be transmitted into the memory of the current host in a DMA manner by using the DMA controller and the memory free information.

Optionally, the DMA management device is further configured to broadcast the memory information of the interconnected device to any host connected to the PCIE interface.

Optionally, the DMA management device is further configured to: store host memory information broadcast by any host connected to the PCIE interface.

Optionally, the interconnection device is an FPGA (Field Programmable Gate Array) accelerator card, an ASIC (Application Specific Integrated Circuit) accelerator card or a multi-core processor.

The present application provides an interconnection device, comprising: a network interface, a logic interconnection module and a plurality of PCIE interfaces;

The network interface is set to connect to the master device;

Any PCIE interface is configured in EP mode and connected to a host to form a host cluster of mesh topology or a host cluster of crossbar topology;

The logic interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces;

Forward the data sent by the master device to any host connected to the PCIE interface; forward the data sent by any host connected to the PCIE interface to the master device.

Optionally, the interconnection device further includes: a configuration device;

Accordingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface.

Optionally, the network interface is built with a first register configured to record a network protocol supported by the master control device;

Correspondingly, the logic interconnection module is also configured to: encapsulate data sent by a host connected to any PCIE interface using a network protocol supported by the main control device, and forward the encapsulated data to the main control device.

Optionally, any PCIE interface is configured as RP (Root Port) mode and connected to an accelerator card;

The logical interconnection module is configured to: forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the acceleration card connected to any PCIE interface; and forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the main control device.

The present application provides an Internet network, comprising: a plurality of any of the aforementioned Internet devices.

Optionally, network interfaces of different interconnected devices are connected to the same main control device.

It can be seen from the above scheme that the present application provides an interconnection system, including: an interconnection device and multiple hosts; the interconnection device includes: a network interface, a logical interconnection module and multiple PCIE interfaces; the network interface is configured to connect to a master control device; any PCIE interface is configured to EP mode and connected to a host to form a host cluster of a mesh topology or a host cluster of a crossbar topology; the logical interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by the master control device to a host connected to any PCIE interface; forward data sent by a host connected to any PCIE interface to the master control device.

It can be seen that the beneficial effects of the present application are: the interconnected device can directly connect to multiple hosts through its own PCIE interface to form a host cluster of mesh topology or a host cluster of crossbar topology. Since the PCIE interface of the interconnected device is configured as EP mode, the interconnected device can be used to realize the following without increasing the hardware cost: the data path from any host connected to the interconnected device to the network interface of the interconnected device, the data path from the network interface of the interconnected device to the host connected to any PCIE interface of the interconnected device, and the data path between hosts connected to different PCIE interfaces of the interconnected device, without using a network card and a network to connect different hosts.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

FIG1 is a schematic diagram of an interconnection system disclosed in the present application;

FIG2 is a schematic diagram of an Internet network disclosed in the present application;

FIG3 is a schematic diagram of another Internet network disclosed in the present application;

FIG4 is a schematic diagram of a Switch function of an interconnection device implemented based on FPGA disclosed in the present application;

FIG5 is a structural diagram of an interconnection device 1 provided by the present application;

FIG6 is a structural diagram of an interconnection device 2 provided by the present application;

FIG. 7 is a schematic diagram of another interconnection device provided in the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

At present, the interconnection between different host servers is mostly realized through network cards and network cables, and different host servers cannot be directly connected through a hardware network card. To this end, the present application provides an interconnection solution that can directly connect multiple hosts using an interconnection device, so that multiple hosts form a host cluster of mesh topology or a host cluster of crossbar topology, and also use this interconnection device to realize: a data path from any host connected to the interconnection device to the network interface of the interconnection device, a data path from the network interface of the interconnection device to any host connected to the interconnection device, and a data path between hosts connected to different PCIE interfaces of the interconnection device, without using network cards and networks to connect different hosts.

As shown in FIG1 , an interconnection system disclosed in an embodiment of the present application includes: an interconnection device and multiple hosts; the interconnection device includes: a network interface, a logical interconnection module and multiple PCIE interfaces; the network interface is configured to connect to a master control device; any PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface is configured to EP mode and connected to a host to form a host cluster of a mesh topology or a host cluster of a crossbar topology. It can be seen that any device having a network interface, a logical interconnection module, and a PCIE interface configured to EP mode can be used as an interconnection device provided in this embodiment. The logical interconnection module can be a hardware module with a processor function.

Among them, the logical interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by a master control device to a host connected to any PCIE interface; and forward data sent by a host connected to any PCIE interface to the master control device.

This embodiment enables data sent by any host to the interconnected device through the PCIE interface to reach the master device connected to the network interface of the interconnected device. This embodiment enables data sent by any host to the interconnected device through the PCIE interface to reach hosts connected to other PCIE interfaces, thereby realizing data paths between hosts connected to different PCIE interfaces of the interconnected device. This embodiment enables data sent by the master device to the interconnected device to reach hosts connected to any PCIE interface of the interconnected device, thereby realizing data paths from the network interface of the interconnected device to hosts connected to any PCIE interface of the interconnected device.

In this embodiment, the main control device may be a remote host or a remote acceleration device.

In one embodiment, the interconnection device further comprises: a configuration device; correspondingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface, and configure the device number and bus address of the host according to the configuration message.

In one embodiment, the configuration device is configured to: obtain configuration data of the slave device core based on the configuration message, and configure the configuration data in the slave device core. The interconnected device also includes: a bus register and a memory window register; accordingly, the configuration device is configured to: configure the bus register and the memory window register according to the configuration message to configure the root device core of the PCIE interface. Or convert the configuration message into a data format that matches the EP mode, and configure the bus address obtained by converting the host's memory address to the slave device core according to the converted configuration message. Among them, the data format that matches the EP mode is the type0 format, and the data format that matches the RP mode is the type1 format.

An interconnected device has multiple PCIE interfaces, and the configuration of any PCIE interface can be achieved with the help of a configuration device. The interconnected device includes N PCIE interfaces, thereby achieving: a data path from any PCIE interface of the interconnected device to a network interface, a data path from the network interface to any PCIE interface, and a data path between different PCIE interfaces without the help of an expansion controller. Therefore, the interconnected device can support mesh topology and crossbar topology, and can enable a master control device and multiple hosts to construct mesh topology diagrams and crossbar topology diagrams.

When configuring the IP (Internet Protocol Address) address for the PCIE interface, configure the command registers such as the enable memory space register, IO space register, and bus master register; configure the write maximum load length register, the maximum read request register, and the strong order mode register. When the PCIE interface is initialized, configure the bus registers such as the root bus register, the sub-bus register, and the maximum bus register; configure the memory window register to set the interface pre-fetchable memory range, the window base address of the non-pre-fetchable memory, the window size and other information; configure the host device identification information (BDF value). At this point, the PCIE interface can implement the Switch function based on the built-in root device core. Generally, the RP's capability configuration space register is in the root interface (Root Port), while the Switch's capability configuration register is in the Switch. The BDF (Bus Device Function) value refers to: bus number, device number, and function number.

When configuring the built-in slave core of the PCIE interface, first convert the TLP (Transaction Layer Packet, a transaction layer data packet for data transmission) configuration message in type0 format to type1 format, and then configure the BDF register to configure the identification information for the host device of the current interface; then configure the BAR (Base Address Register) address (converted from the memory address of the host device) so that the current interface can read the memory address of the host device; then configure the command registers such as the enable memory space register, IO space register, and bus master register; configure the write maximum load length register, the maximum read request register, and the strong order mode register. At this point, the PCIE interface can implement the Switch function based on the built-in slave core.

In one embodiment, the network interface is built with a first register configured to record the network protocol supported by the master device; accordingly, the logic interconnection module is also configured to: encapsulate data sent by any host connected to the PCIE interface using the network protocol supported by the master device, and forward the encapsulated data to the master device. In one example, the user uses the master device to change the transmission protocol supported by the master device. Transmission protocols such as TCP (Transmission Control Protocol, a transport layer communication protocol) and the like.

In one implementation, the network interface is further configured to: update the network protocol recorded in the first register according to the protocol update information sent by the master control device.

It should be noted that when some PCIE interfaces in the interconnected devices are connected to the host and some PCIE interfaces are connected to the accelerator card, communication between the host connected to one PCIE interface and the accelerator card connected to another PCIE interface can be achieved. In one embodiment, any PCIE interface is configured as RP mode and connected to an accelerator card; the logical interconnection module is configured to: forward the accelerator card data sent by the PCIE interface connected to the accelerator card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the accelerator card connected to any one PCIE interface; forward the accelerator card data sent by the PCIE interface connected to the accelerator card to the main control device. This forwarding process also depends on the destination address of the forwarded data. The logical interconnection module can determine through this destination address: whether the data is forwarded to the network interface or which PCIE interface.

In this embodiment, the network interface and each PCIE interface can be flexibly enabled and disabled. Therefore, before the logical interconnection module determines the transmission protocol according to the current protocol information in the first register, the enabling device can also enable the network interface and disable other PCIE interfaces so that data can be sent through the network interface. Accordingly, before the logical interconnection module forwards data to the host connected to the PCIE interface through any PCIE interface, the enabling device can also enable the PCIE interface, disable the network interface and other PCIE interfaces, so that data can be sent through the enabled PCIE interface. In one embodiment, the enabling device is also configured to: disable the network interface and other PCIE interfaces when enabling any two PCIE interfaces. In one embodiment, the interconnection device also includes: an enabling device; accordingly, the enabling device is configured to: disable other PCIE interfaces when enabling the network interface and any one PCIE interface.

In one embodiment, the logical interconnection module is further configured to: encapsulate the network protocol message sent by the master device into a PCIE message, and forward the PCIE message to any PCIE interface, so that the data sent by the master device connected to the network interface to the interconnection device through the network interface can reach the host connected to at least one PCIE interface.

In one embodiment, the logical interconnect module is further configured to discard data with missing forwarding addresses. That is, the forwarded data contains a forwarding address, that is, the destination address of the data, and the logical interconnect module can determine whether the data is forwarded to a network interface or a PCIE interface through the destination address.

In one example, the interconnected device also includes: a DMA (Direct Memory Access) management device and a DMA controller; accordingly, the DMA management device is set to: query the memory free information of any host connected to the PCIE interface; use the DMA controller and the memory free information to write the data to be transmitted into the memory of the current host in DMA mode, thereby realizing direct DMA write operations between the interconnected device and the host.

The DMA management device is further configured to: broadcast the memory information of the interconnected device to any host connected to the PCIE interface, and store the host memory information broadcast by any host connected to the PCIE interface.

In one embodiment, the interconnection device is an FPGA (Field Programmable Gate Array) accelerator card, an ASIC (Application Specific Integrated Circuit) accelerator card, or a multi-core processor.

It can be seen that in this embodiment, the interconnection device can directly connect multiple hosts through its own PCIE interface to form a host cluster of mesh topology or a host cluster of crossbar topology. Since the PCIE interface of the interconnection device is configured as EP mode, the interconnection device can be used to realize the following without increasing the hardware cost: the data path from any host connected to the interconnection device to the network interface of the interconnection device, the data path from the network interface of the interconnection device to the host connected to any PCIE interface of the interconnection device, and the data path between hosts connected to different PCIE interfaces of the interconnection device, without the need to use network cards and networks to connect different hosts. Of course, the interconnection device also supports other topologies.

Please refer to Figure 2. An embodiment of the present application provides an interconnection network, including: N interconnection devices provided in the aforementioned embodiments, and different interconnection devices are connected to the same main control device. Among them, each interconnection device has multiple PCIE interfaces, and each PCIE interface is connected to a host. In this embodiment, the interconnection device can be a GPU (Graphics Processing Unit), FPGA, NPU (Neural Processing Unit) and TPU (Tensor Processing Unit). GPU usually performs pure computing acceleration, and FPGA can complete application acceleration processing such as computing acceleration, network acceleration and storage acceleration.

As shown in Figure 3, it is assumed that a task needs to be accelerated, and the acceleration is achieved based on interconnected device 1, interconnected device 2 and interconnected device 3. These three interconnected devices are all connected to the same master device. The initialization process of the system: the master device initializes the PCIE interfaces of the three interconnected devices respectively, completes the configuration of the configuration space and the allocation of the bus base address. The three interconnected devices periodically broadcast their free memory information to other interconnected devices through the PCIE interface. The three interconnected devices can all be accelerator cards, and can realize the interconnection between different hosts without the help of network cards and networks, forming a host cluster with mesh topology or a host cluster with crossbar topology to achieve higher performance computing.

Referring to the above embodiment, the PCIE interface of the interconnected device is an RP mode interface or an EP mode interface, and the bus address range of the PCIE interface is not less than the bus address range of the device connected to it. When configured in EP mode, it can be connected to a host server to form an integration of multiple host servers; when configured in RP mode, it can be connected to an acceleration card to form an AI (Artificial Intelligence) acceleration card system. The PCIE interface of the interconnected device has RP (Root Port) mode and EP (End Point) mode. The current RP mode and the current EP mode only support one-to-one communication between the interconnected device and the device connected to its PCIE interface, and do not support communication between the main control device connected to the network interface of the interconnected device and the device connected to the PCIE interface of the interconnected device, nor do they support communication between devices connected to different PCIE interfaces of the interconnected device. However, after the PCIE interface of this embodiment is made into an RP mode interface or an EP mode interface, the communication between the device connected to the network interface of the interconnected device and the device connected to the PCIE interface of the interconnected device, and the communication between devices connected to different PCIE interfaces of the interconnected device are realized accordingly. The network interface of the interconnected device provided in the embodiment of the present application can be directly connected to the server. When the interconnected device is an acceleration card, its direct connection to the server can form a "host directly connected to the acceleration card" system with the server.

Inside the interconnected device, data follows the PCIE protocol. According to this application, the following data paths can be implemented in this interconnected device: bottom-up data paths, top-down data paths, and data paths between host devices connected to different PCIE interfaces of the interconnected device. And the type of transmission protocol used by the main control device can be flexibly determined according to the scene requirements. It can be seen that the interconnected device supports full interconnection of mesh topology, crossbar topology, etc., that is, any interface of the interconnected device can communicate with other interfaces of the interconnected device.

The following takes the interconnected devices implemented by the FPGA accelerator card as an example to introduce the communication process between the main control device connected to the FPGA's network interface and the device connected to the FPGA's PCIE interface, and the communication process between devices connected to different PCIE interfaces of the FPGA when the FPGA's PCIE interface is in RP mode.

Optionally, this embodiment enables the PCIE interface of the FPGA to implement the PCIE switch function based on the PCIE RP hard core inside the FPGA, and can also improve the utilization rate of FPGA logic resources. When configuring the PCIE interface in RP mode, you only need to change the configuration space content to enable the PCIE interface to implement the PCIE switch function.

Please refer to Figure 4. It is necessary to implement the interface configuration module, device configuration module, logic processing module and network module based on the PCIE RP hard core inside the FPGA; the logic processing module has the following modules for the network module and the two downstream PCIE interfaces: analysis module, multiplexing module and arbitration module. The FPGA in Figure 4 has two downstream PCIE interfaces, and each downstream PCIE interface has a PCIE RP hard core. Of course, the FPGA can have more or fewer downstream PCIE interfaces, and one downstream PCIE interface is connected to a host or an accelerator card device.

Generally, the PCIE RP hard core provides three groups of user interfaces, namely the user receive bus, the user send bus and the configuration space configuration bus. Among them, the user receive bus and the send bus are user interfaces for transmitting TLP messages. The configuration space configuration bus can be used to complete the configuration of the PCIE RP configuration space, and read the default register value of the configuration space and output it to the parsing module of the logic processing module to assist in parsing and processing. The device configuration module completes the initialization configuration of the configuration space of the two processors through the initiated configuration TLP message, and the BAR base addresses of the two processors are configured as BAR1 and BAR2 respectively. The interface configuration module completes the initialization configuration of the configuration space of the two PCIE interfaces of the FPGA through the cfg_mgnt bus (configuration management, control management bus), and the BAR base addresses of the two PCIE interfaces are configured as BAR3 and BAR4 respectively, wherein the address range of BAR3 is greater than or equal to the address range of BAR1, and the address range of BAR4 is greater than or equal to the address range of BAR2.

It can be seen that the device configuration module is set to initialize the downstream EP device (host or accelerator card). The interface configuration module is set to initialize the configuration of the PCIE interface. The logic processing module is set to realize the forwarding and control of TLP messages, in which a parsing module, a multiplexing module and an arbitration module are provided for each interface. The parsing module parses the TLP message output by the PCIE RP's transmit bus, outputs an arbitration request based on the routing information, and handles abnormal TLP messages; the arbitration module receives the arbitration request and outputs an arbitration signal to select the corresponding transmission path for the message, and the multiplexing module receives the data output by each path parsing module, and selects the appropriate path according to the arbitration signal and sends it to the PCIE RP's receive bus.

The network module is configured to process operations related to the network interface. In this embodiment, the network module is connected to the network interface of the FPGA. The network module implements multiple network transmission protocols, such as RDMA (Remote Direct Memory Access), TCP/IP or a custom low-latency network protocol, etc., and selects one of the network protocols according to the mode configuration input by the user and outputs it to the main control device connected to the network interface through the network interface. As before, the network module not only supports the PCIE protocol inside the FPGA, but also supports external RDMA, TCP/IP and other protocols, and can realize the conversion between internal and external protocols. Please refer to Figure 4. When selecting an externally supported protocol, it can be dynamically configured through the mode selection switch. The user sends a switch register message for configuring the mode selection through the network interface. After receiving the message, the network interface parses the message and extracts the corresponding mode selection switch value to configure it to the mode selection register module, and the network protocol processing module processes the corresponding network protocol according to the value of the mode selection register.

In this example, the PCIE Switch includes three channels, two of which are connected to the AI processor and the other is connected to the network interface. The following describes the communication between the two processors connected by the two PCIE interfaces of the FPGA. AI processor-1 initiates a memory access operation to AI processor-2, and the target address is BAR2. The DMA controller of AI processor-1 initiates the operation. This operation message is first sent to the downstream interface PCIE RP IP-1 corresponding to the FPGA PCIE Switch through the PCIE interface. After the PCIE RPIP-1 is output, it is sent to the parsing module 1. The parsing module 1 parses the TLP message and extracts the corresponding destination address and other information. If the destination address is within the routing window of PCIE IP□2, the destination address arbitration request is output and sent to the arbitration modules of each interface. In the current example, the destination address is the BAR2 address. The arbitration module 2 outputs a valid arbitration enable signal, and other arbitration modules output invalid enable signals. According to the valid arbitration signal, the TLP message is sent to the receiving bus of PCIE RP IP-2, and then sent to AI processor-2 through the PCIE interface. The DMA controller of AI processor-2 extracts the data of the TLP message and stores it in the corresponding storage medium. If the destination address of the TLP message is not within the routing window range (that is, not within the routing window of PCIE IP-2, nor within the routing window of the network path) or the TLP message is abnormal, the message is discarded.

It should be noted that, according to this embodiment, each PCIE interface of the FPGA can be configured so that the PCIE interface becomes a PCIE interface with a PCIE Switch function. Of course, the network interface of the FPGA can also be configured as a Switch network interface accordingly. In this way, communication between AI processors or hosts can be achieved by configuring the FPGA, and communication between the AI processor and the upstream network interface of the FPGA can be achieved without the help of an expansion controller or expansion card.

It can be seen that this embodiment can enable the PCIE switch function of the PCIE interface of the FPGA to be realized based on the PCIE RP IP hard core that comes with the FPGA, without the need to use an additional PCIE Switch controller, with low cost, simple implementation, and low utilization of FPGA logic resources. At the same time, this method can be applied to almost all FPGAs and has strong portability. This method can also be extended to other PCIE processors. If its PCIE interface comes with a PCIE RP IP, but does not support the PCIE Switch mode, the PCIE interface of the PCIE Switch can be realized through the PCI RP IP to realize the Switch forwarding function. Referring to this implementation method, the PCIE interface that realizes the PCIE Switch can also be configured with the help of the PCIE EP IP hard core that comes with the interconnected device without adding a Switch controller; but it should be noted that in the EP mode, the configuration TLP message format for configuring the PCIE Switch needs to be converted from the type0 format to the type1 format, and other configuration contents can refer to the configuration of the RP mode provided in this application. The IP (Intellectual Property) hard core is a controller in the form of a hardware module.

An interconnection device provided in an embodiment of the present application is introduced below. The interconnection device described below can be referenced to other embodiments described in this document.

The embodiment of the present application discloses an interconnection device, including: a network interface, a PCIE interface and a logical interconnection module; the network interface has a built-in first register and is connected to a main control device; the PCIE interface is configured as an RP mode or an EP mode and is connected to a host device or an accelerator card. The PCIE interface is configured to receive target data sent by a device connected thereto. The logical interconnection module is configured to convert the target data into a first message that complies with a first transmission protocol recorded in the first register, and send the first message to the main control device through the network interface, if it is determined that the destination address of the target data is within the routing address recorded in the first register (network register).

In one embodiment, the interconnect device is an FPGA acceleration card, an ASIC acceleration card, or a multi-core processor.

The embodiment of the present application also provides an interconnection device. The interconnection device can be either the interconnection device 1 shown in FIG5 or the interconnection device 2 shown in FIG6. FIG5 and FIG6 are both interconnection device structure diagrams according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.

FIG5 is a schematic diagram of the structure of an interconnection device 1 provided in an embodiment of the present application. The interconnection device 1 may include: at least one processor, at least one memory, a power supply, a communication interface, an input/output interface, and a communication bus. The memory is configured to store a computer program, which is loaded and executed by the processor and can implement the relevant steps implemented by the logical interconnection module disclosed in any of the aforementioned embodiments.

In this embodiment, the power supply is configured to provide working voltage for each hardware device on the interconnected device 1; the communication interface can create a PCIE-based data transmission channel between the interconnected device 1 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, which is not limited here; the input and output interface is configured to obtain external input data or output data to the outside world, and its interface type can be selected according to actual application needs and is not limited here.

In addition, the memory as a carrier of resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources include operating systems, computer programs, and data, and the storage method can be temporary or permanent.

The operating system is configured to manage and control the hardware devices and computer programs on the interconnected device 1 to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the relevant steps implemented by the aforementioned logical interconnection module, computer programs can also include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, data can also include data such as application developer information.

FIG6 is a schematic diagram of the structure of an interconnected device 2 provided in an embodiment of the present application. The interconnected device 2 may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

Generally, the interconnection device 2 in this embodiment includes: a processor and a memory.

Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA, and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU, which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

The memory may include one or more computer non-volatile readable storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps implemented by the logical interconnection module executed by the interconnection device 2 side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include operating systems and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

In some embodiments, the interconnection device 2 may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

Those skilled in the art will appreciate that the structure shown in FIG. 6 does not constitute a limitation on the interconnection device 2 , and may include more or fewer components than those shown in the figure.

Please refer to Figure 7. The present application provides an interconnection device, including: a network interface, a logical interconnection module and multiple PCIE interfaces; the network interface is configured to connect to a master control device; any PCIE interface is configured to EP mode and connected to a host to form a host cluster of a mesh topology or a host cluster of a crossbar topology; the logical interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by the master control device to a host connected to any PCIE interface; forward data sent by a host connected to any PCIE interface to the master control device.

The interconnection device also includes: a configuration device; accordingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface. The configuration device is configured to: obtain the configuration data of the slave device core based on the configuration message, and configure the configuration data in the slave device core. The network interface is built with a first register configured to record the network protocol supported by the master device; accordingly, the logical interconnection module is also configured to: encapsulate the data sent by the host connected to any PCIE interface using the network protocol supported by the master device, and forward the encapsulated data to the master device. The network interface is also configured to: update the network protocol recorded in the first register according to the protocol update information sent by the master device.

Any PCIE interface is configured as RP mode and connected to an accelerator card; the logic interconnection module is set to: forward the accelerator card data sent by the PCIE interface connected to the accelerator card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the accelerator card connected to any PCIE interface; forward the accelerator card data sent by the PCIE interface connected to the accelerator card to the main control device.

The interconnection device also includes an enabling device; accordingly, the enabling device is configured to enable the network interface and any one PCIE interface to disable other PCIE interfaces. The enabling device is also configured to enable any two PCIE interfaces to disable the network interface and other PCIE interfaces.

The logical interconnection module is further configured to: encapsulate the network protocol message sent by the master control device into a PCIE message, and forward the PCIE message to any PCIE interface. The logical interconnection module is further configured to: discard data with missing forwarding addresses.

The interconnection device also includes: a DMA management device and a DMA controller; accordingly, the DMA management device is configured to: query the memory free information of any host connected to the PCIE interface; and use the DMA controller and the memory free information to write the data to be transmitted into the memory of the current host in a DMA manner. The DMA management device is also configured to: broadcast the memory information of the interconnection device to any host connected to the PCIE interface. The DMA management device is also configured to: store the host memory information broadcast by any host connected to the PCIE interface.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM (Random Access Memory), memory, read-only memory (ROM (Read-Only Memory), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of non-volatile readable storage medium known in the art.

This article uses examples to illustrate the principles and implementation methods of this application. The above examples are only used to help understand the application. The present invention relates to a method and its core idea of the present invention; at the same time, for a person skilled in the art, according to the idea of the present invention, there may be changes in the specific implementation method and the scope of application. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (20)

An interconnection system, comprising: an interconnection device and a plurality of hosts; The interconnection device includes: a network interface, a logic interconnection module and a plurality of high-speed serial computer expansion bus standard PCIE interfaces; The network interface is configured to connect to a main control device; Any PCIE interface is configured as endpoint EP mode and connected to a host to form a host cluster of mesh topology or a host cluster of crossbar topology; The logic interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by the main control device to a host connected to any PCIE interface; and forward data sent by a host connected to any PCIE interface to the main control device. The interconnection system according to claim 1, characterized in that the interconnection device further comprises: a configuration device; Correspondingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface. The interconnection system according to claim 2 is characterized in that the configuration device is configured to: obtain configuration data of the slave device core based on the configuration message, and configure the configuration data in the slave device core. The interconnection system according to claim 1, characterized in that the network interface has a built-in first register configured to record the network protocol supported by the master device; Correspondingly, the logic interconnection module is further configured to: encapsulate data sent by a host connected to any PCIE interface using a network protocol supported by the main control device, and forward the encapsulated data to the main control device. The interconnection system according to claim 4 is characterized in that the network interface is further configured to: update the network protocol recorded in the first register according to the protocol update information sent by the master control device. The interconnection system according to claim 1, characterized in that any PCIE interface is configured as a root interface RP mode and connected to an accelerator card; The logic interconnection module is configured to: forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the acceleration card connected to any one of the PCIE interfaces; and forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the main control device. The interconnection system according to claim 1, characterized in that the interconnection device further comprises: an enabling device; Correspondingly, the enabling device is configured to: enable the network interface and any one PCIE interface and disable other PCIE interfaces. The interconnection system according to claim 7 is characterized in that the enabling device is further configured to: disable the network interface and other PCIE interfaces when any two PCIE interfaces are enabled. The interconnection system according to claim 4 is characterized in that the logical interconnection module is also configured to: encapsulate the network protocol message sent by the master control device into a PCIE message, and forward the PCIE message to any PCIE interface. The interconnection system according to any one of claims 1 to 9 is characterized in that the logical interconnection module is further configured to discard data with missing forwarding addresses. The interconnection system according to any one of claims 1 to 9, characterized in that the interconnection device further comprises: a memory direct access DMA management device and a DMA controller; Accordingly, the DMA management device is configured to: query the memory idle information of any host connected to the PCIE interface; and write the data to be transmitted into the memory of the current host in a DMA manner by using the DMA controller and the memory idle information. The interconnection system according to claim 11 is characterized in that the DMA management device is also configured to: broadcast the memory information of the interconnection device to any host connected to the PCIE interface. The interconnection system according to claim 11 is characterized in that the DMA management device is also configured to: store host memory information broadcast by any host connected to the PCIE interface. The interconnection system according to any one of claims 1 to 9 is characterized in that the interconnection device is a field programmable gate array FPGA acceleration card, an application specific integrated circuit ASIC acceleration card or a multi-core processor. An interconnection device, characterized in that it comprises: a network interface, a logic interconnection module and a plurality of PCIE interfaces; The network interface is configured to connect to a main control device; Any PCIE interface is configured in EP mode and connected to a host to form a host cluster of mesh topology or a host cluster of crossbar topology; The logic interconnection module is configured to: forward data sent by a host connected to any PCIE interface to hosts connected to other PCIE interfaces; forward data sent by the main control device to a host connected to any PCIE interface; and forward data sent by a host connected to any PCIE interface to the main control device. The interconnection device according to claim 15, characterized in that the interconnection device further comprises: a configuration device; Correspondingly, the configuration device is configured to: configure the host connected to the current PCIE interface and the slave device core of the current PCIE interface according to the configuration message of any PCIE interface. The interconnection device according to claim 15, characterized in that the network interface is built with a first register configured to record the network protocol supported by the master control device; Correspondingly, the logic interconnection module is further configured to: encapsulate data sent by a host connected to any PCIE interface using a network protocol supported by the main control device, and forward the encapsulated data to the main control device. The interconnection device according to claim 15, characterized in that any PCIE interface is configured as RP mode and connected to an accelerator card; The logic interconnection module is configured to: forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the host connected to other PCIE interfaces; forward the data sent by the main control device to the acceleration card connected to any one of the PCIE interfaces; and forward the acceleration card data sent by the PCIE interface connected to the acceleration card to the main control device. An Internet network, characterized in that it comprises: a plurality of Internet devices as described in any one of claims 15 to 18. The Internet network according to claim 19 is characterized in that the network interfaces of different Internet devices are connected to the same master control device.