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WO2025085571A1 - Réseau d'impédance fixe géométriquement programmable - Google Patents

Réseau d'impédance fixe géométriquement programmable Download PDF

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Publication number
WO2025085571A1
WO2025085571A1 PCT/US2024/051663 US2024051663W WO2025085571A1 WO 2025085571 A1 WO2025085571 A1 WO 2025085571A1 US 2024051663 W US2024051663 W US 2024051663W WO 2025085571 A1 WO2025085571 A1 WO 2025085571A1
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WO
WIPO (PCT)
Prior art keywords
fixed
integrated circuit
array
conductive portion
impedances
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
PCT/US2024/051663
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English (en)
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WO2025085571A8 (fr
Inventor
Giho Lee
Min-Kyu Song
Jeehwan Kim
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Massachusetts Institute of Technology
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Massachusetts Institute of Technology
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Publication of WO2025085571A1 publication Critical patent/WO2025085571A1/fr
Publication of WO2025085571A8 publication Critical patent/WO2025085571A8/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/48—Analogue computers for specific processes, systems or devices, e.g. simulators
    • G06G7/62—Analogue computers for specific processes, systems or devices, e.g. simulators for electric systems or apparatus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H15/00—Transversal filters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H15/00—Transversal filters
    • H03H2015/007—Programmable filters

Definitions

  • CPUs general- purpose central processing units
  • CPUs are designed to process information serially and are less efficient for highly parallel computation, such as machine learning processing, which typically involves parallel processing of large, multi-dimensional inputs.
  • Alternative solutions to general-purpose CPUs are therefore desirable to improve speed, power efficiency, and associated costs of highly parallel computation.
  • the present disclosure provides circuits and systems with fixed impedances (e.g., arranged in an array) that, in accordance with certain embodiments, are fast, reliable, highly- scalable, and may be programmable for performing multiplication or similar functions.
  • Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between conductive portions of respective layers of the integrated circuit, at least some of the fixed impedances having different fixed impedance values.
  • Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between an input terminal and an output terminal of the integrated circuit, the array having fixed impedance values programmed for multiplying a value of an input signal received at the input terminal to produce an output at the output terminal.
  • an integrated circuit comprises a first layer comprising a first conductive portion, a second layer comprising a second conductive portion, and an array of fixed impedances electrically coupled to and between the first conductive portion of the first layer and the second conductive portion of the second layer, and at least some of the fixed impedances are coupled to and between the first and second conductive portions and have different fixed impedance values.
  • the at least some of the fixed impedances of the array are coupled in parallel with one another to and between the first and second conductive portions.
  • the array of fixed impedances comprises a first dimension along which at least most of the fixed impedances have different fixed impedance values. In some embodiments, each fixed impedance along the first dimension of the array has a different fixed impedance value.
  • the array of fixed impedances comprises an array of conductive traces in which resistances of the conductive traces are fixed by geometries of the conductive traces.
  • the conductive traces each comprise a first electrode, a second electrode, and a meandering conductive geometry coupling the first electrode to the second electrode, with the meandering conductive geometry fixing the resistance of the conductive trace.
  • the array of fixed impedances comprises an array of channelbased resistors in which resistances of the channel-based resistors are fixed by a number and/or size of channels of the channel-based resistors.
  • the channelbased resistors each comprise one or more channels coupled to and between the first conductive portion and the second conductive portion, with the number and/or size of one or more contact points, at which the one or more channels contact the first and/or second conductive portions, fixing the resistance of the channel-based resistor.
  • the channel-based resistors each further comprise a passivation structure at least partially surrounding the one or more channels and separating the first conductive portion from the second conductive portion, where the one or more contact points comprise openings in the passivation structure.
  • the first conductive portion is coupled to a plurality of fixed impedances of the array of fixed impedances.
  • the second conductive portion is coupled to a plurality of fixed impedances of the array of fixed impedances.
  • an integrated circuit comprises an input terminal, an output terminal, and an array of fixed impedances electrically coupled to and between the input terminal and the output terminal, and the array of fixed impedances has fixed impedance values programmed for multiplying a value of an input signal received at the input terminal to produce an output signal at the output terminal.
  • the integrated circuit further comprises a first layer comprising a first conductive portion coupled to the input terminal, and a second layer comprising a second conductive portion coupled to the output terminal.
  • the array of fixed impedances comprises a first plurality of fixed impedances coupled in parallel with one another to and between the first conductive portion and the second conductive portion. In some embodiments, the first plurality of fixed impedances are disposed along a first dimension of the array of fixed impedances. In some embodiments, the integrated circuit further comprises a second input terminal and a third conductive portion coupled to the second input terminal, and the array of fixed impedances further comprises a second plurality of fixed impedances coupled to and between the third conductive portion and the second conductive portion.
  • the integrated circuit further comprises a second output terminal and a third conductive portion coupled to the second output terminal, and the array of fixed impedances further comprises a second plurality of fixed impedances coupled to and between the first conductive portion and the third conductive portion.
  • one of the input signal and the output signal is a voltage signal and the other of the input signal and the output signal is a current signal.
  • a characteristic of the input signal is indicative of a multiplicand as the value of the input signal and a characteristic of the output signal is indicative of a product of the multiplicand with a multiplier value for which the fixed impedance values are programmed.
  • a system comprises the integrated circuit and a processor coupled to the integrated circuit and configured to perform a multiplication at least in part by providing, to the integrated circuit, the input signal as an analog version of a multiplicand, and obtaining, via the integrated circuit, a digitized version of the output signal as a product of the multiplicand and a multiplier for which the fixed impedance values are programmed.
  • FIG. l is a block diagram of an example system including an integrated circuit having an array of fixed impedances, according to some embodiments;
  • FIG. 2 is a block diagram of an example integrated circuit having an array of fixed impedances electrically coupled to and between a plurality of conductive portions of a respective plurality of layers of the integrated circuit, according to some embodiments;
  • FIG. 3 A is a block diagram of a first example configuration of an array of fixed impedances configured to receive a plurality of inputs and produce therefrom a plurality of respective outputs, according to some embodiments;
  • FIG. 3B is a block diagram of a second example configuration of an array of fixed impedances configured to receive a plurality of inputs and produce therefrom a plurality of respective outputs, according to some embodiments;
  • FIG. 3C is a block diagram of a third example configuration of an array of fixed impedances configured to receive a plurality of inputs and produce therefrom a plurality of respective outputs, according to some embodiments;
  • FIG. 3D is a block diagram of a fourth example configuration of an array of fixed impedances configured to receive an input and produce therefrom an output, according to some embodiments;
  • FIG. 4 is a top view of a first example array of fixed impedances electrically coupled to and between a plurality of conductive portions of an integrated circuit, according to some embodiments;
  • FIG. 5 A is a side view of a cross-section of a portion of an example integrated circuit including a fixed impedance coupled to and between a first conductive portion on a first layer and a second conductive portion on a second layer, with the fixed impedance on a third layer that is above or below each of the first and second layers, according to some embodiments;
  • FIG. 5B is a side view of a cross-section of a portion of an alternative example integrated circuit including a fixed impedance coupled to and between a first conductive portion on a first layer and a second conductive portion on a second layer, with the fixed impedance on a third layer that is between the first and second layers, according to some embodiments;
  • FIG. 6A is a top view of example array of fixed impedances, according to some embodiments.
  • FIG. 6B is a magnified view of a quadrant of the array of FIG. 6A, according to some embodiments.
  • FIG. 7A is a top view of a first example resistor that may be included in the array of FIG. 4, according to some embodiments;
  • FIG. 7B is a perspective view of the resistor of FIG. 7A, according to some embodiments.
  • FIG. 7C is a top view of the resistive region of the resistor of FIG. 7A, according to some embodiments.
  • FIG. 8A is a top view of an example unit cell that may be included in an array of fixed impedances, the unit cell including the resistor of FIGs. 7A-7C in series with a transistor, according to some embodiments;
  • FIG. 8B is a top view of an alternative example unit cell that may be included in an array of fixed impedances, the unit cell including a plurality of resistors of FIGs. 7A-7C in series with respective transistors and sharing an electrode, according to some embodiments;
  • FIG. 9A is a graph of logscale area for the resistor of FIG. 7A vs. the width and length (in microns) of the resistor, according to some embodiments;
  • FIG. 9B is a graph of conductance gradient for the resistor of FIG. 7A vs. the width and length (in microns) of the resistor, according to some embodiments;
  • FIG. 9C is a graph identifying logscale conductance-based and logscale area-based constrained regions of the width and length (in microns) for the resistor of FIG. 7A, according to some embodiments;
  • FIG. 9D is a graph identifying a range of width-length pairs (in microns) for the resistor of FIG. 7A satisfying the constraints of the graph of FIG. 9C, according to some embodiments;
  • FIG. 10 is a top view of a second example array of fixed impedances electrically coupled to and between a plurality of conductive portions of an integrated circuit, according to some embodiments;
  • FIG. 11 A is a side view of a cross-section of a second example resistor that may be included in the array of FIG. 10, according to some embodiments;
  • FIG. 11B is a perspective view of the resistor of FIG. HAwith one of the electrodes and a portion of the passivation structure removed, according to some embodiments;
  • FIG. 12A is a side view of a cross-section of a third example resistor that may be included in the array of FIG. 10, according to some embodiments;
  • FIG. 12B is a perspective view of the resistor of FIG. 12A with one of the electrodes and a portion of the passivation structure removed, according to some embodiments;
  • FIG. 13 A is a top view of a plurality of conductive portions configured as electrodes for a plurality of resistors of FIGs. 11A-11B, according to some embodiments;
  • FIG. 13B is a side view of a cross-section of one of the conductive portions of FIG.
  • FIG. 14A is a top view of the conductive portions of FIG. 13A with channels coupled to the conductive portions, according to some embodiments;
  • FIG. 14B is a side view of a cross-section of one of the conductive portions and one of the channels of FIG. 14A, according to some embodiments;
  • FIG. 15A is a top view of the conductive portions and channels of FIG. 14A with a passivation structure having openings for the channels, according to some embodiments;
  • FIG. 15B is a side view of a cross-section of one of the conductive portions, one of the channels, and a portion of the passivation structure of FIG. 15 A, according to some embodiments;
  • FIG. 16A is a top view of an array of resistors of FIGs. 11A-11B, according to some embodiments.
  • FIG. 16B is a side view of a cross-section of one of the resistors of FIG. 15 A, according to some embodiments.
  • FIG. 17 is a top view of an example unit cell that may be included in an array of fixed impedances, the unit cell including the resistor of FIG. 11A-11B in series with a transistor, according to some embodiments;
  • FIG. 18A is a graph of actual vs. target conductance for the resistor of FIGs. 11A-11B, according to some embodiments.
  • FIG. 18B is a graph of conductance error vs. target conductance for the resistor of FIGs. 11A-11B, according to some embodiments.
  • FIG. 18C is a graph of actual vs. target conductance for the resistor of FIGs. 12A- 12B, according to some embodiments.
  • FIG. 18D is a graph of conductance error vs. target conductance for the resistor of FIGs. 12A-12B, according to some embodiments.
  • FIG. 19 is a graph of calibrated conductance error vs. target conductance for each of the resistors ofFIGs. 11A-11B and 12A-12B, according to some embodiments.
  • the present disclosure provides circuits and systems with fixed impedances (e.g., arranged in an array) that, in accordance with some embodiments, are fast, reliable, highly scalable, and may be programmable for performing multiplication or similar functions.
  • Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between conductive portions of respective layers of the integrated circuit, at least some of the fixed impedances having different fixed impedance values.
  • Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between an input terminal and an output terminal of the integrated circuit, the array having fixed impedance values programmed for multiplying a value of an input signal received at the input terminal to produce an output at the output terminal.
  • Embodiments of the present disclosure may be produced at high scale, efficiently, and reliably by leveraging existing integrated circuit technologies.
  • Memristors are circuit elements that may be programmed with a particular input-to-output transfer function, which may be used to perform a multiplication.
  • a large array of memristors may be programmed to apply respective scalar multiplication to a large number of input signals and thereby perform massively parallel multiplication at high speed.
  • Memristors are particularly attractive for this purpose because they may be easily reprogrammed on-the-fly (e.g., without any changes to their fabricated structure) to obtain different transfer functions, permitting the array to be trained or retrained. For instance, changing the transfer functions of the memristors may update multiplier values (e.g., connection weights used for memristive neuron multiplication). As a result, the same memristive structure could be reused repeatedly and retrained and/or adapted for completely different tasks (e.g., machine learning tasks). [0057] On the other hand, however, the inventors recognized that memristive structures do not presently achieve reliable and accurate processing.
  • memristive structures may be advantageously reprogrammed with different transfer functions
  • memristive structures may not hold their programmed transfer functions with the degree of accuracy needed for consistent and low error computation.
  • memristive technologies may require a tradeoff between performance over time and re-programmability.
  • circuitry with fixed impedances may achieve better performance than memristive structures with a similar programmability advantage.
  • a multiplication may be achieved by processing an input signal using one or more fixed impedances to obtain an output representing a multiple of the input.
  • the multiplier value used to multiply the input value may be programmed (or re-programmed) by selecting a particular subset of fixed impedances to couple in parallel using switches coupled to respective ones of the fixed impedances.
  • an array of fixed impedances having different fixed impedance values may be coupled to and between conductive portions of an integrated circuit (e.g., on different respective layers of the integrated circuit) to provide processing (e.g., multiplication) that is adaptable to a particular application.
  • processing e.g., multiplication
  • multiplication may be adapted using switches coupled in series with the fixed impedances, and/or the same array of fixed impedances may be configured (e.g., at the time of fabrication) into a variety of processing architectures, such as depending on how, how many, and/or which conductive portions of the integrated circuit are coupled to ones of the fixed impedances.
  • circuit structures may be implemented using existing integrated circuit technologies, making the resulting circuits efficient and reliable to produce at scale.
  • Such circuits may be especially useful, when configured as an array for implementing a machine learning inference machine programmed (and/or reprogrammable) to perform multiplication on a large number of inputs.
  • circuits described herein may be useful for a variety of applications, including applications requiring highly parallel processing, such as high-resolution image processing.
  • FIG. 1 is a block diagram of an example system 100 including an integrated circuit (IC) 110 having an array of fixed impedances 112, of which impedance values Rl, R2, R3, and R4 are labeled, according to some embodiments.
  • IC integrated circuit
  • system 100 of FIG. 1 may be formed using a number of integrated circuits on one or more circuit boards, such as a computer motherboard, although a single integrated circuit may be used other some embodiments.
  • at least some components may be in communication with one another over a communication network, such as in a distributed cloud computing environment.
  • an integrated circuit may include one or more semiconductor dies having circuitry fabricated thereon and encapsulated in a package. Multiple dies within an integrated circuit package may be stacked and/or wire bonded together within the package.
  • the integrated circuit 110 may be coupled to a processor, such as a central processing unit (CPU) 102 via an input/output (I/O) interface 104.
  • a processor such as a central processing unit (CPU) 102
  • I/O interface 104 may include a slot on a motherboard having the CPU 102 and integrated circuit 110 mounted and/or otherwise coupled thereto, and/or the CPU 102 and integrated circuit 110 may be bonded together within the same package with the I/O interface 104 including signal-carrying bonds.
  • the CPU 102 and integrated circuit 110 may be in communication over a wired and/or wireless network, as embodiments described herein are not so limited.
  • the processor may be implemented as or include a graphics processing unit (GPU), field programmable gate array (FPGA), and/or application specific integrated circuit (ASIC).
  • GPU graphics processing unit
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • fixed impedances 112 of the integrated circuit 110 may be configured for various analog processing tasks.
  • each fixed impedance 112 may be configured to receive an input signal (e.g., a voltage or current signal) via the I/O interface 104 and to provide, to the I/O interface 104, an output signal (e.g., a current or voltage signal) encoded with respect to the input signal.
  • input-output encoding may be a multiplication product of the input (e.g., indicating a multiplicand) by a scalar multiplier value, with the scalar multiplier value determined by the fixed impedance value of the fixed impedance 112.
  • a characteristic of the input may indicate a multiplicand value for multiplying.
  • groups of fixed impedances 112 may have inputs and/or outputs coupled together such that the output(s) is/are encoded with respect to the input(s) based on a combination (e.g., series and/or parallel combination) of fixed impedance values of the group of fixed impedances 112.
  • a group of fixed impedances 112 may be and/or include a subarray of fixed impedances 112 having different fixed impedance values, as described further below.
  • the fixed impedances 112 of the array may have different fixed impedance values.
  • impedance value R1 may be different from at least some of impedance values R2-R4.
  • impedance values R1 and R3 may be the same fixed impedance value and impedance values R2 and R4 may be the same fixed impedance value.
  • each impedance in a row may have a different fixed impedance value, such as with impedance values Rl, R2, R3, and R4 each being a different fixed impedance value.
  • each impedance in the row may have a binary- weighted impedance value, such as with R2 being twice the impedance value of impedance value Rl, impedance value R3 being twice the impedance value of R2, and impedance value R4 having twice the impedance value of impedance value R3.
  • each impedance of the same column e.g., impedances in the same column as the impedance having impedance value Rl
  • an array of fixed impedances 112 may include subarrays, in which rows and/or columns of a subarray may have fixed impedances with different fixed impedance values, though at least some fixed impedances of one subarray may have the same fixed impedance value(s) as at least some fixed impedances of another subarray.
  • an array may have rows of impedances having binary -weighted fixed impedance values within the row and the same impedance values from one row to another.
  • a subarray may include a first portion of a row of an array with binary- weighted fixed impedance values within the first portion of the row and another subarray may include a second portion of the row with the same binary -weighted fixed impedance values within the second portion.
  • FIG. 2 is a block diagram of an example integrated circuit (IC) 200 having an array 210 of fixed impedances 212 electrically coupled to and between a plurality of conductive portions 202a, 202b of a respective plurality of layers of the integrated circuit 200, according to some embodiments.
  • IC integrated circuit
  • fixed impedances 212 of the integrated circuit 200 may be configured to receive and/or provide signals from and/or to an I/O interface 204 of the integrated circuit 200 via conductive portions 202a, 202b of the integrated circuit 200.
  • a first conductive portion 202a is shown elongated in the direction of a first array dimension (e.g., row direction, horizontal in FIG. 2) and a second conductive portion 202b is shown elongated in the direction of a second array dimension (e.g., column direction, vertical in FIG. 2), though it should be appreciated that conductive portions 202a, 202b may extend in any direction and that array dimensions may not be regular (e.g., for an irregular array).
  • one of the illustrated conductive portions 202a, 202b may be configured to provide an input signal to one or more (e.g., a row) of the fixed impedances and another of the illustrated conductive portions 202a, 202b may be configured to receive an output signal from one or more (e.g., a column) of the fixed impedances.
  • the illustrated conductive portions 202a, 202b may be coupled to input and/or output terminals of the integrated circuit 200 (not shown), which in turn may be coupled to the I/O interface 204.
  • the conductive portions 202a, 202b of the integrated circuit 200 may be disposed on different layers of the integrated circuit 200.
  • conductive portions e.g., 202a
  • conductive portions e.g., 202b
  • conductive portions e.g., 202b
  • receive output signals from fixed impedances 212 may be disposed on a second layer.
  • not all conductive portions configured to provide input signals to fixed impedances 212 need be on the same layer, and that not all conductive portions configured to receive output signals from fixed impedances 212 need be on the same layer, and further, that at least some conductive portions configured to provide input signals to fixed impedances 212 may be disposed on a same layer as at least some conductive portions configured to receive output signals from fixed impedances 212.
  • FIG. 3 A is a block diagram of a first example configuration 300a of an array of fixed impedances 302 configured to receive a plurality of inputs 310a and produce therefrom a plurality of outputs 320a, according to some embodiments.
  • each current signal may represent a multiplication of the voltage signal by a value associated with the fixed impedance value R1 or R2 of the impedance 302.
  • the impedances 302 shown having impedance values R3 and R4 are configured to receive respective inputs 2 and 3 and combine to provide output 3.
  • output 3 may be encoded with an accumulated multiplication of inputs 1 and 2 by respective values associated with the fixed impedance values R3 and R4 of the impedance 302.
  • current signals provided by each impedance 302 shown having impedance values R3 and R4 may represent a multiplication of the respective input 1 or 2 by the value associated with the fixed impedance value R3 or R4 of the respective impedance 302, and the current signals may sum to represent a sum of the multiplication results.
  • FIG. 3B is a block diagram of a second example configuration 300b of an array of fixed impedances 302 configured to receive an input 310b and produce therefrom a plurality of outputs 320b, according to some embodiments.
  • output 1 may represent a multiplication of the input by a value associated with the parallel impedance value of Rl, R2, and R3.
  • output 2 may represent a multiplication of the input by a value associated with the fixed impedance value R4.
  • FIG. 3C is a block diagram of a third example configuration 300c of an array of fixed impedances 302 configured to receive a plurality of inputs 310c and produce therefrom an output 320c, according to some embodiments.
  • impedances 302 having impedance values Rl, R2, R3, and R4 are configured to receive respective inputs 1, 2, 3, and 4 and to provide the output 320c.
  • the output may represent an accumulated multiplication of the inputs 1, 2, 3, 4 by respective values associated with the fixed impedance values Rl, R2, R3, and R4, respectively.
  • FIG. 3D is a block diagram of a fourth example configuration 300d of an array of fixed impedances 302 configured to receive an input 3 lOd and produce therefrom an output 320d, according to some embodiments.
  • impedances 302 having impedance values Rl, R2, R3, and R4 are configured to receive an input 3 lOd and provide an output 320d.
  • the output 320d may represent a multiplication of the input 3 lOd by a value associated with a parallel impedance value of impedance values Rl, R2, R3, and R4.
  • the input 3 lOd provided to the fixed impedances 302 may represent a first value and the output 320d obtained from the fixed impedances 302 may be representative of a second value that is a scalar multiplication of the first value.
  • one of the input 3 lOd and the output 320d may have a voltage signal and the other of the input 3 lOd and the output 320d may have a current signal.
  • the output 320d may have a current amplitude that represents an output value that is a scalar multiple of an input value represented in a voltage amplitude of the input 3 lOd.
  • an input may be a voltage signal having a voltage of 1 Volt (V) and an output may be a current signal having a current of 1 Milliampere (mA).
  • the fixed impedances may apply an impedance of 1 kilohm (kQ) to the input to produce the output.
  • the range of input voltages of the input may be from 1 V to 2 V, representing a range of scalar values from 1 to 2
  • the range of output currents of the output may be from 0.5 mA to 2 mA, representing a range of multiplication results from 1 to 4.
  • the input may represent a scalar value of 1 and the output may represent a multiplication result of 2, indicating that the 1 kQ impedance of the fixed impedances applied a connection weight multiplier of scalar value 2 to the input to produce the output. While this example uses only nonzero voltages and currents as indicating values, other examples may use a zero voltage and/or zero current as indicating a value.
  • an integrated circuit with an impedance configuration may be controllable to set an impedance between the input and the output.
  • each impedance may be within its own selectable path (e.g., with a switch in series with the impedance).
  • the impedance may be controlled by selecting which paths are to be included in an overall parallel path from the input to the output, with at least a portion of the input propagating through each selected path within the parallel path.
  • an input might be applied only to some of the impedances, such that the impedances to which the input is applied are the selected paths.
  • the four impedances having impedance values Rl, R2, R3, and R4 shown in FIG. 3C may have impedance values of IkQ, 2 kQ, 3 kQ, and 4 kQ.
  • impedance values Rl, R2, R3, and R4 shown in FIG. 3C may have impedance values of IkQ, 2 kQ, 3 kQ, and 4 kQ.
  • While this example selects one path to apply an impedance to an input to achieve a desired output, other examples may select multiple paths to provide an overall (e.g., parallel) impedance, as this may provide more resolution (e.g., possible discrete impedance values) in setting the overall impedance.
  • the same fixed impedance structures may be at least partially configurable into each of the configurations of FIGs. 3A-3D.
  • the same fixed impedances 302 having impedance values R1-R4 such as shown in FIGs. 1-2, may be coupled to the same or separate conductive portions configured to provide respective input signals and/or may be coupled to the same or separate conductive portions configured to receive respective output signals.
  • the fixed impedance array configurations shown in FIG. 3C and FIG. 3D may differ only in that the impedances 302 having impedance values R1-R4 are coupled to separate, respective input conductive portions in FIG. 3C whereas the impedances 302 having impedance values R1-R4 are coupled the same input conductive portion in FIG. 3D.
  • the arrangement of fixed impedances in an integrated circuit may be further controlled into an appropriate configuration for the particular application by interconnecting the fixed impedances with conductive portions of the integrated circuit.
  • each fixed impedance of an array may be included in a unit cell with an input and an output (e.g., with the array having a grid of unit cells).
  • the inputs of impedances 302 having impedance values R1 and R2 may be coupled together by having a same input conductive portion connect to the unit cells that include the respective impedances R1 and R2, whereas the outputs of impedances 302 having impedance values R1 and R2 may separate by having separate output conductive portions connect to the respective unit cells.
  • FIG. 4 is a top view of a first example array 400 of fixed impedances electrically coupled to and between a plurality of conductive portions 410a, 410b of an integrated circuit, according to some embodiments.
  • the array 400 includes a grid of unit cells 420, each including a pair of electrodes 422a, 422b connected by a resistive region 424.
  • the unit cell 420 identified by dashed box in FIG. 4 is further connected to a first conductive portion 410a extending in the row direction (horizontally in FIG. 4), which may be configured to provide an input signal to the unit cell 420, and a second conductive portion 410b extending in the column direction (vertically in FIG. 4), which may be configured to receive an output signal from the unit cell 420.
  • the first conductive portion 410a may be coupled to the unit cell 420 at a first electrode 422a of the electrodes 422a, 422b and the second conductive portion 410b may be coupled to the unit cell 420 at a second electrode 422b of the electrodes 422a, 422b, such that the input signal may flow through the resistive region 424 and emerge therefrom as the output signal.
  • the resistive region 424 may have a fixed resistance value to form at least a portion of a fixed impedance, as described further below.
  • conductive portions 410a, 410b of the integrated circuit may be coupled to multiple unit cells 420, such as to provide an input signal to multiple fixed impedances and/or to receive an output signal from multiple fixed impedances.
  • a conductive portion 410b is shown extending in the column direction, between the fourth and fifth columns.
  • the conductive portion 410b may be configured to receive output signals from each fixed impedance in the fourth column (e.g., through contact with the electrodes 422b over which the conductive portion 410b extends in FIG. 4).
  • the illustrated conductive portion 410b may be configured to combine current signals output from the fixed impedances (e.g., as described in connection with FIGs. 3C- 3D). In other embodiments, the illustrated conductive portion 410b may be configured to provide the same signal (e.g., a voltage signal) to the fixed impedances (e.g., as described in connection with FIGs. 3B and 3D).
  • the same signal e.g., a voltage signal
  • fixed impedances of the unit cells 420 of the array 400 may have different impedance values, such as due to differences in geometries of the fixed impedances.
  • the resistive regions 424 of some of the unit cells 420 in the array differ in their width and number of meandering sections.
  • the resistive regions 424 may have conductive traces, whose geometries (e.g., width and number of meandering sections) may impact the resistance of the trace, thereby providing the resistance value of the resistive region 424.
  • some unit cells 420 have impedances with the same fixed impedance values, as the resistive regions 424 have identical geometries (e.g., widths and numbers of meandering sections), whereas other unit cells 420 have impedances with different fixed impedance values, as the resistive regions 424 have different geometries.
  • FIG. 5 A is a side view of a cross-section of a portion 500a of an example integrated circuit including a fixed impedance 532a coupled to and between a first conductive portion 512 on a first layer 510a and a second conductive portion 522a on a second layer, with the fixed impedance 532a on a third layer 530a that is above or below each of the first layer 510a and the second layer 520a, according to some embodiments.
  • FIG. 5A three layers 510a-530a of an integrated circuit are shown, with a first conductive portion 512 and a second conductive portion 522a on a respective first layer 510a and second layer 520a and a fixed impedance 532a on a third layer 530a.
  • the portion 500a of the integrated circuit shown in FIG. 5 A may correspond to the unit cell 420 identified by dashed box in FIG. 4.
  • the first conductive portion 512 and the second conductive portion 522a shown in FIG. 5 A may be elongated in different directions.
  • 5 A may have a resistive region (e.g., 424) coupled between first and second electrodes (e.g., 422a, 422b), such as shown in FIG. 4.
  • first and second electrodes e.g., 422a, 422b
  • the fixed impedance 532a is shown on the third layer 530a, which is an end (e.g., top or bottom) layer of the illustrated portion 500a of the structure, and the first conductive portion 512 and the second conductive portion 522a are disposed on first layer 510a and second layer 520a, respectively, which are each above or each below the fixed impedance 532a.
  • the second layer 520a having the second conductive portion 522a is shown directly adjacent the third layer 530a having the fixed impedance 532a such that the second conductive portion 522a may directly contact an electrode of the fixed impedance 532a
  • the first layer 510a having the first conductive portion 512 is shown separated from the third layer 530a having the fixed impedance 532a by the second layer 520a having the second conductive portion 522a, with a via 526 connecting the fixed impedance 532a to the first conductive portion 512.
  • FIG. 5B is a side view of a cross-section of a portion 500b of an alternative example integrated circuit including a fixed impedance 522b coupled to and between a first conductive portion 512 on a first layer 510a and a second conductive portion 532b on a second layer 530b, with the fixed impedance 522b on a third layer 520b that is between the first layer 510a and the second layer 530b, according to some embodiments.
  • FIG. 5B three layers of an alternative integrated circuit are shown configured similar to FIG. 5B.
  • the impedance 522b is shown on a third layer 520b that is between the first layer 510a that has the first conductive portion 512 and the second layer 530b that has the second conductive portion 532b.
  • the first layer 510a having the first conductive portion 512 and the second layer 530b having the second conductive portion 532b, respectively are shown directly adjacent and on opposing sides of the third layer 520b having the impedance 522b on opposite sides, such that the impedance 522b may directly contact the first conductive portion 512 on a first side and directly contact the second conductive portion 532b on a second side.
  • An insulator 514 is shown on the first layer 510b including the first conductive portion 512 and an insulator 534b is shown on the second layer 530b including the second conductive portion 532b, which may be configured to maintain electrical separation from other portions of the impedance 522b.
  • any portion of the impedance may be coupled to the respective conductive portions by vias rather than or in addition to direct contact.
  • any subset or each of the layers shown in FIGs. 5A-5B may be separate wafers, which may be wire and/or pad bonded to one another within an integrated circuit package.
  • FIG. 6A is a top view of example array 600 of fixed impedances, according to some embodiments.
  • FIG. 6B is a magnified view of a quadrant 602 of the array 600, according to some embodiments.
  • the array 600 includes first trace pads 604a and second trace pads 604b which may be configured as part of an VO interface of an integrated circuit, such as to obtain or provide signals outside of the integrated circuit.
  • first trace pads 604a and second trace pads 604b may be configured as bond pads for the integrated circuit.
  • first trace pads 604a may be coupled to fixed impedances of the array 600 via first traces 606a and second trace pads 604b may be coupled to fixed impedances of the array 600 via second traces 606b.
  • first traces 606a may be coupled to and/or may form part of first conductive portions of the array 600 and second traces 606b may be coupled to and/or may form part of second conductive portions of the array 600.
  • FIG. 6A is further intended to convey that an array of fixed impedances, such as shown in FIGs. 6A-6B, may include as many as thousands or millions of unit cells, making such an array useful for highly parallel analog signal processing applications, such as machine learning inference processing and/or high-resolution image processing. It should be appreciated, however, that any number of fixed impedances may be included without departing from the scope of the present aspects.
  • FIG. 7A is a top view of a first example resistor 700 that may be included in the array 400 of FIG. 4, according to some embodiments.
  • the resistor 700 includes a resistive region 704 connected between a pair of electrodes 702a, 702b, each electrode 702a, 702b connected to a respective conductive portion 706a, 706b, such as in FIG. 4.
  • the fixed impedance of each unit cell (e.g., 420) of an array (e.g., 400) may include a resistor 700, which may provide substantially all of the impedance of the unit cell.
  • other forms of impedance such as inductance and/or capacitance, may be negligible in comparison to the amount of resistance provided by the resistive region, resulting in substantially all of the impedance of the structure to be in its real component as opposed to its imaginary component.
  • FIG. 7B is a perspective view of the resistor 700, according to some embodiments.
  • FIG. 7C is a top view of the resistive region 704 and electrodes 702a, 702b of the resistor 700, according to some embodiments.
  • a resistor 700 having a conductive trace in its resistive region 704, such as shown in FIGs. 7A-7C, may be fabricated with a fixed impedance value by controlling, among other factors, its conductive material, trace width, and length (e.g., number of trace meandering sections). For the resistor 700 shown in FIGs.
  • the conductance of the resistor may be given by the following equation: where ⁇ J is the conductivity of the trace material, w is the width of the trace, t is the thickness of the trace (e.g., in the plane orthogonal to its width and to its direction of elongation), I is the length of the trace, and N is the number of comers in the meandering conductive geometry of the trace. It should be appreciated that this equation may be adapted in cases where any one of the factors (e.g., conductivity, width, thickness, or shape of the meandering conductive geometry) is nonuniform in the trace, such as where the meandering geometry is non-periodic.
  • the factors e.g., conductivity, width, thickness, or shape of the meandering conductive geometry
  • FIG. 8A is a top view of an example unit cell 820 that may be included in an array 800 of fixed impedances, the unit cell 820 including a resistor in series with a transistor 826, according to some embodiments.
  • the resistor shown in FIG. 8A may be configured as described herein for resistor 700.
  • the illustrated unit cell 820 includes a resistor including an impedance 824 coupled between electrodes 822a, 822b and, in addition to the resistor, a transistor 826.
  • the transistor 826 may be configured to couple and decouple the resistor to and/or from one of a first conductive portion 810a and a second conductive portion 810b of the integrated circuit.
  • the transistor 826 has a first channel terminal (e.g., source S) coupled to the second conductive portion 810b, a second channel terminal (e.g., drain D) coupled to the resistor, and a control terminal (e.g., gate G) coupled to a switch-control conductive portion 812, and the resistor is coupled between the transistor 826 and the first conductive portion 810a. Accordingly, as shown, the transistor 826 may couple the resistor to the second conductive portion 810b or decouple the resistor from the second conductive portion 810b, depending on the signal received via the switch-control conductive portion 812.
  • a first channel terminal e.g., source S
  • a second channel terminal e.g., drain D
  • a control terminal e.g., gate G
  • FIG. 8B is a top view of an alternative example unit cell 850 that may be included in an array of fixed impedances, the unit cell 850 including a plurality of resistors in series with respective transistors 860a, 860b, 860c, and 860d and sharing an electrode 874, according to some embodiments.
  • each resistor shown in FIG. 8B may be configured as described herein for resistor 700.
  • the unit cell 850 includes four fixed impedances in series with respective switches.
  • the unit cell 850 of FIG. 8B includes four conductive traces 870a, 870b, 870c, and 870d, each coupled in series with a respective transistor 860a, 860b, 860c, and 860d.
  • each trace 870a, 870b, 870c, and 870d terminates at one end at a respective electrode 872a, 872b, 872c, 872d coupled to the respective transistor 860a, 860b, 860c, 860d.
  • FIG. 8A the unit cell 850 of FIG. 8B includes four conductive traces 870a, 870b, 870c, and 870d, each coupled in series with a respective transistor 860a, 860b, 860c, and 860d.
  • each trace 870a, 870b, 870c, and 870d terminates at one end at a respective electrode 872a, 872b, 872c, 872
  • each trace 870a, 870b, 870c, and 870d terminates at another end at a common electrode 874.
  • each trace 870a, 870b, 870c, and 870d may have a different fixed impedance value, such as due to different meandering trace geometries. It should be appreciated that, in some embodiments, at least some traces within a unit cell may have the same fixed impedance value.
  • unit cells 850 of FIG. 8B may have different fixed impedances (e.g., combinations of fixed impedances) along at least a part of each row and/or column, depending on the application.
  • the unit cell 850 of FIG. 8B may be coupled to and between one or more first conductive portions and a second conductive portion.
  • channel terminals of transistors 860a, 860b, 860c, and 860d may be coupled to one first conductive portion and the common electrode 874 may be coupled to the second conductive portion, such that the series pairs of fixed impedances and transistors are coupled in parallel with one another.
  • control terminals of transistors 860a, 860b, 860c, and 860d may be configured to receive respective signals selecting the respective trace 870a, 870b, 870c, and 870d, which may set the parallel impedance that the unit cell 850 provides between the first conductive portion and the second conductive portion.
  • at least some channel terminals of transistor 860a, 860b, 860c, and 860d may be coupled to respective first conductive portions.
  • control terminals of transistor 860a, 860b, 860c, and 860d may be configured to receive respective signals selecting the respective trace 870a, 870b, 870c, and 870d, which may select which first conductive portion(s) to couple to.
  • one or more input signals may be received at transistor 860a, 860b, 860c, and 860d, and/or at the common electrode 874, and/or one or more output signals may be provided at transistor 860a, 860b, 860c, and 860d, and/or at the common electrode 874, depending on the application.
  • an integrated circuit may be reconfigurable (e.g., based on interaction with input and output terminals at the VO interface) to use the same unit cell in either configuration.
  • transistors shown in FIGs. 8A-8B are metal-oxide-semiconductor fieldeffect transistors (MOSFETs), it should be appreciated that other transistors may be used, such as bipolar junction transistors (BJTs).
  • MOSFETs metal-oxide-semiconductor fieldeffect transistors
  • BJTs bipolar junction transistors
  • FIG. 9A is a graph 900a of logscale area for the resistor 700 of FIG. 7A vs. the width and length (in microns) of the resistor 700, according to some embodiments.
  • FIG. 9B is a graph 900b of conductance gradient for the resistor 700 of FIG. 7A vs. the width and length (in microns) of the resistor 700, according to some embodiments.
  • FIG. 9C is a graph 900c identifying logscale conductance-based and logscale area-based constrained regions of the width and length (in microns) for the resistor 700 of FIG. 7A, according to some embodiments.
  • FIG. 9A is a graph 900a of logscale area for the resistor 700 of FIG. 7A vs. the width and length (in microns) of the resistor 700, according to some embodiments.
  • FIG. 9B is a graph 900b of conductance gradient for the resistor 700 of FIG. 7A vs. the width and length (in micron
  • FIG. 9D is a graph 900d identifying a range of width-length pairs (in microns) for the resistor 700 of FIG. 7A satisfying the constraints of the graph 900c of FIG. 9C, according to some embodiments.
  • logscale area may follow the length and width of the resistor 700 of FIG. 7A-7C. For example, widening the conductive trace and/or elongating its meandering path may cause the footprint to expand.
  • the gradient of conductance indicates the impact on the conductance value of a conductive trace due to adjusting the width of the conductive trace at a given length of the conductive trace. As may be discerned from FIG.
  • lengthening the trace decreases the conductance gradient, thus tolerating a larger range of widths at which the conductance may remain within a desired conductance range.
  • the change in conductance may be much more significant at a length of 20 microns than at a length of 100 microns.
  • a minimum length may be needed (e.g., specific to the application) such that the conductance of the trace as manufactured (e.g., within practical manufacturing tolerances for trace width) is within an acceptable range of the desired conductance. For example, where the length is below minimum, a change in width due to expected manufacturing error may cause a significant conductance error too large to be tolerated in the particular application.
  • the amount of area permitted for the application may be set by external factors, such as the maximum size of the integrated circuit and/or number of resistors and/or unit cells that must fit in the integrated circuit.
  • the desired conductance gradient may be set by external factors, such as the amount of conductance error tolerated in the application.
  • the signal-to-noise ratio (SNR) of an analog signal processed by the resistor may be impacted by the conductance error in the structure, which is the difference between the actual fabricated conductance of the resistor compared to the target conductance for which the resistor was intended to be fabricated (e.g., which may correspond to a conductance expected by a processor interfacing with the resistor).
  • the amount of area permitted corresponds to the right curve separating the center region of the graph from the area constraining region
  • the amount of tolerated conductance area corresponds to the left curve separating the center region of the graph from the conductance error constraining region.
  • the possible length and width combinations for the resistor satisfying both constraints lie in the center region.
  • FIG. 9D a subset of length and width values lying on the right curve from FIG. 9C are identified as appropriate length and width values maximizing a given area while achieving a given conductance.
  • FIG. 10 is a top view of a second example array 1000 of fixed impedances electrically coupled to and between a plurality of conductive portions 1010a, 1010b of an integrated circuit, according to some embodiments.
  • the array 1000 shown in FIG. 10 may be configured in the manner described herein for the array 400 shown in FIG. 4.
  • the array 1000 includes a grid of unit cells 1020, each unit cell 1020 including a resistive region 1024.
  • first conductive portion 1010a extending in the row direction (horizontally in FIG. 10), which may be configured to provide an input signal to the unit cell 1020
  • second conductive portion 1010b extending in the column direction (vertically in FIG. 10), which may be configured to receive an output signal from the unit cell 1020.
  • the first conductive portion 1010a may be coupled to the unit cell 1020 at one or more contact points of the resistive region 1024 and the second conductive portion may be coupled to the unit cell 1020 at another one or more contact points of the resistive region 1024, such that the input signal may flow through the resistive region 1024 and emerge therefrom as the output signal.
  • the resistive region 1024 may have a fixed resistance value to form at least a portion of a fixed impedance.
  • each resistive region 1024 has a plurality of channels 1026.
  • the resistive region 1024 may include material (e.g., semiconductor material) with channels 1026 disposed therein to provide conductive paths from the first conductive portion 1010a to the second conductive portion 1010b.
  • the channels 1026 of each resistive region 1024 are disposed in a passivation structure 1028 that may electrically separate the channels 1026 from one another so as to dispose the channels 1026 in parallel with one another.
  • fixed impedances of the unit cells 1020 of the array 1000 may have different impedance values.
  • the resistive regions 1024 of some of the unit cells 1020 in the array differ in their number and size of channels 1026.
  • the number and size of the channels 1026 of a channelbased resistive region 1024 may impact the resistance of the resistive region 1024, thereby providing the resistance value of the resistive region 1024.
  • FIG. 11 A is a side view of a cross-section of a unit cell 1100 containing a second example resistor that may be included in the array 1000 of FIG. 10, according to some embodiments.
  • the resistor has a first electrode 1102a, a second electrode 1102b, a channel 1104 coupled between the first electrode 1102a and the second electrode 1102b, and a passivation structure 1108 disposed, at least in part, between the first electrode 1102a and the second electrode 1102b. While shown as a layer of the resistor in FIG.
  • the first electrode 1102a may be at least a part of, and/or may be coupled to, a first conductive portion (e.g., 1010a) on a first layer and the second electrode 1102b may be at least a part of, and/or may be coupled to, a second conductive portion (e.g., 1010b) on a second layer.
  • a first conductive portion e.g., 1010a
  • a second conductive portion e.g., 1010b
  • the resistor may be configured as a semiconductor element.
  • the channel 1104 may include semiconductor material, such as may be used in a thin-film resistor.
  • the resistance of the resistor may be fixed based on a size of the channel 1104. For example, substantially all current flowing in the resistor may flow through the channel 1104 from and/or to the first electrode 1102a to and/or from the second electrode 1102b. In this example, the cross-sectional area, length (e.g., from the first electrode to the second electrode), and conductivity of the semiconductor material of the channel 1104 may fix the resistance provided by the channel 1104.
  • the impact of the length of the channel 1104 on its resistance may be negligible compared to the impact of cross-sectional area.
  • semiconductor material is described, other materials may be alternatively or additionally used to provide resistance, such as carbon, metal-oxides, metals, transition-metal dichalcogenides, and/or polymers, and similar techniques may be used to obtain a desired resistance value.
  • the passivation structure 1108 may be configured to electrically separate the first electrode 1102a from the second electrode 1102b.
  • the passivation structure 1108 may include insulative material, such as silicon dioxide.
  • the passivation structure 1108 has an opening 1106 through which the channel 1104 is coupled to the first electrode 1102a.
  • the opening 1106 may form a contact point.
  • the resistance of the resistor may be fixed, at least in part, by the size (e.g., cross-sectional area) of the contact point, which in turn may be fixed by the size of the opening 1106.
  • the passivation structure 1108 may be configured to electrically separate the channel 1104 from the first electrode 1102a at locations other than the contact point.
  • the passivation structure 1108 is shown disposed on opposing sides (e.g., horizontally in FIG. 11 A) of the channel 1104 between the channel 1104 and portions of the first electrode 1102a that extend (e.g., vertically in FIG. 11 A) toward the second electrode 1102b.
  • the passivation structure 1108 may partially and/or completely surround the channel 1104, such as at the opening 1106 and/or where the first electrode 1102a is separated from the channel 1104 by the passivation structure 1108. It should be appreciated that more than one passivation structure may be included, depending on the application, such as using a plurality of passivation structures in place of the single passivation structure 1108 shown in FIG. 11 A.
  • FIG. 1 IB is a perspective view of the unit cell 1100 of FIG. HAwith the first electrode 1102a and a portion of the passivation structure 1108 removed, according to some embodiments.
  • the channel 1104 may have a rectangular cross-section exposed through the opening 1106 in the passivation structure 1108.
  • the first electrode 1102a and portions of the passivation structure 1108 that may electrically separate the channel 1104 from the first electrode 1102a have been removed.
  • the cross-sectional area of the channel 1104 that is exposed at the opening to form a contact point is smaller than the largest cross-sectional area of the channel 1104 (e.g., where exposed horizontally in FIG. 11B).
  • the conductance of the resistor may be given by the following equation:
  • G re sistor where ⁇ J is the conductivity of the channel material, A is the cross-sectional area of the channel 1104 at its contact point with an electrode (e.g., which may be limited by the size of an opening in the passivation structure), and t is the thickness of the trace (e.g., in the direction from the first conductive portion to the second conductive portion). It should be appreciated that this equation may be adapted in cases where any one of the factors (e.g., conductivity, area, or thickness) is nonuniform in the resistor. Where a resistor has multiple channels (e.g., FIGs.
  • the conductance of the resistor may be a sum of conductance of all channels in the resistor (e.g., using equivalent parallel conductance). In some cases, the conductance may reduce into the same equation as above, but with the area A including the total cross-sectional area of all channels at their respective contact points (e.g., where other parameters are substantially uniform). [0121] The inventors recognized that, in some embodiments, the length (e.g., vertically in FIGs.
  • the resistance of the channel-based resistor may be controlled substantially entirely by the size of the opening 1106 formed in the passivation structure 1108, which, advantageously, may be easily controlled using existing integrated circuit fabrication techniques.
  • FIG. 12A is a side view of a cross-section of a unit cell 1200 containing a third example resistor that may be included in the array 1000 of FIG. 10, according to some embodiments.
  • FIG. 12B is a perspective view of the unit cell 1200 of FIG. 12A with the first electrode 1202a and a portion of the passivation structure 1208 removed.
  • the resistor of FIGs. 12A-12B may be configured as described herein for the resistor of FIGs. 11A-11B, such as including a first electrode 1202a, a second electrode 1202b, and a passivation structure 1208.
  • the resistor is configured as a channel-based resistor with a plurality of channels 1204 coupled between the first electrode 1202a and the second electrode 1202b.
  • the size and/or number of the channels 1204 may fix the resistance of the channel-based resistor. For example, a large number of channels 1204 may provide a low resistance compared to a small number of channels 1204. Similar to as described above in connection with FIGs.
  • openings 1206 may be formed in the passivation structure 1208 to form contact points between the channels 1204 and the first electrode 1202a. In some embodiments, openings may not need to be provided proximate the second electrode 1202b where openings 1206 are provided proximate the first electrode 1202a (or vice versa). For example, as shown in FIGs. 12A-12B, at the opposite (e.g., bottom) end of the resistor, the channels 1204 of the resistor terminate, proximate the second electrode 1202b, in a single structure of channel material that contacts the second electrode 1202b. As described above in connection with FIGs.
  • the channels 1204 may have small enough lengths that the resistance of the channels 1204, in combination, may be controlled substantially entirely by the sizes and/or number of openings 1206 formed in the passivation structure 1208 (e.g., proximate the first electrode in FIG.
  • FIG. 13 A is a top view of a plurality of conductive portions 1120b configured as electrodes 1102b for a plurality of resistors of FIGs. 11A-11B, according to some embodiments.
  • FIG. 13B is a side view of a cross-section of one of the conductive portions 1120b of FIG. 13 A, according to some embodiments.
  • three conductive portions 1120b may be configured to provide electrodes 1102b for an array of resistors of FIGs. 11A-11B, such as with each electrode 1102b being at least a part of the respective conductive portion 1120b.
  • each conductive portion 1120b may be configured to provide an input signal to three resistors, such that the illustrated array is configured to receive and provide three input signals to nine resistors. It should be appreciated that the illustrated array could be configured to support more than three resistors per conductive portion, and/or that more or fewer conductive portions may be included.
  • FIG. 14A is a top view of the conductive portions 1120b of FIG. 13 A with channels 1104 coupled to the conductive portions 1120b, according to some embodiments.
  • FIG. 14B is a side view of a cross-section of one of the conductive portions 1120b and one of the channels 1104 of FIG. 14A, according to some embodiments.
  • each conductive portion 1120b is coupled to three respective channels 1104, which may be configured as described above in connection with FIGs. 11A- 12B.
  • each channel 1104 may have a smaller cross-sectional area than the conductive portion 1120b in an array direction (e.g., row or column) perpendicular to the direction of elongation of the conductive portion 1120b.
  • each channel 1104 may be configured as its own resistor, with the resistance of the resistor fixed based on the size (e.g., cross-sectional area) of the channel 1104.
  • each resistor may have more than one channel (e.g., as in FIGs. 12A-12B).
  • the channels of each resistor may be interconnected via channel material.
  • FIG. 15A is a top view of the conductive portions 1120b and channels 1104 of FIG. 14Awith a passivation structure 1108 having openings 1106 for the channels 1104, according to some embodiments.
  • FIG. 15B is a side view of a cross-section of one of the conductive portions 1120b, one of the channels 1104, and a portion of the passivation structure 1108 of FIG. 15 A, according to some embodiments.
  • a passivation structure 1108 may be disposed between and/or over the channels 1104 and conductive portions 1120b.
  • the passivation structure 1108 may be configured to electrically separate the channels 1104 from one another, to electrically separate the electrodes 1102a, 1102b from one another (e.g., conductive portions 1120a and 1120b in FIGs. 16A-16B), and/or to electrically separate the channels 1104 from the electrodes 1102a, 1102b.
  • an opening 1106 in the passivation structure 1108 exposes the channel 1104 for coupling to another electrode (e.g., conductive portion 1120a in FIGs. 16A-16B).
  • the passivation structure 1108 may be configured to electrically separate the channels 1104 from the electrodes 1102a, 1102b except where the channels 1104 form contact points with the electrodes 1102a, 1102b, such as through the openings 1106.
  • FIG. 16A is a top view of an array of resistors of FIGs. 11A-11B, according to some embodiments.
  • FIG. 16B is a side view of a cross-section of one of the resistors of FIG. 15 A, according to some embodiments.
  • an additional layer of conductive portions 1120a is elongated perpendicularly to the conductive portions 1120b of FIGs. 13A-13B and configured to form electrodes (e.g., 1102a) of the resistors, such as with each electrode being at least a part of the respective conductive portion 1120a.
  • each of the conductive portions 1120a further shown in FIGs. 16A-16B may be configured to obtain an output signal combined from three resistors, such that the illustrated array is configured to receive and provide three input signals to nine resistors and obtain three output signals from the nine resistors. It should be appreciated that more or fewer output-configured conductive portions 1120a may be included. It should also be appreciated that either set of conductive portions 1120a, 1120b shown in FIGs. 16A-16B could be configured for input signals or for output signals, as embodiments described herein are not so limited.
  • the resistor array shown in FIG. 16A may include nine unit cells, of which one unit cell 1100 is identified by dashed box. Each illustrated unit cell has a resistor configured as a channel-based resistor with a single channel 1104 coupled between a first conductive portion 1120a and a second conductive portion 1120b, though in other embodiments multiple channels may be included (e.g., as shown in FIGs. 12A-12B).
  • the single channel 1104 of each illustrated unit cell in FIGs. 14A-16A has a same size, which may provide the same fixed impedance value, although in other embodiments channels of different sizes may be used, and/or channel-based resistors may have multiple channels with different sizes and/or numbers of channels per resistor.
  • FIG. 17 is a top view of an example unit cell 1700 that may be included in an array of fixed impedances, the unit cell 1700 including the resistor of FIGs. 11A-11B in series with a transistor 1730, according to some embodiments.
  • the unit cell 1700 shown in FIG. 17 may be configured as described herein in connection with FIG. 8 A.
  • the illustrated unit cell 1700 includes a resistor configured as a channelbased resistor having a channel 1720 (e.g., as in FIGs.
  • the unit cell 1700 further includes a transistor 1730.
  • the transistor 1730 may be configured to couple and decouple the resistor to and/or from a conductive portion 1710a of the integrated circuit.
  • the transistor 1730 has a first channel terminal (e.g., source S) coupled to the first conductive portion 1710a, a second channel terminal (e.g., drain D) coupled to the resistor, and a control terminal (e.g., gate G) coupled to a switch-control conductive portion 1712, and the resistor is coupled between the transistor 1730 and the second conductive portion 1710b.
  • the transistor 1730 may couple the resistor to the first conductive portion 1710a or decouple the resistor from the first conductive portion 1710a, depending on the signal received via the switch-control conductive portion 1712, as described herein in connection with FIG. 8 A.
  • the unit cell 1700 of FIG. 17 may be alternatively or additionally configured like the unit cell 820 of FIG. 8B, such as by including multiple transistors (e.g., series coupled to respective channelbased resistors) within the same unit cell.
  • FIG. 18A is a graph 1800a of actual vs. target conductance (in microSiemens (pS)) for the resistor of FIGs. 11A-11B, according to some embodiments.
  • FIG. 18B is a graph 1800b of conductance error vs. target conductance for the resistor of FIGs. 11 A-l IB, according to some embodiments.
  • FIG. 18C is a graph 1800c of actual vs. target conductance for the resistor of FIGs. 12A-12B, according to some embodiments.
  • FIG. 18D is a graph 1800d of conductance error vs. target conductance for the resistor of FIGs. 12A-12B, according to some embodiments.
  • FIGs. 18A-18D illustrate how the resistors of FIGs. 11A- 11B and 12A-12B may exhibit different conductance error behavior that may make the resistors more suitable for different applications.
  • FIGs. 18A and 18C illustrate the difference between actual and target conductance of channel -based resistors of FIGs.
  • FIGs. 18B and 18D illustrate the difference between conductance error for the resistors of FIGs. 11A-11B and 12A-12B, respectively, from which it can be discerned that conductance error for the resistor of FIGs.
  • connection weights used by the neuron to multiply an input value may be linearly mapped to conductance of the resistors, in which case linear conductance error may be beneficial.
  • resistor of FIGs. 12A-12B may benefit from using the resistor of FIGs. 12A-12B due to a larger range and/or resolution of possible conductance values that may be obtained, in some cases, since both the size and number of channels may be adjusted to reach a particular conductance value in the resistor. It should be appreciated that these and/or other design considerations may make either of the resistors of FIGs. 11A-11B and/or 12A-12B appropriate for a particular application.
  • FIG. 19 is a graph 1900 of calibrated conductance error vs. target conductance for each of the resistors of FIGs. 11A-11B and 12A-12B, according to some embodiments.
  • calibrated conductance may be the actual conductance of a resistor normalized with respect to (e.g., divided by) the actual conductance of the resistor with the largest actual conductance.
  • the calibrated conductance error in the graph 1900 of FIG. 19 may be the differences between normalized actual conductance of the resistor compared to normalized target conductance (e.g., normalized to the largest target conductance). For instance, in the graph 1900 of FIG.
  • the calibrated conductance error at a given target conductance may be obtained by normalizing the actual conductance (e.g., 10.6 in graph 1800a of FIG. 18A) by the maximum actual conductance (e.g., 15.8 in the graph 1800a of FIG. 18 A) and determining the difference between the normalized actual conductance (e.g., 10.6/15.8) and the normalized target conductance (e.g., 10/15, from normalizing the target conductance of 10 by the maximum target conductance of 15 in the graph 1800b of FIG. 18B).
  • calibrated conductance error may be characterized, at least in part, by the difference in linearity of conductance error between the resistors of FIGs. 11A-11B and 12A-12B.
  • the calibrated conductance error for the resistor of FIGs. 11 A-l IB reaches a peak magnitude of almost 0.2, at a target conductance of about 4, with respect to the minimum calibrated conductance error at the minimum and maximum target conductance.
  • the calibrated conductance error of the resistor of FIGs. 12A- 12B has a magnitude less than 0.05 for all target conductance values, and the calibrated conductance error oscillates about a line, indicating that a linear response of calibrated conductance error may be advantageously leveraged (e.g., when linearly mapping conductance to connection weights for use in a neural network).
  • One or more aspects and embodiments of the present disclosure involving the performance of processes or methods may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform, or control performance of, the processes or methods.
  • a device e.g., a computer, a processor, or other device
  • inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above.
  • the computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various ones of the aspects described above.
  • computer readable media may be non-transitory media.
  • program or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present disclosure need not reside on a single computer or processor, but may be distributed in a modular fashion among a number of different computers or processors to implement various aspects of the present disclosure.
  • Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • data structures may be stored in computer-readable media in any suitable form.
  • data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields.
  • any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.
  • the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
  • a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer, as non-limiting examples. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smartphone or any other suitable portable or fixed electronic device.
  • PDA Personal Digital Assistant
  • a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible formats.
  • Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet.
  • networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.
  • some aspects may be embodied as one or more methods.
  • the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
  • resistive regions providing substantially the entire impedance of a unit cell
  • fixed impedances described herein may have substantial imaginary impedance, such as inductance and/or capacitance.
  • inductance and/or capacitance within some or each of the unit cells, as an alternative or in addition to a resistive region may provide alternative or additional encoding of input values.
  • input signals may include frequency information (e.g., frequency modulation) and output signals may be encoded based on the fixed impedance value(s) of the unit cell(s), such as using frequency-based filtering (e.g., based on the resonance frequency or frequencies of a combined inductance and capacitance of the unit cell) and/or phase shift keying (e.g., based on a phase shift introduced by the inductance and/or capacitance of the unit cell).
  • frequency-based filtering e.g., based on the resonance frequency or frequencies of a combined inductance and capacitance of the unit cell
  • phase shift keying e.g., based on a phase shift introduced by the inductance and/or capacitance of the unit cell.
  • a reference to “A and/or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A without B (optionally including elements other than B); in another embodiment, to B without A (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
  • the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
  • This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.
  • “at least one of A and B” can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

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Abstract

L'invention concerne des circuits et des systèmes à impédances fixes (par exemple, agencés dans un réseau) qui, selon certains modes de réalisation, peuvent être programmables pour effectuer une multiplication ou des fonctions similaires. Certains modes de réalisation de la présente divulgation concernent un circuit intégré avec un réseau d'impédances fixes couplées à et entre des parties conductrices de couches respectives du circuit intégré, au moins certaines des impédances fixes ayant différentes valeurs d'impédance fixes. Certains modes de réalisation de la présente divulgation concernent un circuit intégré avec un réseau d'impédances fixes couplées à et entre une borne d'entrée et une borne de sortie du circuit intégré, le réseau ayant des valeurs d'impédance fixes programmées pour multiplier une valeur d'un signal d'entrée reçu au niveau de la borne d'entrée pour produire une sortie au niveau de la borne de sortie. Des modes de réalisation de la présente divulgation peuvent être produits à grande échelle, de manière efficace et fiable en exploitant des technologies de circuit intégré existantes.
PCT/US2024/051663 2023-10-17 2024-10-16 Réseau d'impédance fixe géométriquement programmable Pending WO2025085571A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100156840A1 (en) * 2008-02-28 2010-06-24 Frey Matthew H Touch screen sensor having varying sheet resistance
US20170279425A1 (en) * 2016-03-23 2017-09-28 Infineon Technologies Ag System and Method for Signal Amplification Using a Resistance Network
US20200395053A1 (en) * 2019-06-12 2020-12-17 Nokia Technologies Oy Integrated circuits
US20220373584A1 (en) * 2021-05-20 2022-11-24 Changxin Memory Technologies, Inc. Contact resistor test method and device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100156840A1 (en) * 2008-02-28 2010-06-24 Frey Matthew H Touch screen sensor having varying sheet resistance
US20170279425A1 (en) * 2016-03-23 2017-09-28 Infineon Technologies Ag System and Method for Signal Amplification Using a Resistance Network
US20200395053A1 (en) * 2019-06-12 2020-12-17 Nokia Technologies Oy Integrated circuits
US20220373584A1 (en) * 2021-05-20 2022-11-24 Changxin Memory Technologies, Inc. Contact resistor test method and device

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