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WO2025084080A1 - Semiconductor device, production method for same, and power conversion device - Google Patents

Semiconductor device, production method for same, and power conversion device Download PDF

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Publication number
WO2025084080A1
WO2025084080A1 PCT/JP2024/034081 JP2024034081W WO2025084080A1 WO 2025084080 A1 WO2025084080 A1 WO 2025084080A1 JP 2024034081 W JP2024034081 W JP 2024034081W WO 2025084080 A1 WO2025084080 A1 WO 2025084080A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
metal block
block
substrate
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/034081
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French (fr)
Japanese (ja)
Inventor
純司 藤野
稔 江草
裕基 滝下
翔平 小川
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Publication of WO2025084080A1 publication Critical patent/WO2025084080A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D

Definitions

  • This disclosure relates to a semiconductor device having a main terminal for transmitting external signals, such as a power module.
  • Patent Document 1 discloses a component mounting board on which electronic components such as power transistors are mounted. The above-mentioned electronic components become the constituent elements of a power module.
  • Power modules are becoming more common in all aspects of electrical energy generation, transmission, and regeneration.
  • Power modules used in electric vehicles, home appliances, and other applications require particularly high productivity and ease of assembly. They also need to be small and lightweight to reduce energy consumption during manufacturing.
  • the component mounting board disclosed in Patent Document 1 shows a method of placing a terminal block with a screw hole on the board and tightening the terminal block to the main terminal of a wiring cable or the like with a screw.
  • This disclosure has been made to solve the above problems, and aims to provide a semiconductor device with a main terminal that improves yield and performance.
  • the semiconductor device is a semiconductor device having a main terminal for transmitting an external signal, comprising: a substrate having first and second main surfaces; a semiconductor element provided on the first main surface of the substrate; a metal block provided on a block mounting member which is at least one of the substrate and the semiconductor element; the block mounting member and the metal block are joined via a block bonding material, the metal block has a main terminal mounting region, the main terminal is fixed to the metal block at the main terminal mounting region, and the semiconductor device further comprises a sealing resin provided on the first main surface of the substrate, covering at least the block mounting member and the block bonding material.
  • the semiconductor device disclosed herein can reduce damage to the metal block when attaching the main terminal to the metal block in the main terminal attachment area by using the sealing resin that covers at least the block mounting member and the block bonding material.
  • the semiconductor device disclosed herein since a sealing resin is provided on the first main surface of the substrate, when the main terminal is fixed to the metal block in the main terminal mounting area, the first main surface of the substrate is protected by the sealing resin, and the performance of the substrate is not deteriorated.
  • the semiconductor device disclosed herein has a structure that does not adversely affect the substrate during the manufacturing stage, which can improve the yield and performance of the device.
  • FIG. 1 is an explanatory diagram illustrating a planar structure of a power module according to a first embodiment of the present invention
  • FIG. 2 is an explanatory diagram showing a schematic cross-sectional structure taken along line AA in FIG.
  • FIG. 2 is a perspective view showing the overall structure of the power module shown in FIG. 1 .
  • FIG. 1 is an explanatory diagram (part 1) showing a schematic cross-sectional structure of a power module according to a basic aspect of the first embodiment during a manufacturing process.
  • FIG. 2 is an explanatory diagram (part 2) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process.
  • FIG. 1 is an explanatory diagram (part 1) showing a schematic cross-sectional structure of a power module according to a basic aspect of the first embodiment during a manufacturing process.
  • FIG. 2 is an explanatory diagram (part 2) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process.
  • FIG. 11 is an explanatory diagram (part 3) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process.
  • FIG. 4 is an explanatory diagram (part 4) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process.
  • FIG. 5 is an explanatory diagram (part 5) showing a schematic cross-sectional structure of the power module during the manufacturing process according to the first embodiment;
  • FIG. 2 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a second aspect of the first embodiment.
  • FIG. 11 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a third aspect of the first embodiment.
  • FIG. 11 is an explanatory diagram illustrating a planar structure of a power module according to a second embodiment of the present invention
  • 12 is an explanatory diagram showing a schematic cross-sectional structure taken along the line BB in FIG. 11.
  • FIG. 11 is an explanatory diagram (part 1) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process.
  • FIG. 13 is an explanatory diagram (part 2) illustrating a cross-sectional structure during a manufacturing process of a power module according to a basic aspect of the second embodiment.
  • FIG. 11 is an explanatory diagram (part 3) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process.
  • FIG. 4 is an explanatory diagram (part 4) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process.
  • FIG. 5 is an explanatory diagram (part 5) illustrating a cross-sectional structure during a manufacturing process of a power module according to a basic aspect of the second embodiment.
  • FIG. 11 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a second aspect of the second embodiment.
  • FIG. 11 is an explanatory diagram illustrating a planar structure of a power module according to a third embodiment.
  • 20 is an explanatory diagram showing a schematic cross-sectional structure taken along the line CC in FIG. 19.
  • FIG. 19 is an explanatory diagram showing a schematic cross-sectional structure taken along the line CC in FIG. 19.
  • FIG. 11 is an explanatory diagram (part 1) illustrating a schematic cross-sectional structure during a manufacturing process of a power module according to embodiment 3.
  • FIG. 13 is an explanatory diagram (part 2) illustrating a cross-sectional structure during a manufacturing process of the power module according to the third embodiment.
  • FIG. 13 is an explanatory diagram (part 3) illustrating a schematic cross-sectional structure during the manufacturing process of the power module according to the third embodiment.
  • FIG. 11 is an explanatory diagram (part 4) illustrating a cross-sectional structure during a manufacturing process of the power module according to the third embodiment.
  • FIG. 5 is an explanatory diagram (part 5) illustrating a cross-sectional structure during the manufacturing process of the power module according to the third embodiment.
  • FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.
  • FIG. 1 is an explanatory diagram showing a schematic planar structure of the power module 1.
  • FIG. 2 is an explanatory diagram showing a schematic cross-sectional structure taken along the line A-A in FIG. 1.
  • FIG. 3 is a perspective view showing the overall structure of the power module 1. An XYZ orthogonal coordinate system is shown in each of FIGS. 1 to 3. Note that the sealing resin 7 is not shown in FIG. 3.
  • a fin base 15, which is a heat dissipation fin, is provided on the bottom layer of the power module 1.
  • the fin base 15 has a base portion 15m and a number of pins 15p.
  • the planar shape of the base portion 15m is, for example, 100 mm x 100 mm, and the thickness of the base portion 15m is set to, for example, 3 mm. Possible materials for the base portion 15m include copper, nickel plating, etc.
  • the upper surface of the base portion 15m on the +Z direction side becomes the mounting surface 15s.
  • the planar shape of the mounting surface 15s is, for example, 100 mm x 100 mm.
  • the case 5 and ceramic substrate 10, which will be described later, are provided on the mounting surface 15s.
  • On the lower surface on the -Z direction side of the base portion 15m multiple pins 15p are provided in a matrix shape at equal intervals.
  • the diameter of each of the multiple pins 15p in the XY plane is set to, for example, 1.5 mm, and the length along the Z direction is set to, for example, 8 mm.
  • the case 5 is attached to the mounting surface 15s of the fin base 15.
  • the planar shape of the case 5 in the XY plane is set to, for example, 92 mm x 80 mm, and the height of the case 5 in the Z direction is approximately 10 mm.
  • the case 5 is thought to be made of PPS resin.
  • the planar shape (100 mm x 100 mm) of the mounting surface 15s of the fin base 15 has dimensional characteristics that are wider than the planar shape (92 mm x 80 mm) of the case 5.
  • the case 5, which is the storage space forming member, has a hollow structure with a case storage space S5 inside, and within the case storage space S5, the ceramic substrate 10, which serves as an insulating substrate, is joined by solder 30 onto the mounting surface 15s of the fin base 15.
  • the depth of the case storage space S5 is approximately 10 mm, reflecting the formation height of the case 5.
  • the case storage space S5 is the element storage space formed by the storage space forming member.
  • the ceramic substrate 10 which is an insulating substrate, has a silicon nitride substrate 11 that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11 on the +Z direction side, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10 on the -Z direction side.
  • the surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.
  • the planar shape of the silicon nitride substrate 11 in the XY plane is, for example, 70 mm x 58 mm, and the film thickness of the silicon nitride substrate 11, i.e., the height along the Z direction, is set to, for example, 0.32 mm.
  • planar shape in the XY plane may be referred to simply as the "planar shape,” and the height in the Z direction may be referred to simply as the "height.”
  • each of the upper conductor layer 12 and the lower conductor layer 13 is set to, for example, 0.8 mm, and the constituent material is, for example, copper.
  • a plurality of semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10 via solder 31. That is, the first main surface of the substrate and the plurality of semiconductor elements 20 are joined via the solder 31. As shown in FIG. 1, in the power module 1 which is the basic aspect of the first embodiment, four semiconductor elements 20 are shown as the plurality of semiconductor elements 20.
  • the solder 30 that serves as the substrate bonding material between the fin base 15 and the ceramic substrate 10 and the solder 31 that serves as the substrate bonding material between the ceramic substrate 10 and the semiconductor element 20, are composed of, for example, 96.5% tin, 3% silver, and 0.5% copper, and the melting points of the solder 30 and the solder 31 are set to, for example, 217°C.
  • the multiple semiconductor elements 20 may be diodes or IGBTs (Insulated Gate Bipolar Transistors).
  • Diodes may be made of silicon, for example, and have a planar configuration of 10 mm x 8 mm, with a thickness (formation height) set to 0.2 mm, for example.
  • IGBTs may be made of silicon, for example, and have a planar configuration of 10 mm x 10 mm, with a thickness set to 0.2 mm, for example.
  • the signal terminal 63 is fixed to the case 5 in such a manner that a portion of it is inserted into the case 5.
  • the signal terminal 63 is made of, for example, copper, and its width in the Y direction is set to, for example, 1.5 mm, and its thickness is set to, for example, 0.6 mm.
  • the case 5 has an intermediate horizontal portion 5a and an outer frame standing portion 5b
  • the signal terminal 63 has a bent shape consisting of a terminal horizontal portion 63a and a terminal standing portion 63b, with the terminal horizontal portion 63a inserted into the intermediate horizontal portion 5a and a part of the terminal standing portion 63b inserted into the outer frame standing portion 5b.
  • a portion of the upper surface of the terminal horizontal portion 63a of the signal terminal 63 is exposed from the intermediate horizontal portion 5a, and the upper surface of the exposed terminal horizontal portion 63a is electrically connected to the upper surface of the semiconductor element 20 by a wire 41.
  • a wire 41 For example, an aluminum wire having a diameter of 0.15 mm is used as the wire 41.
  • the signal terminal 63 and the wire 41 form a signal circuit.
  • wire 42 electrically connects the surface of upper conductor layer 12 to the surface of semiconductor element 20.
  • Wire 43 electrically connects the surfaces of semiconductor elements 20, 20.
  • Wires 42 and 43 are, for example, aluminum wires with a diameter of 0.4 mm.
  • the metal block 60 is fixed to the surface of the upper conductor layer 12 of the ceramic substrate 10 by solder 31. That is, a portion of the solder 31 is used as a block bonding material for fixing the metal block 60.
  • the thickness (5 mm) of the metal block 60 in the height direction along the Z direction is set to be sufficiently thick compared to the film thickness (0.8 mm) of the upper conductor layer 12.
  • the ceramic substrate 10 functions as a block mounting member. That is, the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 are joined via solder 31.
  • the solder 31 between the ceramic substrate 10 and the metal block 60 functions as a joining material for the block.
  • the screw 61 is made of brass, for example, and meets the standard for an "M4 pan head screw.”
  • the screw 61 has a head 61a and a threaded portion 61b, and the length of the threaded portion 61b is set to, for example, 5 mm.
  • the main terminal 62 is fixed onto the top surface of the metal block 60 in an attachment manner in which the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole area 60x of the metal block 60.
  • the metal block 60 has an upper surface and a screw hole area 60x as a main terminal mounting area, and the main terminal 62 is fixed to the metal block 60 in the main terminal mounting area by the screw 61.
  • the metal block 60, the screw 61, and the main terminal 62 are components included in the main circuit of the power module 1.
  • sealing resin 7 is provided to cover the solder 30 provided on the mounting surface 15s of the fin base 15, the ceramic substrate 10, the solder 31, the semiconductor elements 20, and the wires 41 to 43.
  • the sealing resin 7 may be made of, for example, epoxy resin with silica filler dispersed therein.
  • the top surface and a portion of the upper side of the metal block 60 are not covered by the sealing resin 7 and are exposed.
  • the case storage space S5 is sealed with the sealing resin 7 to a depth of 8 mm, and the metal block 60 is exposed about 2 mm from the top surface.
  • an upper portion of the side of the metal block 60 is not covered by the sealing resin 7 and is exposed, and the exposed side of the metal block 60 includes a pair of exposed side surfaces 60s and 60s that are parallel to the Y direction and face each other in the X direction.
  • the metal block 60 can be restrained by clamping the pair of exposed side surfaces 60s and 60s using an existing restraining tool.
  • the exposed width and exposed length of the exposed side surface 60s must be set to a length that allows the metal block 60 to be restrained using an existing restraining tool.
  • the power module 1 has a case housing space S5 in the case 5 as an element housing space that houses the ceramic substrate 10, the multiple semiconductor elements 20, and the metal block 60.
  • the sealing resin 7 is provided in the case housing space S5.
  • the power module 1 which is the basic aspect of the first embodiment, is provided with sealing resin 7 covering the ceramic substrate 10 that serves as the block mounting member and the solder 31 that serves as the bonding material for the block. Therefore, the base portion of the metal block 60 is reinforced by the sealing resin 7.
  • the sealing resin 7 can reduce damage to the metal block 60 when the main terminal 62 is attached to the main terminal attachment area using the screw 61.
  • the top surface of the metal block 60 and the screw hole area 60x form the main terminal attachment area.
  • the sealing resin 7 is provided on the surface of the upper conductor layer 12, which is the first main surface of the substrate, the surface of the upper conductor layer 12 is protected by the sealing resin 7 when the main terminal 62 is attached to the metal block 60 in the main terminal attachment region described above. Therefore, the performance of the ceramic substrate 10 is not deteriorated when the main terminal 62 is fixed to the metal block 60.
  • the insulating property can be considered as the performance of the ceramic substrate 10, which is an insulating substrate.
  • the power module 1 which is the basic aspect of the first embodiment, has a structure that does not adversely affect the ceramic substrate 10 during the manufacturing stage, thereby improving the yield and performance of the device.
  • the top surface of the metal block 60 in the power module 1 is exposed and not covered by the sealing resin 7, so that even after the device is completed, rework can be performed relatively easily to replace the main terminal 62 fixed on the top surface of the metal block 60 with a new main terminal. This allows for flexibility in the selection of the main terminal 62.
  • the power module 1 can be attached relatively easily by fixing the main terminal 62 to the top surface of the metal block 60 using screws 61.
  • the power module 1 has sealing resin 7 disposed in the case housing space S5, which is the element housing space of the case 5, which is the housing space forming member, and this allows the height of the sealing resin 7 to be adjusted relatively easily during manufacturing.
  • the power module 1 has a fin base 15, which serves as a heat dissipation fin, provided via solder 30 on the surface of the lower conductor layer 13 of the ceramic substrate 10, which forms the second main surface of the substrate. Therefore, heat generated during operation of the multiple semiconductor elements 20 can be effectively dissipated by a heat dissipation path that includes the ceramic substrate 10 and the fin base 15.
  • the case 5, which is the storage space forming member in the power module 1, is provided on the mounting surface 15s of the fin base 15, which serves as the heat dissipation fin, so that the case storage space S5, which serves as the element storage space, can be secured and provided with good stability.
  • the power module 1 has a case housing space S5 secured by a dedicated case 5, so multiple semiconductor elements 20 and metal blocks 60 can be stably housed within the case housing space S5, and the height of the sealing resin 7 can be adjusted with high precision during manufacturing.
  • FIGS. 4 to 8 are explanatory diagrams that show schematic cross-sectional structures of the power module 1 during the manufacturing process, which is a basic aspect of the first embodiment.
  • An XYZ orthogonal coordinate system is depicted in each of Figs. 4 to 8.
  • the manufacturing method of the power module 1 will be described below with reference to Figs. 4 to 8.
  • the power module 1 includes four semiconductor elements 20 and three metal blocks 60, but for ease of explanation, the following description will be based on the structure shown in Figures 4 to 8.
  • a ceramic substrate 10 is prepared as the substrate for the semiconductor device of the first embodiment.
  • the ceramic substrate 10 has a silicon nitride substrate 11 which is an insulating substrate, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11, and a lower conductor layer 13 provided on the lower surface of the silicon nitride substrate 11.
  • the ceramic substrate 10 serves as a block mounting member.
  • solder 31, two semiconductor elements 20, and one metal block 60 are positioned above the upper conductor layer 12 of the ceramic substrate 10, and solder bonding is performed using the solder 31 in a reflow furnace.
  • two semiconductor elements 20 and one metal block 60 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10. That is, the metal block 60 is joined via the solder 31 to the first main surface of the ceramic substrate 10, which serves as the block mounting member.
  • the surface of the lower conductor layer 13 of the ceramic substrate 10 is joined to the mounting surface 15s of the fin base 15 via solder 30.
  • the fin base 15, which is a heat dissipation fin is fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10.
  • the case 5 is glued and fixed onto the mounting surface 15s of the fin base 15.
  • the case 5, which is a member forming the housing space, has a case housing space S5 that serves as the element housing space, and the case 5 is fixed onto the mounting surface 15s of the fin base 15 to house the solder 30 and the ceramic substrate 10 within the case housing space S5.
  • the signal terminal 63 is integrated with the case 5, with the terminal horizontal portion 63a provided within the intermediate horizontal portion 5a and a portion of the terminal standing portion 63b provided within the outer frame standing portion 5b. After being fixed to the fin base 15 of the case 5, the intermediate horizontal portion 5a is located above the upper surface conductor layer 12 and a portion of the surface of the terminal horizontal portion 63a is exposed.
  • wire 41 to 43 After the case 5 is fixed to the fin base 15, wiring is performed using wires 41 to 43. That is, wire 41 electrically connects the surface of the terminal horizontal portion 63a to the semiconductor element 20, wire 42 electrically connects the semiconductor element 20 to the upper surface conductor layer 12, and wire 43 electrically connects the semiconductor elements 20, 20 together. After wiring the wires 41 to 43, a circuit is formed that includes the two semiconductor elements 20, wires 41 to 43, metal block 60, and signal terminal 63.
  • sealing resin 7 is injected into the case housing space S5 to the extent that the top surface and a portion of the upper side of the metal block 60 are exposed, and then heated and cured. As a result, the solder 30, ceramic substrate 10, semiconductor elements 20, and wires 41 to 43 are all covered with sealing resin 7 within the case housing space S5.
  • the top surface and a portion of the upper part of the side surface of the metal block 60 are not covered with the sealing resin 7 and are exposed. That is, the exposed side surface of the metal block 60 includes a pair of exposed side surfaces 60s and 60s that face each other in the X direction. The pair of exposed side surfaces 60s and 60s are both parallel to the YZ plane. Furthermore, no sealing resin 7 is provided in the screw hole region 60x.
  • the screw hole area 60x of the metal block 60 and the opening 62o of the main terminal 62 are positioned so that they match in a plan view, and the metal block 60 and the main terminal 62 are connected and fixed using the screw 61.
  • the main terminal 62 is fixed to the top surface of the metal block 60 in an installation manner in which the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole region 60x of the metal block 60.
  • the metal block 60 is sealed partway with the sealing resin 7, so when the main terminal 62 is attached to the top surface of the metal block 60 with the screw 61, the tightening torque of the screw 61 reduces damage to the solder 31, which serves as the block bonding material that bonds the metal block 60 to the top conductor layer 12.
  • the metal block 60 can be restrained by clamping the pair of exposed side surfaces 60s and 60s using an existing restraining tool.
  • the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole area 60x of the metal block 60, and then the screw 61 is tightened with a predetermined torque, thereby fastening and fixing the main terminal 62 to the upper surface of the metal block 60.
  • the main terminal 62 can be fixed with the metal block 60 stably restrained by the pair of exposed side surfaces 60s and 60s, which further reduces damage to the solder 31, which is the joining material for the fixing block, when the main terminal 62 is fixed, and further reduces damage to the semiconductor element 20.
  • the material for the fin base 15 copper is used as the material for the fin base 15, but the same effect can be obtained by using aluminum partially nickel-plated as the constituent material for the fin base 15.
  • the semiconductor element 20 is made of silicon, the same effect can be obtained by constructing the semiconductor element 20 using a wide band gap semiconductor such as silicon carbide or gallium nitride.
  • solder 30 and solder 31 a solder material consisting of 96.5% tin, 3% silver, 0.5% copper, with a melting point of 217°C was used, but the same effect can be obtained by using a solder material consisting of 99.3% tin, 0.7% copper, with a melting point of 224°C, etc. for solder 30 or solder 31.
  • the same effect can also be obtained by replacing the solder 31 used as the substrate bonding material for bonding the semiconductor element 20 to the ceramic substrate 10 or the block bonding material for bonding the metal block 60 to the ceramic substrate 10 with a silver sintered material or brazing material that has better heat resistance than solder.
  • the wires 41 to 43 used are made of aluminum, but the same effect can be obtained by using wires 41 to 43 made of aluminum alloy containing trace amounts of additives such as iron or copper. The same effect can also be obtained by using aluminum or copper ribbon bonds as an alternative material for the wires 41 to 43, or by soldering using a lead frame made of copper or the like.
  • the screw 61 if there is concern about noise due to the protruding shape, it is expected that this can be improved by using a "pan head screw”, “low head screw” or a screw made of plastic.
  • Epoxy resin with dispersed silica filler was used as the potting sealing resin 7, but fillers such as alumina may also be used, and the same effect can be obtained by mixing epoxy resin with silicone resin or using silicone gel as the constituent material of the sealing resin 7.
  • case-type module in which sealing resin 7 is injected into case 5 is shown as the power module 1, but the same effect can be obtained by configuring it as a transfer mold type module in which the sealing resin is molded using a die.
  • the manufacturing method for the power module 1 described above includes the following steps (a) to (e) as a manufacturing method for a semiconductor device having a main terminal 62 for transmitting an external signal.
  • Step (a) is a step of preparing a ceramic substrate 10 as a substrate having a first and second main surfaces.
  • Step (b) is a step of mounting multiple semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate.” Step (b) corresponds to the process described with reference to FIG. 4.
  • At least one of the ceramic substrate 10 and the semiconductor element 20 serves as a block mounting member.
  • the ceramic substrate 10 functions as the block mounting member.
  • Step (c) is a step of joining the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 via the solder 31, which functions as a joining material for the block. Step (c) corresponds to the process described with reference to FIG. 4.
  • Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10, which serves as a block mounting member, and solder 31, which serves as a bonding material for the block. Step (d) corresponds to the process described with reference to Figures 6 and 7.
  • step (d) After step (d) is performed, the top surface and a portion of the upper part of the side surface of the metal block 60 are not covered by the sealing resin 7 and are exposed. Therefore, there is a pair of exposed side surfaces 60s and 60s that are exposed by about 2 mm from the sealing resin 7.
  • Step (d) includes the following steps (d-1) and (d-2).
  • Step (d-1) is a step of fixing the case 5, which is a member for forming a storage space and surrounds the ceramic substrate 10, the semiconductor element 20, and the metal block 60, onto the mounting surface 15s of the fin base 15.
  • Step (d-1) corresponds to the process described with reference to FIG. 6.
  • Step (d-2) is a step of forming sealing resin 7 to cover ceramic substrate 10 and solder 31 in case housing space S5, which is an element housing space surrounded by case 5. Step (d-2) corresponds to the process described with reference to FIG. 7.
  • Step (e) is performed after the above-mentioned step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60.
  • Step (e) corresponds to the process described with reference to FIG. 8.
  • the power module 1, which is a semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment, can reduce damage to the metal block 60 during the screw tightening process in step (e) by the sealing resin 7 that is provided to cover at least the ceramic substrate 10 that serves as the block mounting member and the solder 31 that serves as the block bonding material.
  • step (e) of the method for manufacturing a semiconductor device according to the first embodiment When step (e) of the method for manufacturing a semiconductor device according to the first embodiment is performed, the upper surface and a part of the upper side of the metal block 60 are not covered by the sealing resin 7 and are exposed. Therefore, rework in which the main terminal 62 attached to the upper surface of the metal block 60 is replaced with a new main terminal can be performed relatively easily without any problems as step (e).
  • the main terminal 62 can be fixed in a state where the metal block 60 is stably held by the pair of exposed side surfaces 60s and 60s, so damage to the solder 31 and the semiconductor element 20 when the main terminal 62 is fixed can be suppressed.
  • step (d-2) by forming the sealing resin 7 in the case accommodation space S5 of the case 5 that was provided when step (d-1) was performed, the height of the sealing resin 7 can be adjusted relatively easily.
  • Fig. 9 is an explanatory diagram showing a schematic cross-sectional structure of a power module 1B which is a semiconductor device according to a second aspect of the first embodiment.
  • Fig. 9 corresponds to the cross-sectional structure taken along line A-A in Fig. 1 which shows the basic aspect.
  • An XYZ orthogonal coordinate system is shown in Fig. 9.
  • the power module 1B which is the second aspect of the first embodiment, components similar to those of the power module 1 of the basic aspect are given the same reference numerals and explanations thereof are omitted as appropriate. The following will focus on the characteristics of the power module 1B that differ from the power module 1 of the basic aspect shown in Figures 1 to 3.
  • power module 1B differs from power module 1 in that the main terminals 62 are fixed to the top surface of the metal block 60 by a main terminal joining process such as laser welding.
  • the main terminal attachment area for the metal block 60 of power module 1B is only the top surface of the metal block 60.
  • power module 1B does not include screws 61 as a component, at least at the device completion stage.
  • the welded portion 62w of the main terminal 62 is positioned on the top surface of the metal block 60, and a laser welding process is performed by irradiating a laser 65, and the welded portion 62w of the main terminal 62 is joined to the top surface of the metal block 60.
  • the laser 65 may be, for example, a YAG laser with an output of 5 kW.
  • FIG. 9 shows the laser welding process as the main terminal joining process.
  • the metal block 60 may be made of copper or a copper alloy, and a nut made of brass or other material may also be used.
  • the power module 1B which is the second aspect of the first embodiment, is provided with sealing resin 7 covering ceramic substrate 10, which serves as the block mounting member, and solder 31, which serves as the bonding material for the block.
  • the sealing resin 7 can reduce damage to the metal block 60 when fixing the main terminal 62 by a main terminal joining process such as laser welding.
  • the sealing resin 7 is provided on the surface of the upper conductor layer 12, which is the first main surface of the substrate. Therefore, when the main terminals 62 are fixed to the metal block 60, the surface of the upper conductor layer 12 is protected by the sealing resin 7, and the performance of the ceramic substrate 10 is not degraded by welding spatters, etc., that occur when performing the main terminal joining process.
  • the power module 1B which is the second aspect of the first embodiment, has a structure that does not adversely affect the ceramic substrate 10 during the manufacturing stage, and thus, like the basic aspect, it is possible to improve the yield and performance of the device.
  • the height-wise thickness (5 mm) of the metal block 60 in the power module 1B is sufficiently thicker than the film thickness (0.8 mm) of the upper conductor layer, so the metal block 60 has a relatively large heat capacity.
  • the thermal effect on the ceramic substrate 10, which is an insulating substrate can be suppressed by the metal block 60, which has a relatively large thermal capacity.
  • the power module 1B has the case 5 and fin base 15, just like the basic version, and therefore has the same effects as the power module 1, which is the basic version, with respect to the case 5 and fin base 15.
  • the manufacturing method of the power module 1B described above is a manufacturing method of a semiconductor device having a main terminal 62 for transmitting an external signal, and includes the following steps (a) to (e).
  • Steps (a) to (d) are performed in the same manner as steps (a) to (d) of the manufacturing method for the power module 1, which is the basic embodiment.
  • Step (e) is performed after step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60 by a main terminal joining process such as laser welding.
  • a representative process for the main terminal joining process is laser welding.
  • a YAG laser is used as the laser 65, but a carbon dioxide laser or a green laser can also be used instead of a YAG laser.
  • resistance welding, MIG (Metal Inert Gas) welding, ultrasonic joining, etc. may also be used as the main terminal joining process.
  • the main terminal 62 and the metal block 60 can be joined by the main terminal joining process, which includes a variety of processes.
  • the insulation of the device may be reduced due to scattering spatter.
  • the power module 1B covers the semiconductor element 20 and ceramic substrate 10 with sealing resin 7, even if spatter scatters, the insulation of the device including the semiconductor element 20 and ceramic substrate 10 is not affected.
  • the metal block 60 is sufficiently thick compared to the upper conductor layer 12 of the ceramic substrate 10 and has a relatively large heat capacity, so it can absorb the excessive heat energy generated during the main terminal bonding process and suppress thermal damage to the upper conductor layer 12 and the ceramic base material 11.
  • main terminal joining process may be performed using solder.
  • solder used in this main terminal joining process will be referred to as "main terminal solder.”
  • the welded fixing portion 62w of the main terminal 62 can be fixed to the upper surface of the metal block 60 via the main terminal solder.
  • the screw 61 may be used to position the welded fixing portion 62w of the main terminal 62 on the upper surface of the metal block 60. That is, after the main terminal joining process is performed in a state in which the main terminal 62 is temporarily fixed on the upper surface of the metal block 60 by the screw 61, the screw 61 may be removed from the metal block 60 to complete the power module 1B. That is, the screw 61 may be used for temporary positioning and fixing used in an intermediate stage during the manufacture of the power module 1B.
  • the power module 1B which is a semiconductor device manufactured by the manufacturing method of the second aspect, can reduce damage to the metal block 60 during the main terminal joining process such as laser welding in step (e) by using the sealing resin 7 that covers the ceramic substrate 10 and the solder 31.
  • step (e) of the manufacturing method of the second embodiment the upper surface of the metal block 60 is not covered with the sealing resin and is exposed. Therefore, rework can be performed relatively easily as step (e) by removing the main terminal 62 fixed on the upper surface of the metal block 60 and replacing it with a new main terminal by a main terminal joining process.
  • Fig. 10 is an explanatory diagram showing a schematic cross-sectional structure of a power module 1C which is a semiconductor device according to a third aspect of the first embodiment.
  • Fig. 10 corresponds to the cross-sectional structure taken along line A-A in Fig. 1 which shows the basic aspect.
  • An XYZ orthogonal coordinate system is shown in Fig. 10.
  • the power module 1C which is the third aspect of the first embodiment, components similar to those of the power module 1 of the basic aspect are given the same reference numerals and explanations are omitted as appropriate. The following will focus on the characteristics of the power module 1C that are different from the power module 1 of the basic aspect shown in Figures 1 to 3.
  • the power module 1C is provided with a case 5T with main terminals instead of the case 5.
  • the planar shape of the case 5T with main terminals in the XY plane is set to, for example, 92 mm x 80 mm, similar to the case 5, and it is desirable that the height of the case 5T with main terminals in the Z direction is slightly higher than 10 mm.
  • the material of the case 5T with main terminals may be PPS resin.
  • the planar shape (100 mm x 100 mm) of the mounting surface 15s of the fin base 15 has dimensional characteristics that are wider than the planar shape (92 mm x 80 mm) of the main terminal case 5T.
  • the main terminal 62 is connected to the case 5T with the main terminal in such a manner that the main terminal 62 protrudes from the case housing space S5 to the outside. In other words, the main terminal 62 is insert molded into the case 5T with the main terminal.
  • the main terminal 62 has an externally exposed portion 62b that protrudes from the main terminal case 5T in the X direction, and an internal case insertion portion 62c that exists within the main terminal case 5T.
  • sealing resin 72 is further provided on the sealing resin 7 within the case housing space S5.
  • the upper part of the metal block 60 exposed from the sealing resin 7, the screw mounting parts 62a of the main terminals 62, and the screws 61 are all covered with sealing resin 72.
  • the manufacturing method of the power module 1C described above is a manufacturing method of a semiconductor device having a main terminal 62 for transmitting an external signal, and includes the following steps (a) to (e) and step (x).
  • Steps (a) and (b) are performed in the same manner as steps (a) and (b) of the method for manufacturing the power module 1.
  • Step (c) is a step in which the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 are joined via solder 31, which is a joining material for the block.
  • solder 31 which is a joining material for the block.
  • the main terminal case 5T is fixed onto the mounting surface 15s of the fin base 15.
  • the screw attachment portion 62a of the main terminals 62 is positioned so that it contacts the upper surface of the metal block 60.
  • the metal block 60 and the main terminals 62 are set so that they can be positioned when the case 5T with main terminals is mounted on the mounting surface 15s of the fin base 15.
  • Step (d) is performed in the same manner as step (d) in the method for manufacturing the power module 1.
  • Step (e) is performed after step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60.
  • the stress generated during fastening is also distributed to the main terminal case 5T, thereby reducing the stress on the metal block 60.
  • Joule heat (resistance heat) generated during fastening can be diffused to the fin base 15 via the main terminal case 5T.
  • the screw 61 for fastening and then use a laser welding process by irradiating a laser.
  • a gap at the joint between the screw attachment portion 62a and the upper surface of the metal block 60 may affect the joining quality, but by also using the screw 61 for fastening, the above-mentioned gap can be minimized.
  • by removing the screw 61 after the laser welding process it is possible to suppress the generation of noise caused by the screw 61 being present as a protrusion.
  • Step (x) is a step in which sealing resin 72 is further formed on the sealing resin 7 within the case housing space S5, and the metal block 60, the main terminals 62, and the screw mounting portions 62a are all covered with the sealing resin 72.
  • This step (x) is a process specific to power module 1C that is not performed in power module 1 or power module 1B.
  • sealing resin 72 is injected into the case housing space S5 of the main terminal case 5T to insulate and seal the exposed parts of the metal block 60 and the screws 61, etc., thereby improving insulation and reducing noise caused by the shape of the heads 61a of the screws 61, etc.
  • sealing resin 72 may be made of the same material as sealing resin 7, but it may also have a lower filler content than sealing resin 7 to increase fluidity, or it may be replaced with an inexpensive silicone gel.
  • the third embodiment of the power module 1C has the same effects as the basic embodiment of the power module 1, except for the effects resulting from the upper surface of the metal block 60 being exposed at the completed stage, and further has the following effects:
  • the power module 1C has sealing resin 72 in addition to sealing resin 7 as the sealing resin provided in the case housing space S5, so that the ceramic substrate 10, the multiple semiconductor elements 20, the metal block 60, and the screw mounting portion 62a of the main terminal 62 that are present in the case housing space S5 are all covered with sealing resin 7 and sealing resin 72.
  • the power module 1C improves the insulation of the device and reduces noise caused by protrusions such as the head 61a that remain when the top surface of the metal block 60 is fixed to the screw mounting portion 62a of the main terminal 62.
  • a pair of exposed side surfaces 60s and 60s that are parallel to the Y direction and face each other in the X direction are shown as a pair of exposed side surfaces for restraint in the metal block 60.
  • a pair of exposed side surfaces that are parallel to the X direction and face each other in the Y direction may also be used as a pair of exposed side surfaces for restraint.
  • the metal block 60 is shown in the shape of a rectangular prism, but the metal block 60 may be in the shape of a polygonal prism of hexagonal or greater prism that can be provided with a pair of exposed side surfaces 60s and 60s.
  • FIG. 11 is an explanatory diagram that shows a schematic planar structure of the power module 2.
  • FIG. 12 is an explanatory diagram that shows a schematic cross-sectional structure taken along line B-B of FIG. 11. An XYZ orthogonal coordinate system is shown in each of FIG. 11 and FIG. 12.
  • power module 2B which is the basic aspect of embodiment 2
  • components similar to those of power module 1, which is the basic aspect of embodiment 1, are given the same reference numerals and explanations are omitted as appropriate.
  • the following will focus on the characteristics of power module 2 that are different from power module 1 shown in Figures 1 to 3.
  • a fin base 15B which is a heat dissipation fin, is provided on the bottom layer of the power module 2.
  • the fin base 15B has a base portion 15m and a number of pins 15p.
  • the planar shape of the base portion 15m is, for example, 90 mm x 100 mm, and the thickness of the base portion 15m is set to, for example, 3 mm.
  • Possible materials for the base portion 15m include, for example, copper and nickel plating.
  • a dam section 8 is provided on the mounting surface 15s of the fin base 15B, surrounding the ceramic substrate 10B, the semiconductor elements 20, and the metal blocks 66.
  • the height of the dam section 8, which is a member forming the storage space, in the Z direction is set to, for example, about 6 mm.
  • four semiconductor elements 20 are shown as the multiple semiconductor elements 20 in the power module 2.
  • the dam section 8 is constructed by stacking multiple dam materials 81.
  • a process for obtaining a layered structure using multiple dam materials 81 can be, for example, a drawing process using a dispenser.
  • a material obtained by dispersing silica filler in epoxy resin can be used as a constituent material for the dam material 81.
  • the ceramic substrate 10B which is an insulating substrate, has a silicon nitride substrate 11B that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11B, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10B.
  • the surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.
  • the planar shape of the silicon nitride substrate 11B is, for example, 65 mm x 58 mm, and the thickness of the silicon nitride substrate 11B in the Z direction is set to, for example, 0.32 mm.
  • the solder 30, which serves as the bonding material for the board, is composed of, for example, 96.5% tin, 3% silver, and 0.5% copper, and the melting point of the solder 30 is set to, for example, 217°C.
  • each of the upper conductor layer 12 and the lower conductor layer 13 is set to, for example, 0.8 mm, and the constituent material is, for example, copper.
  • a number of semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10B via solder 31.
  • the first main surface of the substrate and the number of semiconductor elements 20 are joined via the solder 31.
  • the multiple semiconductor elements 20 may be diodes or IGBTs.
  • the diodes may be made of silicon, have a planar configuration of, for example, 10 mm x 8 mm, and have a thickness of, for example, 0.2 mm.
  • the IGBTs may be made of silicon, have a planar configuration of, for example, 10 mm x 10 mm, and have a thickness of, for example, 0.2 mm.
  • a terminal block 51 is provided on a portion of the upper conductor layer 12 of the ceramic substrate 10B.
  • a signal terminal 63 is fixed to the terminal block 51 in such a manner that a portion of the signal terminal 63 is inserted into the terminal block 51.
  • the signal terminal 63 is made of copper, for example, and has a width in the Y direction of, for example, 1.5 mm and a thickness of, for example, 0.6 mm.
  • the terminal block 51 has a terminal horizontal portion 51a and a terminal standing portion 51b
  • the signal terminal 63 has a bent shape consisting of the terminal horizontal portion 63a and the terminal standing portion 63b, with the terminal horizontal portion 63a being inserted into the terminal horizontal portion 51a and a part of the terminal standing portion 63b being inserted into the terminal standing portion 51b. In this way, the signal terminal 63 is insert molded into the terminal block 51.
  • a portion of the upper surface of the terminal horizontal portion 63a of the signal terminal 63 is exposed from the terminal horizontal section 51a, and the upper surface of the exposed terminal horizontal portion 63a is electrically connected to the upper surface of the semiconductor element 20 by a wire 41.
  • a wire 41 For example, an aluminum wire having a diameter of 0.15 mm is used as the wire 41.
  • the signal terminal 63 and the wire 41 form a signal circuit.
  • the metal block 60 is fixed to the surface of the upper conductor layer 12 of the ceramic substrate 10B by solder 31.
  • the solder 31 used to join the metal block 60 serves as a joining material for the block.
  • a metal block 66 is fixed onto each of the semiconductor elements 20 by solder 32, which is a bonding material for the block.
  • the metal block is divided into a metal block 60 provided on the surface of the upper conductor layer 12 of the ceramic substrate 10B and a metal block 66 provided on the semiconductor element 20.
  • the constituent materials and shapes of the metal blocks 60 and 66 are the same.
  • the power module 2 includes four semiconductor elements 20, two metal blocks 60, and four metal blocks 66.
  • the metal blocks 60 and 66 are made of brass, for example, and each has a rectangular shape measuring 7 mm x 6 mm in plan view, with each having a height of 5 mm along the Z direction. In other words, the metal blocks 60 and 66 each have a rectangular prism shape.
  • the metal block 60 has a screw hole region 60x that runs from the center of the top surface to the bottom surface.
  • the metal block 66 has a screw hole region 66x that runs from the top surface to the bottom surface.
  • the screw hole regions 60x and 66x that penetrate the metal blocks 60 and 66 along the height direction function as main terminal mounting regions, respectively.
  • the thickness (5 mm) of each of the metal blocks 60 and 66 in the height direction along the Z direction is set to be sufficiently thick compared to the film thickness (0.8 mm) of the upper conductor layer 12.
  • solder 31 is used as a block bonding material between the ceramic substrate 10B, which serves as the block mounting member, and the metal block 60
  • solder 32 is used as a block bonding material between the semiconductor element 20, which serves as the block mounting member, and the metal block 66.
  • one main terminal 67 is fixed to the top surfaces of two metal blocks 66 by two screws 61.
  • the main terminal 67 has two openings 67o in the screw attachment portion 67a.
  • the main terminal 67 is made of copper, for example, and has a width of 8 mm in the Y direction and a thickness of 1 mm.
  • the end of the main terminal 67 opposite the screw attachment portion 67a is provided so as to protrude from the case housing space S5 to the outside.
  • the main terminal 67 may be a bus bar or a terminal for an external wiring cable.
  • One main terminal 67 is fixed onto the top surface of two metal blocks 66 in an installation manner in which the threaded portions 61b of two screws 61 are inserted into the two openings 67o of the main terminal 67 and the screw hole areas 66x of the two metal blocks 66.
  • the metal block 66 has an upper surface and a screw hole area 66x as a main terminal mounting area, and the main terminal 67 is fixed to the metal block 66 in the main terminal mounting area by the screw 61.
  • the main circuit of the power module 2 includes metal blocks 60 and 66, a screw 61, and a main terminal 67 as components.
  • sealing resin 7 is provided to cover the solder 30, ceramic substrate 10B, solder 31, multiple semiconductor elements 20, solder 32, and wires 41 to 43 provided on the mounting surface 15s of the fin base 15.
  • the constituent material of the sealing resin 7 may be, for example, an epoxy resin with silica filler dispersed therein.
  • the top surface and a portion of the upper side of the metal block 66 are not covered by the sealing resin 7 and are exposed.
  • the dam portion housing area S8 is sealed with the sealing resin 7 to a depth of about 4 mm, and the metal block 66 is exposed about 2 mm from the top surface.
  • an upper portion of the side of the metal block 66 is not covered by the sealing resin 7 and is exposed, and the exposed side of the metal block 66 includes a pair of exposed side surfaces 66s and 66s that are parallel to the Y direction and face each other in the X direction.
  • the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.
  • the exposed width and exposed length of the exposed side surface 66s must be set to a length that allows the metal block 66 to be restrained using an existing restraining tool.
  • the power module 2 has a dam portion housing area S8 in the dam portion 8 as an element housing space that houses the ceramic substrate 10B, the multiple semiconductor elements 20, and the metal blocks 60 and 66.
  • the sealing resin 7 is provided in the dam portion housing area S8.
  • a semiconductor element 20 is used as a block mounting member.
  • the module metal block used in the power module 2 includes a metal block 60 provided on the ceramic substrate 10B and a metal block 66 provided on the power module 2.
  • the power module 2 has metal blocks 66 in addition to the metal blocks 60 as metal blocks for the module. As shown in FIG. 11, the power module 2 has four metal blocks 66 and two metal blocks 60.
  • the power module 2 can reduce the number of metal blocks 60. Specifically, compared to the power module 1 of the first embodiment, the power module 2 reduces the number of metal blocks 60 from “three" to "two,” and increases the total number of metal blocks for the module from "three" to "six.”
  • the silicon nitride substrate 11 having a planar shape of 70 mm x 58 mm can be reduced in size to the silicon nitride substrate 11B having a planar shape of 65 mm x 58 mm.
  • the power module 2 which is the basic form of the second embodiment, is provided with a sealing resin 7 covering the ceramic substrate 10B, the semiconductor element 20, the solder 31, and the solder 32.
  • power module 2 which is the basic aspect of embodiment 2
  • the upper surfaces of the metal blocks 60 and 66 in the power module 2 are not covered with the sealing resin 7 and are exposed. Therefore, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 67 fixed on the upper surface of the metal block 66 with a new main terminal. Similarly, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 62 fixed on the upper surface of the metal block 60 with a new main terminal. Therefore, flexibility can be provided when selecting the main terminals 62 and 67.
  • the power module 2 when the power module 2 is completed, it has the same effects as the basic power module 1, except for the effects attributable to the case 5, and further has the following effects:
  • the power module 2 makes it relatively easy to adjust the height of the sealing resin 7 during manufacturing without the need for a dedicated case.
  • FIG. 13 to 17 are explanatory diagrams that show a schematic cross-sectional structure during the manufacturing process of the power module 2.
  • An XYZ orthogonal coordinate system is shown in each of Fig. 13 to 17. The manufacturing method of the power module 2 will be described below with reference to Fig. 13 to 17.
  • a ceramic substrate 10B is prepared as the substrate for the semiconductor device of the second embodiment.
  • the ceramic substrate 10B and the semiconductor element 20 serve as block mounting members.
  • solder 31 and two semiconductor elements 20 are positioned above the upper conductor layer 12 of the ceramic substrate 10B, and solder 32 and two metal blocks 66 are positioned above the two semiconductor elements 20, and solder bonding is performed using the solders 31 and 32 in a reflow furnace.
  • two semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10B via solder 31, and two metal blocks 66 are mounted on the upper surfaces of the two semiconductor elements 20 via solder 32. That is, the metal blocks 66 are joined via solder 32 to the upper surfaces of the semiconductor elements 20 that serve as block mounting members.
  • a metal block 60 is joined via solder 31 to the surface of the upper conductor layer 12 of the ceramic substrate 10B that serves as the block mounting member.
  • the surface of the lower conductor layer 13 of the ceramic substrate 10B is joined to the mounting surface 15s of the fin base 15B via solder 30.
  • the fin base 15B which is a heat dissipation fin, is fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10B.
  • a plurality of dam materials 81 are stacked on the mounting surface 15s of the fin base 15B to form the dam portion 8.
  • the stacking process of the dam materials 81 is performed, for example, by a coating process using a dispenser.
  • the completed dam portion 8 has a dam portion accommodation area S8, and the dam portion 8 is provided on the mounting surface 15s of the fin base 15B so that the solder 30 and the ceramic substrate 10B are present within the dam portion accommodation area S8.
  • the terminal block 51 is adhered and fixed onto a portion of the surface of the upper conductor layer 12 of the ceramic substrate 10B.
  • the signal terminal 63 is integrated with the terminal block 51, with the terminal horizontal portion 63a provided within the terminal horizontal portion 51a and a portion of the terminal standing portion 63b provided within the terminal standing portion 51b. After the terminal block 51 is fixed to the fin base 15B, a portion of the surface of the terminal horizontal portion 63a is exposed.
  • the dam portion 8 is formed and fixed to the fin base 15B of the terminal block 51
  • wiring is performed using the wires 41. That is, the surface of the terminal horizontal portion 63a and the semiconductor element 20 are electrically connected by the wires 41.
  • a circuit is formed that includes multiple semiconductor elements 20, the wires 41, the metal blocks 60 and 66, and the signal terminals 63.
  • sealing resin 7 is injected into the dam portion housing area S8 and heated to harden so that a portion of the upper surface and upper side of each of the two metal blocks 66 is exposed. Therefore, a portion of the upper surface and upper side of each of the two metal blocks 66 is not covered by the sealing resin 7 and is exposed.
  • the side of the exposed metal block 66 includes a pair of exposed side surfaces 66s and 66s that face each other in the X direction.
  • the pair of exposed side surfaces 66s and 66 are both parallel to the YZ plane. Furthermore, no sealing resin 7 is provided in the screw hole region 66x.
  • the solder 30, the ceramic substrate 10B, the solder 31, the two semiconductor elements 20, the solder 32 and the wire 41 are all covered with the sealing resin 7.
  • the screw hole regions 66x of the two metal blocks 66 are positioned so that they match the two openings 62o of the main terminal 67 in a plan view, and the metal blocks 66 and the main terminal 67 are connected and fixed using two screws 61.
  • the main terminal 67 is fixed onto the top surface of the metal block 66 in an installation manner in which the threaded portions 61b of the two screws 61 are inserted into the two openings 62o of the main terminal 67 and into the screw hole regions 66x of each of the two metal blocks 66.
  • the two metal blocks 66 are sealed partway with the sealing resin 7, so when the main terminal 67 is attached to the top surface of the metal block 66 with the two screws 61, the tightening torque of each of the two screws 61 reduces damage to the solder 32, which forms the joint between the metal block 66 and the semiconductor element 20.
  • the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.
  • the threaded portion 61b of the screw 61 is inserted into the opening 67o of the main terminal 67 and the threaded hole area 66x of the metal block 66, and then the screw 61 is tightened with a predetermined torque, thereby fastening and fixing the main terminal 67 to the upper surface of the metal block 66.
  • the main terminal 67 can be fixed with the metal block 66 stably restrained by the pair of exposed side surfaces 66s and 66s, which further reduces damage to the solder 31, which is the bonding material for the fixed block, when the main terminal 67 is fixed, and also reduces damage to the semiconductor element 20.
  • dam-type module in which sealing resin 7 is injected into dam section 8 is shown as the power module 2, but the same effect can be obtained by configuring it as a transfer mold type module in which the sealing resin is molded using a die.
  • the manufacturing method for the power module 2 described above includes the following steps (a) to (e) as a manufacturing method for a semiconductor device having a main terminal 67 for transmitting an external signal.
  • Step (a) is a step of preparing a ceramic substrate 10B as a substrate having a first and second main surfaces.
  • Step (b) is a step of mounting multiple semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate.” Step (b) corresponds to the process described with reference to FIG. 13.
  • the ceramic substrate 10 and the semiconductor elements 20 function as block mounting members.
  • Step (c) is a step of joining the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 via solder 31, which serves as a bonding material for the block, and joining the semiconductor element 20, which serves as the block mounting member, and the metal block 66 via solder 32, which serves as a bonding material for the block.
  • Step (c) corresponds to the process described with reference to FIG. 13.
  • Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10 and semiconductor element 20, which are block mounting members, as well as solders 31 and 32. Step (d) corresponds to the process described with reference to Figures 15 and 16.
  • step (d) After step (d) is performed, the upper surfaces and upper portions of the sides of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, there are a pair of exposed side surfaces 60s and 60s and a pair of exposed side surfaces 66s and 66s that are exposed by about 2 mm from the sealing resin 7.
  • Step (d) includes the following steps (d-1) and (d-2).
  • Step (d-1) is a step of forming the dam portion 8, which is a member for forming the storage space, around the ceramic substrate 10, the semiconductor element 20, and the metal blocks 60 and 66 on the mounting surface 15s of the fin base 15. Step (d-1) corresponds to the process described with reference to FIG. 15.
  • Step (d-2) is a step of forming sealing resin 7 to cover ceramic substrate 10B, semiconductor element 20, and solders 31 and 32 within dam portion accommodation area S8, which is an element accommodation space surrounded by dam portion 8. Step (d-2) corresponds to the process described with reference to FIG. 16.
  • Step (e) is performed after step (d) described above, and is a step of attaching main terminals 62 and 67 to the upper surfaces of metal blocks 60 and 66, respectively. Step (e) corresponds to the process described with reference to FIG. 17.
  • the power module 2 which is a semiconductor device manufactured by the semiconductor device manufacturing method of the second embodiment, can reduce damage to the metal blocks 60 and 66 during the screw tightening process in step (e) by using the sealing resin 7 that covers the ceramic substrate 10B, the semiconductor element 20, and the solders 31 and 32.
  • step (e) of the method for manufacturing a semiconductor device according to the second embodiment When step (e) of the method for manufacturing a semiconductor device according to the second embodiment is performed, the upper surfaces and upper portions of the side surfaces of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, rework in which the main terminals 62 and main terminals 67 attached to the upper surfaces of the metal blocks 60 and 66 are replaced with new main terminals can be performed relatively easily without any problems as step (e).
  • the main terminal 62 can be fixed in a state where the metal block 60 is stably held by the pair of exposed side surfaces 60s and 60s, so damage to the solder 31 and the semiconductor element 20 when the main terminal 62 is fixed can be suppressed.
  • step (d-2) the sealing resin 7 is formed in the dam portion accommodation area S8 of the case 5 that was provided when step (d-1) was performed, making it relatively easy to adjust the height of the sealing resin 7.
  • Fig. 18 is an explanatory diagram showing a schematic cross-sectional structure of a power module 2B which is a semiconductor device according to a second aspect of the second embodiment.
  • Fig. 18 corresponds to the cross-sectional structure taken along line B-B in Fig. 11 which shows the basic aspect.
  • An XYZ orthogonal coordinate system is shown in Fig. 18.
  • the power module 2B which is the second aspect of the second embodiment
  • components similar to those of the power module 2 of the basic aspect are given the same reference numerals and explanations thereof are omitted as appropriate.
  • the following will focus on the characteristics of the power module 2B that are different from the power module 2 of the basic aspect shown in Figures 11 and 2.
  • Power module 2B differs from power module 2 in that it does not have a dam section 8, a terminal block 51, or a signal terminal 63.
  • pin terminals 64 are provided in an upright state directly on the surface of the upper conductor layer 12 of the ceramic substrate 10.
  • the area under the pin terminals 64 and the area under the multiple semiconductor elements 20 are electrically separated.
  • the area of the upper conductor layer 12 below the pin terminal 64 and the semiconductor element 20 are electrically connected by a wire 41.
  • sealing resin 7B which has a higher viscosity than sealing resin 7, is used instead of sealing resin 7. Therefore, without providing a dam portion 8, sealing resin 7B is provided on the mounting surface 15s of the fin base 15B, and a structure is realized in which the solder 30-32, ceramic substrate 10B, semiconductor element 20, wire 41, part of the pin terminal 64, and part of the metal block 66 are covered with sealing resin 7B.
  • the second embodiment, power module 2B has the same effects as the basic embodiment, power module 2, except for the effect of providing the dam section 8.
  • the power module 2B does not have a dam portion 8, which has the effect of simplifying the manufacturing process. Specifically, when manufacturing the power module 2B, the process described with reference to FIG. 15 is not necessary.
  • the manufacturing method of the power module 2B described above includes the following steps (a) to (e) as a manufacturing method of a semiconductor device having a main terminal 67 for transmitting an external signal.
  • Steps (a) to (c) are the same as steps (a) to (c) in the manufacturing method of power module 2.
  • Step (d) is a step of forming sealing resin 7B to cover ceramic substrate 10 and semiconductor element 20, which are block mounting members, as well as solders 31 and 32. Step (d) corresponds to the process described with reference to FIG. 16. After step (d) is performed, a portion of the upper part of the top surface and side surfaces of each of metal blocks 60 and 66 is not covered by sealing resin 7B and is exposed.
  • step (d) can be simplified by not performing the process of forming the dam portion 8 shown in step (d-1) of the basic embodiment.
  • Step (e) is the same as step (e) in the manufacturing method of power module 2.
  • the manufacturing method for power module 2B has the same effect as the manufacturing method for power module 2, and further has the effect of simplifying the manufacturing process of step (d) described above.
  • the pair of exposed side surfaces for restraint in the metal blocks 60 and 66 are shown as exposed side surfaces 60s and 60s, and exposed side surfaces 66s and 66s, which are parallel to the Y direction and face each other in the X direction.
  • a pair of exposed side surfaces parallel to the X direction and facing each other in the Y direction may be used as a pair of exposed side surfaces for restraining the metal blocks 60 and 66, respectively.
  • the metal blocks 60 and 66 are shown to have a rectangular prism shape, but the metal blocks 60 and 66 may each be shaped like a polygonal prism of hexagonal or greater size on which a pair of exposed side surfaces 60s and 60s or a pair of exposed side surfaces 66s and 66s can be provided.
  • FIG. 19 is an explanatory diagram that shows a schematic planar structure of the power module 3.
  • FIG. 20 is an explanatory diagram that shows a schematic cross-sectional structure taken along the line C-C of FIG. 19. An XYZ orthogonal coordinate system is shown in each of FIG. 19 and FIG. 20.
  • the ceramic substrate 10C which is an insulating substrate, has a silicon nitride substrate 11C that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11C, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10C.
  • the surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.
  • the planar shape of the silicon nitride substrate 11C is, for example, 90 mm x 75 mm, and the thickness of the silicon nitride substrate 11C in the Z direction is set to, for example, 0.32 mm.
  • the power module 3 has a fin base 15, which is a heat dissipation fin, fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10C via a heat dissipation sheet 73.
  • a dam portion 9 is provided circumferentially on the silicon nitride base material 11C of the ceramic substrate 10C, surrounding the upper conductor layer 12, the multiple semiconductor elements 20, and the multiple metal blocks 66.
  • the formation height of the dam portion 9, which is a member forming the storage space, in the Z direction is set to, for example, about 6 mm.
  • the multiple semiconductor elements 20 may be diodes or IGBTs.
  • the dam section 9 is constructed by stacking a plurality of dam materials 81.
  • a process for stacking a plurality of dam materials 81 for example, a drawing process using a dispenser can be considered.
  • the main circuit of the power module 3 includes metal blocks 60 and 66, a screw 61, and a main terminal 67 as components.
  • sealing resin 7 is provided to cover the solder 30, ceramic substrate 10C, solder 31, multiple semiconductor elements 20, solder 32, and wires 41 provided on the mounting surface 15s of the fin base 15.
  • the sealing resin 7 may be made of, for example, epoxy resin with silica filler dispersed therein.
  • each metal block 66 The top surface and a portion of the upper side of each metal block 66 are not covered with the sealing resin 7 and are exposed.
  • the dam portion housing area S9 is sealed with the sealing resin 7 to a depth of about 4 mm, and the metal block 60 is exposed about 2 mm from the top surface.
  • the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.
  • the power module 3 has a dam portion housing area S9 in the dam portion 9 as an element housing space that houses the ceramic substrate 10C, the multiple semiconductor elements 20, and the metal blocks 60 and 66.
  • the sealing resin 7 is provided in the dam portion housing area S9.
  • the power module 3 which is the basic form of the third embodiment, is provided with a sealing resin 7 covering the ceramic substrate 10C, the semiconductor element 20, the solder 31, and the solder 32.
  • the power module 3 which is the basic aspect of the third embodiment, has a structure that does not adversely affect the ceramic substrate 10C during the manufacturing stage, and therefore it is possible to improve the performance, including the yield and insulation properties, of the device.
  • the upper surfaces of the metal blocks 60 and 66 in the power module 3 are not covered with the sealing resin 7 and are exposed. Therefore, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 67 fixed on the upper surface of the metal block 66 with a new main terminal. Similarly, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 62 fixed on the upper surface of the metal block 60 with a new main terminal. Therefore, flexibility can be provided when selecting the main terminals 62 and 67.
  • the power module 3 when the power module 3 is completed, it provides the same effects as the basic power module 1, except for the effects attributable to the case 5, and further provides the following effects:
  • the power module 3 does not require a dedicated case and allows the height of the sealing resin 7 to be adjusted relatively easily during manufacturing.
  • the bottom conductor layer 13 of the ceramic substrate 10C is not restricted by the dam portion 9 and the sealing resin 7, which increases the design freedom of the structures formed on the surface of the bottom conductor layer 13, which is the second main surface of the substrate.
  • the fin base 15, which is a heat dissipation fin can be fixed relatively easily by using a material that can be bonded at room temperature as the heat dissipation sheet 73. Therefore, even after the device is completed, the power module 3 can be relatively easily reworked using the heat dissipation sheet 73 to replace the fin base 15 fixed on the surface of the lower conductor layer 13 with a new fin base. In this way, the power module 3 can be relatively easily provided with heat dissipation fins of various shapes.
  • the heat generated during operation of the semiconductor element 20 can be effectively dissipated to the fin base 15 via the ceramic substrate 10C and the heat dissipation sheet 73.
  • the lower conductor layer 13 of the ceramic substrate 10C of the power module 3 is not covered with the sealing resin 7 and is open. Therefore, the mounting surface 15s of the fin base 15 can be relatively easily bonded to the surface of the lower conductor layer 13 via the heat dissipation sheet 73, which can be bonded at room temperature.
  • FIG. 21 to 25 are explanatory diagrams that show a schematic cross-sectional structure during the manufacturing process of the power module 3.
  • An XYZ orthogonal coordinate system is shown in each of Fig. 21 to Fig. 25.
  • the manufacturing method of the power module 3 will be described with reference to Fig. 21 to Fig. 25.
  • the power module 3 includes four semiconductor elements 20, four metal blocks 66, and two metal blocks 60, but for convenience of explanation, the structure shown in Figures 21 to 25 will be used as the basis.
  • the process for forming the metal blocks 60, which are not shown in Figures 21 to 25, is the same as the manufacturing method of the first embodiment shown in Figures 4 to 8.
  • a ceramic substrate 10C is prepared as a substrate for the semiconductor device of the third embodiment.
  • the ceramic substrate 10C and the semiconductor element 20 serve as block mounting members.
  • solder 31 and two semiconductor elements 20 are positioned above the upper conductor layer 12 of the ceramic substrate 10C, and solder 32 and two metal blocks 66 are positioned above the two semiconductor elements 20, and solder bonding is performed using the solder 31 and the solder 32 in a reflow furnace.
  • two semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10C via solder 31, and two metal blocks 66 are mounted on the upper surfaces of the two semiconductor elements 20 via solder 32.
  • the metal blocks 66 are joined via solder 32 to the upper surfaces of the semiconductor elements 20 that serve as block mounting members.
  • a plurality of dam materials 81 are laminated on the upper surface of the silicon nitride base material 11C of the ceramic substrate 10C to form the dam portion 9.
  • the dam materials 81 are laminated, for example, by a coating process using a dispenser.
  • the completed dam portion 9 has a dam portion accommodation area S9, and the dam portion 9 is provided on the upper surface of the silicon nitride base material 11 so that the solder 31, the upper surface conductor layer 12, and the two semiconductor elements 20 are present within the dam portion accommodation area S9.
  • the terminal block 51 is adhered and fixed to a portion of the surface of the upper conductor layer 12 of the ceramic substrate 10C.
  • the signal terminal 63 is integrated with the terminal block 51.
  • wiring is performed using the wire 41. That is, the surface of the terminal horizontal portion 63a and the semiconductor element 20 are electrically connected by the wire 41. After wiring the wire 41, a circuit is formed that includes the two semiconductor elements 20, the wire 41, the two metal blocks 66, and the signal terminal 63.
  • sealing resin 7 is injected into the dam portion housing area S9 and heated to harden so that the upper surfaces and upper portions of the sides of each of the two metal blocks 66 are exposed. In other words, the upper surfaces and upper portions of the sides of the metal blocks 66 are not covered by the sealing resin 7 and are exposed.
  • the solders 31 and 32, the upper surface conductor layer 12 of the ceramic substrate 10C, the two semiconductor elements 20, and the wires 41 are all covered with the sealing resin 7.
  • parts of the two metal blocks 66 and parts of the terminal block 51 are covered with sealing resin 7.
  • the top surfaces and upper parts of the side surfaces of the two metal blocks 66 are not covered with sealing resin 7 and are exposed.
  • the side surfaces of the exposed metal blocks 66 include a pair of exposed side surfaces 66s and 66s that face each other in the X direction.
  • the lower conductor layer 13 of the ceramic substrate 10C and the mounting surface 15s of the fin base 15 are adhesively fixed via the heat dissipation sheet 73.
  • the screw hole regions 66x of the two metal blocks 66 are positioned so that they match the two openings 62o of one main terminal 67 in a plan view, and the metal blocks 66 and the main terminal 67 are connected and fixed using two screws 61.
  • the power module 3 of the third embodiment can fix the main terminal 67 in a state where the metal block 66 is stably restrained by a pair of exposed side surfaces 66s and 66s, so that damage to the solder 31 and the semiconductor element 20 when the main terminal 67 is fixed can be suppressed.
  • the metal block 66 is partially sealed with the sealing resin 7, so when the main terminal 67 is attached to the top surface of the metal block 66 with the two screws 61, the tightening torque of each of the two screws 61 has the effect of reducing damage to the solder 32, which serves as the block bonding material between the metal block 66 and the semiconductor element 20.
  • the manufacturing method for the power module 3 described above includes the following steps (a) to (f) as a manufacturing method for a semiconductor device having a main terminal 67 for transmitting an external signal.
  • Step (a) is a step of preparing a ceramic substrate 10C as a substrate having a first and second main surfaces.
  • Step (b) is a step of mounting a plurality of semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate.”
  • the ceramic substrate 10C and the semiconductor elements 20 function as block mounting members. Step (b) corresponds to the process described with reference to FIG. 21.
  • Step (c) is a step of joining the ceramic substrate 10C, which serves as the block mounting member, and the metal block 60 via solder 31, which functions as a block bonding material, and joining the semiconductor element 20, which serves as the block mounting member, and the metal block 66 via solder 32, which functions as a block bonding material. Step (c) corresponds to the process described with reference to FIG. 21.
  • Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10C, semiconductor element 20, and solders 31 and 32. Step (d) corresponds to the process described with reference to Figures 22 to 24.
  • step (d) After step (d) is performed, the upper surfaces and upper portions of the sides of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, there are a pair of exposed side surfaces 60s and 60s and a pair of exposed side surfaces 66s and 66s that are exposed by about 2 mm from the sealing resin 7.
  • Step (d) includes the following steps (d-1) and (d-2).
  • Step (d-1) is a step of providing a dam portion 9, which is a member for forming a storage space, on the surface of the silicon nitride base material 11C of the ceramic substrate 10C, surrounding the upper surface conductor layer 12, the semiconductor element 20, and the metal blocks 60 and 66 of the ceramic substrate 10C.
  • Step (d-1) corresponds to the process described with reference to FIG. 22.
  • Step (d-2) is a step of forming sealing resin 7 to cover upper surface conductor layer 12, semiconductor element 20, and solders 31 and 32 within dam portion accommodation area S9, which is an element accommodation space surrounded by dam portion 9. Step (d-2) corresponds to the process described with reference to FIG. 24.
  • Step (e) is performed after step (d) described above, and is a step of attaching main terminals 62 and 67 to the upper surfaces of metal blocks 60 and 66, respectively. Step (e) corresponds to the process described with reference to FIG. 25.
  • Step (f) is a step of joining the lower conductor layer 13 and the fin base 15, which is a heat dissipation fin, via the heat dissipation sheet 73. Step (f) corresponds to the process described with reference to FIG. 24.
  • steps (d) and (f) are carried out almost simultaneously, and then step (e) is carried out.
  • the dam portion 9 is formed by stacking multiple dam materials 81 in step (d-1), the height of the sealing resin 7 formed in the dam portion accommodation area S9 of the dam portion 9 in step (d-2) can be adjusted relatively easily without requiring a dedicated case.
  • the fin base 15, which is a heat dissipation fin can be manufactured relatively easily using the heat dissipation sheet 73.
  • the power module 3 which is a semiconductor device manufactured by the manufacturing method of the power module 3
  • a material with relatively high thermal conductivity can be used as the heat dissipation sheet 73 to fix the mounting surface 15s of the fin base 15 and the surface of the lower conductor layer 13 of the ceramic substrate 10C. Therefore, the power module 3 can effectively dissipate heat generated during operation of the semiconductor element 20 to the fin base 15 via the ceramic substrate 10C and the heat dissipation sheet 73.
  • solder 31 is used to join the semiconductor element 20 to the upper conductor layer 12
  • solder 32 is used to join the semiconductor element 20 to the metal block 66, but instead of the solders 31 and 32, a high-melting-point solder with high heat resistance or a silver sintered material may be used.
  • heat dissipation can be improved by using fin base solder with a low melting point instead of the heat dissipation sheet 73 as the joining material between the ceramic substrate 10C and the fin base 15.
  • the metal block 66 is connected to the outside world through the screw hole region 66x, which is the main terminal mounting region, even if the solder 32, whose surface is exposed in the screw hole region 66x, remelts, the increase in volume of the solder 32 is unlikely to cause damage to the sealing resin 7.
  • the power modules 1, 1B, 1C, 2, 2B, and 3 which are the semiconductor devices according to the first to third embodiments, are applied to a power conversion device.
  • the present disclosure is not limited to a specific power conversion device, the following describes the fourth embodiment in the case where the present disclosure is applied to a three-phase inverter.
  • FIG. 26 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to embodiment 4 of the present disclosure is applied.
  • the power conversion system shown in FIG. 26 is composed of a power source 1000, a power conversion device 2000, and a load 3000.
  • the power source 1000 is a DC power source, and supplies DC power to the power conversion device 2000.
  • the power source 1000 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC/DC converter.
  • the power source 1000 may also be composed of a DC/DC converter that converts the DC power output from the DC system into a specified power.
  • the power conversion device 2000 will be described in detail below.
  • the main conversion circuit 2001 includes switching elements and free wheel diodes (not shown), and converts DC power supplied from the power source 1000 into AC power by switching the switching elements, and supplies it to the load 3000.
  • the main conversion circuit 2001 in this embodiment is a two-level three-phase full bridge circuit that can be configured from six switching elements and six free wheel diodes connected in inverse parallel to each switching element.
  • At least one of the switching elements and free wheel diodes of the main conversion circuit 2001 is configured from one of the power modules 1, 1B, 1C, 2, 2B, and 3 used in the above-mentioned embodiments 1 to 3.
  • each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of each upper and lower arm i.e., the three output terminals of the main conversion circuit 2001, are connected to the load 3000.
  • the control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 2001 should be in the on state based on the power to be supplied to the load 3000.
  • the main conversion circuit 2001 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 2001 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • any of the power modules 1, 1B, 1C, 2, 2B, and 3, which are the semiconductor devices of the first to third embodiments, are used as the switching elements and free wheel diodes of the main conversion circuit 2001, thereby improving the yield and performance of the device.
  • the present disclosure is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load.
  • the present disclosure can also be applied to a DC/DC converter or an AC/DC converter when supplying power to a DC load, etc.
  • the power conversion device to which this disclosure is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine or laser processing machine, or an induction heating cooker or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.
  • a semiconductor device having a main terminal for transmitting an external signal, a substrate having first and second major surfaces; A semiconductor element provided on a first main surface of the substrate; a metal block provided on a block mounting member which is at least one of the substrate and the semiconductor element; The block mounting member and the metal block are joined via a block joining material, the metal block has a main terminal attachment region, the main terminal is fixed to the metal block at the main terminal attachment region,
  • the semiconductor device includes: The block mounting member and the block bonding material are covered with a sealing resin provided on the first main surface of the substrate.
  • the semiconductor device has an opening
  • the metal block has a screw hole region extending from an upper surface to a lower surface
  • the main terminal mounting area includes the screw hole area
  • the semiconductor device includes: The main terminal is fixed on the upper surface of the metal block in an attachment manner by inserting the screw portion into the opening and the screw hole region of the main terminal, further comprising a screw having a head and a screw portion.
  • the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material, a surface of the upper conductor layer being a first main surface of the substrate, and a surface of the lower conductor layer being a second main surface of the substrate, The thickness of the metal block in the height direction is greater than the thickness of the upper surface conductor layer.
  • a semiconductor device according to any one of claims 1 to 4, a housing space forming member having an element housing space for housing the substrate, the semiconductor element, and the metal block therein; The sealing resin is provided in the element accommodating space.
  • Semiconductor device
  • the accommodation space forming member includes a case having a case accommodation space, and the element accommodation space includes the case accommodation space; Semiconductor device.
  • the case includes a main terminal case connected to the main terminal such that the main terminal protrudes from the case receiving space to the outside,
  • the sealing resin is provided to cover all of the substrate, the semiconductor element, the metal block, and the main terminals present in the case housing space.
  • the storage space forming member includes a dam portion, A space surrounded by the dam portion is a dam portion accommodating region, and the element accommodating space includes the dam portion accommodating region, The dam portion is composed of a laminated structure of multiple dam materials. Semiconductor device.
  • a dam portion provided to surround the upper surface conductor layer of the insulating substrate, the semiconductor element, and the metal block; the dam portion is provided on the insulating base material of the insulating substrate, The space surrounded by the dam portion becomes a dam portion accommodation area, The dam portion is formed of a laminated structure of a plurality of dam materials, The sealing resin is provided in the dam portion accommodation region of the dam portion.
  • Semiconductor device a dam portion provided to surround the upper surface conductor layer of the insulating substrate, the semiconductor element, and the metal block; the dam portion is provided on the insulating base material of the insulating substrate, The space surrounded by the dam portion becomes a dam portion accommodation area, The dam portion is formed of a laminated structure of a plurality of dam materials, The sealing resin is provided in the dam portion accommodation region of the dam portion.
  • the semiconductor device according to claim 10 The insulating substrate further includes a heat dissipation fin fixed to the surface of the lower conductor layer via a heat dissipation sheet.
  • Semiconductor device Semiconductor device.
  • a method for manufacturing a semiconductor device having a main terminal for transmitting an external signal comprising the steps of: (a) providing a substrate having first and second major surfaces; (b) mounting a semiconductor element on a first main surface of the substrate, wherein at least one of the substrate and the semiconductor element serves as a block mounting member; (c) joining the block mounting member and a metal block via a block joining material; (d) forming a sealing resin to cover at least the block mounting member and the block bonding material, and an upper surface of the metal block is not covered with the sealing resin and is exposed; (e) performing the step after (d), further comprising the step of attaching the main terminal onto an upper surface of the metal block; A method for manufacturing a semiconductor device.
  • a method for manufacturing a semiconductor device comprising: The step (d) (d-1) providing a storage space forming member surrounding the substrate, the semiconductor element, and the metal block; (d-2) forming the sealing resin to cover at least the block mounting member and the block bonding material within the element accommodating space, which is a space surrounded by the accommodating space forming member; A method for manufacturing a semiconductor device.
  • a method for manufacturing a semiconductor device comprising: the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material;
  • the step (b) (b-1) a step of mounting the semiconductor element on the upper surface conductor layer of the insulating substrate, at least one of the insulating substrate having the upper surface conductor layer and the semiconductor element becomes the block mounting member;
  • the method for manufacturing a semiconductor device includes: (f) further comprising a step of joining the lower conductor layer and a heat dis
  • a main conversion circuit having the semiconductor device according to any one of claims 1 to 11, which converts input power and outputs the converted power; a control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit, Power conversion equipment.

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Abstract

The purpose of the present disclosure is to provide a structure for a semiconductor device that has a principal terminal that improves performance and yield. A case accommodation space (S5) that is enclosed by a case (5) of a power module (1) accommodates solder (30, 31), a ceramic substrate (10), a plurality of semiconductor elements (20), wire (41–43), and a sealing resin (7) that is provided on an installation surface (15s) of a fin base (15). The entirety of the solder (30, 31), the plurality of semiconductor elements (20), and the wire (41–43) and a portion of a metal block (60) are covered by the sealing resin (7), but an upper surface and a portion of an upper part of a side surface of the metal block (60) are not covered by the sealing resin (7) and are exposed. A principal terminal (62) is fixed onto the upper surface of the metal block (60) with a screw (61).

Description

半導体装置及びその製造方法並びに電力変換装置Semiconductor device, its manufacturing method, and power conversion device

 本開示は、パワーモジュール等の外部信号伝達用の主端子を有する半導体装置に関する。 This disclosure relates to a semiconductor device having a main terminal for transmitting external signals, such as a power module.

 外部信号伝達用の主端子を有する代表的な半導体装置としてパワーモジュールがある。産業機器から家電・情報端末まであらゆる製品にパワーモジュールが普及しつつあり、高い生産性と組み立て性とともに小型・軽量であることが求められる。パワーモジュールは、発電・送電から効率的なエネルギーの利用・再生まであらゆる場面で利用されている。 Power modules are a typical example of semiconductor devices that have a main terminal for transmitting external signals. Power modules are becoming more common in all kinds of products, from industrial equipment to home appliances and information terminals, and they are required to be small and lightweight, with high productivity and ease of assembly. Power modules are used in a wide range of situations, from power generation and transmission to efficient energy utilization and regeneration.

 パワーモジュールは、動作温度が高く、効率に優れている点で、今後の主流となる可能性が高い。加えて、パワーモジュールは、SiCをはじめとするワイドバンドギャップ半導体に適用できるパッケージ形態であることも同時に求められている。 Power modules are likely to become mainstream in the future due to their high operating temperature and excellent efficiency. In addition, power modules are also required to be packaged in a form that can be applied to wide band gap semiconductors such as SiC.

 パワートランジスタ等の電子部品を搭載する部品搭載基板が例えば特許文献1に開示されている。上述した電子部品がパワーモジュールの構成素子となる。 For example, Patent Document 1 discloses a component mounting board on which electronic components such as power transistors are mounted. The above-mentioned electronic components become the constituent elements of a power module.

特開2016-4644号公報JP 2016-4644 A

 前述したように、パワーモジュールは、環境問題の高まりとともに、電気エネルギーの発電・送電・回生のあらゆる場面で普及しつつある。電気自動車や家電などに用いられるパワーモジュールは特に高い生産性と組み立て性が求められる。また、製造時のエネルギー低減などのために小型・軽量であることが求められる。 As mentioned above, as environmental issues grow, power modules are becoming more common in all aspects of electrical energy generation, transmission, and regeneration. Power modules used in electric vehicles, home appliances, and other applications require particularly high productivity and ease of assembly. They also need to be small and lightweight to reduce energy consumption during manufacturing.

 パワーモジュールは大電流・高電圧を扱うため、機器との電気的な接続は金属板からなり主端子となるバスバーや銅撚線を用いることが多い。パワー半導体素子を搭載した主端子となるバスバーと絶縁基板との固定において、ねじ締めや溶接、はんだ付けなどいくつかの固定方法が用いられている。 Because power modules handle large currents and high voltages, electrical connections to the equipment are often made using bus bars made of metal plates that serve as the main terminals, or copper twisted wire. Several fixing methods, such as screwing, welding, and soldering, are used to fasten the bus bars, which serve as the main terminals and carry the power semiconductor elements, to the insulating substrate.

 特許文献1に開示された部品搭載基板では、基板上にねじ穴を形成した端子台を配置し、端子台と配線ケーブル等の主端子とのねじ締めを行う方法が示されている。 The component mounting board disclosed in Patent Document 1 shows a method of placing a terminal block with a screw hole on the board and tightening the terminal block to the main terminal of a wiring cable or the like with a screw.

 特許文献1で開示された方法をパワーモジュールに適用しようとすると、絶縁基板として一般的に用いられるセラミック基板が脆いために、ねじ締め時のトルクで破損する懸念があった。また、抵抗溶接やレーザ溶接などで主端子となるバスバーと端子台を接合しようとすると、絶縁基板の表面よりも高い位置からのスパッタ飛散によって、完成段階のパワーモジュールにおける絶縁性の劣化の懸念があった。 When attempting to apply the method disclosed in Patent Document 1 to a power module, there was concern that the ceramic substrates commonly used as insulating substrates would be fragile and would be damaged by the torque applied when tightening the screws. In addition, when attempting to join the bus bars that serve as the main terminals to the terminal block by resistance welding or laser welding, there was concern that spatter would fly from a position higher than the surface of the insulating substrate, deteriorating the insulation of the completed power module.

 従来のパワーモジュールで代表される半導体装置は以上のように構成されており、装置の歩留まり及び性能が低いという問題点があった。  Conventional semiconductor devices, such as power modules, are constructed as described above, and have problems with low device yield and performance.

 本開示は上記問題点を解決するためになされたもので、歩留まり及び性能の向上を図った、主端子を有する半導体装置を得ることを目的とする。 This disclosure has been made to solve the above problems, and aims to provide a semiconductor device with a main terminal that improves yield and performance.

 本開示に係る半導体装置は、外部信号伝達用の主端子を有する半導体装置であって、第1及び第2の主面を有する基板と、前記基板の第1の主面上に設けられる半導体素子と、前記基板及び前記半導体素子のうち少なくとも一つであるブロック搭載部材上に設けられる金属ブロックと、前記ブロック搭載部材と前記金属ブロックとはブロック用接合材を介して接合されており、前記金属ブロックは主端子取付領域を有し、前記主端子は前記主端子取付領域にて前記金属ブロックに固定され、前記半導体装置は、少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記基板の第1の主面上に設けられる封止樹脂をさらに備える。 The semiconductor device according to the present disclosure is a semiconductor device having a main terminal for transmitting an external signal, comprising: a substrate having first and second main surfaces; a semiconductor element provided on the first main surface of the substrate; a metal block provided on a block mounting member which is at least one of the substrate and the semiconductor element; the block mounting member and the metal block are joined via a block bonding material, the metal block has a main terminal mounting region, the main terminal is fixed to the metal block at the main terminal mounting region, and the semiconductor device further comprises a sealing resin provided on the first main surface of the substrate, covering at least the block mounting member and the block bonding material.

 本開示の半導体装置は、少なくともブロック搭載部材及びブロック用接合材を覆って設けられる封止樹脂によって、主端子取付領域にて金属ブロックに主端子を取り付ける際における金属ブロックへのダメージを軽減することができる。 The semiconductor device disclosed herein can reduce damage to the metal block when attaching the main terminal to the metal block in the main terminal attachment area by using the sealing resin that covers at least the block mounting member and the block bonding material.

 また、本開示の半導体装置は、基板の第1の主面上に封止樹脂が設けられているため、主端子取付領域にて金属ブロックに主端子を固定する際に基板の第1の主面は封止樹脂により保護されており、基板の性能が劣化することは無い。 In addition, in the semiconductor device disclosed herein, since a sealing resin is provided on the first main surface of the substrate, when the main terminal is fixed to the metal block in the main terminal mounting area, the first main surface of the substrate is protected by the sealing resin, and the performance of the substrate is not deteriorated.

 このように、本開示の半導体装置は、製造段階で基板に悪影響を与えない構造を呈するため、装置の歩留まり及び性能の向上を図ることができる。 In this way, the semiconductor device disclosed herein has a structure that does not adversely affect the substrate during the manufacturing stage, which can improve the yield and performance of the device.

 本開示の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

実施の形態1の基本態様であるパワーモジュールの平面構造を模式的に示す説明図である。FIG. 1 is an explanatory diagram illustrating a planar structure of a power module according to a first embodiment of the present invention; 図1のA-A断面構造を模式的に示す説明図である。FIG. 2 is an explanatory diagram showing a schematic cross-sectional structure taken along line AA in FIG. 図1で示したパワーモジュールの全体構造を示す斜視図である。FIG. 2 is a perspective view showing the overall structure of the power module shown in FIG. 1 . 実施の形態1の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その1)である。FIG. 1 is an explanatory diagram (part 1) showing a schematic cross-sectional structure of a power module according to a basic aspect of the first embodiment during a manufacturing process. 実施の形態1の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その2)である。FIG. 2 is an explanatory diagram (part 2) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process. 実施の形態1の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その3)である。FIG. 11 is an explanatory diagram (part 3) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process. 実施の形態1の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その4)である。FIG. 4 is an explanatory diagram (part 4) showing a schematic cross-sectional structure of the power module according to the basic aspect of the first embodiment during the manufacturing process. 実施の形態1の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その5)である。FIG. 5 is an explanatory diagram (part 5) showing a schematic cross-sectional structure of the power module during the manufacturing process according to the first embodiment; 実施の形態1の第2の態様であるパワーモジュールの断面構造を模式的に示す説明図である。FIG. 2 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a second aspect of the first embodiment. 実施の形態1の第3の態様であるパワーモジュールの断面構造を模式的に示す説明図である。FIG. 11 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a third aspect of the first embodiment. 実施の形態2の基本態様であるパワーモジュールの平面構造を模式的に示す説明図である。FIG. 11 is an explanatory diagram illustrating a planar structure of a power module according to a second embodiment of the present invention; 図11のB-B断面構造を模式的に示す説明図である。12 is an explanatory diagram showing a schematic cross-sectional structure taken along the line BB in FIG. 11. 実施の形態2の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その1)である。FIG. 11 is an explanatory diagram (part 1) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process. 実施の形態2の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その2)である。FIG. 13 is an explanatory diagram (part 2) illustrating a cross-sectional structure during a manufacturing process of a power module according to a basic aspect of the second embodiment. 実施の形態2の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その3)である。FIG. 11 is an explanatory diagram (part 3) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process. 実施の形態2の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その4)である。FIG. 4 is an explanatory diagram (part 4) showing a schematic cross-sectional structure of a power module according to a basic aspect of the second embodiment during a manufacturing process. 実施の形態2の基本態様であるパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その5)である。FIG. 5 is an explanatory diagram (part 5) illustrating a cross-sectional structure during a manufacturing process of a power module according to a basic aspect of the second embodiment. 実施の形態2の第2の態様となるパワーモジュールの断面構造を模式的に示す説明図である。FIG. 11 is an explanatory diagram illustrating a cross-sectional structure of a power module according to a second aspect of the second embodiment. 実施の形態3のパワーモジュールの平面構造を模式的に示す説明図である。FIG. 11 is an explanatory diagram illustrating a planar structure of a power module according to a third embodiment. 図19のC-C断面構造を模式的に示す説明図である。20 is an explanatory diagram showing a schematic cross-sectional structure taken along the line CC in FIG. 19. 実施の形態3のパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その1)である。FIG. 11 is an explanatory diagram (part 1) illustrating a schematic cross-sectional structure during a manufacturing process of a power module according to embodiment 3. 実施の形態3のパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その2)である。FIG. 13 is an explanatory diagram (part 2) illustrating a cross-sectional structure during a manufacturing process of the power module according to the third embodiment. 実施の形態3のパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その3)である。FIG. 13 is an explanatory diagram (part 3) illustrating a schematic cross-sectional structure during the manufacturing process of the power module according to the third embodiment. 実施の形態3のパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その4)である。FIG. 11 is an explanatory diagram (part 4) illustrating a cross-sectional structure during a manufacturing process of the power module according to the third embodiment. 実施の形態3のパワーモジュールの製造工程時における断面構造を模式的に示す説明図(その5)である。FIG. 5 is an explanatory diagram (part 5) illustrating a cross-sectional structure during the manufacturing process of the power module according to the third embodiment. 実施の形態4である電力変換装置を適用した電力変換システムの構成を示すブロック図である。FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.

 <実施の形態1>
 (基本態様)
 以下、本開示の実施の形態1の基本態様の半導体装置となるパワーモジュール1について説明する。
<First embodiment>
(Basic form)
Hereinafter, a power module 1 serving as a semiconductor device according to a basic aspect of the first embodiment of the present disclosure will be described.

 図1はパワーモジュール1の平面構造を模式的に示す説明図である。図2は図1のA-A断面構造を模式的に示す説明図である。図3はパワーモジュール1の全体構造を示す斜視図である。図1~図3それぞれにXYZ直交座標系を記している。なお、図3では封止樹脂7の図示を省略している。 FIG. 1 is an explanatory diagram showing a schematic planar structure of the power module 1. FIG. 2 is an explanatory diagram showing a schematic cross-sectional structure taken along the line A-A in FIG. 1. FIG. 3 is a perspective view showing the overall structure of the power module 1. An XYZ orthogonal coordinate system is shown in each of FIGS. 1 to 3. Note that the sealing resin 7 is not shown in FIG. 3.

 これらの図に示すように、放熱用フィンであるフィンベース15がパワーモジュール1の最下層に設けられている。フィンベース15はベース部15m及び複数のピン15pを有している。ベース部15mの平面形状は例えば100mm×100mmの構成であり、ベース部15mの厚さは例えば3mmに設定される。ベース部15mの構成材料として、銅、ニッケルめっき等が考えられる。 As shown in these figures, a fin base 15, which is a heat dissipation fin, is provided on the bottom layer of the power module 1. The fin base 15 has a base portion 15m and a number of pins 15p. The planar shape of the base portion 15m is, for example, 100 mm x 100 mm, and the thickness of the base portion 15m is set to, for example, 3 mm. Possible materials for the base portion 15m include copper, nickel plating, etc.

 ベース部15mの+Z方向側の上面が載置面15sとなる。載置面15sの平面形状は上述したように例えば100mm×100mmの構成を呈している。後述するケース5やセラミック基板10が載置面15s上に設けられる。ベース部15mの-Z方向側の下面上には、複数のピン15pが等間隔でマトリックス状に設けられている。複数のピン15pそれぞれのXY平面における直径は例えば1.5mmに設定され、Z方向に沿った長さは例えば8mmに設定される。 The upper surface of the base portion 15m on the +Z direction side becomes the mounting surface 15s. As described above, the planar shape of the mounting surface 15s is, for example, 100 mm x 100 mm. The case 5 and ceramic substrate 10, which will be described later, are provided on the mounting surface 15s. On the lower surface on the -Z direction side of the base portion 15m, multiple pins 15p are provided in a matrix shape at equal intervals. The diameter of each of the multiple pins 15p in the XY plane is set to, for example, 1.5 mm, and the length along the Z direction is set to, for example, 8 mm.

 フィンベース15の載置面15s上にケース5が接着された状態で設けられる。ケース5のXY平面での平面形状は例えば92mm×80mmに設定され、ケース5のZ方向に沿った高さは10mm程度有している。ケース5の構成材料としてPPS樹脂が考えられる。 The case 5 is attached to the mounting surface 15s of the fin base 15. The planar shape of the case 5 in the XY plane is set to, for example, 92 mm x 80 mm, and the height of the case 5 in the Z direction is approximately 10 mm. The case 5 is thought to be made of PPS resin.

 このように、パワーモジュール1において、フィンベース15の載置面15sの平面形状(100mm×100mm)は、ケース5の平面形状(92mm×80mm)より広い寸法特性を有している。 In this way, in the power module 1, the planar shape (100 mm x 100 mm) of the mounting surface 15s of the fin base 15 has dimensional characteristics that are wider than the planar shape (92 mm x 80 mm) of the case 5.

 収容空間形成部材であるケース5は内部にケース収容空間S5を有する中空構造を呈しており、ケース収容空間S5内において、フィンベース15の載置面15s上に絶縁基板となるセラミック基板10がはんだ30によって接合されている。ケース収容空間S5の形成深さはケース5の形成高さを反映して10mm程度となる。ケース収容空間S5が収容空間形成部材によって形成される素子収容空間となる。 The case 5, which is the storage space forming member, has a hollow structure with a case storage space S5 inside, and within the case storage space S5, the ceramic substrate 10, which serves as an insulating substrate, is joined by solder 30 onto the mounting surface 15s of the fin base 15. The depth of the case storage space S5 is approximately 10 mm, reflecting the formation height of the case 5. The case storage space S5 is the element storage space formed by the storage space forming member.

 絶縁基板であるセラミック基板10は、絶縁基材となる窒化ケイ素基材11と、窒化ケイ素基材11の+Z方向側の上面上に設けられる上面導体層12と、セラミック基板10の-Z方向側の下面上に設けられる下面導体層13とを有している。上面導体層12の表面が基板の第1の主面となり、下面導体層13の表面が基板の第2の主面となる。 The ceramic substrate 10, which is an insulating substrate, has a silicon nitride substrate 11 that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11 on the +Z direction side, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10 on the -Z direction side. The surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.

 窒化ケイ素基材11のXY平面における平面形状は例えば70mm×58mm構成であり、窒化ケイ素基材11の膜厚、すなわち、Z方向に沿った高さは例えば0.32mmに設定されている。 The planar shape of the silicon nitride substrate 11 in the XY plane is, for example, 70 mm x 58 mm, and the film thickness of the silicon nitride substrate 11, i.e., the height along the Z direction, is set to, for example, 0.32 mm.

 以降、XY平面における平面形状を単に「平面形状」と表記し、Z方向における高さを単に「高さ」と表記する場合がある。 Hereinafter, the planar shape in the XY plane may be referred to simply as the "planar shape," and the height in the Z direction may be referred to simply as the "height."

 上面導体層12及び下面導体層13それぞれの膜厚は例えば0.8mmに設定され、構成材料として例えば銅が用いられる。 The thickness of each of the upper conductor layer 12 and the lower conductor layer 13 is set to, for example, 0.8 mm, and the constituent material is, for example, copper.

 セラミック基板10の上面導体層12の表面上にはんだ31を介して複数の半導体素子20が搭載されている。すなわち、はんだ31を介して基板の第1の主面と複数の半導体素子20とが接合されている。なお、図1に示すように、実施の形態1の基本態様であるパワーモジュール1では複数の半導体素子20として4つの半導体素子20が図示されている。 A plurality of semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10 via solder 31. That is, the first main surface of the substrate and the plurality of semiconductor elements 20 are joined via the solder 31. As shown in FIG. 1, in the power module 1 which is the basic aspect of the first embodiment, four semiconductor elements 20 are shown as the plurality of semiconductor elements 20.

 フィンベース15とセラミック基板10との基板用接合材となるはんだ30や、セラミック基板10と半導体素子20との基板用接合材となるはんだ31は、例えば、スズ96.5%、銀3%、銅0.5%で構成され、はんだ30及びはんだ31の融点は例えば217℃に設定されている。 The solder 30 that serves as the substrate bonding material between the fin base 15 and the ceramic substrate 10, and the solder 31 that serves as the substrate bonding material between the ceramic substrate 10 and the semiconductor element 20, are composed of, for example, 96.5% tin, 3% silver, and 0.5% copper, and the melting points of the solder 30 and the solder 31 are set to, for example, 217°C.

 複数の半導体素子20としてダイオードやIGBT(Insulated Gate Bipolar Transistor)が考えられる。ダイオードは例えばシリコンを構成材料として、平面構成は例えば10mm×8mm構成であり、厚さ(形成高さ)は例えば0.2mmに設定される。IGBTは、例えばシリコンを構成材料として、平面構成は例えば10mm×10mm構成であり、厚さは例えば0.2mmに設定される。 The multiple semiconductor elements 20 may be diodes or IGBTs (Insulated Gate Bipolar Transistors). Diodes may be made of silicon, for example, and have a planar configuration of 10 mm x 8 mm, with a thickness (formation height) set to 0.2 mm, for example. IGBTs may be made of silicon, for example, and have a planar configuration of 10 mm x 10 mm, with a thickness set to 0.2 mm, for example.

 信号端子63は一部がケース5内に挿入される態様でケース5に固定されている。信号端子63は例えば銅を構成材料としており、Y方向に沿った幅は例えば1.5mmに設定され、厚さは例えば0.6mmに設定される。 The signal terminal 63 is fixed to the case 5 in such a manner that a portion of it is inserted into the case 5. The signal terminal 63 is made of, for example, copper, and its width in the Y direction is set to, for example, 1.5 mm, and its thickness is set to, for example, 0.6 mm.

 ケース5は中間水平部5a及び外枠立設部5bを有しており、信号端子63は端子水平部分63aと端子立設部分63bとからなる屈曲形状を呈しており、端子水平部分63aが中間水平部5a内に挿入され、端子立設部分63bの一部が外枠立設部5b内に挿入されている。 The case 5 has an intermediate horizontal portion 5a and an outer frame standing portion 5b, and the signal terminal 63 has a bent shape consisting of a terminal horizontal portion 63a and a terminal standing portion 63b, with the terminal horizontal portion 63a inserted into the intermediate horizontal portion 5a and a part of the terminal standing portion 63b inserted into the outer frame standing portion 5b.

 信号端子63の端子水平部分63aの上面の一部が中間水平部5aから露出しており、露出状態の端子水平部分63aの上面と半導体素子20の上面とがワイヤ41によって電気的に接続されている。ワイヤ41として例えば直径0.15mmでアルミ製のワイヤが用いられる。信号端子63及びワイヤ41を含んで信号回路が構成される。 A portion of the upper surface of the terminal horizontal portion 63a of the signal terminal 63 is exposed from the intermediate horizontal portion 5a, and the upper surface of the exposed terminal horizontal portion 63a is electrically connected to the upper surface of the semiconductor element 20 by a wire 41. For example, an aluminum wire having a diameter of 0.15 mm is used as the wire 41. The signal terminal 63 and the wire 41 form a signal circuit.

 さらに、ワイヤ42は上面導体層12の表面と半導体素子20の表面とを電気的に接続している。ワイヤ43は半導体素子20,20の表面間を電気的に接続している。ワイヤ42及び43として例えば直径0.4mmでアルミ製のワイヤが用いられる。 Furthermore, wire 42 electrically connects the surface of upper conductor layer 12 to the surface of semiconductor element 20. Wire 43 electrically connects the surfaces of semiconductor elements 20, 20. Wires 42 and 43 are, for example, aluminum wires with a diameter of 0.4 mm.

 セラミック基板10の上面導体層12の表面上にはんだ31によって金属ブロック60が固定されている。すなわち、はんだ31の一部が金属ブロック60を固定するためのブロック用接合材として用いられる。 The metal block 60 is fixed to the surface of the upper conductor layer 12 of the ceramic substrate 10 by solder 31. That is, a portion of the solder 31 is used as a block bonding material for fixing the metal block 60.

 金属ブロック60は例えば真鍮製であり、平面構成が7mm×6mmの四角形状で高さが5mmに設定されている。すなわち、金属ブロック60は四角柱形状を呈している。金属ブロック60は上面の中央から下面にかけて設けられるねじ穴領域60xを有している。このように高さ方向に沿って金属ブロック60を貫通するねじ穴領域60xは、主端子取付領域として機能する。 The metal block 60 is made of brass, for example, and has a rectangular shape with a planar configuration of 7 mm x 6 mm and a height of 5 mm. In other words, the metal block 60 has a rectangular prism shape. The metal block 60 has a screw hole region 60x that is provided from the center of the upper surface to the lower surface. The screw hole region 60x that penetrates the metal block 60 in this way along the height direction functions as a main terminal attachment region.

 金属ブロック60のZ方向に沿った高さ方向における厚み(5mm)は、上面導体層12の膜厚(0.8mm)と比較して、十分厚くなるように設定されている。 The thickness (5 mm) of the metal block 60 in the height direction along the Z direction is set to be sufficiently thick compared to the film thickness (0.8 mm) of the upper conductor layer 12.

 パワーモジュール1において、セラミック基板10がブロック搭載部材として機能している。すなわち、ブロック搭載部材となるセラミック基板10と金属ブロック60とははんだ31を介して接合されている。セラミック基板10と金属ブロック60との間のはんだ31がブロック用接合材として機能する。 In the power module 1, the ceramic substrate 10 functions as a block mounting member. That is, the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 are joined via solder 31. The solder 31 between the ceramic substrate 10 and the metal block 60 functions as a joining material for the block.

 金属ブロック60の上面において主端子62がねじ61によって固定されている。主端子62は-X方向側のねじ取付部62aに開口部62oを有している。主端子62は例えば銅製であり、Y方向に沿った幅が8mmに設定され、厚さが1mmに設定される。 The main terminal 62 is fixed to the top surface of the metal block 60 by a screw 61. The main terminal 62 has an opening 62o in the screw attachment portion 62a on the -X direction side. The main terminal 62 is made of copper, for example, and has a width in the Y direction set to 8 mm and a thickness set to 1 mm.

 主端子62において、ねじ取付部62aと反対の+X方向側の端部はケース収容空間S5から、外部にはみ出して設けられる。なお、主端子62としてバスバーや外部配線ケーブル用の端子等が考えられる。 The end of the main terminal 62 on the +X side opposite the screw mounting portion 62a is provided to protrude from the case housing space S5 to the outside. Note that the main terminal 62 may be a bus bar or a terminal for an external wiring cable.

 ねじ61は例えば真鍮製であり、「M4なべねじ」の規格を満足している。ねじ61は頭部61a及びねじ部61bを有し、ねじ部61bの長さは例えば5mmに設定される。主端子62の開口部62o及び金属ブロック60のねじ穴領域60xにねじ61のねじ部61bを挿入する取付態様で金属ブロック60の上面上に主端子62が固定されている。 The screw 61 is made of brass, for example, and meets the standard for an "M4 pan head screw." The screw 61 has a head 61a and a threaded portion 61b, and the length of the threaded portion 61b is set to, for example, 5 mm. The main terminal 62 is fixed onto the top surface of the metal block 60 in an attachment manner in which the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole area 60x of the metal block 60.

 このように、金属ブロック60は主端子取付領域として上面及びねじ穴領域60xを有し、ねじ61によって、主端子62は主端子取付領域にて金属ブロック60に固定されている。 In this way, the metal block 60 has an upper surface and a screw hole area 60x as a main terminal mounting area, and the main terminal 62 is fixed to the metal block 60 in the main terminal mounting area by the screw 61.

 金属ブロック60、ねじ61及び主端子62はパワーモジュール1の主回路に含まれる構成要素となる。 The metal block 60, the screw 61, and the main terminal 62 are components included in the main circuit of the power module 1.

 ケース5によって囲まれるケース収容空間S5内において、フィンベース15の載置面15s上に設けられるはんだ30、セラミック基板10、はんだ31、複数の半導体素子20、ワイヤ41~43を覆って封止樹脂7が設けられる。封止樹脂7の構成材料として、例えばエポキシ樹脂にシリカフィラーを分散させた材料が考えられる。 In the case housing space S5 surrounded by the case 5, sealing resin 7 is provided to cover the solder 30 provided on the mounting surface 15s of the fin base 15, the ceramic substrate 10, the solder 31, the semiconductor elements 20, and the wires 41 to 43. The sealing resin 7 may be made of, for example, epoxy resin with silica filler dispersed therein.

 金属ブロック60の上面及び側面の上方の一部は封止樹脂7よって覆われておらず露出状態となっている。例えば、ケース収容空間S5内において封止樹脂7により深さ8mmまで封止されており、金属ブロック60は上面から2mm程度、露出している。 The top surface and a portion of the upper side of the metal block 60 are not covered by the sealing resin 7 and are exposed. For example, the case storage space S5 is sealed with the sealing resin 7 to a depth of 8 mm, and the metal block 60 is exposed about 2 mm from the top surface.

 すなわち、金属ブロック60の側面の上方の一部は封止樹脂7によって覆われておらず露出状態であり、露出状態の金属ブロック60の側面は、Y方向に平行な面でかつX方向で対向する一対の露出側面60s及び60sを含んでいる。 In other words, an upper portion of the side of the metal block 60 is not covered by the sealing resin 7 and is exposed, and the exposed side of the metal block 60 includes a pair of exposed side surfaces 60s and 60s that are parallel to the Y direction and face each other in the X direction.

 一対の露出側面60s及び60sは封止樹脂7から2mm程度露出しているため、既存の拘束用治具を用いて一対の露出側面60s及び60sを挟んで把持する態様で金属ブロック60を拘束することができる。 Since the pair of exposed side surfaces 60s and 60s are exposed from the sealing resin 7 by about 2 mm, the metal block 60 can be restrained by clamping the pair of exposed side surfaces 60s and 60s using an existing restraining tool.

 なお、露出側面60sにおける露出幅及び露出長は、既存の拘束用治具を用いて金属ブロック60を拘束することができる範囲の長さに設定する必要がある。 The exposed width and exposed length of the exposed side surface 60s must be set to a length that allows the metal block 60 to be restrained using an existing restraining tool.

 パワーモジュール1は、セラミック基板10、複数の半導体素子20、金属ブロック60を内部に収容する素子収容空間として、ケース5内にケース収容空間S5を設けている。そして、封止樹脂7はケース収容空間S5内に設けられる。 The power module 1 has a case housing space S5 in the case 5 as an element housing space that houses the ceramic substrate 10, the multiple semiconductor elements 20, and the metal block 60. The sealing resin 7 is provided in the case housing space S5.

 実施の形態1の基本態様であるパワーモジュール1は、ブロック搭載部材となるセラミック基板10及びブロック用接合材となるはんだ31を覆って封止樹脂7が設けられている。このため、金属ブロック60の付け根部分が封止樹脂7によって補強されている。 The power module 1, which is the basic aspect of the first embodiment, is provided with sealing resin 7 covering the ceramic substrate 10 that serves as the block mounting member and the solder 31 that serves as the bonding material for the block. Therefore, the base portion of the metal block 60 is reinforced by the sealing resin 7.

 したがって、ねじ61を用いて、主端子取付領域にて主端子62を取り付ける際における金属ブロック60のダメージを封止樹脂7によって軽減することができる。なお、パワーモジュール1において、金属ブロック60の上面及びねじ穴領域60xが主端子取付領域となる。 Therefore, the sealing resin 7 can reduce damage to the metal block 60 when the main terminal 62 is attached to the main terminal attachment area using the screw 61. In the power module 1, the top surface of the metal block 60 and the screw hole area 60x form the main terminal attachment area.

 また、パワーモジュール1では、基板の第1の主面となる上面導体層12の表面上に封止樹脂7が設けられているため、上述した主端子取付領域にて金属ブロック60に主端子62を取り付ける際に上面導体層12の表面は封止樹脂7により保護されている。このため、主端子62を金属ブロック60に固定する際にセラミック基板10の性能が劣化することは無い。絶縁基板であるセラミック基板10の性能として例えば絶縁性が考えられる。 In addition, in the power module 1, since the sealing resin 7 is provided on the surface of the upper conductor layer 12, which is the first main surface of the substrate, the surface of the upper conductor layer 12 is protected by the sealing resin 7 when the main terminal 62 is attached to the metal block 60 in the main terminal attachment region described above. Therefore, the performance of the ceramic substrate 10 is not deteriorated when the main terminal 62 is fixed to the metal block 60. For example, the insulating property can be considered as the performance of the ceramic substrate 10, which is an insulating substrate.

 このように、実施の形態1の基本態様であるパワーモジュール1は、製造段階でセラミック基板10に悪影響を与えない構造を呈するため、装置の歩留まり及び性能の向上を図ることができる。 In this way, the power module 1, which is the basic aspect of the first embodiment, has a structure that does not adversely affect the ceramic substrate 10 during the manufacturing stage, thereby improving the yield and performance of the device.

 パワーモジュール1における金属ブロック60の上面は封止樹脂7によって覆われておらず露出状態であるため、装置完成後においても金属ブロック60の上面上に固定される主端子62を新たな主端子に取り替えるリワークを比較的簡単に行うことができる。したがって、主端子62の選択に際しフレキシビリティを持たせることができる。 The top surface of the metal block 60 in the power module 1 is exposed and not covered by the sealing resin 7, so that even after the device is completed, rework can be performed relatively easily to replace the main terminal 62 fixed on the top surface of the metal block 60 with a new main terminal. This allows for flexibility in the selection of the main terminal 62.

 パワーモジュール1は、ねじ61を用いた取付態様で金属ブロック60の上面上に主端子62を比較的簡単に固定することができる。 The power module 1 can be attached relatively easily by fixing the main terminal 62 to the top surface of the metal block 60 using screws 61.

 パワーモジュール1は、収容空間形成部材であるケース5の素子収容空間となるケース収容空間S5内に封止樹脂7を設けることにより、製造時における封止樹脂7の高さ調整を比較的簡単に行うことができる。 The power module 1 has sealing resin 7 disposed in the case housing space S5, which is the element housing space of the case 5, which is the housing space forming member, and this allows the height of the sealing resin 7 to be adjusted relatively easily during manufacturing.

 パワーモジュール1は基板の第2の主面側となるセラミック基板10の下面導体層13の表面上にはんだ30を介して放熱用フィンとなるフィンベース15が設けられている。このため、複数の半導体素子20の動作時に発生する熱を、セラミック基板10及びフィンベース15を含む放熱経路によって効果的に放熱することができる。 The power module 1 has a fin base 15, which serves as a heat dissipation fin, provided via solder 30 on the surface of the lower conductor layer 13 of the ceramic substrate 10, which forms the second main surface of the substrate. Therefore, heat generated during operation of the multiple semiconductor elements 20 can be effectively dissipated by a heat dissipation path that includes the ceramic substrate 10 and the fin base 15.

 パワーモジュール1における収容空間形成部材となるケース5は、放熱用フィンとなるフィンベース15の載置面15s上に設けられているため、素子収容空間となるケース収容空間S5を確保して安定性良く設けることができる。 The case 5, which is the storage space forming member in the power module 1, is provided on the mounting surface 15s of the fin base 15, which serves as the heat dissipation fin, so that the case storage space S5, which serves as the element storage space, can be secured and provided with good stability.

 パワーモジュール1は専用のケース5によってケース収容空間S5を確保しているため、ケース収容空間S5内に複数の半導体素子20及び金属ブロック60を安定性良く収容し、製造時における封止樹脂7の高さ調整を精度良く行うことができる。 The power module 1 has a case housing space S5 secured by a dedicated case 5, so multiple semiconductor elements 20 and metal blocks 60 can be stably housed within the case housing space S5, and the height of the sealing resin 7 can be adjusted with high precision during manufacturing.

 (基本態様の製造方法)
 図4~図8は実施の形態1の基本態様であるパワーモジュール1の製造工程時における断面構造を模式的に示す説明図である。図4~図8それぞれにXYZ直交座標系を記している。以下、図4~図8を参照してパワーモジュール1の製造方法を説明する。
(Production method of the basic embodiment)
4 to 8 are explanatory diagrams that show schematic cross-sectional structures of the power module 1 during the manufacturing process, which is a basic aspect of the first embodiment. An XYZ orthogonal coordinate system is depicted in each of Figs. 4 to 8. The manufacturing method of the power module 1 will be described below with reference to Figs. 4 to 8.

 なお、図1~図3に示すように、パワーモジュール1は、4つの半導体素子20と3つの金属ブロック60を含んでいるが、以下では説明の都合上、図4~図8で図示された構造を基準として説明する。 As shown in Figures 1 to 3, the power module 1 includes four semiconductor elements 20 and three metal blocks 60, but for ease of explanation, the following description will be based on the structure shown in Figures 4 to 8.

 まず、実施の形態1の半導体装置用の基板となるセラミック基板10が準備される。セラミック基板10は絶縁基材である窒化ケイ素基材11と窒化ケイ素基材11の上面上に設けられる上面導体層12と、窒化ケイ素基材11の下面上に設けられる下面導体層13とを有している。パワーモジュール1ではセラミック基板10がブロック搭載部材となっている。 First, a ceramic substrate 10 is prepared as the substrate for the semiconductor device of the first embodiment. The ceramic substrate 10 has a silicon nitride substrate 11 which is an insulating substrate, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11, and a lower conductor layer 13 provided on the lower surface of the silicon nitride substrate 11. In the power module 1, the ceramic substrate 10 serves as a block mounting member.

 次に、図4に示すように、セラミック基板10の上面導体層12の上方に、はんだ31と2つの半導体素子20及び1つの金属ブロック60を位置決め配置し、リフロー炉を用いてはんだ31によるはんだ接合を行う。 Next, as shown in FIG. 4, the solder 31, two semiconductor elements 20, and one metal block 60 are positioned above the upper conductor layer 12 of the ceramic substrate 10, and solder bonding is performed using the solder 31 in a reflow furnace.

 その結果、セラミック基板10の上面導体層12の表面上に2つの半導体素子20及び1つの金属ブロック60搭載される。すなわち、金属ブロック60はブロック搭載部材となるセラミック基板10の第1の主面上にはんだ31を介して接合される。 As a result, two semiconductor elements 20 and one metal block 60 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10. That is, the metal block 60 is joined via the solder 31 to the first main surface of the ceramic substrate 10, which serves as the block mounting member.

 その後、図5に示すように、フィンベース15の載置面15s上にはんだ30を介してセラミック基板10の下面導体層13の表面を接合する。すなわち、セラミック基板10の下面導体層13の表面上に放熱用フィンであるフィンベース15が固定される。 Then, as shown in FIG. 5, the surface of the lower conductor layer 13 of the ceramic substrate 10 is joined to the mounting surface 15s of the fin base 15 via solder 30. In other words, the fin base 15, which is a heat dissipation fin, is fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10.

 次に、図6に示すように、フィンベース15の載置面15s上にケース5を接着して固定する。収容空間形成部材であるケース5は素子収容空間となるケース収容空間S5を有しており、ケース収容空間S5内にはんだ30及びセラミック基板10を収容すべく、ケース5はフィンベース15の載置面15s上に固定される。 Next, as shown in FIG. 6, the case 5 is glued and fixed onto the mounting surface 15s of the fin base 15. The case 5, which is a member forming the housing space, has a case housing space S5 that serves as the element housing space, and the case 5 is fixed onto the mounting surface 15s of the fin base 15 to house the solder 30 and the ceramic substrate 10 within the case housing space S5.

 また、信号端子63はケース5に一体化されており、端子水平部分63aが中間水平部5a内に設けられ、外枠立設部5b内に端子立設部分63bの一部が設けられている。ケース5のフィンベース15に固定後において、中間水平部5aは上面導体層12の上方に位置しており、端子水平部分63aの表面の一部が露出している。 The signal terminal 63 is integrated with the case 5, with the terminal horizontal portion 63a provided within the intermediate horizontal portion 5a and a portion of the terminal standing portion 63b provided within the outer frame standing portion 5b. After being fixed to the fin base 15 of the case 5, the intermediate horizontal portion 5a is located above the upper surface conductor layer 12 and a portion of the surface of the terminal horizontal portion 63a is exposed.

 ケース5をフィンベース15に固定した後、ワイヤ41~43による配線が行われる。すなわち、ワイヤ41によって端子水平部分63aの表面と半導体素子20とが電気的に接続され、ワイヤ42によって半導体素子20と上面導体層12とが電気的に接続され、ワイヤ43によって、半導体素子20,20間が電気的に接続される。ワイヤ41~43の配線後、2つの半導体素子20、ワイヤ41~43、金属ブロック60及び信号端子63を含む回路が形成される。 After the case 5 is fixed to the fin base 15, wiring is performed using wires 41 to 43. That is, wire 41 electrically connects the surface of the terminal horizontal portion 63a to the semiconductor element 20, wire 42 electrically connects the semiconductor element 20 to the upper surface conductor layer 12, and wire 43 electrically connects the semiconductor elements 20, 20 together. After wiring the wires 41 to 43, a circuit is formed that includes the two semiconductor elements 20, wires 41 to 43, metal block 60, and signal terminal 63.

 次に、図7に示すように、金属ブロック60の上面及び側面の上方の一部が露出する程度に、ケース収容空間S5内に封止樹脂7を注入して加熱硬化させる。その結果、ケース収容空間S5内において、はんだ30、セラミック基板10、複数の半導体素子20及びワイヤ41~43は全て封止樹脂7によって覆われる。 Next, as shown in FIG. 7, sealing resin 7 is injected into the case housing space S5 to the extent that the top surface and a portion of the upper side of the metal block 60 are exposed, and then heated and cured. As a result, the solder 30, ceramic substrate 10, semiconductor elements 20, and wires 41 to 43 are all covered with sealing resin 7 within the case housing space S5.

 一方、金属ブロック60の上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となっている。すなわち、露出状態の金属ブロック60の側面は、X方向で対向する一対の露出側面60s及び60sを含んでいる。一対の露出側面60s及び60sは共にYZ面に平行な面となる。また、ねじ穴領域60x内にも封止樹脂7は設けられない。 On the other hand, the top surface and a portion of the upper part of the side surface of the metal block 60 are not covered with the sealing resin 7 and are exposed. That is, the exposed side surface of the metal block 60 includes a pair of exposed side surfaces 60s and 60s that face each other in the X direction. The pair of exposed side surfaces 60s and 60s are both parallel to the YZ plane. Furthermore, no sealing resin 7 is provided in the screw hole region 60x.

 最後に、図8に示すように、金属ブロック60のねじ穴領域60xと主端子62の開口部62oとが平面視して合致するように位置決めし、ねじ61を用いて金属ブロック60と主端子62とを接続固定する。 Finally, as shown in FIG. 8, the screw hole area 60x of the metal block 60 and the opening 62o of the main terminal 62 are positioned so that they match in a plan view, and the metal block 60 and the main terminal 62 are connected and fixed using the screw 61.

 すなわち、主端子62の開口部62o及び金属ブロック60のねじ穴領域60xにねじ61のねじ部61bを挿入する取付態様で金属ブロック60の上面上に主端子62が固定される。 In other words, the main terminal 62 is fixed to the top surface of the metal block 60 in an installation manner in which the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole region 60x of the metal block 60.

 図8に示すように、封止樹脂7により金属ブロック60を途中まで封止しているため、ねじ61によって主端子62を金属ブロック60の上面上に取り付ける際、ねじ61の締め付けるトルクによって金属ブロック60と上面導体層12とを接合するブロック用接合材となるはんだ31等へのダメージを低減することができる効果を奏する。この効果を最大化するために、金属ブロック60の高さの20%以上まで封止樹脂7が存在するように、封止樹脂7の形成深さを設定することが望ましい。 As shown in FIG. 8, the metal block 60 is sealed partway with the sealing resin 7, so when the main terminal 62 is attached to the top surface of the metal block 60 with the screw 61, the tightening torque of the screw 61 reduces damage to the solder 31, which serves as the block bonding material that bonds the metal block 60 to the top conductor layer 12. To maximize this effect, it is desirable to set the depth of the sealing resin 7 so that the sealing resin 7 is present up to 20% or more of the height of the metal block 60.

 加えて、一対の露出側面60s及び60sは封止樹脂7から2mm程度露出しているため、既存の拘束用治具を用いて一対の露出側面60s及び60sを挟んで把持する態様で金属ブロック60を拘束することができる。 In addition, since the pair of exposed side surfaces 60s and 60s are exposed by about 2 mm from the sealing resin 7, the metal block 60 can be restrained by clamping the pair of exposed side surfaces 60s and 60s using an existing restraining tool.

 したがって、金属ブロック60を安定性良く固定した状態で、主端子62の開口部62o及び金属ブロック60のねじ穴領域60xにねじ61のねじ部61bを挿入した後、ねじ61を既定のトルクで締め付けることにより、金属ブロック60の上面上に主端子62を締結して固定することができる。 Therefore, with the metal block 60 stably fixed, the threaded portion 61b of the screw 61 is inserted into the opening 62o of the main terminal 62 and the threaded hole area 60x of the metal block 60, and then the screw 61 is tightened with a predetermined torque, thereby fastening and fixing the main terminal 62 to the upper surface of the metal block 60.

 このように、一対の露出側面60s及び60sにて金属ブロック60を安定性良く拘束した状態で主端子62を固定することができるため、主端子62の固定時における固定ブロック用接合材であるはんだ31へのダメージをさらに抑制し、さらに半導体素子20へのダメージを抑制することができる。 In this way, the main terminal 62 can be fixed with the metal block 60 stably restrained by the pair of exposed side surfaces 60s and 60s, which further reduces damage to the solder 31, which is the joining material for the fixing block, when the main terminal 62 is fixed, and further reduces damage to the semiconductor element 20.

 パワーモジュール1では、フィンベース15の素材として銅を用いたが、一部にニッケルめっきを施したアルミをフィンベース15の構成材料として用いても同様の効果が得られる。 In the power module 1, copper is used as the material for the fin base 15, but the same effect can be obtained by using aluminum partially nickel-plated as the constituent material for the fin base 15.

 半導体素子20をシリコン製としたが、シリコンカーバイドや窒化ガリウムなどのワイドバンドギャップ半導体を用いて半導体素子20を構成しても同様の効果が得られる。 Although the semiconductor element 20 is made of silicon, the same effect can be obtained by constructing the semiconductor element 20 using a wide band gap semiconductor such as silicon carbide or gallium nitride.

 はんだ30及びはんだ31については、スズ96.5%、銀3%、銅0.5%、融点217℃のはんだ材を用いたが、スズ99.3%、銅0.7%、融点224℃等のはんだ材をはんだ30またははんだ31に用いても同様の効果が得られる。 For solder 30 and solder 31, a solder material consisting of 96.5% tin, 3% silver, 0.5% copper, with a melting point of 217°C was used, but the same effect can be obtained by using a solder material consisting of 99.3% tin, 0.7% copper, with a melting point of 224°C, etc. for solder 30 or solder 31.

 また、半導体素子20とセラミック基板10とを接合する基板用接合材または金属ブロック60とセラミック基板10とを接合するブロック用接合材として用いたはんだ31を、はんだよりも耐熱性に優れた銀焼結材やろう付け材に置き換えても同様の効果が得られる。 The same effect can also be obtained by replacing the solder 31 used as the substrate bonding material for bonding the semiconductor element 20 to the ceramic substrate 10 or the block bonding material for bonding the metal block 60 to the ceramic substrate 10 with a silver sintered material or brazing material that has better heat resistance than solder.

 ワイヤ41~43はアルミ製のものを用いたが、鉄などの添加剤を微量含んだアルミ合金製や銅製のワイヤをワイヤ41~43として用いても同様の効果が得られる。また、ワイヤ41~43の代替材としてアルミや銅製のリボンボンドを用いたり、銅製などのリードフレームを用いてはんだ付けを行ったりしても同様の効果が得られる。 The wires 41 to 43 used are made of aluminum, but the same effect can be obtained by using wires 41 to 43 made of aluminum alloy containing trace amounts of additives such as iron or copper. The same effect can also be obtained by using aluminum or copper ribbon bonds as an alternative material for the wires 41 to 43, or by soldering using a lead frame made of copper or the like.

 ねじ61については、突起形状によるノイズの懸念がある場合、「なべねじ」や「低頭ねじ」または樹脂製のねじを用いることで改善することが期待できる。 As for the screw 61, if there is concern about noise due to the protruding shape, it is expected that this can be improved by using a "pan head screw", "low head screw" or a screw made of plastic.

 ポッティング封止樹脂である封止樹脂7としてシリカフィラーを分散させたエポキシ樹脂を用いたが、アルミナなどのフィラーでもよく、エポキシ樹脂にシリコン樹脂を混合させたものや、シリコーンゲルを封止樹脂7の構成材料としても同様の効果が得られる。 Epoxy resin with dispersed silica filler was used as the potting sealing resin 7, but fillers such as alumina may also be used, and the same effect can be obtained by mixing epoxy resin with silicone resin or using silicone gel as the constituent material of the sealing resin 7.

 また、本明細書では、パワーモジュール1としてケース5に封止樹脂7を注入したケース型モジュールを示したが、封止樹脂を金型成型したトランスファモールド型モジュールで構成しても同様の効果が得られる。 In addition, in this specification, a case-type module in which sealing resin 7 is injected into case 5 is shown as the power module 1, but the same effect can be obtained by configuring it as a transfer mold type module in which the sealing resin is molded using a die.

 上述したパワーモジュール1の製造方法は、外部信号伝達用の主端子62を有する半導体装置の製造方法として以下のステップ(a)~(e)を備えている。 The manufacturing method for the power module 1 described above includes the following steps (a) to (e) as a manufacturing method for a semiconductor device having a main terminal 62 for transmitting an external signal.

 ステップ(a)は、第1及び第2の主面を有する基板としてセラミック基板10を準備するステップである。 Step (a) is a step of preparing a ceramic substrate 10 as a substrate having a first and second main surfaces.

 ステップ(b)は、「基板の第1の主面」となる上面導体層12の表面上に複数の半導体素子20を搭載するステップである。ステップ(b)は図4を参照して説明した処理に対応している。 Step (b) is a step of mounting multiple semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate." Step (b) corresponds to the process described with reference to FIG. 4.

 セラミック基板10及び半導体素子20のうち少なくとも一つがブロック搭載部材となる。実施の形態1の基本態様では、セラミック基板10がブロック搭載部材として機能している。 At least one of the ceramic substrate 10 and the semiconductor element 20 serves as a block mounting member. In the basic form of the first embodiment, the ceramic substrate 10 functions as the block mounting member.

 ステップ(c)は、ブロック搭載部材となるセラミック基板10と金属ブロック60とをブロック用接合材として機能するはんだ31を介して接合するステップである。ステップ(c)は図4を参照して説明した処理に対応している。 Step (c) is a step of joining the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 via the solder 31, which functions as a joining material for the block. Step (c) corresponds to the process described with reference to FIG. 4.

 ステップ(d)は、ブロック搭載部材となるセラミック基板10及びブロック用接合材となるはんだ31を覆って封止樹脂7を形成するステップである。ステップ(d)は図6及び図7を参照して説明した処理に対応している。 Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10, which serves as a block mounting member, and solder 31, which serves as a bonding material for the block. Step (d) corresponds to the process described with reference to Figures 6 and 7.

 ステップ(d)の実行後、金属ブロック60の上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となる。したがって、封止樹脂7から2mm程度露出した一対の露出側面60s及び60sが存在する。 After step (d) is performed, the top surface and a portion of the upper part of the side surface of the metal block 60 are not covered by the sealing resin 7 and are exposed. Therefore, there is a pair of exposed side surfaces 60s and 60s that are exposed by about 2 mm from the sealing resin 7.

 ステップ(d)は以下のステップ(d-1)及び(d-2)を含んでいる。 Step (d) includes the following steps (d-1) and (d-2).

 ステップ(d-1)は、セラミック基板10、半導体素子20、及び金属ブロック60を囲んで収容空間形成部材であるケース5をフィンベース15の載置面15s上に固定するステップである。ステップ(d-1)は図6を参照して説明した処理に対応している。 Step (d-1) is a step of fixing the case 5, which is a member for forming a storage space and surrounds the ceramic substrate 10, the semiconductor element 20, and the metal block 60, onto the mounting surface 15s of the fin base 15. Step (d-1) corresponds to the process described with reference to FIG. 6.

 ステップ(d-2)は、ケース5で囲われた素子収容空間であるケース収容空間S5内において、セラミック基板10及びはんだ31を覆って封止樹脂7を形成するステップである。ステップ(d-2)は図7を参照して説明した処理に対応している。 Step (d-2) is a step of forming sealing resin 7 to cover ceramic substrate 10 and solder 31 in case housing space S5, which is an element housing space surrounded by case 5. Step (d-2) corresponds to the process described with reference to FIG. 7.

 ステップ(e)は、上述したステップ(d)後に実行され、金属ブロック60の上面上に主端子62を取り付けるステップである。ステップ(e)は図8を参照して説明した処理に対応している。 Step (e) is performed after the above-mentioned step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60. Step (e) corresponds to the process described with reference to FIG. 8.

 実施の形態1の半導体装置の製造方法で製造される半導体装置であるパワーモジュール1は、少なくともブロック搭載部材となるセラミック基板10及びブロック用接合材となるはんだ31を覆って設けられる封止樹脂7によって、ステップ(e)のねじ締め処理の実行時における金属ブロック60へのダメージを軽減することができる。 The power module 1, which is a semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment, can reduce damage to the metal block 60 during the screw tightening process in step (e) by the sealing resin 7 that is provided to cover at least the ceramic substrate 10 that serves as the block mounting member and the solder 31 that serves as the block bonding material.

 実施の形態1の半導体装置の製造方法のステップ(e)の実行時に、金属ブロック60の上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態である。このため、金属ブロック60の上面上に取り付けられる主端子62を新たな主端子に取り替えるリワークを、ステップ(e)として支障なく比較的簡単に行うことができる。 When step (e) of the method for manufacturing a semiconductor device according to the first embodiment is performed, the upper surface and a part of the upper side of the metal block 60 are not covered by the sealing resin 7 and are exposed. Therefore, rework in which the main terminal 62 attached to the upper surface of the metal block 60 is replaced with a new main terminal can be performed relatively easily without any problems as step (e).

 加えて、前述したように、一対の露出側面60s及び60sにて金属ブロック60を安定性良く拘束した状態で主端子62を固定することができるため、主端子62の固定時におけるはんだ31や半導体素子20へのダメージを抑制することができる。 In addition, as described above, the main terminal 62 can be fixed in a state where the metal block 60 is stably held by the pair of exposed side surfaces 60s and 60s, so damage to the solder 31 and the semiconductor element 20 when the main terminal 62 is fixed can be suppressed.

 さらに、ステップ(d-2)において、ステップ(d-1)の実行時に設けられたケース5のケース収容空間S5内に封止樹脂7を形成することにより、封止樹脂7の高さ調整を比較的簡単に行うことができる。 Furthermore, in step (d-2), by forming the sealing resin 7 in the case accommodation space S5 of the case 5 that was provided when step (d-1) was performed, the height of the sealing resin 7 can be adjusted relatively easily.

 (第2の態様)
 図9は実施の形態1の第2の態様の半導体装置となるパワーモジュール1Bの断面構造を模式的に示す説明図である。図9は基本態様で示した図1のA-A断面構造に相当する。図9にXYZ直交座標系を記している。
(Second Aspect)
Fig. 9 is an explanatory diagram showing a schematic cross-sectional structure of a power module 1B which is a semiconductor device according to a second aspect of the first embodiment. Fig. 9 corresponds to the cross-sectional structure taken along line A-A in Fig. 1 which shows the basic aspect. An XYZ orthogonal coordinate system is shown in Fig. 9.

 実施の形態1の第2の態様であるパワーモジュール1Bに関し、基本態様のパワーモジュール1と同様な構成要素は同一符号を付して説明を適宜省略する。以下、図1~図3で示した基本態様のパワーモジュール1と異なるパワーモジュール1Bの特徴箇所を中心に説明する。 With regard to the power module 1B, which is the second aspect of the first embodiment, components similar to those of the power module 1 of the basic aspect are given the same reference numerals and explanations thereof are omitted as appropriate. The following will focus on the characteristics of the power module 1B that differ from the power module 1 of the basic aspect shown in Figures 1 to 3.

 図9に示すように、パワーモジュール1Bは主端子62の金属ブロック60の上面への固定をレーザ溶接等の主端子接合処理によって行った点がパワーモジュール1と異なる。すなわち、パワーモジュール1Bの金属ブロック60に関し、主端子取付領域は金属ブロック60の上面のみとなる。 As shown in FIG. 9, power module 1B differs from power module 1 in that the main terminals 62 are fixed to the top surface of the metal block 60 by a main terminal joining process such as laser welding. In other words, the main terminal attachment area for the metal block 60 of power module 1B is only the top surface of the metal block 60.

 したがって、パワーモジュール1Bは、パワーモジュール1と異なり、少なくとも装置完成段階においてねじ61を構成要素として含んでいない。 Therefore, unlike power module 1, power module 1B does not include screws 61 as a component, at least at the device completion stage.

 図9に示すように、主端子62の溶接固定部62wを金属ブロック60の上面上に位置決めして、レーザ65を照射するレーザ溶接処理を行い、金属ブロック60の上面上に主端子62の溶接固定部62wを接合している。なお、レーザ65として例えば、出力5kWのYAGレーザが考えられる。このように、図9では主端子接合処理としてレーザ溶接処理を示している。 As shown in FIG. 9, the welded portion 62w of the main terminal 62 is positioned on the top surface of the metal block 60, and a laser welding process is performed by irradiating a laser 65, and the welded portion 62w of the main terminal 62 is joined to the top surface of the metal block 60. Note that the laser 65 may be, for example, a YAG laser with an output of 5 kW. Thus, FIG. 9 shows the laser welding process as the main terminal joining process.

 なお、金属ブロック60は銅や銅合金製でもよく、真鍮などを素材とするナットでも代用することができる。 The metal block 60 may be made of copper or a copper alloy, and a nut made of brass or other material may also be used.

 実施の形態1の第2の態様であるパワーモジュール1Bは、ブロック搭載部材となるセラミック基板10及びブロック用接合材となるはんだ31を覆って封止樹脂7が設けられている。 The power module 1B, which is the second aspect of the first embodiment, is provided with sealing resin 7 covering ceramic substrate 10, which serves as the block mounting member, and solder 31, which serves as the bonding material for the block.

 したがって、レーザ溶接等の主端子接合処理によって、主端子62を固定する際における金属ブロック60のダメージを封止樹脂7によって軽減することができる。 Therefore, the sealing resin 7 can reduce damage to the metal block 60 when fixing the main terminal 62 by a main terminal joining process such as laser welding.

 また、パワーモジュール1Bでは、基板の第1の主面となる上面導体層12の表面上に封止樹脂7が設けられているため、金属ブロック60に主端子62を固定する際に上面導体層12の表面は封止樹脂7により保護されており、主端子接合処理の実行時に生じる溶接スパッタ等によりセラミック基板10の性能が劣化することは無い。 In addition, in the power module 1B, the sealing resin 7 is provided on the surface of the upper conductor layer 12, which is the first main surface of the substrate. Therefore, when the main terminals 62 are fixed to the metal block 60, the surface of the upper conductor layer 12 is protected by the sealing resin 7, and the performance of the ceramic substrate 10 is not degraded by welding spatters, etc., that occur when performing the main terminal joining process.

 このように、実施の形態1の第2の態様であるパワーモジュール1Bは、製造段階でセラミック基板10に悪影響を与えない構造を呈するため、基本態様と同様、装置の歩留まり及び性能の向上を図ることができる。 In this way, the power module 1B, which is the second aspect of the first embodiment, has a structure that does not adversely affect the ceramic substrate 10 during the manufacturing stage, and thus, like the basic aspect, it is possible to improve the yield and performance of the device.

 パワーモジュール1Bにおける金属ブロック60の高さ方向における厚み(5mm)は、上面導体層の膜厚(0.8mm)より十分厚いため、金属ブロック60は比較的大きな熱容量を有している。 The height-wise thickness (5 mm) of the metal block 60 in the power module 1B is sufficiently thicker than the film thickness (0.8 mm) of the upper conductor layer, so the metal block 60 has a relatively large heat capacity.

 このため、レーザ溶接等の主端子接合処理を実行して、金属ブロック60の上面上に主端子62を固定する際に、絶縁基板であるセラミック基板10に対する熱影響を、比較的大きな熱容量を有する金属ブロック60によって抑制することができる。 As a result, when performing a main terminal joining process such as laser welding to fix the main terminal 62 onto the upper surface of the metal block 60, the thermal effect on the ceramic substrate 10, which is an insulating substrate, can be suppressed by the metal block 60, which has a relatively large thermal capacity.

 パワーモジュール1Bは、基本態様と同様、ケース5及びフィンベース15を有するため、ケース5及びフィンベース15に関し、基本態様であるパワーモジュール1と同様な効果を奏する。 The power module 1B has the case 5 and fin base 15, just like the basic version, and therefore has the same effects as the power module 1, which is the basic version, with respect to the case 5 and fin base 15.

 (第2の態様の製造方法)
 上述したパワーモジュール1Bの製造方法は、外部信号伝達用の主端子62を有する半導体装置の製造方法として、以下のステップ(a)~(e)を備えている。
(Production method of the second embodiment)
The manufacturing method of the power module 1B described above is a manufacturing method of a semiconductor device having a main terminal 62 for transmitting an external signal, and includes the following steps (a) to (e).

 ステップ(a)~(d)は、基本態様であるパワーモジュール1の製造方法のステップ(a)~(d)と同様に行われる。 Steps (a) to (d) are performed in the same manner as steps (a) to (d) of the manufacturing method for the power module 1, which is the basic embodiment.

 ステップ(e)は、ステップ(d)後に実行され、金属ブロック60の上面上に主端子62をレーザ溶接等の主端子接合処理により取り付けるステップである。 Step (e) is performed after step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60 by a main terminal joining process such as laser welding.

 以下、主端子接合処理について詳述する。主端子接合処理の代表的処理としてレーザ溶接処理がある。上述したレーザ溶接処理ではレーザ65としてYAGレーザを用いたが、YAGレーザ以外にも炭酸ガスレーザやグリーンレーザなどでも代替できる。さらに、レーザ溶接に替えて、抵抗溶接やMIG(Metal Inert Gas)溶接さらに超音波接合等を主端子接合処理として採用しても良い。このように様々な処理を含む主端子接合処理によって主端子62と金属ブロック60との接合を行うことができる。 The main terminal joining process will be described in detail below. A representative process for the main terminal joining process is laser welding. In the laser welding process described above, a YAG laser is used as the laser 65, but a carbon dioxide laser or a green laser can also be used instead of a YAG laser. Furthermore, instead of laser welding, resistance welding, MIG (Metal Inert Gas) welding, ultrasonic joining, etc. may also be used as the main terminal joining process. In this way, the main terminal 62 and the metal block 60 can be joined by the main terminal joining process, which includes a variety of processes.

 レーザ溶接等の上述した主端子接合処理を実行すると、飛散するスパッタによる装置としての絶縁性の低下が懸念される。しかし、パワーモジュール1Bは、封止樹脂7によって半導体素子20やセラミック基板10を覆っているため、スパッタが飛散しても、半導体素子20及びセラミック基板10を含む装置の絶縁性に影響しない。 When performing the above-mentioned main terminal joining process such as laser welding, there is a concern that the insulation of the device may be reduced due to scattering spatter. However, since the power module 1B covers the semiconductor element 20 and ceramic substrate 10 with sealing resin 7, even if spatter scatters, the insulation of the device including the semiconductor element 20 and ceramic substrate 10 is not affected.

 また、金属ブロック60は、セラミック基板10の上面導体層12と比較して十分厚く、比較的大きな熱容量を有するため、主端子接合処理で生じる過大な熱エネルギーを吸収し、上面導体層12やセラミック基材11に生じる熱損傷を抑制することができる。 In addition, the metal block 60 is sufficiently thick compared to the upper conductor layer 12 of the ceramic substrate 10 and has a relatively large heat capacity, so it can absorb the excessive heat energy generated during the main terminal bonding process and suppress thermal damage to the upper conductor layer 12 and the ceramic base material 11.

 また、主端子接合処理としてはんだを用いた接合を採用しても良い。以下、この主端子接合処理に用いるはんだを「主端子用はんだ」と称する。金属ブロック60の上面上に主端子用はんだを介して主端子62の溶接固定部62wを固定することができる。 Furthermore, the main terminal joining process may be performed using solder. Hereinafter, the solder used in this main terminal joining process will be referred to as "main terminal solder." The welded fixing portion 62w of the main terminal 62 can be fixed to the upper surface of the metal block 60 via the main terminal solder.

 この場合、セラミック基板10の上面導体層12と金属ブロック60との接合用のはんだ31よりも融点の低い性質の主端子用はんだを用いることにより、主端子用はんだを用いた主端子接合処理の実行時にはんだ30及び31を含む内部はんだの再溶融を抑制することができる。 In this case, by using a main terminal solder that has a lower melting point than the solder 31 used to join the upper conductor layer 12 of the ceramic substrate 10 to the metal block 60, remelting of the internal solder, including the solders 30 and 31, can be suppressed when performing the main terminal joining process using the main terminal solder.

 主端子62の溶接固定部62wを金属ブロック60の上面上に位置決めに際しねじ61を用いても良い。すなわち、ねじ61によって主端子62を金属ブロック60の上面上に仮固定した位置決め状態で主端子接合処理を行った後、ねじ61を金属ブロック60から取り外してパワーモジュール1Bを完成させても良い。すなわち、パワーモジュール1Bの製造時において、中間段階で使用される位置決め仮固定用にねじ61を用いても良い。 The screw 61 may be used to position the welded fixing portion 62w of the main terminal 62 on the upper surface of the metal block 60. That is, after the main terminal joining process is performed in a state in which the main terminal 62 is temporarily fixed on the upper surface of the metal block 60 by the screw 61, the screw 61 may be removed from the metal block 60 to complete the power module 1B. That is, the screw 61 may be used for temporary positioning and fixing used in an intermediate stage during the manufacture of the power module 1B.

 この場合、ねじ61の締め付けトルクについては、締め付け後の主端子62のせん断強度を、金属ブロック60のセラミック基板10に対するはんだ31のせん断強度よりも小さくなるように設定することが望ましい。なぜなら、上記設定により、部材間の膨張係数差による熱応力によりはんだ付け部となるはんだ31の破損を抑制することができるからである。 In this case, it is desirable to set the tightening torque of the screw 61 so that the shear strength of the main terminal 62 after tightening is smaller than the shear strength of the solder 31 to the ceramic substrate 10 of the metal block 60. This is because the above setting makes it possible to suppress damage to the solder 31, which is the soldered portion, due to thermal stress caused by the difference in the expansion coefficient between the components.

 ねじ61を用いる場合、溶接固定部62wに開口部62oを設ける必要がある。この際、主端子62のねじ締め開口部である開口部62oの径を、ねじ61のねじ径に対して1.5倍以上とすることにより、温度サイクル性をより確保することができる。 When using the screw 61, it is necessary to provide an opening 62o in the welded fixing portion 62w. In this case, by making the diameter of the opening 62o, which is the screw fastening opening of the main terminal 62, 1.5 times or more the thread diameter of the screw 61, it is possible to ensure better temperature cycle resistance.

 第2の態様の製造方法で製造される半導体装置であるパワーモジュール1Bは、セラミック基板10及びはんだ31を覆って設けられる封止樹脂7によって、ステップ(e)のレーザ溶接等の主端子接合処理の実行時における金属ブロック60へのダメージを軽減することができる。 The power module 1B, which is a semiconductor device manufactured by the manufacturing method of the second aspect, can reduce damage to the metal block 60 during the main terminal joining process such as laser welding in step (e) by using the sealing resin 7 that covers the ceramic substrate 10 and the solder 31.

 第2の態様の製造方法のステップ(e)の実行時に、金属ブロック60の上面は封止樹脂によって覆われておらず露出状態である。このため、金属ブロック60の上面上に固定されている主端子62を取り外し、主端子接合処理によって新たな主端子に取り替えるリワークを、ステップ(e)として比較的簡単に行うことができる。 When performing step (e) of the manufacturing method of the second embodiment, the upper surface of the metal block 60 is not covered with the sealing resin and is exposed. Therefore, rework can be performed relatively easily as step (e) by removing the main terminal 62 fixed on the upper surface of the metal block 60 and replacing it with a new main terminal by a main terminal joining process.

 (第3の態様)
 図10は実施の形態1の第3の態様の半導体装置となるパワーモジュール1Cの断面構造を模式的に示す説明図である。図10は基本態様で示した図1のA-A断面構造に相当する。図10にXYZ直交座標系を記している。
(Third Aspect)
Fig. 10 is an explanatory diagram showing a schematic cross-sectional structure of a power module 1C which is a semiconductor device according to a third aspect of the first embodiment. Fig. 10 corresponds to the cross-sectional structure taken along line A-A in Fig. 1 which shows the basic aspect. An XYZ orthogonal coordinate system is shown in Fig. 10.

 実施の形態1の第3の態様であるパワーモジュール1Cに関し、基本態様のパワーモジュール1と同様な構成要素は同一符号を付して説明を適宜省略する。以下、図1~図3で示した基本態様のパワーモジュール1と異なるパワーモジュール1Cの特徴箇所を中心に説明する。 With regard to the power module 1C, which is the third aspect of the first embodiment, components similar to those of the power module 1 of the basic aspect are given the same reference numerals and explanations are omitted as appropriate. The following will focus on the characteristics of the power module 1C that are different from the power module 1 of the basic aspect shown in Figures 1 to 3.

 図10に示すように、パワーモジュール1Cは、ケース5に替えて主端子付ケース5Tを設けている。主端子付ケース5TのXY平面での平面形状はケース5と同様、例えば92mm×80mmに設定され、主端子付ケース5TのZ方向に沿った高さは10mmより少し高い方が望ましい。主端子付ケース5Tの構成材料として、ケース5と同様、PPS樹脂が考えられる。 As shown in FIG. 10, the power module 1C is provided with a case 5T with main terminals instead of the case 5. The planar shape of the case 5T with main terminals in the XY plane is set to, for example, 92 mm x 80 mm, similar to the case 5, and it is desirable that the height of the case 5T with main terminals in the Z direction is slightly higher than 10 mm. As with the case 5, the material of the case 5T with main terminals may be PPS resin.

 したがって、パワーモジュール1Cにおいて、フィンベース15の載置面15sの平面形状(100mm×100mm)は、主端子付ケース5Tの平面形状(92mm×80mm)より広い寸法特性を有している。 Therefore, in the power module 1C, the planar shape (100 mm x 100 mm) of the mounting surface 15s of the fin base 15 has dimensional characteristics that are wider than the planar shape (92 mm x 80 mm) of the main terminal case 5T.

 主端子付ケース5Tは、主端子62がケース収容空間S5から外部に突き抜ける態様で主端子62と連結されている。すなわち、主端子62は主端子付ケース5Tにインサート成型されている。 The main terminal 62 is connected to the case 5T with the main terminal in such a manner that the main terminal 62 protrudes from the case housing space S5 to the outside. In other words, the main terminal 62 is insert molded into the case 5T with the main terminal.

 したがって、主端子62は、ねじ取付部62aに加え、主端子付ケース5TからX方向に沿って突き抜けている外部露出部62bと、主端子付ケース5T内に存在するケース内挿入部62cとを有している。 Therefore, in addition to the screw attachment portion 62a, the main terminal 62 has an externally exposed portion 62b that protrudes from the main terminal case 5T in the X direction, and an internal case insertion portion 62c that exists within the main terminal case 5T.

 パワーモジュール1Bは、ケース収容空間S5内において封止樹脂7上に封止樹脂72をさらに設けている。封止樹脂7から露出していた金属ブロック60の上部、主端子62のねじ取付部62a及びねじ61はすべて封止樹脂72によって覆われている。 In the power module 1B, sealing resin 72 is further provided on the sealing resin 7 within the case housing space S5. The upper part of the metal block 60 exposed from the sealing resin 7, the screw mounting parts 62a of the main terminals 62, and the screws 61 are all covered with sealing resin 72.

 (第3の態様の製造方法)
 上述したパワーモジュール1Cの製造方法は、外部信号伝達用の主端子62を有する半導体装置の製造方法として、以下のステップ(a)~(e)及びステップ(x)を備えている。
(Production method of the third embodiment)
The manufacturing method of the power module 1C described above is a manufacturing method of a semiconductor device having a main terminal 62 for transmitting an external signal, and includes the following steps (a) to (e) and step (x).

 ステップ(a),(b)は、パワーモジュール1の製造方法のステップ(a),(b)と同様に行われる。 Steps (a) and (b) are performed in the same manner as steps (a) and (b) of the method for manufacturing the power module 1.

 ステップ(c)は、ブロック搭載部材となるセラミック基板10と金属ブロック60とをブロック用接合材であるはんだ31を介して接合するステップである。ステップ(c)の実行に先がけ、フィンベース15の載置面15s上に主端子付ケース5Tが固定される。 Step (c) is a step in which the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 are joined via solder 31, which is a joining material for the block. Prior to the execution of step (c), the main terminal case 5T is fixed onto the mounting surface 15s of the fin base 15.

 主端子付ケース5Tの固定時に、主端子62のねじ取付部62aが金属ブロック60の上面に接するように位置決めされる。すなわち、主端子付ケース5Tをフィンベース15の載置面15s上に搭載した時点で、金属ブロック60と主端子62との位置決めができるように設定されている。 When the case 5T with main terminals is fixed, the screw attachment portion 62a of the main terminals 62 is positioned so that it contacts the upper surface of the metal block 60. In other words, the metal block 60 and the main terminals 62 are set so that they can be positioned when the case 5T with main terminals is mounted on the mounting surface 15s of the fin base 15.

 ステップ(d)は、パワーモジュール1の製造方法のステップ(d)と同様に行われる。 Step (d) is performed in the same manner as step (d) in the method for manufacturing the power module 1.

 ステップ(e)は、ステップ(d)後に実行され、金属ブロック60の上面上に主端子62を取り付けるステップである。 Step (e) is performed after step (d) and is a step of attaching the main terminal 62 to the upper surface of the metal block 60.

 ステップ(e)の実行時に主端子62を金属ブロック60の上面上にねじ61によるねじ締めを行う際、ねじ締め時の応力が、主端子付ケース5Tにも分散されることにより金属ブロック60にかかる応力を低減することができる。また、ねじ締め時に発生するジュール熱(抵抗熱)が主端子付ケース5Tを経由してフィンベース15に拡散させることもできる。 When the main terminal 62 is fastened to the top surface of the metal block 60 by the screw 61 during step (e), the stress generated during fastening is also distributed to the main terminal case 5T, thereby reducing the stress on the metal block 60. In addition, Joule heat (resistance heat) generated during fastening can be diffused to the fin base 15 via the main terminal case 5T.

 さらに、ねじ61を用いて固定した上で、レーザ照射によるレーザ溶接処理を併用することも可能である。レーザ溶接処理の実行時に、ねじ取付部62aと金属ブロック60の上面との接合部のギャップが接合品質に影響を与える場合があるが、ねじ61によるねじ締め固定を併用することにより、上述したギャップを最小化することができる。また、レーザ溶接処理後にねじ61を除去することにより、ねじ61が突起部として存在することによるノイズの発生を抑えることができる。 Furthermore, it is possible to use the screw 61 for fastening and then use a laser welding process by irradiating a laser. When performing the laser welding process, a gap at the joint between the screw attachment portion 62a and the upper surface of the metal block 60 may affect the joining quality, but by also using the screw 61 for fastening, the above-mentioned gap can be minimized. Furthermore, by removing the screw 61 after the laser welding process, it is possible to suppress the generation of noise caused by the screw 61 being present as a protrusion.

 ステップ(x)は、ケース収容空間S5内において封止樹脂7上にさらに封止樹脂72を形成し、金属ブロック60、主端子62及びねじ取付部62aを全て封止樹脂72よって覆うステップである。 Step (x) is a step in which sealing resin 72 is further formed on the sealing resin 7 within the case housing space S5, and the metal block 60, the main terminals 62, and the screw mounting portions 62a are all covered with the sealing resin 72.

 このステップ(x)は、パワーモジュール1及びパワーモジュール1Bで行わないパワーモジュール1Cに固有の工程である。 This step (x) is a process specific to power module 1C that is not performed in power module 1 or power module 1B.

 ステップ(x)は、主端子付ケース5Tのケース収容空間S5内に封止樹脂72を注入し、金属ブロック60の露出部分及びねじ61等を絶縁封止し、絶縁性を高めたり、ねじ61の頭部61aの形状等に起因するノイズを低減したりすることもできる。 In step (x), sealing resin 72 is injected into the case housing space S5 of the main terminal case 5T to insulate and seal the exposed parts of the metal block 60 and the screws 61, etc., thereby improving insulation and reducing noise caused by the shape of the heads 61a of the screws 61, etc.

 第2の封止樹脂となる封止樹脂72は、封止樹脂7と同じ材料でも良いが、フィラー含有率を封止樹脂7より減らして流動性を高めたり、安価なシリコーンゲルに置き替えたりすることもできる。 The second sealing resin, sealing resin 72, may be made of the same material as sealing resin 7, but it may also have a lower filler content than sealing resin 7 to increase fluidity, or it may be replaced with an inexpensive silicone gel.

 第3の態様であるパワーモジュール1Cは、完成段階において、金属ブロック60の上面が露出状態であることに起因する効果を除き、基本態様のパワーモジュール1と同様な効果を奏し、さらに、以下の効果を奏する。 The third embodiment of the power module 1C has the same effects as the basic embodiment of the power module 1, except for the effects resulting from the upper surface of the metal block 60 being exposed at the completed stage, and further has the following effects:

 パワーモジュール1Cはケース収容空間S5内に設けられる封止樹脂として、封止樹脂7に加え封止樹脂72を有するため、ケース収容空間S5内に存在する、セラミック基板10、複数の半導体素子20、金属ブロック60及び主端子62のねじ取付部62aの全てが封止樹脂7及び封止樹脂72によって覆われる構造となる。 The power module 1C has sealing resin 72 in addition to sealing resin 7 as the sealing resin provided in the case housing space S5, so that the ceramic substrate 10, the multiple semiconductor elements 20, the metal block 60, and the screw mounting portion 62a of the main terminal 62 that are present in the case housing space S5 are all covered with sealing resin 7 and sealing resin 72.

 このため、パワーモジュール1Cは、装置における絶縁性を向上させ、かつ、金属ブロック60の上面と主端子62のねじ取付部62aとの固定時に残存した頭部61a等の突起部に起因するノイズを低減することができる。 As a result, the power module 1C improves the insulation of the device and reduces noise caused by protrusions such as the head 61a that remain when the top surface of the metal block 60 is fixed to the screw mounting portion 62a of the main terminal 62.

 なお、実施の形態1のパワーモジュール1では、金属ブロック60における拘束用の一対の露出側面として、Y方向に平行な面でかつX方向で対向する一対の露出側面60s及び60sを示したが、X方向に平行な面でかつY方向で対向する一対の露出側面を拘束用の一対の露出側面としても良い。 In the power module 1 of embodiment 1, a pair of exposed side surfaces 60s and 60s that are parallel to the Y direction and face each other in the X direction are shown as a pair of exposed side surfaces for restraint in the metal block 60. However, a pair of exposed side surfaces that are parallel to the X direction and face each other in the Y direction may also be used as a pair of exposed side surfaces for restraint.

 また、実施の形態1では、四角柱形状の金属ブロック60を示したが、一対の露出側面60s及び60sが設けることができる六角柱以上の多角柱状に金属ブロック60を設けても良い。 In addition, in the first embodiment, the metal block 60 is shown in the shape of a rectangular prism, but the metal block 60 may be in the shape of a polygonal prism of hexagonal or greater prism that can be provided with a pair of exposed side surfaces 60s and 60s.

 <実施の形態2>
 (基本態様)
 以下、本開示の実施の形態2の基本態様の半導体装置となるパワーモジュール2について説明する。
<Embodiment 2>
(Basic form)
Hereinafter, a power module 2 that is a semiconductor device according to a basic aspect of the second embodiment of the present disclosure will be described.

 図11はパワーモジュール2の平面構造を模式的に示す説明図である。図12は図11のB-B断面構造を模式的に示す説明図である。図11及び図12それぞれにXYZ直交座標系を記している。 FIG. 11 is an explanatory diagram that shows a schematic planar structure of the power module 2. FIG. 12 is an explanatory diagram that shows a schematic cross-sectional structure taken along line B-B of FIG. 11. An XYZ orthogonal coordinate system is shown in each of FIG. 11 and FIG. 12.

 実施の形態2の基本態様であるパワーモジュール2Bに関し、実施の形態1の基本態様のパワーモジュール1と同様な構成要素は同一符号を付して説明を適宜省略する。以下、図1~図3で示したパワーモジュール1と異なるパワーモジュール2の特徴箇所を中心に説明する。 With regard to power module 2B, which is the basic aspect of embodiment 2, components similar to those of power module 1, which is the basic aspect of embodiment 1, are given the same reference numerals and explanations are omitted as appropriate. The following will focus on the characteristics of power module 2 that are different from power module 1 shown in Figures 1 to 3.

 図11及び図12に示すように、放熱用フィンであるフィンベース15Bがパワーモジュール2の最下層に設けられている。フィンベース15Bはベース部15m及び複数のピン15pを有している。ベース部15mの平面形状は例えば90mm×100mmの構成であり、ベース部15mの厚さは例えば3mmに設定される。ベース部15mの構成材料として、例えば、銅、ニッケルめっき等が考えられる。 As shown in Figures 11 and 12, a fin base 15B, which is a heat dissipation fin, is provided on the bottom layer of the power module 2. The fin base 15B has a base portion 15m and a number of pins 15p. The planar shape of the base portion 15m is, for example, 90 mm x 100 mm, and the thickness of the base portion 15m is set to, for example, 3 mm. Possible materials for the base portion 15m include, for example, copper and nickel plating.

 フィンベース15Bの載置面15s上に周状にセラミック基板10B、複数の半導体素子20及び複数の金属ブロック66を囲んでダム部8が設けられる。収容空間形成部材であるダム部8のZ方向に沿った形成高さは例えば6mm程度に設定される。なお、図11に示すように、パワーモジュール2では複数の半導体素子20として4つの半導体素子20が図示されている。 A dam section 8 is provided on the mounting surface 15s of the fin base 15B, surrounding the ceramic substrate 10B, the semiconductor elements 20, and the metal blocks 66. The height of the dam section 8, which is a member forming the storage space, in the Z direction is set to, for example, about 6 mm. As shown in FIG. 11, four semiconductor elements 20 are shown as the multiple semiconductor elements 20 in the power module 2.

 ダム部8は複数のダム材81を積層して構成される。複数のダム材81による積層構造を得る処理として、例えばディスペンサーを用いた描画処理が考えられる。ダム材81の構成材料として例えばシリカフィラーをエポキシ樹脂に分散して得られる材料が考えられる。 The dam section 8 is constructed by stacking multiple dam materials 81. A process for obtaining a layered structure using multiple dam materials 81 can be, for example, a drawing process using a dispenser. A material obtained by dispersing silica filler in epoxy resin can be used as a constituent material for the dam material 81.

 絶縁基板であるセラミック基板10Bは、絶縁基材となる窒化ケイ素基材11Bと、窒化ケイ素基材11Bの上面上に設けられる上面導体層12と、セラミック基板10Bの下面上に設けられる下面導体層13とを有している。上面導体層12の表面が基板の第1の主面となり、下面導体層13の表面が基板の第2の主面となる。 The ceramic substrate 10B, which is an insulating substrate, has a silicon nitride substrate 11B that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11B, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10B. The surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.

 窒化ケイ素基材11Bの平面形状は例えば65mm×58mm構成であり、窒化ケイ素基材11BのZ方向に沿った厚さは例えば0.32mmに設定されている。 The planar shape of the silicon nitride substrate 11B is, for example, 65 mm x 58 mm, and the thickness of the silicon nitride substrate 11B in the Z direction is set to, for example, 0.32 mm.

 基板用接合材となるはんだ30は、例えば、スズ96.5%、銀3%、銅0.5%で構成され、はんだ30の融点は例えば217℃に設定されている。 The solder 30, which serves as the bonding material for the board, is composed of, for example, 96.5% tin, 3% silver, and 0.5% copper, and the melting point of the solder 30 is set to, for example, 217°C.

 上面導体層12及び下面導体層13それぞれの厚みは例えば0.8mmに設定され、構成材料として例えば銅が用いられる。 The thickness of each of the upper conductor layer 12 and the lower conductor layer 13 is set to, for example, 0.8 mm, and the constituent material is, for example, copper.

 セラミック基板10Bの上面導体層12の表面上にはんだ31を介して複数の半導体素子20が搭載されている。すなわち、はんだ31を介して基板の第1の主面と複数の半導体素子20とが接合されている。 A number of semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10B via solder 31. In other words, the first main surface of the substrate and the number of semiconductor elements 20 are joined via the solder 31.

 複数の半導体素子20としてダイオードやIGBTが考えられる。ダイオードは例えばシリコンを構成材料として、平面構成は例えば10mm×8mm構成であり、厚みは例えば0.2mmに設定される。IGBTは、例えばシリコンを構成材料として、平面構成は例えば10mm×10mm構成であり、厚さは例えば0.2mmに設定される。 The multiple semiconductor elements 20 may be diodes or IGBTs. The diodes may be made of silicon, have a planar configuration of, for example, 10 mm x 8 mm, and have a thickness of, for example, 0.2 mm. The IGBTs may be made of silicon, have a planar configuration of, for example, 10 mm x 10 mm, and have a thickness of, for example, 0.2 mm.

 セラミック基板10Bの上面導体層12の一部上に端子台51が設けられる。信号端子63は一部が端子台51内に挿入される態様で端子台51に固定されている。信号端子63は例えば銅を構成材料としており、Y方向に沿った幅は例えば1.5mmに設定され、厚さは例えば0.6mmに設定される。 A terminal block 51 is provided on a portion of the upper conductor layer 12 of the ceramic substrate 10B. A signal terminal 63 is fixed to the terminal block 51 in such a manner that a portion of the signal terminal 63 is inserted into the terminal block 51. The signal terminal 63 is made of copper, for example, and has a width in the Y direction of, for example, 1.5 mm and a thickness of, for example, 0.6 mm.

 端子台51は端子水平部51a及び端子立設部51bを有しており、信号端子63は端子水平部分63aと端子立設部分63bとからなる屈曲形状を呈しており、端子水平部分63aが端子水平部51a内に挿入され、端子立設部分63bの一部が端子立設部51b内に挿入されている。このように、信号端子63は端子台51内にインサート成形されている。 The terminal block 51 has a terminal horizontal portion 51a and a terminal standing portion 51b, and the signal terminal 63 has a bent shape consisting of the terminal horizontal portion 63a and the terminal standing portion 63b, with the terminal horizontal portion 63a being inserted into the terminal horizontal portion 51a and a part of the terminal standing portion 63b being inserted into the terminal standing portion 51b. In this way, the signal terminal 63 is insert molded into the terminal block 51.

 信号端子63の端子水平部分63aの上面の一部が端子水平部51aから露出しており、露出状態の端子水平部分63aの上面と半導体素子20の上面とがワイヤ41によって電気的に接続されている。ワイヤ41として例えば直径0.15mmでアルミ製のワイヤが用いられる。信号端子63及びワイヤ41を含んで信号回路が構成される。 A portion of the upper surface of the terminal horizontal portion 63a of the signal terminal 63 is exposed from the terminal horizontal section 51a, and the upper surface of the exposed terminal horizontal portion 63a is electrically connected to the upper surface of the semiconductor element 20 by a wire 41. For example, an aluminum wire having a diameter of 0.15 mm is used as the wire 41. The signal terminal 63 and the wire 41 form a signal circuit.

 実施の形態1のパワーモジュール1,1B,1Cと同様、パワーモジュール2において、セラミック基板10Bの上面導体層12の表面上にはんだ31によって金属ブロック60が固定されている。金属ブロック60の接合用に用いられるはんだ31はブロック用接合材となる。 Similar to the power modules 1, 1B, and 1C of the first embodiment, in the power module 2, the metal block 60 is fixed to the surface of the upper conductor layer 12 of the ceramic substrate 10B by solder 31. The solder 31 used to join the metal block 60 serves as a joining material for the block.

 さらに、図12に示すように、複数の半導体素子20それぞれ上にブロック用接合材であるはんだ32によって金属ブロック66が固定されている。 Furthermore, as shown in FIG. 12, a metal block 66 is fixed onto each of the semiconductor elements 20 by solder 32, which is a bonding material for the block.

 実施の形態2では、説明の都合上、セラミック基板10Bの上面導体層12の表面上に設けられる金属ブロック60と、半導体素子20上に設けられる金属ブロック66とに分類している。ただし、金属ブロック60及び66間での構成材料及び形状等は共通している。 In the second embodiment, for convenience of explanation, the metal block is divided into a metal block 60 provided on the surface of the upper conductor layer 12 of the ceramic substrate 10B and a metal block 66 provided on the semiconductor element 20. However, the constituent materials and shapes of the metal blocks 60 and 66 are the same.

 なお、図11に示すように、パワーモジュール2は、4つの半導体素子20と2つの金属ブロック60と4つの金属ブロック66とを含んでいる。 As shown in FIG. 11, the power module 2 includes four semiconductor elements 20, two metal blocks 60, and four metal blocks 66.

 金属ブロック60及び66は例えば真鍮製であり、金属ブロック60及び66それぞれの平面構成が7mm×6mmの四角形状であり、それぞれのZ方向に沿った高さが5mmに設定されている。すなわち、金属ブロック60及び66はそれぞれ四角柱形状を呈している。金属ブロック60は上面の中央から下面にかけて設けられるねじ穴領域60xを有している。同様に、金属ブロック66は上面から下面にかけて設けられるねじ穴領域66xを有している。 The metal blocks 60 and 66 are made of brass, for example, and each has a rectangular shape measuring 7 mm x 6 mm in plan view, with each having a height of 5 mm along the Z direction. In other words, the metal blocks 60 and 66 each have a rectangular prism shape. The metal block 60 has a screw hole region 60x that runs from the center of the top surface to the bottom surface. Similarly, the metal block 66 has a screw hole region 66x that runs from the top surface to the bottom surface.

 このように高さ方向に沿って金属ブロック60及び66を貫通するねじ穴領域60x及び66xはそれぞれ主端子取付領域として機能する。 In this way, the screw hole regions 60x and 66x that penetrate the metal blocks 60 and 66 along the height direction function as main terminal mounting regions, respectively.

 したがって、金属ブロック60及び66それぞれのZ方向に沿った高さ方向における厚み(5mm)は、上面導体層12の膜厚(0.8mm)と比較して、十分厚くなるように設定されている。 Therefore, the thickness (5 mm) of each of the metal blocks 60 and 66 in the height direction along the Z direction is set to be sufficiently thick compared to the film thickness (0.8 mm) of the upper conductor layer 12.

 パワーモジュール2において、セラミック基板10B及び半導体素子20がブロック搭載部材として機能している。すなわち、ブロック搭載部材となるセラミック基板10Bと金属ブロック60とのブロック用接合材としてはんだ31が用いられ、ブロック搭載部材となる半導体素子20と金属ブロック66とのブロック用接合材としてはんだ32が用いられる。 In the power module 2, the ceramic substrate 10B and the semiconductor element 20 function as block mounting members. That is, solder 31 is used as a block bonding material between the ceramic substrate 10B, which serves as the block mounting member, and the metal block 60, and solder 32 is used as a block bonding material between the semiconductor element 20, which serves as the block mounting member, and the metal block 66.

 図12に示すように、2つの金属ブロック66の上面に対し1つの主端子67が2つのねじ61によって固定されている。主端子67はねじ取付部67aに2つの開口部67oを有している。主端子67は例えば銅製であり、Y方向に沿った幅が8mmに設定され、厚さが1mmに設定される。 As shown in FIG. 12, one main terminal 67 is fixed to the top surfaces of two metal blocks 66 by two screws 61. The main terminal 67 has two openings 67o in the screw attachment portion 67a. The main terminal 67 is made of copper, for example, and has a width of 8 mm in the Y direction and a thickness of 1 mm.

 主端子67においてねじ取付部67aと反対側の端部はケース収容空間S5から、外部にはみ出して設けられる。なお、主端子67としてバスバーや外部配線ケーブル用の端子等が考えられる。 The end of the main terminal 67 opposite the screw attachment portion 67a is provided so as to protrude from the case housing space S5 to the outside. Note that the main terminal 67 may be a bus bar or a terminal for an external wiring cable.

 主端子67の2つの開口部67o及び2つの金属ブロック66のねじ穴領域66xに2つのねじ61のねじ部61bを挿入する取付態様で2つの金属ブロック66の上面上に1つの主端子67が固定されている。 One main terminal 67 is fixed onto the top surface of two metal blocks 66 in an installation manner in which the threaded portions 61b of two screws 61 are inserted into the two openings 67o of the main terminal 67 and the screw hole areas 66x of the two metal blocks 66.

 このように、金属ブロック66は主端子取付領域として上面及びねじ穴領域66xを有し、ねじ61によって、主端子67は主端子取付領域にて金属ブロック66に固定されている。 In this way, the metal block 66 has an upper surface and a screw hole area 66x as a main terminal mounting area, and the main terminal 67 is fixed to the metal block 66 in the main terminal mounting area by the screw 61.

 パワーモジュール2の主回路は金属ブロック60及び66、ねじ61並びに主端子67を構成要素として含んでいる。 The main circuit of the power module 2 includes metal blocks 60 and 66, a screw 61, and a main terminal 67 as components.

 ダム部8によって囲まれるダム部収容領域S8内において、フィンベース15の載置面15s上に設けられるはんだ30、セラミック基板10B、はんだ31、複数の半導体素子20、はんだ32、及びワイヤ41~43を覆って封止樹脂7が設けられる。封止樹脂7の構成材料として、例えばエポキシ樹脂にシリカフィラーを分散させた材料が考えられる。 In the dam portion accommodation area S8 surrounded by the dam portion 8, sealing resin 7 is provided to cover the solder 30, ceramic substrate 10B, solder 31, multiple semiconductor elements 20, solder 32, and wires 41 to 43 provided on the mounting surface 15s of the fin base 15. The constituent material of the sealing resin 7 may be, for example, an epoxy resin with silica filler dispersed therein.

 金属ブロック66の上面及び側面の上方の一部は封止樹脂7よって覆われておらず露出状態となっている。例えば、ダム部収容領域S8内において封止樹脂7により深さ4mm程度で封止されており、金属ブロック66は上面から2mm程度、露出している。 The top surface and a portion of the upper side of the metal block 66 are not covered by the sealing resin 7 and are exposed. For example, the dam portion housing area S8 is sealed with the sealing resin 7 to a depth of about 4 mm, and the metal block 66 is exposed about 2 mm from the top surface.

 すなわち、金属ブロック66の側面の上方の一部は封止樹脂7によって覆われておらず露出状態であり、露出状態の金属ブロック66の側面は、Y方向に平行な面でかつX方向で対向する一対の露出側面66s及び66sを含んでいる。 In other words, an upper portion of the side of the metal block 66 is not covered by the sealing resin 7 and is exposed, and the exposed side of the metal block 66 includes a pair of exposed side surfaces 66s and 66s that are parallel to the Y direction and face each other in the X direction.

 一対の露出側面66s及び66sは封止樹脂7から2mm程度露出しているため、既存の拘束用治具を用いて一対の露出側面66s及び66sを挟んで把持する態様で金属ブロック66を拘束することができる。 Since the pair of exposed side surfaces 66s and 66s are exposed from the sealing resin 7 by about 2 mm, the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.

 なお、露出側面66sの露出幅及び露出長は、既存の拘束用治具を用いて金属ブロック66を拘束することができる範囲の長さに設定する必要がある。 The exposed width and exposed length of the exposed side surface 66s must be set to a length that allows the metal block 66 to be restrained using an existing restraining tool.

 パワーモジュール2は、セラミック基板10B、複数の半導体素子20、金属ブロック60及び66を内部に収容する素子収容空間として、ダム部8内にダム部収容領域S8を設けている。そして、封止樹脂7はダム部収容領域S8内に設けられる。 The power module 2 has a dam portion housing area S8 in the dam portion 8 as an element housing space that houses the ceramic substrate 10B, the multiple semiconductor elements 20, and the metal blocks 60 and 66. The sealing resin 7 is provided in the dam portion housing area S8.

 パワーモジュール2において、ブロック搭載部材としてセラミック基板10Bに加え、半導体素子20を用いている。パワーモジュール2に用いられるモジュール用金属ブロックは、セラミック基板10B上に設けられる金属ブロック60と、パワーモジュール2上に設けられる金属ブロック66とを含んでいる。 In the power module 2, in addition to the ceramic substrate 10B, a semiconductor element 20 is used as a block mounting member. The module metal block used in the power module 2 includes a metal block 60 provided on the ceramic substrate 10B and a metal block 66 provided on the power module 2.

 このように、パワーモジュール2は、モジュール用金属ブロックとして金属ブロック60以外に金属ブロック66を設けている。パワーモジュール2は、図11で示すように、4つの金属ブロック66と2つの金属ブロック60とを有している。 In this way, the power module 2 has metal blocks 66 in addition to the metal blocks 60 as metal blocks for the module. As shown in FIG. 11, the power module 2 has four metal blocks 66 and two metal blocks 60.

 したがって、パワーモジュール2は金属ブロック60の個数を減少させることができる。具体的にはパワーモジュール2は、実施の形態1のパワーモジュール1と比較して、金属ブロック60の数を「3つ」から「2つ」に低減し、かつモジュール用金属ブロックの総数を「3つ」から「6つ」に増加させている。 Therefore, the power module 2 can reduce the number of metal blocks 60. Specifically, compared to the power module 1 of the first embodiment, the power module 2 reduces the number of metal blocks 60 from "three" to "two," and increases the total number of metal blocks for the module from "three" to "six."

 このように、パワーモジュール2は、金属ブロック60の個数を減少させることにより、比較的高価なセラミック基板10Bの面積を縮小できる。 In this way, by reducing the number of metal blocks 60, the power module 2 can reduce the area of the relatively expensive ceramic substrate 10B.

 具体的には、実施の形態1のセラミック基板10とセラミック基板10Bとの間において、平面形状が70mm×58mm構成の窒化ケイ素基材11から、平面形状が65mm×58mm構成の窒化ケイ素基材11Bに縮小化を図ることができる。 Specifically, between the ceramic substrate 10 and the ceramic substrate 10B of the first embodiment, the silicon nitride substrate 11 having a planar shape of 70 mm x 58 mm can be reduced in size to the silicon nitride substrate 11B having a planar shape of 65 mm x 58 mm.

 セラミック基板10Bの縮小化により、フィンベース15Bとセラミック基板10Bとの間における膨張係数の大きな違いによって生じる熱応力を低減し、装置としての信頼性を向上させることもできる。 By reducing the size of the ceramic substrate 10B, it is possible to reduce the thermal stress caused by the large difference in the expansion coefficient between the fin base 15B and the ceramic substrate 10B, thereby improving the reliability of the device.

 実施の形態2の基本態様であるパワーモジュール2は、セラミック基板10B及び半導体素子20並びにはんだ31及びはんだ32を覆って封止樹脂7が設けられている。 The power module 2, which is the basic form of the second embodiment, is provided with a sealing resin 7 covering the ceramic substrate 10B, the semiconductor element 20, the solder 31, and the solder 32.

 したがって、実施の形態2の基本態様であるパワーモジュール2は、実施の形態1の基本態様であるパワーモジュール1と同様、製造段階でセラミック基板10Bに悪影響を与えない構造を呈するため、装置の歩留まり及び絶縁性を含む性能の向上を図ることができる。 Therefore, like power module 1, which is the basic aspect of embodiment 1, power module 2, which is the basic aspect of embodiment 2, has a structure that does not adversely affect ceramic substrate 10B during the manufacturing stage, and therefore it is possible to improve the device's performance, including its yield and insulation properties.

 さらに、パワーモジュール2における金属ブロック60及び66それぞれの上面は封止樹脂7によって覆われておらず露出状態である。このため、装置完成後においても金属ブロック66の上面上に固定される主端子67を新たな主端子に取り替えるねじ61を用いたリワークを比較的簡単に行うことができる。同様に、装置完成後においても金属ブロック60の上面上に固定される主端子62を新たな主端子に取り替えるねじ61を用いたリワークを比較的簡単に行うことができる。したがって、主端子62及び主端子67の選択に際しフレキシビリティを持たせることができる。 Furthermore, the upper surfaces of the metal blocks 60 and 66 in the power module 2 are not covered with the sealing resin 7 and are exposed. Therefore, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 67 fixed on the upper surface of the metal block 66 with a new main terminal. Similarly, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 62 fixed on the upper surface of the metal block 60 with a new main terminal. Therefore, flexibility can be provided when selecting the main terminals 62 and 67.

 加えて、パワーモジュール2は、完成段階において、ケース5に起因する効果を除き、基本態様のパワーモジュール1と同様な効果を奏し、さらに、以下の効果を奏する。 In addition, when the power module 2 is completed, it has the same effects as the basic power module 1, except for the effects attributable to the case 5, and further has the following effects:

 さらに、パワーモジュール2は、フィンベース15Bの載置面15s上に設けられたダム部8のダム部収容領域S8内に封止樹脂7を設けることにより、専用のケースを要することなく、製造時における封止樹脂7の高さ調整を比較的簡単に行うことができる。 Furthermore, by providing the sealing resin 7 in the dam portion accommodation area S8 of the dam portion 8 provided on the mounting surface 15s of the fin base 15B, the power module 2 makes it relatively easy to adjust the height of the sealing resin 7 during manufacturing without the need for a dedicated case.

 (基本態様の製造方法)
 図13~図17はパワーモジュール2の製造工程時における断面構造を模式的に示す説明図である。図13~図17それぞれにXYZ直交座標系を記している。以下、図13~図17を参照してパワーモジュール2の製造方法を説明する。
(Production method of the basic embodiment)
13 to 17 are explanatory diagrams that show a schematic cross-sectional structure during the manufacturing process of the power module 2. An XYZ orthogonal coordinate system is shown in each of Fig. 13 to 17. The manufacturing method of the power module 2 will be described below with reference to Fig. 13 to 17.

 なお、図11及び図12に示すように、パワーモジュール2は、4つの半導体素子20と4つの金属ブロック66と2つの金属ブロック60を含んでいるが、説明の都合上、図13~図17で図示された構造を基準として説明する。なお、図13~図17では図示しない金属ブロック60の形成工程は図4~図8で示した実施の形態1の製造方法と同様な工程となる。 As shown in Figures 11 and 12, the power module 2 includes four semiconductor elements 20, four metal blocks 66, and two metal blocks 60, but for convenience of explanation, the structure shown in Figures 13 to 17 will be used as the basis for explanation. The process for forming the metal blocks 60, which are not shown in Figures 13 to 17, is the same as the manufacturing method of the first embodiment shown in Figures 4 to 8.

 まず、実施の形態2の半導体装置用の基板となるセラミック基板10Bが準備される。パワーモジュール2ではセラミック基板10B及び半導体素子20がブロック搭載部材となっている。 First, a ceramic substrate 10B is prepared as the substrate for the semiconductor device of the second embodiment. In the power module 2, the ceramic substrate 10B and the semiconductor element 20 serve as block mounting members.

 次に、図13に示すように、セラミック基板10Bの上面導体層12の上方に、はんだ31と2つの半導体素子20とを位置決め配置し、さらに、2つの半導体素子20の上方に、はんだ32と2つの金属ブロック66とを位置決め配置し、リフロー炉を用いてはんだ31及び32によるはんだ接合を行う。 Next, as shown in FIG. 13, solder 31 and two semiconductor elements 20 are positioned above the upper conductor layer 12 of the ceramic substrate 10B, and solder 32 and two metal blocks 66 are positioned above the two semiconductor elements 20, and solder bonding is performed using the solders 31 and 32 in a reflow furnace.

 その結果、セラミック基板10Bの上面導体層12の表面上にはんだ31を介して2つの半導体素子20が搭載され、2つの半導体素子20の上面上にはんだ32を介して2つの金属ブロック66が搭載される。すなわち、金属ブロック66はブロック搭載部材となる半導体素子20の上面上にはんだ32を介して接合される。図13では図示していないが、実施の形態1と同様、ブロック搭載部材となるセラミック基板10Bの上面導体層12の表面上にはんだ31を介して金属ブロック60が接合される。 As a result, two semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10B via solder 31, and two metal blocks 66 are mounted on the upper surfaces of the two semiconductor elements 20 via solder 32. That is, the metal blocks 66 are joined via solder 32 to the upper surfaces of the semiconductor elements 20 that serve as block mounting members. Although not shown in FIG. 13, as in embodiment 1, a metal block 60 is joined via solder 31 to the surface of the upper conductor layer 12 of the ceramic substrate 10B that serves as the block mounting member.

 その後、図14に示すように、フィンベース15Bの載置面15s上にはんだ30を介してセラミック基板10Bの下面導体層13の表面を接合する。すなわち、セラミック基板10Bの下面導体層13の表面上に放熱用フィンであるフィンベース15Bが固定される。 Then, as shown in FIG. 14, the surface of the lower conductor layer 13 of the ceramic substrate 10B is joined to the mounting surface 15s of the fin base 15B via solder 30. In other words, the fin base 15B, which is a heat dissipation fin, is fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10B.

 次に、図15に示すように、フィンベース15Bの載置面15s上に複数のダム材81を積層してダム部8を形成する。ダム材81の積層処理として例えばディスペンサーを用いた塗布処理が実行される。完成後のダム部8はダム部収容領域S8を有しており、ダム部収容領域S8内にはんだ30及びセラミック基板10Bが存在するように、ダム部8はフィンベース15Bの載置面15s上に設けられる。 Next, as shown in FIG. 15, a plurality of dam materials 81 are stacked on the mounting surface 15s of the fin base 15B to form the dam portion 8. The stacking process of the dam materials 81 is performed, for example, by a coating process using a dispenser. The completed dam portion 8 has a dam portion accommodation area S8, and the dam portion 8 is provided on the mounting surface 15s of the fin base 15B so that the solder 30 and the ceramic substrate 10B are present within the dam portion accommodation area S8.

 同時に、セラミック基板10Bの上面導体層12の表面の一部上に端子台51が接着して固定される。信号端子63は端子台51に一体化されており、端子水平部分63aが端子水平部51a内に設けられ、端子立設部51b内に端子立設部分63bの一部が設けられている。端子台51のフィンベース15Bへの固定後において、端子水平部分63aの表面の一部が露出している。 At the same time, the terminal block 51 is adhered and fixed onto a portion of the surface of the upper conductor layer 12 of the ceramic substrate 10B. The signal terminal 63 is integrated with the terminal block 51, with the terminal horizontal portion 63a provided within the terminal horizontal portion 51a and a portion of the terminal standing portion 63b provided within the terminal standing portion 51b. After the terminal block 51 is fixed to the fin base 15B, a portion of the surface of the terminal horizontal portion 63a is exposed.

 ダム部8の形成及び端子台51のフィンベース15Bに固定後、ワイヤ41による配線が行われる。すなわち、ワイヤ41によって端子水平部分63aの表面と半導体素子20とが電気的に接続される。ワイヤ41の配線後、複数の半導体素子20、ワイヤ41、金属ブロック60及び66並びに信号端子63を含む回路が形成される。 After the dam portion 8 is formed and fixed to the fin base 15B of the terminal block 51, wiring is performed using the wires 41. That is, the surface of the terminal horizontal portion 63a and the semiconductor element 20 are electrically connected by the wires 41. After wiring the wires 41, a circuit is formed that includes multiple semiconductor elements 20, the wires 41, the metal blocks 60 and 66, and the signal terminals 63.

 次に、図16に示すように、2つの金属ブロック66それぞれの上面及び側面の上方の一部が露出する程度に、ダム部収容領域S8内に封止樹脂7を注入して加熱硬化させる。したがって。2つの金属ブロック66それぞれの上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となっている。 Next, as shown in FIG. 16, sealing resin 7 is injected into the dam portion housing area S8 and heated to harden so that a portion of the upper surface and upper side of each of the two metal blocks 66 is exposed. Therefore, a portion of the upper surface and upper side of each of the two metal blocks 66 is not covered by the sealing resin 7 and is exposed.

 すなわち、露出状態の金属ブロック66の側面は、X方向で対向する一対の露出側面66s及び66sを含んでいる。一対の露出側面66s及び66は共にYZ面に平行な面となる。また、ねじ穴領域66x内にも封止樹脂7は設けられない。 In other words, the side of the exposed metal block 66 includes a pair of exposed side surfaces 66s and 66s that face each other in the X direction. The pair of exposed side surfaces 66s and 66 are both parallel to the YZ plane. Furthermore, no sealing resin 7 is provided in the screw hole region 66x.

 一方、ダム部収容領域S8内において、はんだ30、セラミック基板10B、はんだ31、2つの半導体素子20、はんだ32及びワイヤ41は全て封止樹脂7によって覆われている。 On the other hand, within the dam portion accommodation area S8, the solder 30, the ceramic substrate 10B, the solder 31, the two semiconductor elements 20, the solder 32 and the wire 41 are all covered with the sealing resin 7.

 最後に、図17に示すように、2つの金属ブロック66それぞれのねじ穴領域66xと主端子67の2つの開口部62oとが平面視して合致するように位置決めし、2つのねじ61を用いて金属ブロック66と主端子67とを接続固定する。 Finally, as shown in FIG. 17, the screw hole regions 66x of the two metal blocks 66 are positioned so that they match the two openings 62o of the main terminal 67 in a plan view, and the metal blocks 66 and the main terminal 67 are connected and fixed using two screws 61.

 すなわち、主端子67の2つの開口部62o及び2つの金属ブロック66それぞれのねじ穴領域66xに2つのねじ61のねじ部61bを挿入する取付態様で金属ブロック66の上面上に主端子67が固定される。 In other words, the main terminal 67 is fixed onto the top surface of the metal block 66 in an installation manner in which the threaded portions 61b of the two screws 61 are inserted into the two openings 62o of the main terminal 67 and into the screw hole regions 66x of each of the two metal blocks 66.

 図17に示すように、封止樹脂7により2つの金属ブロック66は途中まで封止されているため、2つのねじ61によって主端子67を金属ブロック66の上面上に取り付ける際、2つのねじ61それぞれの締め付けるトルクによって金属ブロック66と半導体素子20との接合部となるはんだ32等へのダメージを低減することができる効果を奏する。この効果を最大化するために、金属ブロック66の高さの20%以上まで封止樹脂7が存在するように、封止樹脂7の形成深さを設定することが望ましい。 As shown in FIG. 17, the two metal blocks 66 are sealed partway with the sealing resin 7, so when the main terminal 67 is attached to the top surface of the metal block 66 with the two screws 61, the tightening torque of each of the two screws 61 reduces damage to the solder 32, which forms the joint between the metal block 66 and the semiconductor element 20. To maximize this effect, it is desirable to set the depth of the sealing resin 7 so that the sealing resin 7 is present up to 20% or more of the height of the metal block 66.

 加えて、一対の露出側面66s及び66sは封止樹脂7から2mm程度露出しているため、既存の拘束用治具を用いて一対の露出側面66s及び66sを挟む態様で金属ブロック66を拘束することができる。 In addition, since the pair of exposed side surfaces 66s and 66s are exposed from the sealing resin 7 by about 2 mm, the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.

 したがって、金属ブロック66を安定性良く固定した状態で、主端子67の開口部67o及び金属ブロック66のねじ穴領域66xにねじ61のねじ部61bを挿入した後、ねじ61を既定のトルクで締め付けることにより、金属ブロック66の上面上に主端子67を締結して固定することができる。 Therefore, with the metal block 66 stably fixed, the threaded portion 61b of the screw 61 is inserted into the opening 67o of the main terminal 67 and the threaded hole area 66x of the metal block 66, and then the screw 61 is tightened with a predetermined torque, thereby fastening and fixing the main terminal 67 to the upper surface of the metal block 66.

 このように、一対の露出側面66s及び66sにて金属ブロック66を安定性良く拘束した状態で主端子67を固定することができるため、主端子67の固定時における固定ブロック用接合材であるはんだ31へのダメージをさらに抑制し、半導体素子20へのダメージを抑制することができる。 In this way, the main terminal 67 can be fixed with the metal block 66 stably restrained by the pair of exposed side surfaces 66s and 66s, which further reduces damage to the solder 31, which is the bonding material for the fixed block, when the main terminal 67 is fixed, and also reduces damage to the semiconductor element 20.

 また、本明細書では、パワーモジュール2としてダム部8に封止樹脂7を注入したダム部型モジュールを示したが、封止樹脂を金型成型したトランスファモールド型モジュールで構成しても同様の効果が得られる。 In addition, in this specification, a dam-type module in which sealing resin 7 is injected into dam section 8 is shown as the power module 2, but the same effect can be obtained by configuring it as a transfer mold type module in which the sealing resin is molded using a die.

 上述したパワーモジュール2の製造方法は、外部信号伝達用の主端子67を有する半導体装置の製造方法として以下のステップ(a)~(e)を備えている。 The manufacturing method for the power module 2 described above includes the following steps (a) to (e) as a manufacturing method for a semiconductor device having a main terminal 67 for transmitting an external signal.

 ステップ(a)は、第1及び第2の主面を有する基板としてセラミック基板10Bを準備するステップである。 Step (a) is a step of preparing a ceramic substrate 10B as a substrate having a first and second main surfaces.

 ステップ(b)は、「基板の第1の主面」となる上面導体層12の表面上に複数の半導体素子20を搭載するステップである。ステップ(b)は図13を参照して説明した処理に対応している。実施の形態2の基本態様では、セラミック基板10及び半導体素子20がブロック搭載部材として機能している。 Step (b) is a step of mounting multiple semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate." Step (b) corresponds to the process described with reference to FIG. 13. In the basic aspect of the second embodiment, the ceramic substrate 10 and the semiconductor elements 20 function as block mounting members.

 ステップ(c)は、ブロック搭載部材となるセラミック基板10と金属ブロック60とをブロック用接合材であるはんだ31を介して接合し、かつ、ブロック搭載部材となる半導体素子20と金属ブロック66とをブロック用接合材となるはんだ32を介して接合するステップである。ステップ(c)は図13を参照して説明した処理に対応している。 Step (c) is a step of joining the ceramic substrate 10, which serves as the block mounting member, and the metal block 60 via solder 31, which serves as a bonding material for the block, and joining the semiconductor element 20, which serves as the block mounting member, and the metal block 66 via solder 32, which serves as a bonding material for the block. Step (c) corresponds to the process described with reference to FIG. 13.

 ステップ(d)は、ブロック搭載部材となるセラミック基板10及び半導体素子20並びにはんだ31及び32を覆って封止樹脂7を形成するステップである。ステップ(d)は図15及び図16を参照して説明した処理に対応する。 Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10 and semiconductor element 20, which are block mounting members, as well as solders 31 and 32. Step (d) corresponds to the process described with reference to Figures 15 and 16.

 ステップ(d)の実行後、金属ブロック60及び66それぞれの上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となる。したがって、封止樹脂7から2mm程度露出した一対の露出側面60s及び60s並びに一対の露出側面66s及び66sが存在する。 After step (d) is performed, the upper surfaces and upper portions of the sides of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, there are a pair of exposed side surfaces 60s and 60s and a pair of exposed side surfaces 66s and 66s that are exposed by about 2 mm from the sealing resin 7.

 ステップ(d)は以下のステップ(d-1)及び(d-2)を含んでいる。 Step (d) includes the following steps (d-1) and (d-2).

 ステップ(d-1)は、フィンベース15の載置面15s上において、セラミック基板10、半導体素子20、並びに金属ブロック60及び66の周囲に収容空間形成部材であるダム部8を形成するステップである。ステップ(d-1)は図15を参照して説明した処理に対応する。 Step (d-1) is a step of forming the dam portion 8, which is a member for forming the storage space, around the ceramic substrate 10, the semiconductor element 20, and the metal blocks 60 and 66 on the mounting surface 15s of the fin base 15. Step (d-1) corresponds to the process described with reference to FIG. 15.

 ステップ(d-2)は、ダム部8で囲われた素子収容空間であるダム部収容領域S8内において、セラミック基板10B、半導体素子20並びにはんだ31及び32を覆って封止樹脂7を形成するステップである。ステップ(d-2)は図16を参照して説明した処理に対応する。 Step (d-2) is a step of forming sealing resin 7 to cover ceramic substrate 10B, semiconductor element 20, and solders 31 and 32 within dam portion accommodation area S8, which is an element accommodation space surrounded by dam portion 8. Step (d-2) corresponds to the process described with reference to FIG. 16.

 ステップ(e)は、上述したステップ(d)後に実行され、金属ブロック60及び66それぞれの上面上に主端子62及び67を取り付けるステップである。ステップ(e)は図17を参照して説明した処理に対応する。 Step (e) is performed after step (d) described above, and is a step of attaching main terminals 62 and 67 to the upper surfaces of metal blocks 60 and 66, respectively. Step (e) corresponds to the process described with reference to FIG. 17.

 実施の形態2の半導体装置の製造方法で製造される半導体装置であるパワーモジュール2は、セラミック基板10B及び半導体素子20並びにはんだ31及び32を覆って設けられる封止樹脂7によって、ステップ(e)のねじ締め処理の実行時における金属ブロック60及び66へのダメージを軽減することができる。 The power module 2, which is a semiconductor device manufactured by the semiconductor device manufacturing method of the second embodiment, can reduce damage to the metal blocks 60 and 66 during the screw tightening process in step (e) by using the sealing resin 7 that covers the ceramic substrate 10B, the semiconductor element 20, and the solders 31 and 32.

 実施の形態2の半導体装置の製造方法のステップ(e)の実行時に、金属ブロック60及び66それぞれの上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態である。このため、金属ブロック60及び66の上面上に取り付けられる主端子62及び主端子67を新たな主端子に取り替えるリワークを、ステップ(e)として支障なく比較的簡単に行うことができる。 When step (e) of the method for manufacturing a semiconductor device according to the second embodiment is performed, the upper surfaces and upper portions of the side surfaces of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, rework in which the main terminals 62 and main terminals 67 attached to the upper surfaces of the metal blocks 60 and 66 are replaced with new main terminals can be performed relatively easily without any problems as step (e).

 加えて、前述したように、一対の露出側面60s及び60sにて金属ブロック60を安定性良く拘束した状態で主端子62を固定することができるため、主端子62の固定時におけるはんだ31や半導体素子20へのダメージを抑制することができる。 In addition, as described above, the main terminal 62 can be fixed in a state where the metal block 60 is stably held by the pair of exposed side surfaces 60s and 60s, so damage to the solder 31 and the semiconductor element 20 when the main terminal 62 is fixed can be suppressed.

 同様に、一対の露出側面66s及び66sにて金属ブロック66を安定性良く拘束した状態で主端子67を固定することができるため、主端子67の固定時におけるはんだ31や半導体素子20へのダメージを抑制することができる。 Similarly, the main terminal 67 can be fixed in place while the metal block 66 is stably held by the pair of exposed side surfaces 66s and 66s, so damage to the solder 31 and the semiconductor element 20 when the main terminal 67 is fixed can be suppressed.

 さらに、実施の形態2の製造方法は、ステップ(d-2)において、ステップ(d-1)の実行時に設けられたケース5のダム部収容領域S8内に封止樹脂7を形成することにより、封止樹脂7の高さ調整を比較的簡単に行うことができる。 Furthermore, in the manufacturing method of the second embodiment, in step (d-2), the sealing resin 7 is formed in the dam portion accommodation area S8 of the case 5 that was provided when step (d-1) was performed, making it relatively easy to adjust the height of the sealing resin 7.

 (第2の態様)
 図18は実施の形態2の第2の態様の半導体装置となるパワーモジュール2Bの断面構造を模式的に示す説明図である。図18は基本態様で示した図11のB-B断面構造に相当する。図18にXYZ直交座標系を記している。
(Second Aspect)
Fig. 18 is an explanatory diagram showing a schematic cross-sectional structure of a power module 2B which is a semiconductor device according to a second aspect of the second embodiment. Fig. 18 corresponds to the cross-sectional structure taken along line B-B in Fig. 11 which shows the basic aspect. An XYZ orthogonal coordinate system is shown in Fig. 18.

 実施の形態2の第2の態様であるパワーモジュール2Bに関し、基本態様のパワーモジュール2と同様な構成要素は同一符号を付して説明を適宜省略する。以下、図11及び図2で示した基本態様のパワーモジュール2と異なるパワーモジュール2Bの特徴箇所を中心に説明する。 With regard to the power module 2B, which is the second aspect of the second embodiment, components similar to those of the power module 2 of the basic aspect are given the same reference numerals and explanations thereof are omitted as appropriate. The following will focus on the characteristics of the power module 2B that are different from the power module 2 of the basic aspect shown in Figures 11 and 2.

 パワーモジュール2Bはダム部8、端子台51及び信号端子63を設けていない点でパワーモジュール2と異なる。パワーモジュール2Bでは端子台51及び信号端子63に替えて、ピン端子64をセラミック基板10の上面導体層12の表面上に直接、立設状態で設けている。なお、上面導体層12において、ピン端子64下の領域と、複数の半導体素子20下の領域とは電気的に分離されている。 Power module 2B differs from power module 2 in that it does not have a dam section 8, a terminal block 51, or a signal terminal 63. In power module 2B, instead of the terminal block 51 and the signal terminal 63, pin terminals 64 are provided in an upright state directly on the surface of the upper conductor layer 12 of the ceramic substrate 10. In addition, in the upper conductor layer 12, the area under the pin terminals 64 and the area under the multiple semiconductor elements 20 are electrically separated.

 ピン端子64下の上面導体層12の領域と半導体素子20とがワイヤ41によって電気的に接続されている。 The area of the upper conductor layer 12 below the pin terminal 64 and the semiconductor element 20 are electrically connected by a wire 41.

 さらに、パワーモジュール2Bでは、封止樹脂7に替えて封止樹脂7より粘度の高い封止樹脂7Bを用いている。したがって、ダム部8を設けることなく、フィンベース15Bの載置面15s上に封止樹脂7Bを設け、はんだ30~32、セラミック基板10B、半導体素子20、ワイヤ41、ピン端子64の一部、金属ブロック66の一部を封止樹脂7Bにより覆った構造を実現している。 Furthermore, in the power module 2B, sealing resin 7B, which has a higher viscosity than sealing resin 7, is used instead of sealing resin 7. Therefore, without providing a dam portion 8, sealing resin 7B is provided on the mounting surface 15s of the fin base 15B, and a structure is realized in which the solder 30-32, ceramic substrate 10B, semiconductor element 20, wire 41, part of the pin terminal 64, and part of the metal block 66 are covered with sealing resin 7B.

 第2の態様であるパワーモジュール2Bは、ダム部8を設けることによる効果を除き、基本態様であるパワーモジュール2と同様な効果を奏する。 The second embodiment, power module 2B, has the same effects as the basic embodiment, power module 2, except for the effect of providing the dam section 8.

 さらに、パワーモジュール2Bではダム部8を設けていない分、製造工程の簡単化を図る効果を奏する。具体的には、パワーモジュール2Bを製造する際、図15を参照して説明した処理を不要にしている。 Furthermore, the power module 2B does not have a dam portion 8, which has the effect of simplifying the manufacturing process. Specifically, when manufacturing the power module 2B, the process described with reference to FIG. 15 is not necessary.

 (第2の態様の製造方法)
 上述したパワーモジュール2Bの製造方法は、外部信号伝達用の主端子67を有する半導体装置の製造方法として以下のステップ(a)~(e)を備えている。
(Production method of the second embodiment)
The manufacturing method of the power module 2B described above includes the following steps (a) to (e) as a manufacturing method of a semiconductor device having a main terminal 67 for transmitting an external signal.

 ステップ(a)~(c)は、パワーモジュール2の製造方法におけるステップ(a)~(c)と同様である。 Steps (a) to (c) are the same as steps (a) to (c) in the manufacturing method of power module 2.

 ステップ(d)は、ブロック搭載部材となるセラミック基板10及び半導体素子20並びにはんだ31及び32を覆って封止樹脂7Bを形成するステップである。ステップ(d)は図16を参照して説明した処理に対応している。ステップ(d)の実行後、金属ブロック60及び66それぞれの上面及び側面の上方の一部は封止樹脂7Bによって覆われておらず露出状態となる。 Step (d) is a step of forming sealing resin 7B to cover ceramic substrate 10 and semiconductor element 20, which are block mounting members, as well as solders 31 and 32. Step (d) corresponds to the process described with reference to FIG. 16. After step (d) is performed, a portion of the upper part of the top surface and side surfaces of each of metal blocks 60 and 66 is not covered by sealing resin 7B and is exposed.

 パワーモジュール2Bの製造方法では、基本態様のステップ(d-1)で示したダム部8の形成処理を行わない分、ステップ(d)の製造内容の簡略化を図ることができる。 In the manufacturing method of the power module 2B, the manufacturing process of step (d) can be simplified by not performing the process of forming the dam portion 8 shown in step (d-1) of the basic embodiment.

 ステップ(e)は、パワーモジュール2の製造方法におけるステップ(e)と同様である。 Step (e) is the same as step (e) in the manufacturing method of power module 2.

 パワーモジュール2Bの製造方法は、パワーモジュール2の製造方法と同様な効果を奏し、さらに、上述したステップ(d)の製造内容の簡略化効果を奏する。 The manufacturing method for power module 2B has the same effect as the manufacturing method for power module 2, and further has the effect of simplifying the manufacturing process of step (d) described above.

 なお、実施の形態2のパワーモジュール2では、金属ブロック60及び66それぞれにおける拘束用の一対の露出側面として、Y方向に平行な面でかつX方向で対向する一対の露出側面60s及び60s並びに露出側面66s及び66sを示した。 In the power module 2 of the second embodiment, the pair of exposed side surfaces for restraint in the metal blocks 60 and 66 are shown as exposed side surfaces 60s and 60s, and exposed side surfaces 66s and 66s, which are parallel to the Y direction and face each other in the X direction.

 一対の露出側面60s及び60s並びに一対の露出側面66s及び66sに替えて、X方向に平行な面でかつY方向で対向する一対の露出側面を金属ブロック60及び66それぞれ拘束用の一対の露出側面としても良い。 Instead of the pair of exposed side surfaces 60s and 60s and the pair of exposed side surfaces 66s and 66s, a pair of exposed side surfaces parallel to the X direction and facing each other in the Y direction may be used as a pair of exposed side surfaces for restraining the metal blocks 60 and 66, respectively.

 また、実施の形態2では、それぞれの形状が四角柱形状の金属ブロック60及び66を示したが、一対の露出側面60s及び60sまたは一対の露出側面66s及び66sが設けることができる六角柱以上の多角柱状に金属ブロック60及び66それぞれを設けても良い。 In addition, in the second embodiment, the metal blocks 60 and 66 are shown to have a rectangular prism shape, but the metal blocks 60 and 66 may each be shaped like a polygonal prism of hexagonal or greater size on which a pair of exposed side surfaces 60s and 60s or a pair of exposed side surfaces 66s and 66s can be provided.

 <実施の形態3>
 以下、本開示の実施の形態3の半導体装置となるパワーモジュール3について説明する。
<Third embodiment>
Hereinafter, a power module 3 serving as a semiconductor device according to a third embodiment of the present disclosure will be described.

 図19はパワーモジュール3の平面構造を模式的に示す説明図である。図20は図19のC-C断面構造を模式的に示す説明図である。図19及び図20それぞれにXYZ直交座標系を記している。 FIG. 19 is an explanatory diagram that shows a schematic planar structure of the power module 3. FIG. 20 is an explanatory diagram that shows a schematic cross-sectional structure taken along the line C-C of FIG. 19. An XYZ orthogonal coordinate system is shown in each of FIG. 19 and FIG. 20.

 実施の形態3の基本態様であるパワーモジュール3に関し、実施の形態1の基本態様のパワーモジュール1や実施の形態2の基本態様のパワーモジュール2と同様な構成要素は同一符号を付して説明を適宜省略する。以下、図1~図3で示したパワーモジュール1または図11及び図12で示したパワーモジュール2と異なるパワーモジュール3の特徴箇所を中心に説明する。 With regard to the power module 3 which is the basic aspect of the third embodiment, the same components as those of the power module 1 which is the basic aspect of the first embodiment and the power module 2 which is the basic aspect of the second embodiment are given the same reference numerals and the description thereof is omitted as appropriate. The following description will focus on the characteristic features of the power module 3 which are different from the power module 1 shown in Figures 1 to 3 or the power module 2 shown in Figures 11 and 12.

 絶縁基板であるセラミック基板10Cは、絶縁基材となる窒化ケイ素基材11Cと、窒化ケイ素基材11Cの上面上に設けられる上面導体層12と、セラミック基板10Cの下面上に設けられる下面導体層13とを有している。上面導体層12の表面が基板の第1の主面となり、下面導体層13の表面が基板の第2の主面となる。 The ceramic substrate 10C, which is an insulating substrate, has a silicon nitride substrate 11C that serves as an insulating base material, an upper conductor layer 12 provided on the upper surface of the silicon nitride substrate 11C, and a lower conductor layer 13 provided on the lower surface of the ceramic substrate 10C. The surface of the upper conductor layer 12 becomes the first main surface of the substrate, and the surface of the lower conductor layer 13 becomes the second main surface of the substrate.

 窒化ケイ素基材11Cの平面形状は例えば90mm×75mm構成であり、窒化ケイ素基材11CのZ方向に沿った厚さは例えば0.32mmに設定されている。 The planar shape of the silicon nitride substrate 11C is, for example, 90 mm x 75 mm, and the thickness of the silicon nitride substrate 11C in the Z direction is set to, for example, 0.32 mm.

 パワーモジュール3は、セラミック基板10Cの下面導体層13の表面上に放熱シート73を介して放熱用フィンであるフィンベース15を固定している。 The power module 3 has a fin base 15, which is a heat dissipation fin, fixed to the surface of the lower conductor layer 13 of the ceramic substrate 10C via a heat dissipation sheet 73.

 セラミック基板10Cの窒化ケイ素基材11C上に上面導体層12、複数の半導体素子20及び複数の金属ブロック66を囲んでダム部9が周状に設けられる。収容空間形成部材であるダム部9のZ方向に沿った形成高さは例えば6mm程度に設定される。複数の半導体素子20としてダイオードやIGBTが考えられる。 A dam portion 9 is provided circumferentially on the silicon nitride base material 11C of the ceramic substrate 10C, surrounding the upper conductor layer 12, the multiple semiconductor elements 20, and the multiple metal blocks 66. The formation height of the dam portion 9, which is a member forming the storage space, in the Z direction is set to, for example, about 6 mm. The multiple semiconductor elements 20 may be diodes or IGBTs.

 ダム部9は、実施の形態2のダム部8と同様、複数のダム材81を積層して構成される。複数のダム材81を積層する処理として例えばディスペンサーを用いた描画処理が考えられる。 Similar to the dam section 8 in the second embodiment, the dam section 9 is constructed by stacking a plurality of dam materials 81. As a process for stacking a plurality of dam materials 81, for example, a drawing process using a dispenser can be considered.

 パワーモジュール3の主回路は、金属ブロック60及び66、ねじ61並びに主端子67を構成要素として含んでいる。 The main circuit of the power module 3 includes metal blocks 60 and 66, a screw 61, and a main terminal 67 as components.

 ダム部9によって囲まれるダム部収容領域S9内において、フィンベース15の載置面15s上に設けられるはんだ30、セラミック基板10C、はんだ31、複数の半導体素子20、はんだ32、及びワイヤ41を覆って封止樹脂7が設けられる。封止樹脂7の構成材料として、例えばエポキシ樹脂にシリカフィラーを分散させた材料が考えられる。 In the dam portion accommodation area S9 surrounded by the dam portion 9, sealing resin 7 is provided to cover the solder 30, ceramic substrate 10C, solder 31, multiple semiconductor elements 20, solder 32, and wires 41 provided on the mounting surface 15s of the fin base 15. The sealing resin 7 may be made of, for example, epoxy resin with silica filler dispersed therein.

 各金属ブロック66の上面及び側面の上方の一部は封止樹脂7よって覆われておらず露出状態となっている。例えば、ダム部収容領域S9内において封止樹脂7により深さ4mm程度封止されており、金属ブロック60は上面から2mm程度、露出している。 The top surface and a portion of the upper side of each metal block 66 are not covered with the sealing resin 7 and are exposed. For example, the dam portion housing area S9 is sealed with the sealing resin 7 to a depth of about 4 mm, and the metal block 60 is exposed about 2 mm from the top surface.

 すなわち、実施の形態2と同様、露出状態の金属ブロック66の側面は、Y方向に平行な面でかつX方向で対向する一対の露出側面66s及び66sを含んでいる。 In other words, similar to embodiment 2, the side of the exposed metal block 66 includes a pair of exposed side surfaces 66s and 66s that are parallel to the Y direction and face each other in the X direction.

 一対の露出側面66s及び66sは封止樹脂7から2mm程度露出しているため、既存の拘束用治具を用いて一対の露出側面66s及び66sを挟んで把持する態様で金属ブロック66を拘束することができる。 Since the pair of exposed side surfaces 66s and 66s are exposed from the sealing resin 7 by about 2 mm, the metal block 66 can be restrained by clamping the pair of exposed side surfaces 66s and 66s using an existing restraining tool.

 パワーモジュール3は、セラミック基板10C、複数の半導体素子20、金属ブロック60及び66を内部に収容する素子収容空間として、ダム部9内にダム部収容領域S9を設けている。そして、封止樹脂7はダム部収容領域S9内に設けられる。 The power module 3 has a dam portion housing area S9 in the dam portion 9 as an element housing space that houses the ceramic substrate 10C, the multiple semiconductor elements 20, and the metal blocks 60 and 66. The sealing resin 7 is provided in the dam portion housing area S9.

 実施の形態3の基本態様であるパワーモジュール3は、セラミック基板10C及び半導体素子20並びにはんだ31及びはんだ32を覆って封止樹脂7が設けられている。 The power module 3, which is the basic form of the third embodiment, is provided with a sealing resin 7 covering the ceramic substrate 10C, the semiconductor element 20, the solder 31, and the solder 32.

 したがって、実施の形態3の基本態様であるパワーモジュール3は、実施の形態1の基本態様であるパワーモジュール1と同様、製造段階でセラミック基板10Cに悪影響を与えない構造を呈するため、装置の歩留まり及び絶縁性を含む性能の向上を図ることができる。 Therefore, like the power module 1, which is the basic aspect of the first embodiment, the power module 3, which is the basic aspect of the third embodiment, has a structure that does not adversely affect the ceramic substrate 10C during the manufacturing stage, and therefore it is possible to improve the performance, including the yield and insulation properties, of the device.

 さらに、パワーモジュール3における金属ブロック60及び66それぞれの上面は封止樹脂7によって覆われておらず露出状態である。このため、装置完成後においても金属ブロック66の上面上に固定される主端子67を新たな主端子に取り替えるねじ61を用いたリワークを比較的簡単に行うことができる。同様に、装置完成後においても金属ブロック60の上面上に固定される主端子62を新たな主端子に取り替えるねじ61を用いたリワークを比較的簡単に行うことができる。したがって、主端子62及び主端子67の選択に際しフレキシビリティを持たせることができる。 Furthermore, the upper surfaces of the metal blocks 60 and 66 in the power module 3 are not covered with the sealing resin 7 and are exposed. Therefore, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 67 fixed on the upper surface of the metal block 66 with a new main terminal. Similarly, even after the device is completed, rework can be performed relatively easily by using the screw 61 to replace the main terminal 62 fixed on the upper surface of the metal block 60 with a new main terminal. Therefore, flexibility can be provided when selecting the main terminals 62 and 67.

 加えて、パワーモジュール3は、完成段階において、ケース5に起因する効果を除き、基本態様のパワーモジュール1と同様な効果を奏し、さらに、以下の効果を奏する。 In addition, when the power module 3 is completed, it provides the same effects as the basic power module 1, except for the effects attributable to the case 5, and further provides the following effects:

 また、パワーモジュール3は、窒化ケイ素基材11C上に設けられたダム部9のダム部収容領域S9内に封止樹脂7を設けることにより、専用のケースを要することなく、製造時における封止樹脂7の高さ調整を比較的簡単に行うことができる。 In addition, by providing the sealing resin 7 in the dam portion accommodation area S9 of the dam portion 9 provided on the silicon nitride substrate 11C, the power module 3 does not require a dedicated case and allows the height of the sealing resin 7 to be adjusted relatively easily during manufacturing.

 加えて、パワーモジュール3において、セラミック基板10Cの下面導体層13はダム部9及び封止樹脂7の制約を受けないため、基板の第2の主面となる下面導体層13の表面に形成される構造物の設計自由度を高めることができる。 In addition, in the power module 3, the bottom conductor layer 13 of the ceramic substrate 10C is not restricted by the dam portion 9 and the sealing resin 7, which increases the design freedom of the structures formed on the surface of the bottom conductor layer 13, which is the second main surface of the substrate.

 具体的には、放熱シート73として常温で接着可能な素材を用いて放熱用フィンであるフィンベース15を比較的容易に固定することができる。したがって、パワーモジュール3は、装置完成後においても下面導体層13の表面上に固定されるフィンベース15を新たなフィンベースに取り替える放熱シート73を用いたリワークを比較的簡単に行うことができる。このように、パワーモジュール3は様々な形状の放熱用フィンを比較的簡単に設けることができる。 Specifically, the fin base 15, which is a heat dissipation fin, can be fixed relatively easily by using a material that can be bonded at room temperature as the heat dissipation sheet 73. Therefore, even after the device is completed, the power module 3 can be relatively easily reworked using the heat dissipation sheet 73 to replace the fin base 15 fixed on the surface of the lower conductor layer 13 with a new fin base. In this way, the power module 3 can be relatively easily provided with heat dissipation fins of various shapes.

 加えて、パワーモジュール3において、放熱シート73として熱伝導性が比較的高い素材を用いることにより、半導体素子20の動作時に発生する熱を、セラミック基板10C及び放熱シート73を介してフィンベース15に効果的に放熱することができる。 In addition, by using a material with relatively high thermal conductivity for the heat dissipation sheet 73 in the power module 3, the heat generated during operation of the semiconductor element 20 can be effectively dissipated to the fin base 15 via the ceramic substrate 10C and the heat dissipation sheet 73.

 さらに、パワーモジュール3のセラミック基板10Cにおける下面導体層13は封止樹脂7で覆われておらず開放されている。したがって、常温で接着処理が行える放熱シート73を介して下面導体層13の表面上にフィンベース15の載置面15sを比較的簡単に接着することができる。 Furthermore, the lower conductor layer 13 of the ceramic substrate 10C of the power module 3 is not covered with the sealing resin 7 and is open. Therefore, the mounting surface 15s of the fin base 15 can be relatively easily bonded to the surface of the lower conductor layer 13 via the heat dissipation sheet 73, which can be bonded at room temperature.

 (製造方法)
 図21~図25はパワーモジュール3の製造工程時における断面構造を模式的に示す説明図である。図21~図25それぞれにXYZ直交座標系を記している。以下、図21~図25を参照してパワーモジュール3の製造方法を説明する。
(Production method)
21 to 25 are explanatory diagrams that show a schematic cross-sectional structure during the manufacturing process of the power module 3. An XYZ orthogonal coordinate system is shown in each of Fig. 21 to Fig. 25. Hereinafter, the manufacturing method of the power module 3 will be described with reference to Fig. 21 to Fig. 25.

 なお、図19及び図20に示すように、パワーモジュール3は、4つの半導体素子20と4つの金属ブロック66と2つの金属ブロック60を含んでいるが、説明の都合上、図21~図25で図示された構造を基準として説明する。なお、図21~図25では図示しない金属ブロック60の形成工程は図4~図8で示した実施の形態1の製造方法と同様な工程となる。 As shown in Figures 19 and 20, the power module 3 includes four semiconductor elements 20, four metal blocks 66, and two metal blocks 60, but for convenience of explanation, the structure shown in Figures 21 to 25 will be used as the basis. The process for forming the metal blocks 60, which are not shown in Figures 21 to 25, is the same as the manufacturing method of the first embodiment shown in Figures 4 to 8.

 まず、実施の形態3の半導体装置用の基板となるセラミック基板10Cが準備される。パワーモジュール3ではセラミック基板10C及び半導体素子20がブロック搭載部材となっている。 First, a ceramic substrate 10C is prepared as a substrate for the semiconductor device of the third embodiment. In the power module 3, the ceramic substrate 10C and the semiconductor element 20 serve as block mounting members.

 次に、図21に示すように、セラミック基板10Cの上面導体層12の上方に、はんだ31と2つの半導体素子20とを位置決め配置し、さらに、2つの半導体素子20の上方に、はんだ32と2つの金属ブロック66とを位置決め配置し、リフロー炉を用いてはんだ31及びはんだ32によるはんだ接合を行う。 Next, as shown in FIG. 21, solder 31 and two semiconductor elements 20 are positioned above the upper conductor layer 12 of the ceramic substrate 10C, and solder 32 and two metal blocks 66 are positioned above the two semiconductor elements 20, and solder bonding is performed using the solder 31 and the solder 32 in a reflow furnace.

 その結果、セラミック基板10Cの上面導体層12の表面上に2つの半導体素子20がはんだ31を介して搭載され、2つの半導体素子20の上面上に2つの金属ブロック66がはんだ32を介して搭載される。すなわち、金属ブロック66はブロック搭載部材となる半導体素子20の上面上にはんだ32を介して接合される。 As a result, two semiconductor elements 20 are mounted on the surface of the upper conductor layer 12 of the ceramic substrate 10C via solder 31, and two metal blocks 66 are mounted on the upper surfaces of the two semiconductor elements 20 via solder 32. In other words, the metal blocks 66 are joined via solder 32 to the upper surfaces of the semiconductor elements 20 that serve as block mounting members.

 次に、図22に示すように、セラミック基板10Cの窒化ケイ素基材11Cの上面上に複数のダム材81を積層してダム部9を形成する。ダム材81の積層処理として例えばディスペンサーを用いた塗布処理が実行される。完成後のダム部9はダム部収容領域S9を有しており、ダム部収容領域S9内にはんだ31、上面導体層12及び2つの半導体素子20が存在するように、ダム部9は窒化ケイ素基材11の上面上に設けられる。 Next, as shown in FIG. 22, a plurality of dam materials 81 are laminated on the upper surface of the silicon nitride base material 11C of the ceramic substrate 10C to form the dam portion 9. The dam materials 81 are laminated, for example, by a coating process using a dispenser. The completed dam portion 9 has a dam portion accommodation area S9, and the dam portion 9 is provided on the upper surface of the silicon nitride base material 11 so that the solder 31, the upper surface conductor layer 12, and the two semiconductor elements 20 are present within the dam portion accommodation area S9.

 その後、図23に示すように、セラミック基板10Cの上面導体層12の表面の一部上に端子台51が接着して固定される。信号端子63は端子台51に一体化されている。 Then, as shown in FIG. 23, the terminal block 51 is adhered and fixed to a portion of the surface of the upper conductor layer 12 of the ceramic substrate 10C. The signal terminal 63 is integrated with the terminal block 51.

 端子台51を上面導体層12に固定後、ワイヤ41による配線が行われる。すなわち、ワイヤ41によって端子水平部分63aの表面と半導体素子20とが電気的に接続される。ワイヤ41の配線後、2つの半導体素子20、ワイヤ41、2つの金属ブロック66及び信号端子63を含む回路が形成される。 After the terminal block 51 is fixed to the upper conductor layer 12, wiring is performed using the wire 41. That is, the surface of the terminal horizontal portion 63a and the semiconductor element 20 are electrically connected by the wire 41. After wiring the wire 41, a circuit is formed that includes the two semiconductor elements 20, the wire 41, the two metal blocks 66, and the signal terminal 63.

 次に、図24に示すように、2つの金属ブロック66それぞれの上面及び側面の上方の一部が露出する程度に、ダム部収容領域S9内に封止樹脂7を注入して加熱硬化させる。すなわち、金属ブロック66の上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となっている。 Next, as shown in FIG. 24, sealing resin 7 is injected into the dam portion housing area S9 and heated to harden so that the upper surfaces and upper portions of the sides of each of the two metal blocks 66 are exposed. In other words, the upper surfaces and upper portions of the sides of the metal blocks 66 are not covered by the sealing resin 7 and are exposed.

 一方、ダム部収容領域S9内において、はんだ31及び32、セラミック基板10Cの上面導体層12、2つの半導体素子20及びワイヤ41は全て封止樹脂7によって覆われている。 On the other hand, within the dam portion accommodation area S9, the solders 31 and 32, the upper surface conductor layer 12 of the ceramic substrate 10C, the two semiconductor elements 20, and the wires 41 are all covered with the sealing resin 7.

 さらに、2つの金属ブロック66の一部と端子台51の一部とが封止樹脂7によって覆われる。ただし、2つの金属ブロック66の上面及び側面の上方の一部は封止樹脂7によって覆われず露出している。すなわち、露出状態の金属ブロック66の側面は、X方向で対向する一対の露出側面66s及び66sを含んでいる。 Furthermore, parts of the two metal blocks 66 and parts of the terminal block 51 are covered with sealing resin 7. However, the top surfaces and upper parts of the side surfaces of the two metal blocks 66 are not covered with sealing resin 7 and are exposed. In other words, the side surfaces of the exposed metal blocks 66 include a pair of exposed side surfaces 66s and 66s that face each other in the X direction.

 その後、放熱シート73を介してセラミック基板10Cの下面導体層13とフィンベース15の載置面15sとを接着固定する。 Then, the lower conductor layer 13 of the ceramic substrate 10C and the mounting surface 15s of the fin base 15 are adhesively fixed via the heat dissipation sheet 73.

 最後に、図25に示すように、2つの金属ブロック66それぞれのねじ穴領域66xと1つの主端子67の2つの開口部62oとが平面視して合致するように位置決めし、2つのねじ61を用いて金属ブロック66と主端子67とを接続固定する。 Finally, as shown in FIG. 25, the screw hole regions 66x of the two metal blocks 66 are positioned so that they match the two openings 62o of one main terminal 67 in a plan view, and the metal blocks 66 and the main terminal 67 are connected and fixed using two screws 61.

 実施の形態3のパワーモジュール3は、実施の形態2のパワーモジュール2と同様、一対の露出側面66s及び66sにて金属ブロック66を安定性良く拘束した状態で主端子67を固定することができるため、主端子67の固定時におけるはんだ31や半導体素子20へのダメージを抑制することができる。 The power module 3 of the third embodiment, like the power module 2 of the second embodiment, can fix the main terminal 67 in a state where the metal block 66 is stably restrained by a pair of exposed side surfaces 66s and 66s, so that damage to the solder 31 and the semiconductor element 20 when the main terminal 67 is fixed can be suppressed.

 図25に示すように、封止樹脂7により金属ブロック66が途中まで封止されているため、2つのねじ61によって主端子67を金属ブロック66の上面上に取り付ける際、2つのねじ61それぞれの締め付けるトルクによって金属ブロック66と半導体素子20とのブロック用接合材となるはんだ32等へのダメージを低減する効果を奏する。 As shown in FIG. 25, the metal block 66 is partially sealed with the sealing resin 7, so when the main terminal 67 is attached to the top surface of the metal block 66 with the two screws 61, the tightening torque of each of the two screws 61 has the effect of reducing damage to the solder 32, which serves as the block bonding material between the metal block 66 and the semiconductor element 20.

 上述したパワーモジュール3の製造方法は、外部信号伝達用の主端子67を有する半導体装置の製造方法として以下のステップ(a)~(f)を備えている。 The manufacturing method for the power module 3 described above includes the following steps (a) to (f) as a manufacturing method for a semiconductor device having a main terminal 67 for transmitting an external signal.

 ステップ(a)は、第1及び第2の主面を有する基板としてセラミック基板10Cを準備するステップである。 Step (a) is a step of preparing a ceramic substrate 10C as a substrate having a first and second main surfaces.

 ステップ(b)は、「基板の第1の主面」となる上面導体層12の表面上に複数の半導体素子20を搭載するステップである。実施の形態3の基本態様では、セラミック基板10C及び半導体素子20がブロック搭載部材として機能している。ステップ(b)は図21を参照して説明した処理に対応する。 Step (b) is a step of mounting a plurality of semiconductor elements 20 on the surface of the upper conductor layer 12, which becomes the "first main surface of the substrate." In the basic aspect of the third embodiment, the ceramic substrate 10C and the semiconductor elements 20 function as block mounting members. Step (b) corresponds to the process described with reference to FIG. 21.

 ステップ(c)は、ブロック搭載部材となるセラミック基板10Cと金属ブロック60とをブロック用接合材として機能するはんだ31を介して接合し、かつ、ブロック搭載部材となる半導体素子20と金属ブロック66とをブロック用接合材として機能するはんだ32を介して接合するステップである。ステップ(c)は図21を参照して説明した処理に対応する。 Step (c) is a step of joining the ceramic substrate 10C, which serves as the block mounting member, and the metal block 60 via solder 31, which functions as a block bonding material, and joining the semiconductor element 20, which serves as the block mounting member, and the metal block 66 via solder 32, which functions as a block bonding material. Step (c) corresponds to the process described with reference to FIG. 21.

 ステップ(d)は、セラミック基板10C及び半導体素子20並びにはんだ31及び32を覆って封止樹脂7を形成するステップである。ステップ(d)は図22~図24を参照して説明した処理に対応する。 Step (d) is a step of forming sealing resin 7 to cover ceramic substrate 10C, semiconductor element 20, and solders 31 and 32. Step (d) corresponds to the process described with reference to Figures 22 to 24.

 ステップ(d)の実行後、金属ブロック60及び66それぞれの上面及び側面の上方の一部は封止樹脂7によって覆われておらず露出状態となる。したがって、封止樹脂7から2mm程度露出した一対の露出側面60s及び60s並びに一対の露出側面66s及び66sが存在する。 After step (d) is performed, the upper surfaces and upper portions of the sides of the metal blocks 60 and 66 are not covered by the sealing resin 7 and are exposed. Therefore, there are a pair of exposed side surfaces 60s and 60s and a pair of exposed side surfaces 66s and 66s that are exposed by about 2 mm from the sealing resin 7.

 ステップ(d)は以下のステップ(d-1)及び(d-2)を含んでいる。 Step (d) includes the following steps (d-1) and (d-2).

 ステップ(d-1)は、セラミック基板10Cの上面導体層12、半導体素子20、並びに金属ブロック60及び66を囲んで収容空間形成部材であるダム部9をセラミック基板10Cの窒化ケイ素基材11Cの表面上に設けるステップである。ステップ(d-1)は図22を参照して説明した処理に対応する。 Step (d-1) is a step of providing a dam portion 9, which is a member for forming a storage space, on the surface of the silicon nitride base material 11C of the ceramic substrate 10C, surrounding the upper surface conductor layer 12, the semiconductor element 20, and the metal blocks 60 and 66 of the ceramic substrate 10C. Step (d-1) corresponds to the process described with reference to FIG. 22.

 ステップ(d-2)は、ダム部9で囲われた素子収容空間であるダム部収容領域S9内において、上面導体層12、半導体素子20並びにはんだ31及び32を覆って封止樹脂7を形成するステップである。ステップ(d-2)は図24を参照して説明した処理に対応する。 Step (d-2) is a step of forming sealing resin 7 to cover upper surface conductor layer 12, semiconductor element 20, and solders 31 and 32 within dam portion accommodation area S9, which is an element accommodation space surrounded by dam portion 9. Step (d-2) corresponds to the process described with reference to FIG. 24.

 ステップ(e)は、上述したステップ(d)後に実行され、金属ブロック60及び66それぞれの上面上に主端子62及び67を取り付けるステップである。ステップ(e)は図25を参照して説明した処理に対応する。 Step (e) is performed after step (d) described above, and is a step of attaching main terminals 62 and 67 to the upper surfaces of metal blocks 60 and 66, respectively. Step (e) corresponds to the process described with reference to FIG. 25.

 ステップ(f)は、下面導体層13と放熱用フィンであるフィンベース15とを放熱シート73を介して接合するステップである。ステップ(f)は図24を参照して説明した処理に対応する。 Step (f) is a step of joining the lower conductor layer 13 and the fin base 15, which is a heat dissipation fin, via the heat dissipation sheet 73. Step (f) corresponds to the process described with reference to FIG. 24.

 なお、図21~図25で示してパワーモジュール3の製造方法では、ステップ(d)とステップ(f)とをほぼ同時に行った後、ステップ(e)を実行している。 In the method for manufacturing the power module 3 shown in Figures 21 to 25, steps (d) and (f) are carried out almost simultaneously, and then step (e) is carried out.

 実施の形態3の半導体装置の製造方法は、ステップ(d-1)で複数のダム材81を積層してダム部9を設けているため、ステップ(d-2)にてダム部9のダム部収容領域S9内に形成される封止樹脂7の高さ調整を、専用のケースを要することなく比較的簡単に行うことができる。 In the manufacturing method of the semiconductor device of the third embodiment, since the dam portion 9 is formed by stacking multiple dam materials 81 in step (d-1), the height of the sealing resin 7 formed in the dam portion accommodation area S9 of the dam portion 9 in step (d-2) can be adjusted relatively easily without requiring a dedicated case.

 さらに、実施の形態3の半導体装置の製造方法は、ステップ(f)において、放熱シート73を用いて放熱用フィンであるフィンベース15を比較的容易に製造することができる。 Furthermore, in the method for manufacturing a semiconductor device according to the third embodiment, in step (f), the fin base 15, which is a heat dissipation fin, can be manufactured relatively easily using the heat dissipation sheet 73.

 加えて、パワーモジュール3の製造方法で製造される半導体装置であるパワーモジュール3において、放熱シート73として熱伝導性が比較的高い素材を用いて、フィンベース15の載置面15sとセラミック基板10Cの下面導体層13の表面とを固定することができる。このため、パワーモジュール3は、半導体素子20の動作時に発生する熱を、セラミック基板10C及び放熱シート73を介してフィンベース15に効果的に放熱することができる。 In addition, in the power module 3, which is a semiconductor device manufactured by the manufacturing method of the power module 3, a material with relatively high thermal conductivity can be used as the heat dissipation sheet 73 to fix the mounting surface 15s of the fin base 15 and the surface of the lower conductor layer 13 of the ceramic substrate 10C. Therefore, the power module 3 can effectively dissipate heat generated during operation of the semiconductor element 20 to the fin base 15 via the ceramic substrate 10C and the heat dissipation sheet 73.

 パワーモジュール3の製造方法では半導体素子20と上面導体層12との接合にはんだ31を用い、半導体素子20と金属ブロック66との接合にはんだ32を用いたが、はんだ31及び32に替えて、耐熱性の高い高融点はんだや銀焼結材等を用いても良い。 In the manufacturing method of the power module 3, solder 31 is used to join the semiconductor element 20 to the upper conductor layer 12, and solder 32 is used to join the semiconductor element 20 to the metal block 66, but instead of the solders 31 and 32, a high-melting-point solder with high heat resistance or a silver sintered material may be used.

 高融点はんだや銀焼結材等を用いた場合、セラミック基板10Cとフィンベース15との接合材として、放熱シート73に替えて融点の低いフィンベース用はんだを用いることで放熱性の改善が行える。 When using high melting point solder or silver sintered material, heat dissipation can be improved by using fin base solder with a low melting point instead of the heat dissipation sheet 73 as the joining material between the ceramic substrate 10C and the fin base 15.

 また、金属ブロック66の主端子取付領域であるねじ穴領域66xを通じて外界に繋がっているため、ねじ穴領域66xにおいて表面が露出しているはんだ32が再溶融してもはんだ32の体積増大に伴う封止樹脂7の破壊などが起こりにくい。 In addition, because the metal block 66 is connected to the outside world through the screw hole region 66x, which is the main terminal mounting region, even if the solder 32, whose surface is exposed in the screw hole region 66x, remelts, the increase in volume of the solder 32 is unlikely to cause damage to the sealing resin 7.

 <実施の形態4>
 実施の形態4は、上述した実施の形態1~実施の形態3にかかる半導体装置であるパワーモジュール1,1B,1C,2,2B及び3を電力変換装置に適用したものである。本開示は特定の電力変換装置に限定されるものではないが、以下、実施の形態4として、三相のインバータに本開示を適用した場合について説明する。
<Fourth embodiment>
In the fourth embodiment, the power modules 1, 1B, 1C, 2, 2B, and 3, which are the semiconductor devices according to the first to third embodiments, are applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the following describes the fourth embodiment in the case where the present disclosure is applied to a three-phase inverter.

 図26は、本開示の実施の形態4である電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 26 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to embodiment 4 of the present disclosure is applied.

 図26に示す電力変換システムは、電源1000、電力変換装置2000、負荷3000から構成される。電源1000は、直流電源であり、電力変換装置2000に直流電力を供給する。電源1000は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やAC/DCコンバータで構成することとしてもよい。また、電源1000を、直流系統から出力される直流電力を所定の電力に変換するDC/DCコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 26 is composed of a power source 1000, a power conversion device 2000, and a load 3000. The power source 1000 is a DC power source, and supplies DC power to the power conversion device 2000. The power source 1000 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC/DC converter. The power source 1000 may also be composed of a DC/DC converter that converts the DC power output from the DC system into a specified power.

 電力変換装置2000は、電源1000と負荷3000の間に接続された三相のインバータであり、電源1000から供給された直流電力を交流電力に変換し、負荷3000に交流電力を供給する。電力変換装置2000は、図26に示すように、直流電力を交流電力に変換して出力する主変換回路2001と、主変換回路2001を制御する制御信号を主変換回路2001に出力する制御回路2003とを備えている。 The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, converts the DC power supplied from the power source 1000 into AC power, and supplies the AC power to the load 3000. As shown in FIG. 26, the power conversion device 2000 includes a main conversion circuit 2001 that converts the DC power into AC power and outputs it, and a control circuit 2003 that outputs a control signal to the main conversion circuit 2001 to control the main conversion circuit 2001.

 負荷3000は、電力変換装置2000から供給された交流電力によって駆動される三相の電動機である。なお、負荷3000は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。 The load 3000 is a three-phase motor driven by AC power supplied from the power conversion device 2000. Note that the load 3000 is not limited to a specific use, but is a motor mounted on various electrical devices, and is used, for example, as a motor for hybrid cars, electric cars, railroad cars, elevators, or air conditioning equipment.

 以下、電力変換装置2000の詳細を説明する。主変換回路2001は、スイッチング素子と還流ダイオードを備えており(図示せず)、スイッチング素子がスイッチングすることによって、電源1000から供給される直流電力を交流電力に変換し、負荷3000に供給する。主変換回路2001の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路2001は2レベルの三相フルブリッジ回路であり、6つのスイッチング素子とそれぞれのスイッチング素子に逆並列された6つの還流ダイオードから構成することができる。主変換回路2001の各スイッチング素子と各還流ダイオードの少なくともいずれかを、上述した実施の形態1~実施の形態3で用いられたパワーモジュール1,1B,1C,2,2B及び3のいずれかによって構成する。 The power conversion device 2000 will be described in detail below. The main conversion circuit 2001 includes switching elements and free wheel diodes (not shown), and converts DC power supplied from the power source 1000 into AC power by switching the switching elements, and supplies it to the load 3000. There are various specific circuit configurations for the main conversion circuit 2001, but the main conversion circuit 2001 in this embodiment is a two-level three-phase full bridge circuit that can be configured from six switching elements and six free wheel diodes connected in inverse parallel to each switching element. At least one of the switching elements and free wheel diodes of the main conversion circuit 2001 is configured from one of the power modules 1, 1B, 1C, 2, 2B, and 3 used in the above-mentioned embodiments 1 to 3.

 6つのスイッチング素子は2つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相(U相、V相、W相)を構成する。そして、各上下アームの出力端子、すなわち主変換回路2001の3つの出力端子は、負荷3000に接続される。 The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 2001, are connected to the load 3000.

 また、主変換回路2001は、各スイッチング素子を駆動する駆動回路(図示なし)を備えているが、駆動回路は半導体モジュール2002に内蔵されていてもよいし、半導体モジュール2002とは別に駆動回路を備える構成であってもよい。半導体モジュール2002を上述した実施の形態1~実施の形態3のパワーモジュール1,1B,1C,2,2B及び3で構成しても良い。 The main conversion circuit 2001 also includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built into the semiconductor module 2002, or the drive circuit may be provided separately from the semiconductor module 2002. The semiconductor module 2002 may be configured with the power modules 1, 1B, 1C, 2, 2B, and 3 of the above-mentioned first to third embodiments.

 駆動回路は、主変換回路2001のスイッチング素子を駆動する駆動信号を生成し、主変換回路2001のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路2003からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号(オン信号)であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号(オフ信号)となる。 The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 2001 and supplies them to the control electrodes of the switching elements of the main conversion circuit 2001. Specifically, in accordance with a control signal from the control circuit 2003 described below, it outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

 制御回路2003は、負荷3000に所望の電力が供給されるよう主変換回路2001のスイッチング素子を制御する。具体的には、負荷3000に供給すべき電力に基づいて主変換回路2001の各スイッチング素子がオン状態となるべき時間(オン時間)を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するPWM制御によって主変換回路2001を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路2001が備える駆動回路に制御指令(制御信号)を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号またはオフ信号を駆動信号として出力する。 The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 2001 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 2001 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

 実施の形態4である電力変換装置2000では、主変換回路2001のスイッチング素子や還流ダイオードとして実施の形態1~実施の形態3の半導体装置であるパワーモジュール1,1B,1C,2,2B及び3のいずれかを適用するため、装置の歩留まり及び性能の向上を図ることができる。 In the power conversion device 2000 of the fourth embodiment, any of the power modules 1, 1B, 1C, 2, 2B, and 3, which are the semiconductor devices of the first to third embodiments, are used as the switching elements and free wheel diodes of the main conversion circuit 2001, thereby improving the yield and performance of the device.

 実施の形態4では、2レベルの三相インバータに本開示を適用する例を説明したが、本開示は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、2レベルの電力変換装置としたが3レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本開示を適用しても構わない。また、直流負荷等に電力を供給する場合にはDC/DCコンバータやAC/DCコンバータに本開示を適用することも可能である。 In the fourth embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, the present disclosure can also be applied to a DC/DC converter or an AC/DC converter when supplying power to a DC load, etc.

 また、本開示を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザ加工機、または誘導加熱調理器や非接触給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。 Furthermore, the power conversion device to which this disclosure is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine or laser processing machine, or an induction heating cooker or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.

 なお、本開示は、その開示の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。 In addition, within the scope of this disclosure, it is possible to freely combine the various embodiments, modify them as appropriate, or omit them.

 本開示は詳細に説明されたが、上記した説明は、すべての局面において、例示であって、本開示がそれに限定されるものではない。例示されていない無数の変形例が、本開示の範囲から外れることなく想定され得るものと解される。 Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

 以下、本開示の諸態様を付記としてまとめて記載する。 The various aspects of this disclosure are summarized below as appendices.

 (付記1)
 外部信号伝達用の主端子を有する半導体装置であって、
 第1及び第2の主面を有する基板と、
 前記基板の第1の主面上に設けられる半導体素子と、
 前記基板及び前記半導体素子のうち少なくとも一つであるブロック搭載部材上に設けられる金属ブロックと、
 前記ブロック搭載部材と前記金属ブロックとはブロック用接合材を介して接合されており、
 前記金属ブロックは主端子取付領域を有し、前記主端子は前記主端子取付領域にて前記金属ブロックに固定され、
 前記半導体装置は、
 少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記基板の第1の主面上に設けられる封止樹脂をさらに備える、
半導体装置。
(Appendix 1)
A semiconductor device having a main terminal for transmitting an external signal,
a substrate having first and second major surfaces;
A semiconductor element provided on a first main surface of the substrate;
a metal block provided on a block mounting member which is at least one of the substrate and the semiconductor element;
The block mounting member and the metal block are joined via a block joining material,
the metal block has a main terminal attachment region, the main terminal is fixed to the metal block at the main terminal attachment region,
The semiconductor device includes:
The block mounting member and the block bonding material are covered with a sealing resin provided on the first main surface of the substrate.
Semiconductor device.

 (付記2)
 付記1記載の半導体装置であって、
 前記主端子取付領域は前記金属ブロックの上面を含み、前記金属ブロックの上面上に前記主端子は固定されており、
 前記金属ブロックの上面は前記封止樹脂によって覆われておらず露出状態である、
半導体装置。
(Appendix 2)
2. The semiconductor device according to claim 1,
the main terminal attachment region includes an upper surface of the metal block, and the main terminal is fixed onto the upper surface of the metal block;
The upper surface of the metal block is not covered with the sealing resin and is exposed.
Semiconductor device.

 (付記3)
 付記1または付記2に記載の半導体装置であって、
 前記主端子は開口部を有し、
 前記金属ブロックは上面から下面に向けて設けられるねじ穴領域を有し、
 前記主端子取付領域は前記ねじ穴領域を含み、
 前記半導体装置は、
 頭部及びねじ部を有するねじをさらに備え、前記主端子の前記開口部及び前記ねじ穴領域に前記ねじ部を挿入する取付態様で前記金属ブロックの上面上に前記主端子が固定されている、
半導体装置。
(Appendix 3)
3. The semiconductor device according to claim 1,
The main terminal has an opening,
The metal block has a screw hole region extending from an upper surface to a lower surface,
the main terminal mounting area includes the screw hole area,
The semiconductor device includes:
The main terminal is fixed on the upper surface of the metal block in an attachment manner by inserting the screw portion into the opening and the screw hole region of the main terminal, further comprising a screw having a head and a screw portion.
Semiconductor device.

 (付記4)
 付記1から付記3のいずれか1項に記載の半導体装置であって、
 前記基板は絶縁基板を含み、前記絶縁基板は絶縁基材と前記絶縁基材の上面上に設けられる上面導体層と、前記絶縁基材の下面上に設けられる下面導体層とを有し、前記上面導体層の表面が前記基板の第1の主面となり、前記下面導体層の表面が前記基板の第2の主面となり、
 前記金属ブロックの高さ方向における厚みは、前記上面導体層の膜厚より厚い、
半導体装置。
(Appendix 4)
A semiconductor device according to any one of claims 1 to 3,
the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material, a surface of the upper conductor layer being a first main surface of the substrate, and a surface of the lower conductor layer being a second main surface of the substrate,
The thickness of the metal block in the height direction is greater than the thickness of the upper surface conductor layer.
Semiconductor device.

 (付記5)
 付記1から付記4のいずれか1項に記載の半導体装置であって、
 前記基板、前記半導体素子、及び前記金属ブロックを内部に収容する素子収容空間を有する収容空間形成部材をさらに備え、
 前記封止樹脂は前記素子収容空間内に設けられる、
半導体装置。
(Appendix 5)
A semiconductor device according to any one of claims 1 to 4,
a housing space forming member having an element housing space for housing the substrate, the semiconductor element, and the metal block therein;
The sealing resin is provided in the element accommodating space.
Semiconductor device.

 (付記6)
 付記5記載の半導体装置であって、
 前記基板の第2の主面側に設けられる放熱用フィンをさらに備え、
 前記放熱用フィンは前記基板より広い平面形状の載置面を有し、
 前記収容空間形成部材は前記放熱用フィンの前記載置面上に設けられる、
半導体装置。
(Appendix 6)
6. The semiconductor device according to claim 5,
Further comprising a heat dissipation fin provided on the second main surface side of the substrate,
the heat dissipation fin has a planar mounting surface that is wider than the substrate,
the storage space forming member is provided on the mounting surface of the heat dissipation fin,
Semiconductor device.

 (付記7)
 付記6記載の半導体装置であって、
 前記収容空間形成部材はケース収容空間を有するケースを含み、前記素子収容空間は前記ケース収容空間を含む、
半導体装置。
(Appendix 7)
7. The semiconductor device according to claim 6,
the accommodation space forming member includes a case having a case accommodation space, and the element accommodation space includes the case accommodation space;
Semiconductor device.

 (付記8)
 付記7記載の半導体装置であって、
 前記ケースは、前記主端子が前記ケース収容空間から外部に突き抜ける態様で前記主端子と連結された主端子付ケースを含み、
 前記封止樹脂は、前記ケース収容空間内に存在する、前記基板、前記半導体素子、前記金属ブロック及び前記主端子の全てを覆って設けられる、
半導体装置。
(Appendix 8)
8. The semiconductor device according to claim 7,
the case includes a main terminal case connected to the main terminal such that the main terminal protrudes from the case receiving space to the outside,
The sealing resin is provided to cover all of the substrate, the semiconductor element, the metal block, and the main terminals present in the case housing space.
Semiconductor device.

 (付記9)
 付記6記載の半導体装置であって、
 前記収容空間形成部材はダム部を含み、
 前記ダム部で囲われた空間がダム部収容領域となり、前記素子収容空間は前記ダム部収容領域を含み、
 前記ダム部は複数のダム材の積層構造で構成される、
半導体装置。
(Appendix 9)
7. The semiconductor device according to claim 6,
The storage space forming member includes a dam portion,
A space surrounded by the dam portion is a dam portion accommodating region, and the element accommodating space includes the dam portion accommodating region,
The dam portion is composed of a laminated structure of multiple dam materials.
Semiconductor device.

 (付記10)
 付記4記載の半導体装置であって、
 前記絶縁基板の前記上面導体層、前記半導体素子、及び前記金属ブロックを囲んで設けられるダム部をさらに備え、
 前記ダム部は前記絶縁基板の前記絶縁基材上に設けられ、
 前記ダム部で囲われた空間がダム部収容領域となり、
 前記ダム部は複数のダム材の積層構造で構成され、
 前記封止樹脂は前記ダム部の前記ダム部収容領域内に設けられる、
半導体装置。
(Appendix 10)
5. The semiconductor device according to claim 4,
a dam portion provided to surround the upper surface conductor layer of the insulating substrate, the semiconductor element, and the metal block;
the dam portion is provided on the insulating base material of the insulating substrate,
The space surrounded by the dam portion becomes a dam portion accommodation area,
The dam portion is formed of a laminated structure of a plurality of dam materials,
The sealing resin is provided in the dam portion accommodation region of the dam portion.
Semiconductor device.

 (付記11)
 付記10記載の半導体装置であって、
 前記絶縁基板の前記下面導体層の表面上に放熱シートを介して固定される放熱用フィンをさらに備える、
半導体装置。
(Appendix 11)
11. The semiconductor device according to claim 10,
The insulating substrate further includes a heat dissipation fin fixed to the surface of the lower conductor layer via a heat dissipation sheet.
Semiconductor device.

 (付記12)
 外部信号伝達用の主端子を有する半導体装置の製造方法であって、
 (a) 第1及び第2の主面を有する基板を準備するステップと、
 (b) 前記基板の第1の主面上に半導体素子を搭載するステップとを備え、前記基板及び前記半導体素子のうち少なくとも一つがブロック搭載部材となり、
 (c) 前記ブロック搭載部材と金属ブロックとをブロック用接合材を介して接合するステップと、
 (d) 少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って封止樹脂を形成するステップとをさらに備え、前記金属ブロックの上面は前記封止樹脂によって覆われておらず露出状態であり、
 (e) ステップ(d)後に実行され、前記金属ブロックの上面上に前記主端子を取り付けるステップをさらに備える、
半導体装置の製造方法。
(Appendix 12)
A method for manufacturing a semiconductor device having a main terminal for transmitting an external signal, comprising the steps of:
(a) providing a substrate having first and second major surfaces;
(b) mounting a semiconductor element on a first main surface of the substrate, wherein at least one of the substrate and the semiconductor element serves as a block mounting member;
(c) joining the block mounting member and a metal block via a block joining material;
(d) forming a sealing resin to cover at least the block mounting member and the block bonding material, and an upper surface of the metal block is not covered with the sealing resin and is exposed;
(e) performing the step after (d), further comprising the step of attaching the main terminal onto an upper surface of the metal block;
A method for manufacturing a semiconductor device.

 (付記13)
 付記12記載の半導体装置の製造方法であって、
 前記ステップ(d)は、
 (d-1) 前記基板、前記半導体素子、及び前記金属ブロックを囲んで収容空間形成部材を設けるステップと、
 (d-2) 前記収容空間形成部材で囲われた空間である素子収容空間内において、少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記封止樹脂を形成するステップとを含む、
半導体装置の製造方法。
(Appendix 13)
13. A method for manufacturing a semiconductor device according to claim 12, comprising:
The step (d)
(d-1) providing a storage space forming member surrounding the substrate, the semiconductor element, and the metal block;
(d-2) forming the sealing resin to cover at least the block mounting member and the block bonding material within the element accommodating space, which is a space surrounded by the accommodating space forming member;
A method for manufacturing a semiconductor device.

 (付記14)
 付記12記載の半導体装置の製造方法であって、
 前記基板は絶縁基板を含み、前記絶縁基板は絶縁基材と前記絶縁基材の上面上に設けられる上面導体層と、前記絶縁基材の下面上に設けられる下面導体層とを有し、
 前記ステップ(b)は、
 (b-1) 前記絶縁基板の前記上面導体層上に前記半導体素子を搭載するステップを含み、前記上面導体層を有する前記絶縁基板及び前記半導体素子のうち少なくとも一つが前記ブロック搭載部材となり、
 前記ステップ(d)は、
 (d-1) 前記半導体素子及び前記金属ブロックの周囲における前記絶縁基材上に複数のダム材を積層してダム部を設けるステップと、
 (d-2) 前記ダム部で囲われた空間であるダム部収容領域内において、少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記封止樹脂を形成するステップとを含み、
 前記半導体装置の製造方法は、
 (f) 前記下面導体層と放熱用フィンとを放熱シートを介して接合するステップをさらに備える、
半導体装置の製造方法。
(Appendix 14)
13. A method for manufacturing a semiconductor device according to claim 12, comprising:
the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material;
The step (b)
(b-1) a step of mounting the semiconductor element on the upper surface conductor layer of the insulating substrate, at least one of the insulating substrate having the upper surface conductor layer and the semiconductor element becomes the block mounting member;
The step (d)
(d-1) stacking a plurality of dam materials on the insulating base material around the semiconductor element and the metal block to provide a dam portion;
(d-2) forming the sealing resin in a dam portion accommodation area, which is a space surrounded by the dam portion, to cover at least the block mounting member and the block bonding material;
The method for manufacturing a semiconductor device includes:
(f) further comprising a step of joining the lower conductor layer and a heat dissipation fin via a heat dissipation sheet;
A method for manufacturing a semiconductor device.

 (付記15)
 付記1から付記11のいずれか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
 前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備えた、
電力変換装置。
(Appendix 15)
A main conversion circuit having the semiconductor device according to any one of claims 1 to 11, which converts input power and outputs the converted power;
a control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit,
Power conversion equipment.

 1,1B,1C,2,2B,3 パワーモジュール、5 ケース、5T 主端子付ケース、7,7B,72 封止樹脂、8,9 ダム部、10,10B,10C セラミック基板、11,11B,11C 窒化ケイ素基材、12 上面導体層、13 下面導体層、15,15B フィンベース、20 半導体素子、41~43 ワイヤ、51 端子台、60,66 金属ブロック、61 ねじ、62,67 主端子、63 信号端子、64 ピン端子、81 ダム材、1000 電源、2000 電力変換装置、2001 主変換回路、2002 半導体モジュール、2003 制御回路、3000 負荷。 1, 1B, 1C, 2, 2B, 3 Power module, 5 Case, 5T Case with main terminal, 7, 7B, 72 Sealing resin, 8, 9 Dam section, 10, 10B, 10C Ceramic substrate, 11, 11B, 11C Silicon nitride substrate, 12 Upper conductor layer, 13 Lower conductor layer, 15, 15B Fin base, 20 Semiconductor element, 41-43 Wire, 51 Terminal block, 60, 66 Metal block, 61 Screw, 62, 67 Main terminal, 63 Signal terminal, 64 Pin terminal, 81 Dam material, 1000 Power source, 2000 Power conversion device, 2001 Main conversion circuit, 2002 Semiconductor module, 2003 Control circuit, 3000 Load.

Claims (16)

 外部信号伝達用の主端子を有する半導体装置であって、
 第1及び第2の主面を有する基板と、
 前記基板の第1の主面上に設けられる半導体素子と、
 前記基板及び前記半導体素子のうち少なくとも一つであるブロック搭載部材上に設けられる金属ブロックと、
 前記ブロック搭載部材と前記金属ブロックとはブロック用接合材を介して接合されており、
 前記金属ブロックは主端子取付領域を有し、前記主端子は前記主端子取付領域にて前記金属ブロックに固定され、
 前記半導体装置は、
 少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記基板の第1の主面上に設けられる封止樹脂をさらに備える、
半導体装置。
A semiconductor device having a main terminal for transmitting an external signal,
a substrate having first and second major surfaces;
A semiconductor element provided on a first main surface of the substrate;
a metal block provided on a block mounting member which is at least one of the substrate and the semiconductor element;
The block mounting member and the metal block are joined via a block joining material,
the metal block has a main terminal attachment region, the main terminal is fixed to the metal block at the main terminal attachment region,
The semiconductor device includes:
The block mounting member and the block bonding material are covered with a sealing resin provided on the first main surface of the substrate.
Semiconductor device.
 請求項1記載の半導体装置であって、
 前記主端子取付領域は前記金属ブロックの上面を含み、前記金属ブロックの上面上に前記主端子は固定されており、
 前記金属ブロックの上面は前記封止樹脂によって覆われておらず露出状態である、
半導体装置。
2. The semiconductor device according to claim 1,
the main terminal attachment region includes an upper surface of the metal block, and the main terminal is fixed onto the upper surface of the metal block;
The upper surface of the metal block is not covered with the sealing resin and is exposed.
Semiconductor device.
 請求項2記載の半導体装置であって、
 前記主端子は開口部を有し、
 前記金属ブロックは上面から下面に向けて設けられるねじ穴領域を有し、
 前記主端子取付領域は前記ねじ穴領域を含み、
 前記半導体装置は、
 頭部及びねじ部を有するねじをさらに備え、前記主端子の前記開口部及び前記ねじ穴領域に前記ねじ部を挿入する取付態様で前記金属ブロックの上面上に前記主端子が固定されている、
半導体装置。
3. The semiconductor device according to claim 2,
The main terminal has an opening,
The metal block has a screw hole region extending from an upper surface to a lower surface,
the main terminal mounting area includes the screw hole area,
The semiconductor device includes:
The main terminal is fixed on the upper surface of the metal block in an attachment manner by inserting the screw portion into the opening and the screw hole region of the main terminal, further comprising a screw having a head and a screw portion.
Semiconductor device.
 請求項3記載の半導体装置であって、
 前記金属ブロックの側面の上方の一部は前記封止樹脂によって覆われておらず露出状態であり、
 露出状態の前記金属ブロックの側面は、対向する一対の露出側面を含む、
半導体装置。
4. The semiconductor device according to claim 3,
an upper part of a side surface of the metal block is not covered with the sealing resin and is exposed;
The exposed side surface of the metal block includes a pair of opposing exposed side surfaces.
Semiconductor device.
 請求項1から請求項4のいずれか1項に記載の半導体装置であって、
 前記基板は絶縁基板を含み、前記絶縁基板は絶縁基材と前記絶縁基材の上面上に設けられる上面導体層と、前記絶縁基材の下面上に設けられる下面導体層とを有し、前記上面導体層の表面が前記基板の第1の主面となり、前記下面導体層の表面が前記基板の第2の主面となり、
 前記金属ブロックの高さ方向における厚みは、前記上面導体層の膜厚より厚い、
半導体装置。
5. The semiconductor device according to claim 1,
the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material, a surface of the upper conductor layer being a first main surface of the substrate, and a surface of the lower conductor layer being a second main surface of the substrate,
The thickness of the metal block in the height direction is greater than the thickness of the upper surface conductor layer.
Semiconductor device.
 請求項1から請求項5のいずれか1項に記載の半導体装置であって、
 前記基板、前記半導体素子、及び前記金属ブロックを内部に収容する素子収容空間を有する収容空間形成部材をさらに備え、
 前記封止樹脂は前記素子収容空間内に設けられる、
半導体装置。
6. The semiconductor device according to claim 1,
a housing space forming member having an element housing space for housing the substrate, the semiconductor element, and the metal block therein;
The sealing resin is provided in the element accommodating space.
Semiconductor device.
 請求項6記載の半導体装置であって、
 前記基板の第2の主面側に設けられる放熱用フィンをさらに備え、
 前記放熱用フィンは前記基板より広い平面形状の載置面を有し、
 前記収容空間形成部材は前記放熱用フィンの前記載置面上に設けられる、
半導体装置。
7. The semiconductor device according to claim 6,
Further, a heat dissipation fin is provided on the second main surface side of the substrate,
the heat dissipation fin has a planar mounting surface that is wider than the substrate,
the storage space forming member is provided on the mounting surface of the heat dissipation fin,
Semiconductor device.
 請求項7記載の半導体装置であって、
 前記収容空間形成部材はケース収容空間を有するケースを含み、前記素子収容空間は前記ケース収容空間を含む、
半導体装置。
8. The semiconductor device according to claim 7,
the accommodation space forming member includes a case having a case accommodation space, and the element accommodation space includes the case accommodation space;
Semiconductor device.
 請求項8記載の半導体装置であって、
 前記ケースは、前記主端子が前記ケース収容空間から外部に突き抜ける態様で前記主端子と連結された主端子付ケースを含み、
 前記封止樹脂は、前記ケース収容空間内に存在する、前記基板、前記半導体素子、前記金属ブロック及び前記主端子の全てを覆って設けられる、
半導体装置。
9. The semiconductor device according to claim 8,
the case includes a main terminal case connected to the main terminal such that the main terminal protrudes from the case receiving space to the outside,
The sealing resin is provided to cover all of the substrate, the semiconductor element, the metal block, and the main terminals present in the case housing space.
Semiconductor device.
 請求項7記載の半導体装置であって、
 前記収容空間形成部材はダム部を含み、
 前記ダム部で囲われた空間がダム部収容領域となり、前記素子収容空間は前記ダム部収容領域を含み、
 前記ダム部は複数のダム材の積層構造で構成される、
半導体装置。
8. The semiconductor device according to claim 7,
The storage space forming member includes a dam portion,
A space surrounded by the dam portion is a dam portion accommodating region, and the element accommodating space includes the dam portion accommodating region,
The dam portion is composed of a laminated structure of multiple dam materials.
Semiconductor device.
 請求項5記載の半導体装置であって、
 前記絶縁基板の前記上面導体層、前記半導体素子、及び前記金属ブロックを囲んで設けられるダム部をさらに備え、
 前記ダム部は前記絶縁基板の前記絶縁基材上に設けられ、
 前記ダム部で囲われた空間がダム部収容領域となり、
 前記ダム部は複数のダム材の積層構造で構成され、
 前記封止樹脂は前記ダム部の前記ダム部収容領域内に設けられる、
半導体装置。
6. The semiconductor device according to claim 5,
a dam portion provided to surround the upper surface conductor layer of the insulating substrate, the semiconductor element, and the metal block;
the dam portion is provided on the insulating base material of the insulating substrate,
The space surrounded by the dam portion becomes a dam portion accommodation area,
The dam portion is formed of a laminated structure of a plurality of dam materials,
The sealing resin is provided in the dam portion accommodation region of the dam portion.
Semiconductor device.
 請求項11記載の半導体装置であって、
 前記絶縁基板の前記下面導体層の表面上に放熱シートを介して固定される放熱用フィンをさらに備える、
半導体装置。
12. The semiconductor device according to claim 11,
The insulating substrate further includes a heat dissipation fin fixed to the surface of the lower conductor layer via a heat dissipation sheet.
Semiconductor device.
 外部信号伝達用の主端子を有する半導体装置の製造方法であって、
 (a) 第1及び第2の主面を有する基板を準備するステップと、
 (b) 前記基板の第1の主面上に半導体素子を搭載するステップとを備え、前記基板及び前記半導体素子のうち少なくとも一つがブロック搭載部材となり、
 (c) 前記ブロック搭載部材と金属ブロックとをブロック用接合材を介して接合するステップと、
 (d) 少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って封止樹脂を形成するステップとをさらに備え、前記金属ブロックの上面及び側面の上方の一部は前記封止樹脂によって覆われておらず露出状態であり、露出状態の前記金属ブロックの側面は、対向する一対の露出側面を含み、
 (e) ステップ(d)後に実行され、前記金属ブロックの上面上に前記主端子を取り付けるステップをさらに備える、
半導体装置の製造方法。
A method for manufacturing a semiconductor device having a main terminal for transmitting an external signal, comprising the steps of:
(a) providing a substrate having first and second major surfaces;
(b) mounting a semiconductor element on a first main surface of the substrate, wherein at least one of the substrate and the semiconductor element serves as a block mounting member;
(c) joining the block mounting member and a metal block via a block joining material;
(d) forming a sealing resin to cover at least the block mounting member and the block bonding material, wherein an upper surface and an upper portion of a side surface of the metal block are not covered with the sealing resin and are exposed, and the exposed side surfaces of the metal block include a pair of opposing exposed side surfaces;
(e) performing the step after (d), further comprising the step of attaching the main terminal onto an upper surface of the metal block;
A method for manufacturing a semiconductor device.
 請求項13記載の半導体装置の製造方法であって、
 前記ステップ(d)は、
 (d-1) 前記基板、前記半導体素子、及び前記金属ブロックを囲んで収容空間形成部材を設けるステップと、
 (d-2) 前記収容空間形成部材で囲われた空間である素子収容空間内において、少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記封止樹脂を形成するステップとを含む、
半導体装置の製造方法。
14. The method of manufacturing a semiconductor device according to claim 13,
The step (d)
(d-1) providing a storage space forming member surrounding the substrate, the semiconductor element, and the metal block;
(d-2) forming the sealing resin to cover at least the block mounting member and the block bonding material within the element accommodating space, which is a space surrounded by the accommodating space forming member;
A method for manufacturing a semiconductor device.
 請求項13記載の半導体装置の製造方法であって、
 前記基板は絶縁基板を含み、前記絶縁基板は絶縁基材と前記絶縁基材の上面上に設けられる上面導体層と、前記絶縁基材の下面上に設けられる下面導体層とを有し、
 前記ステップ(b)は、
 (b-1) 前記絶縁基板の前記上面導体層上に前記半導体素子を搭載するステップを含み、前記上面導体層を有する前記絶縁基板及び前記半導体素子のうち少なくとも一つが前記ブロック搭載部材となり、
 前記ステップ(d)は、
 (d-1) 前記半導体素子及び前記金属ブロックの周囲における前記絶縁基材上に複数のダム材を積層してダム部を設けるステップと、
 (d-2) 前記ダム部で囲われた空間であるダム部収容領域内において、少なくとも前記ブロック搭載部材及び前記ブロック用接合材を覆って前記封止樹脂を形成するステップとを含み、
 前記半導体装置の製造方法は、
 (f) 前記下面導体層と放熱用フィンとを放熱シートを介して接合するステップをさらに備える、
半導体装置の製造方法。
14. The method of manufacturing a semiconductor device according to claim 13,
the substrate includes an insulating substrate, the insulating substrate having an insulating base material, an upper conductor layer provided on an upper surface of the insulating base material, and a lower conductor layer provided on a lower surface of the insulating base material;
The step (b)
(b-1) a step of mounting the semiconductor element on the upper surface conductor layer of the insulating substrate, at least one of the insulating substrate having the upper surface conductor layer and the semiconductor element becomes the block mounting member;
The step (d)
(d-1) stacking a plurality of dam materials on the insulating base material around the semiconductor element and the metal block to provide a dam portion;
(d-2) forming the sealing resin in a dam portion accommodation area, which is a space surrounded by the dam portion, to cover at least the block mounting member and the block bonding material;
The method for manufacturing a semiconductor device includes:
(f) further comprising a step of joining the lower conductor layer and a heat dissipation fin via a heat dissipation sheet;
A method for manufacturing a semiconductor device.
 請求項1から請求項12のいずれか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
 前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備えた、
電力変換装置。
A main conversion circuit having the semiconductor device according to any one of claims 1 to 12, which converts input power and outputs the converted power;
a control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit,
Power conversion equipment.
PCT/JP2024/034081 2023-10-18 2024-09-25 Semiconductor device, production method for same, and power conversion device Pending WO2025084080A1 (en)

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