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WO2025075834A1 - Selective removal of redeposited carbon masks during etch - Google Patents

Selective removal of redeposited carbon masks during etch Download PDF

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Publication number
WO2025075834A1
WO2025075834A1 PCT/US2024/048238 US2024048238W WO2025075834A1 WO 2025075834 A1 WO2025075834 A1 WO 2025075834A1 US 2024048238 W US2024048238 W US 2024048238W WO 2025075834 A1 WO2025075834 A1 WO 2025075834A1
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Prior art keywords
mask
stack
plasma
power
sputter deposition
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PCT/US2024/048238
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French (fr)
Inventor
Mingmei Wang
Yongjia Li
Qing Xu
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Lam Research Corp
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Lam Research Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching

Definitions

  • an apparatus for etching recessed features in a stack below a carbon is provided.
  • a substrate support for supports a substrate inside a processing chamber.
  • An RF power source for provides RF power in the processing chamber.
  • a gas source comprises an oxygen containing component source and an etch gas source.
  • a controller is controllably connected to the RF power source and the gas source, configured to at least partially etch the stack, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition, remove at least some of the mask sputter deposition, comprising providing a removing gas comprising an oxygen containing component, and transforming the removing gas into a plasma, comprising providing a multistate pulsed RF power with two or three states, and exposes the mask sputter deposition to the plasma, and further etch the stack.
  • FIGS. 2A-2D illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.
  • the features etched into a stack may be cylinders, trenches, or other recessed features.
  • the aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.
  • Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.
  • an amorphous carbon layer (ACL) mask can be easily sputtered due to the high ion energies suitable for a high aspect ratio contact (HARC) etch.
  • the sputtered carbon particles are un-saturated and quite sticky so that the sputtered carbon particles deposit back to the side of the mask when features are small or deposit back to the lower comer of wide masks.
  • the deposition of sputtered carbon mask on lower corners of wide masks forms local masking when the etch time is long enough, causing partially or completely missing holes. When the holes are not fully covered by this local mask, ‘skeletons’ often form due to non-equal carbon redeposition on spaces versus on holes.
  • FIG. 1 is a high level flow chart of a method that may be used in some embodiments.
  • a stack with a carbon containing mask is provided in a process chamber (step 104).
  • FIG. 2 A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a patterned carbon containing mask 216, such as an organic mask, one example of which would be an amorphous carbon mask.
  • the amorphous carbon mask may also include some amount of hydrogen and/or oxygen.
  • the patterned carbon containing mask 216 has mask features.
  • the stack 204 may be formed over a substrate 208.
  • the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon.
  • the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide.
  • the stack 204 may comprise a germanium containing layer.
  • the stack is a single bulk layer.
  • the stack is a plurality of layers.
  • the stack is a plurality of bilayers, trilayers, or more multiple layers.
  • the stack 204 comprises a plurality of bilayers 212, where each bilayer 212 includes a layer of silicon oxide 224 and a layer of silicon nitride 228.
  • the applied RF power is a continuous RF power.
  • the applied RF power may be pulsed.
  • the pulsed RF may have two or three states, providing multistate pulsed RF power.
  • the high power level has a 1% to 20% duty cycle
  • the medium power level has a 10% to 90% duty cycle
  • the low power level has a 20% to 90% duty cycle.
  • the low power level is 0 Watts.
  • the high power level is 2 to 20 times the low power levels and the medium power level is between the high power level and the low power level.
  • the RF power is pulsed at repetition rates of 1-50,000 Hz.
  • the RF power may be pulsed between two non-zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states).
  • the powers may be a higher power state and a lower power state.
  • the lower power state may correspond to an RF power of about 4 kW or lower.
  • a pulsing duty cycle may be in the range of 1-50%.
  • the pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz.
  • the applied RF power is a continuous RF power.
  • the applied RF power may be pulsed.
  • the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels.
  • FIG. 2C is a schematic cross-sectional view of a stack 204 after the mask sputter deposition 244 (shown in FIG. 2B) has been removed.
  • the mask sputter deposition 244 can be selectively oxidized due to the loose, porous, and unsaturated nature of the mask sputter deposition 244 with minimal removal of the remaining mask 216.
  • mask sputter deposition 244 is only removed from the mask 216 and not sidewalls or the etch front of features of the stack 204.
  • mask sputter deposition 244 is only removed from sidewalls near the top of the mask 216 and on top of the mask 216.
  • a low energy oxygen containing plasma is provided to selectively remove the mask sputter deposition 244 with minimal removal of the mask 216.
  • a bias of absolute value of less than 100 electron volts is provided to minimize the energy at which ions from the plasma interact with the mask sputter deposition 244.
  • a remote plasma is used to provide the low energy oxygen containing plasma.
  • the removal of the mask deposition 214 is selective to the removal of the mask 216 with a selectivity in the range of greater than 20:1 by volume. In some embodiments, the removal of the mask deposition 214 is selective to the removal of the mask 216 with a selectivity of greater than 100:1
  • the flow of inert gas is maintained or started while the flow of the oxygen containing component of the removing gas is stopped.
  • RF power is provided to form the inert gas into a low energy plasma.
  • the low energy plasma has ion energies in the range of 0-100 eV.
  • higher frequency power RF sources such as 60 MHz RF sources, provide 10 W to 1 kW of power
  • lower frequency bias RF sources such as 400 kHz RF sources, provide 0-500 W of power.
  • the ion energy from the inert gases during this step is higher than the ion energy provided when the oxygen containing component is provided.
  • the ion energy provided when the oxygen containing component is provided is kept lower so that the plasma from the oxygen containing component does not remove the mask.
  • the plasma from the inert gas may have a higher ion energy without removing the mask.
  • the cycle of providing a lower ion energy plasma from the oxygen containing component and providing a slightly higher ion energy plasma from the inert gas may be repeated for one or more cycles.
  • the further etch of the stack uses a different than the partial etch of the stack (step 106), since the further etch of the stack (step 112) etches at a different depth than the partial etch of the stack (step 106) and/or the further etch of the stack (step 112) may etch a different material than the partial etch of the stack (step 106).
  • Some embodiments provide a separate removal step of the mask sputter deposition 244 to widen the process window to enable next generation device scaling.
  • Some embodiments utilize the strong oxidation capability of ozone to selectively oxidize the loose, porous, and unsaturated mask sputter deposition 244 materials so that they can be easily removed by a low energy plasma formed from the ozone. The selective oxidation ensures that the impacts on the ACL masks 216 are minimal. Besides the controlling flow and pressure of ozone and the plasma energy, an optimized selectivity between mask sputter deposition 244 and the mask 216 can be achieved.
  • Some embodiments largely widen the current process window without triggering other tradeoffs by adding a separate selective mask sputter deposition 244 removal step by utilizing strong oxidizer ozone gas that can only impact redeposited carbon containing materials. Solving the mask sputter deposition 244 problem brings in better device performance and extends the process capabilities of further scaling of devices.
  • the material into which the feature is etched may have a repeating layered structure.
  • the material may include alternating layers of silicon oxide and silicon nitride.
  • the stack may comprise alternating layers of silicon oxide and polysilicon.
  • the alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers).
  • the feature etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm.
  • the feature may have a width between about 40-450 nm, for example between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm.
  • high aspect ratio as applied to features in a substrate refers to a depth to width aspect ratio on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100:1, 120:1, 140: 1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30: 1, or 10:1.
  • Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
  • an ashable hard mask layer such as an amorphous carbon layer
  • another suitable hard mask such as
  • semiconductor wafer semiconductor wafer
  • wafer semiconductor wafer
  • substrate substrate
  • wafer substrate semiconductor substrate
  • partially fabricated integrated circuit can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon.
  • a wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm.
  • the above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited.
  • the workpiece may be of various shapes, sizes, and materials.
  • other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.
  • non-transient computer readable medium is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals.
  • Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

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Abstract

A method of etching recessed features in a stack below a patterned carbon containing mask forming mask features is provided. The stack is partially etched, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition. At least some of the mask sputter deposition is removed, comprising providing a removing gas comprising an oxygen containing component, transforming the removing gas into a plasma, and removing some of the mask sputter deposition with the plasma. The stack is further etched.

Description

SELECTIVE REMOVAL OF REDEPOSITED CARBON MASKS DURING ETCH
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of priority of U.S. Application No. 63/588,597, filed October 6, 2023, which is incorporated herein by reference for all purposes.
BACKGROUND
[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a carbon containing mask. The stack may be alternating/repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and “not and” devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and/or deep depths.
[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
SUMMARY
[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a stack below a patterned carbon containing mask forming mask features is provided. The stack is partially etched, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition. At least some of the mask sputter deposition is removed, comprising providing a removing gas comprising an oxygen containing component, transforming the removing gas into a plasma, and removing some of the mask sputter deposition with the plasma. The stack is further etched.
[0005] In another manifestation, a method of etching recessed features in a stack below a patterned carbon containing mask forming mask features is provided. The stack is partially etched, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition. At least some of the mask sputter deposition is removed, comprising providing a removing gas comprising an oxygen containing component, transforming the removing gas into a plasma, comprising providing a multistate pulsed RF power with two or three states, and exposing the mask sputter deposition to the plasma. The stack is further etched.
[0006] In another manifestation, an apparatus for etching recessed features in a stack below a carbon is provided. A substrate support for supports a substrate inside a processing chamber. An RF power source for provides RF power in the processing chamber. A gas source comprises an oxygen containing component source and an etch gas source. A controller is controllably connected to the RF power source and the gas source, configured to at least partially etch the stack, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition, remove at least some of the mask sputter deposition, comprising providing a removing gas comprising an oxygen containing component, and transforming the removing gas into a plasma, comprising providing a multistate pulsed RF power with two or three states, and exposes the mask sputter deposition to the plasma, and further etch the stack.
[0007] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
[0009] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a carbon containing mask according to various embodiments.
[0010] FIGS. 2A-2D illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.
[0011] FIG. 3 shows a semiconductor processing system that may be used in some embodiments.
[0012] FIG. 4 illustrates a computer system for implementing a controller used in some embodiments.
[0013] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale. DETAILED DESCRIPTION
[0014] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.
[0015] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxycarbide, poly silicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), or single silicon oxide layer, or single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer below a carbon containing mask. In some embodiments, the carbon containing mask is a carbon containing at least one of a photoresist, a doped carbon, and an amorphous carbon mask.
[0016] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.
[0017] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the carbon containing mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.
[0018] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.
[0019] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.
[0020] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.
[0021] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.
[0022] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.
[0023] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.
[0024] During NAND etch, an amorphous carbon layer (ACL) mask can be easily sputtered due to the high ion energies suitable for a high aspect ratio contact (HARC) etch. The sputtered carbon particles are un-saturated and quite sticky so that the sputtered carbon particles deposit back to the side of the mask when features are small or deposit back to the lower comer of wide masks. The deposition of sputtered carbon mask on lower corners of wide masks forms local masking when the etch time is long enough, causing partially or completely missing holes. When the holes are not fully covered by this local mask, ‘skeletons’ often form due to non-equal carbon redeposition on spaces versus on holes. These ‘skeletons’ cause a lot of process difficulties such as nonuniformity of edge holes, asymmetric mask shadowing, partial or complete missing holes, etc. [0025] The techniques described herein may be used to etch recessed features into a stack below a carbon containing mask without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a carbon containing mask with a high stack to carbon containing mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, with reduced non-uniformity, reduced asymmetric mask shadowing, and sufficient etch rate.
[0026] Current NAND ONON etch processes cannot fully resolve the loading issue caused by dense and isolated patterns. Wide masks usually have higher etch selectivity than narrow masks on dense arrays. The mask height difference between these two facilitates the formation of redeposited mask material at the lower comer of the wide mask due to mask top faceting and ion shadowing. The only way to avoid ‘skeleton’ formation is to reduce the delta between wide mask height and dense array mask height by adding either CxHyFz polymer or ammonium salt protection. Due to the loading issue, the process margin is small, especially when dealing with other tradeoffs such as etch rate, twisting, tapering, etc.
[0027] Some embodiments provide a method to selectively remove redeposited carbon particles sputtered from the masks. By flowing an oxygen containing component gas under a certain pressure and flow rate and forming the oxygen containing component gas into a plasma, the redeposited carbon material (particularly ‘skeletons’) can be selectively oxidized due to the loose, porous, and un-saturated nature of the redeposited carbon material.
Partial etch
[0028] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A stack with a carbon containing mask is provided in a process chamber (step 104). FIG. 2 A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a patterned carbon containing mask 216, such as an organic mask, one example of which would be an amorphous carbon mask. The amorphous carbon mask may also include some amount of hydrogen and/or oxygen. The patterned carbon containing mask 216 has mask features. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide. In some embodiments, the stack 204 may comprise a germanium containing layer. In some embodiments, the stack is a single bulk layer. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, the stack 204 comprises a plurality of bilayers 212, where each bilayer 212 includes a layer of silicon oxide 224 and a layer of silicon nitride 228.
[0029] The stack is partially etched (step 106). In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber.
[0030] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and/or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three- frequency RF power may be used to generate the plasma.
[0031] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non-zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-10 kilovolts (kV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. [0032] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 1 kW is provided.
[0033] The stack 204 is exposed to the plasma causing recessed features to be partially etched into the stack 204. FIG. 2B is a schematic cross-sectional view of a stack 204 after the recessed features 240 have been partially etched. Mask sputter deposition 244 deposits on sidewalls of features. In some embodiments, the mask sputter deposition 244 forms necks. In some embodiments, where there are regions with wider and thicker masks 242 in a bulk mask region, sputter from the wider and thicker masks are redeposit on thinner mask regions (contact regions) forming mask sputter deposition 244 that fills in comers between the wider and thick masks and the thinner masks and partially fills in features 240. In some embodiments, if the mask sputter deposition 244 on the sidewalls of features 240 is not removed the mask sputter deposition 244 on the sidewalls of features 240 would cause the features 240 to become tapered. In some embodiments, if the mask sputter deposition 244 is not removed the mask sputter deposition 244 would cause non-uniformity of etch features, asymmetric mask shadowing, and partially or completely missing holes. In some embodiments, since the features are so deep with a high aspect ratio, no or very little mask sputter deposition 244 deposits on the etch front or on the sidewalls of the features of the stack. Instead, the mask sputter deposition 244 deposits mostly or entirely on the sidewalls of the mask near the top of the mask or on top of the mask.
Deposition Removal
[0034] The mask sputter deposition 244 is removed (step 108). In some embodiments, a removing gas comprising an oxygen containing component is provided. In some embodiments, the oxygen containing component comprises at least one of an oxygen gas (O2), ozone (O3), hydrogen peroxide, such as hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), sulfur dioxide (SO2), sulfur trioxide (SO3), carbonyl sulfide (COS), oxygen difluoride (OF2), nitrous oxide (N2O), and nitric oxide (NO). In some embodiments, the oxygen containing component comprises oxygen gas. In some embodiments, the oxygen containing component comprises ozone. In some embodiments, the oxygen containing component comprises oxygen and 5% to 95% ozone by number of molecules. In some embodiments, the removing gas may further comprise an inert gas nitrogen gas (N2), helium (He), xenon (Xe), neon (Ne), and argon (Ar). In some embodiments, the removing gas does not have an inert gas. In some embodiments, the removing gas is transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the removing gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the etch gas is provided at a pressure of 1 millitorr to 10 torr.
[0035] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 10 Watts (W) to 1 kilowatt (kW). In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 0-500 W, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 10 W to 1 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and/or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three-frequency RF power may be used to generate the plasma. [0036] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively low, for example between about 0-100 electron volts (eV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. [0037] In some embodiments, a bias in the range of 0 Watts (W) to 1 kilowatt (kW) is provided to accelerate ions toward the top surfaces of stack 204.
[0038] The stack 204 is exposed to the plasma formed from the removing gas causing the removal of the mask sputter deposition 244. FIG. 2C is a schematic cross-sectional view of a stack 204 after the mask sputter deposition 244 (shown in FIG. 2B) has been removed. In some embodiments, the mask sputter deposition 244 can be selectively oxidized due to the loose, porous, and unsaturated nature of the mask sputter deposition 244 with minimal removal of the remaining mask 216. In some embodiment, mask sputter deposition 244 is only removed from the mask 216 and not sidewalls or the etch front of features of the stack 204. In some embodiments, mask sputter deposition 244 is only removed from sidewalls near the top of the mask 216 and on top of the mask 216.
[0039] In some embodiments, a low energy oxygen containing plasma is provided to selectively remove the mask sputter deposition 244 with minimal removal of the mask 216. In some embodiments, a bias of absolute value of less than 100 electron volts is provided to minimize the energy at which ions from the plasma interact with the mask sputter deposition 244. In some embodiments, a remote plasma is used to provide the low energy oxygen containing plasma. In some embodiments, the removal of the mask deposition 214 is selective to the removal of the mask 216 with a selectivity in the range of greater than 20:1 by volume. In some embodiments, the removal of the mask deposition 214 is selective to the removal of the mask 216 with a selectivity of greater than 100:1
[0040] In some embodiments, the flow of inert gas is maintained or started while the flow of the oxygen containing component of the removing gas is stopped. RF power is provided to form the inert gas into a low energy plasma. In some embodiments, the low energy plasma has ion energies in the range of 0-100 eV. In some embodiments, higher frequency power RF sources, such as 60 MHz RF sources, provide 10 W to 1 kW of power, and lower frequency bias RF sources, such as 400 kHz RF sources, provide 0-500 W of power. In some embodiments, the ion energy from the inert gases during this step is higher than the ion energy provided when the oxygen containing component is provided. In such embodiments, the ion energy provided when the oxygen containing component is provided is kept lower so that the plasma from the oxygen containing component does not remove the mask. The plasma from the inert gas may have a higher ion energy without removing the mask. In some embodiments, the cycle of providing a lower ion energy plasma from the oxygen containing component and providing a slightly higher ion energy plasma from the inert gas may be repeated for one or more cycles.
[0041] The stack is further etched (step 112). In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the further etch of the stack (step 112) uses the same recipe as the partial etch of the stack 106. In some embodiments, the further etch of the stack (step 112) uses a different than the partial etch of the stack (step 106), since the further etch of the stack (step 112) etches at a different depth than the partial etch of the stack (step 106) and/or the further etch of the stack (step 112) may etch a different material than the partial etch of the stack (step 106).
[0042] The further etch of the stack (step 106) may cause mask sputter deposition. If additional etching is desired (step 116), the steps of removing mask sputter deposition (step 108) and further etching the stack (step 112) may be repeated one or more times until the desired etch is completed. Additional optional processes may be performed. For example, the remaining mask 216 may be removed. The stack is removed from the process chamber (step 120).
[0043] Some embodiments provide a separate removal step of the mask sputter deposition 244 to widen the process window to enable next generation device scaling. Some embodiments utilize the strong oxidation capability of ozone to selectively oxidize the loose, porous, and unsaturated mask sputter deposition 244 materials so that they can be easily removed by a low energy plasma formed from the ozone. The selective oxidation ensures that the impacts on the ACL masks 216 are minimal. Besides the controlling flow and pressure of ozone and the plasma energy, an optimized selectivity between mask sputter deposition 244 and the mask 216 can be achieved.
[0044] In some embodiments, the partial etch (step 106), the removal step (step 108), and the further etch (step 112) are performed in-situ in the same chamber mounted on the same substrate support. The ability to perform the process in-situ allows for faster throughput, less contamination, and a wider process window.
[0045] Some embodiments largely widen the current process window without triggering other tradeoffs by adding a separate selective mask sputter deposition 244 removal step by utilizing strong oxidizer ozone gas that can only impact redeposited carbon containing materials. Solving the mask sputter deposition 244 problem brings in better device performance and extends the process capabilities of further scaling of devices.
[0046] One application for the disclosed methods is in the context of forming a vertical NAND. In this case, the material into which the feature is etched may have a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers). The feature etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm. The feature may have a width between about 40-450 nm, for example between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm.
[0047] As used herein, “high aspect ratio” as applied to features in a substrate refers to a depth to width aspect ratio on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100:1, 120:1, 140: 1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30: 1, or 10:1.
[0048] The dimensional/parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions/parameters may also be applicable or used.
APPARATUS
[0049] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility.
[0050] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.
[0051] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.
[0052] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value. [0053] FIG. 3 is a schematic view of an etch reactor system 300 that may be used in some embodiments. In some embodiments, an etch reactor system 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308, within an etch (or process) chamber 309, enclosed by a chamber wall 352. Within the etch chamber 309, a stack 204 is positioned over the ESC 308 that is used as a substrate support. A bias may be provided to the ESC 308 from an ESC source 348. A gas source 310 is connected to the etch chamber 309 through the gas distribution plate 306. In some embodiments, the gas source 310 comprises an etch gas source 312, an oxygen component source 316, and other gas sources 318. An ESC temperature controller 350 is connected to the ESC 308. A radio frequency (RF) source 330 provides RF power to a lower electrode and/or an upper electrode, which in this embodiment are the ESC 308 and the gas distribution plate 306, respectively. The RF power may be provided in a sinusoidal waveform or in other tailored waveforms. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz, 27 MHz power sources make up the RF source 330 and the ESC source 348. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate RF sources or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller 335 is controllably connected to the RF source 330, the ESC source 348, an exhaust pump 320, and the gas source 310. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.
[0054] FIG. 4 is a high level block diagram showing a computer system 400, which is suitable for implementing the controller 335 used in embodiments. The computer system 400 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 400 includes one or more processors 402 and further can include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disk drive), user interface devices 412 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 414 (e.g., wireless network interface). The communications interface 414 allows software and data to be transferred between the computer system 400 and external devices via a link. The system may also include a communications infrastructure 416 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules are connected.
[0055] Information transferred via communications interface 414 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 414, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communications channels. With such a communications interface 414, it is contemplated that the one or more processors 402 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.
[0056] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor. [0057] It is to be understood that the configurations and/or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.
CONCLUSION
[0058] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMS What is claimed is:
1. A method of etching recessed features in a stack below a patterned carbon containing mask forming mask features, comprising: a. at least partially etching the stack, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition; b. removing at least some of the mask sputter deposition, comprising i. providing a removing gas comprising an oxygen containing component; ii. transforming the removing gas into a plasma; and iii. removing some of the mask sputter deposition with the plasma; and c. further etching the stack.
2. The method of claim 1, further comprising repeating steps b and c at least once.
3. The method of claim 1, wherein the oxygen containing component comprises at least one of an oxygen gas, ozone, peroxide, carbon monoxide, carbon dioxide, sulfur dioxide, sulfur trioxide, carbonyl sulfide, oxygen difluoride, nitrous oxide, and nitric oxide.
4. The method of claim 1 , wherein the oxygen containing component comprises ozone.
5. The method of claim 1, wherein the patterned carbon containing mask comprises amorphous carbon.
6. The method of claim 1 , wherein the transforming the removing gas comprises providing an RF power, wherein the providing the RF power comprises providing at least one of providing continuous RF power and providing multistate pulsed RF power.
7. The method of claim 1, wherein the transforming the removing gas comprises providing a multistate pulsed RF power with two or three states.
8. The method of claim 1 wherein the mask sputter deposition forms necks in the mask features.
9. The method of claim 1 , wherein the patterned carbon containing mask forms bulk mask regions and contact regions.
10. The method, as recited in claim 1, wherein the transforming the removing gas comprises providing a pulsed RF power with a duty cycle in a range of 1% to 50%.
11. The method, as recited in claim 1 , wherein the removing some of the mask sputter deposition with the plasma only removes mask sputter deposition from sidewalls and on top of the mask.
12. The method, as recited in claim 1 , wherein the plasma from the removing gas is a low energy plasma that has an ion energy less than 100 eV.
13. The method, as recited in claim 1, wherein the removing gas further comprises an inert gas.
14. The method, as recited in claim 13, wherein the inert gas comprises at least one of nitrogen gas (N2), helium (He), xenon (Xe), neon (Ne), and argon (Ar).
15. The method, as recited in claim 1, wherein the removing at least some of the mask sputter deposition, further comprises: stopping a flow of the oxygen containing component; and providing a plasma formed from inert gases.
16. The method, as recited in claim 15, wherein the inert gas comprises at least one of nitrogen gas (N2), helium (He), xenon (Xe), neon (Ne), and argon (Ar).
17. The method, as recited in claim 15, wherein the plasma formed from the inert gas has a higher energy than plasma from the removing gas.
18. A method of etching recessed features in a stack below a patterned carbon containing mask forming mask features, comprising: a. at least partially etching the stack, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition; b. removing at least some of the mask sputter deposition, comprising: i. providing a removing gas comprising an oxygen containing component ii. transforming the removing gas into a plasma, comprising providing a multistate pulsed RF power with two or three states; and iii. exposing the mask sputter deposition to the plasma; and c. further etching the stack.
19. The method of claim 18, further comprising repeating steps b and c at least once.
20. An apparatus for etching recessed features in a stack below a carbon containing mask, comprising: a process chamber; a substrate support for supporting a substrate inside the processing chamber; an RF power source for providing RF power in the processing chamber; a gas source comprising: an oxygen containing component source; and an etch gas source; a controller, controllably connected to the RF power source and the gas source, configured to: and a. at least partially etch the stack, wherein the partially etching the stack redeposits sputtered mask to form mask sputter deposition; b. remove at least some of the mask sputter deposition, comprising: i. providing a removing gas comprising an oxygen containing component; ii. transforming the removing gas into a plasma, comprising providing a multistate pulsed RF power with two or three states; and iii. exposing the mask sputter deposition to the plasma; and c. further etch the stack.
PCT/US2024/048238 2023-10-06 2024-09-24 Selective removal of redeposited carbon masks during etch Pending WO2025075834A1 (en)

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