WO2025075367A1 - Optical interconnect-mounted semiconductor package - Google Patents

Abstract

The present technology relates to an optical interconnect-mounted semiconductor package. The optical interconnect-mounted semiconductor package of the present technology includes: a glass base structure including a photonic component implemented through a patterned silicon nitride thin film; and a semiconductor chip including a photonic package disposed on the glass base structure, wherein the photonic component enables smooth optical communication between the photonic package and the glass base structure. The present technology may provide an optical interconnect-mounted, future semiconductor package capable of enhancing various optical functions, such as smooth optical conversion of Si to silica photonics (PIC to Glass), high-efficiency passive optical devices, etc., through the SiN photonics technology mounted on a glass interposer.

Description

Semiconductor package with optical interconnect

The present invention relates to a semiconductor package equipped with an optical connection, and more specifically, to a semiconductor package equipped with an optical connection including a glass base structure.

In AI semiconductor chip design, the method of integrating various semiconductor chips such as XPU (GPU, IPU, TPU, etc.), memory, and network into a single package requires high performance and efficiency. These chips are packaged in the form of chiplets, and a chip-to-chip link is required for high-speed communication between chips.

At this time, the existing electrical connection method can cause a bottleneck phenomenon due to bandwidth limitations and signal delay.

To address this, glass-based structures such as glass interposers and optical input/output (Optical I/O) technologies such as Si, SiN, and Silica photonics are being introduced.

Optical input/output technology is a method of converting electrical signals into optical signals and transmitting them, which can greatly improve data transmission speed and minimize signal loss. In particular, the introduction of this optical I/O technology is essential for AI semiconductor chips that require high-speed communication and large-capacity data transmission.

However, it is a difficult task to implement a high-efficiency, low-loss optical link while maintaining high yield when packaging together photonic integrated circuits (PICs) that perform optical functions and optical fibers.

Many cutting-edge technologies integrate various semiconductor chips into a single package, effectively managing electrical and optical signals. However, these technologies still have some limitations. For example, there is a mismatch due to the difference in refractive index between optical fibers and silicon PICs, the so-called optical coupling problem. In addition, the heat generated during high-speed data transmission must be efficiently managed, and there are manufacturing process issues that arise during the process of integrating various materials and technologies into a single package.

[Prior art literature]

[Patent Document]

Korean Patent Publication No. 10-2016-0058591 A

An embodiment of the present invention provides a semiconductor package equipped with an optical interconnection that can enhance various optical functions such as smooth optical transition of Si to Silica Photonics (PIC to Glass) and high-efficiency passive optical elements through SiN photonics technology mounted on a glass-based structure to solve the above-mentioned problems.

Meanwhile, other unspecified purposes of the present invention will be additionally considered within a range that can be easily inferred from the following detailed description and its effects.

A semiconductor package having an optical interconnection according to one embodiment comprises: a glass base structure including a photonic component implemented through a patterned thin film; and a semiconductor chip including a photonic package disposed on the glass base structure; wherein the photonic component can enable smooth optical communication between the photonic package and the glass base structure.

The above photonic component may include a single-layer or multi-layer first waveguide.

The above patterned thin film includes silicon nitride, and the first waveguide can be formed of the patterned thin film.

The photonic package includes a second waveguide therein, the glass base structure includes a third waveguide therein, and the photonic component can enable smooth optical switching between the second waveguide and the third waveguide.

The photonic component may be positioned between the second waveguide and the third waveguide.

The second waveguide may include a silicon material, and the third waveguide may include silica.

The photonic component may be positioned between the second waveguide and the third waveguide.

The glass base structure may include a base layer; penetrating electrodes penetrating the base layer to connect an upper surface and a lower surface of the base layer; a wiring structure disposed on an upper surface of the base layer; the third waveguide formed by irradiating a laser into the inside of the base layer; a first dielectric layer formed on the wiring structure; the first waveguide formed on the first dielectric layer; and a second dielectric layer formed on the first waveguide.

The above base layer may include glass.

The above glass-based structure can form a multilayer first waveguide by alternately stacking the first waveguide and the second dielectric layer in multiple layers.

The above glass base structure comprises a plurality of semiconductor chips and an optical integrated circuit semiconductor chip connected to the semiconductor chips through a first waveguide,

The above-described optical integrated circuit semiconductor chip includes a plurality of photonic components, and one of the plurality of photonic components may be a switching array.

The above switching array may include MEMS-based switching elements, thermal-based switching elements, switching elements utilizing electro-optical effects, or switching elements utilizing free charge plasma dispersion effects.

The above switching element is formed in the first waveguide and can interact with an optical signal within the first waveguide.

It may further include an optical fiber array of a detachable structure mounted on the above glass base structure.

The glass base structure further includes an edge coupler formed on the wiring structure, and the optical fiber array is connected to the edge coupler to transmit an optical signal and optical power to the third waveguide including the edge coupler.

The above glass base structure includes a receptacle structure, and the optical fiber array includes a connector having a ferrule structure, such that the receptacle structure and the ferrule structure can be detachable from each other.

The glass base structure may include a base layer; penetrating electrodes penetrating the base layer to connect an upper surface and a lower surface of the base layer; a wiring structure disposed on an upper surface of the base layer; the third waveguide formed on the wiring structure; a first dielectric layer formed on the third waveguide; the first waveguide formed on the first dielectric layer; and a second dielectric layer formed on the first waveguide.

The above glass base structure may include a plurality of third waveguides and the first dielectric layer alternately laminated to form a multilayer third waveguide, and the base layer may include glass.

Also, according to one embodiment, a semiconductor package having an optical connection is provided, comprising: a glass base structure including a third waveguide implemented through a patterned third thin film and a first waveguide implemented through a patterned first thin film; and a semiconductor chip including a photonic package having a second waveguide implemented through a patterned second thin film disposed on the glass base structure; wherein smooth optical communication between the photonic package and the glass base structure can be enabled through optical connection between the first waveguide, the second waveguide, and the third waveguide.

The first thin film may include silicon nitride.

The first waveguide may be a nitride waveguide, the second waveguide may be a silica waveguide, and the third waveguide may be a silicon waveguide.

The above first waveguide can have a refractive index between the above second waveguide and the above third waveguide.

The above first waveguide can form a switching matrix including MEMS-based, thermal-based switching elements, switching elements utilizing electro-optical effects or switching elements utilizing free charge plasma dispersion effects.

Also, a method for forming a semiconductor package having an optical interconnection module according to one embodiment of the present invention comprises: forming a glass base structure; attaching a photonic package on top of the glass base structure; and attaching a semiconductor chip including the photonic package on top of the glass base structure; wherein the step of forming the glass base structure comprises: preparing a substrate having a glass through-via; forming a redistribution structure on the substrate; forming a silica layer on the redistribution structure and patterning the silica layer to form a third waveguide; forming a first dielectric layer on the third waveguide; forming a silicon nitride layer on the first dielectric layer and patterning the nitride layer to form a first waveguide; and forming a second dielectric layer on the first waveguide.

The method may further include, prior to the step of forming the first waveguide, a step of forming a second silica layer on the first dielectric layer and forming a fourth waveguide by patterning the second silica layer; and a step of forming an additional first dielectric layer on the fourth waveguide.

After the step of forming the second dielectric layer, the method may further include the step of forming a second silicon nitride layer on the second dielectric layer and patterning the second silicon nitride layer to form a fifth waveguide; and the step of forming an additional second dielectric layer on the fifth waveguide.

This technology can enhance various optical functions such as smooth optical transition of Si to Silica Photonics (PIC to Glass) and high-efficiency passive optical elements through SiN photonics technology mounted on a glass-based structure.

Figure 1 shows the overall configuration of a future semiconductor package equipped with optical interconnection according to one embodiment.

FIG. 2 illustrates a cross-section of a future semiconductor package equipped with optical interconnects according to one embodiment.

FIGS. 3A through 3E illustrate cross-sectional views of a photonic package at various stages of manufacturing according to one embodiment.

FIGS. 4A through 4I illustrate cross-sectional views of a glass base structure having a waveguide at various stages of manufacturing according to one embodiment.

FIG. 5 illustrates a plan view of a semiconductor package for detailing a first waveguide according to one embodiment.

Figure 6 illustrates another implementation example of Figure 5.

It is to be understood that the attached drawings are provided for reference only to help understand the technical concept of the present invention, and the scope of the rights of the present invention is not limited thereby.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, thickness and spacing are expressed for convenience of explanation and may be depicted exaggerated compared to the actual physical thickness. In describing the present invention, well-known configurations that are irrelevant to the gist of the present invention may be omitted. When adding reference numbers to components in each drawing, it should be noted that, as much as possible, identical components are given the same numbers even if they are shown in different drawings.

As discussed above, future semiconductor chips, such as XPU, Memory, and Network, will be packaged on Chiplets, and optical I/O technologies such as glass-based structures and Si, SiN, and Silica photonics will be introduced to solve the bottleneck problem of chip-to-chip links. At this time, it is a difficult task to implement a high-efficiency (low-loss) optical link while maintaining a high yield when packaging PICs and optical fibers that perform optical functions together.

Accordingly, the SiN Photonics technology mounted on the Glass interposer according to one embodiment can enhance various optical functions such as smooth optical transition of Si to Silica Photonics (PIC to Glass) and high-efficiency passive optical elements. This will be described in detail with reference to the drawings below.

FIG. 1 illustrates a plan view of a semiconductor package equipped with an optical interconnect according to one embodiment.

Fig. 2 is a drawing for showing the components illustrated in Fig. 1 in cross-sectional form. The left-right arrangement positions of each component illustrated in Fig. 2 do not necessarily have to match those in Fig. 1, and thus may be arranged differently from Fig. 1 for convenience of explanation.

Referring to FIGS. 1 and 2, a semiconductor package (1000) equipped with an optical connection (hereinafter, also simply referred to as a 'semiconductor package') includes a substrate (10), a package base substrate (100) attached on the substrate (10), a glass base structure (300) attached on the package base substrate (100), and a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip (500, 600, 700, 800) attached on the glass base structure (300). The first semiconductor chip (500) includes a first photonic package (P500). The second semiconductor chip (600) includes a second photonic package (P600).

The drawing illustrates an embodiment in which four semiconductor chips are attached on a glass base structure; however, the present invention is not limited to the illustrated number.

The package base substrate (100) may include, although not shown in the drawing, a base board layer, board upper surface pads and board lower surface pads respectively arranged on the upper and lower surfaces of the base board layer, and board wiring paths electrically connecting them to each other. The package base substrate (100) may be a printed circuit board, a multilayer printed circuit board, or the like.

The base board layer may be formed of at least one material selected from a phenol resin, an epoxy resin, and a polyimide. The base board layer may include at least one material selected from a FR4 (Frame Retardant 4), a tetrafunctional epoxy, a polyphenylene ether, an epoxy/polyphenylene oxide, a BT (Bismaleimide triazine), a Thermount, a cyanate ester, a polyimide, and a liquid crystal polymer. The base board layer can be made of, for example, polyester PET, polyester terephthalate, fluorinated ethylene propylene (FEP), resin-coated paper, liquid polyimide resin, polyethylene naphthalate (PEN) film, etc. The base board layer can be made by laminating a plurality of base layers.

The board top surface pads and the board bottom surface pads can be made of copper, nickel, stainless steel or beryllium copper. The board top surface pads and the board bottom surface pads can be made of plated copper.

The board interconnect path can be formed of horizontally extending buried conductive layers and vertically extending conductive vias. The conductive vias can connect two of the buried conductive layers, the top surface pads, and the bottom surface pads, which are located at different vertical levels. The board interconnect path can be formed of electrolytically deposited (ED) copper, rolled-annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foils, sputtered copper, copper alloys, nickel, stainless steel, or beryllium copper.

Package connection terminals (350) may be connected to the board upper surface pads, and external connection terminals (150) may be connected to the board lower surface pads. The package connection terminals (350) may electrically connect the glass base structure (300) and the package base substrate (100). The external connection terminals (150) may connect the semiconductor package to the outside. For example, the package connection terminals and the external connection terminals may be bumps, solder balls, etc.

In one embodiment of the present invention, the base substrate (100) is arranged on the substrate (10) as an example, but is not limited thereto. For example, when the substrate (10) functions as a circuit board, the base substrate (100) may be omitted.

The glass base structure (300) can perform a role like a kind of interposer. That is, the glass base structure (300) can be a glass interposer.

Additionally, when the substrate (10) is omitted, the glass base structure (300) may also serve as the substrate (10). That is, the glass base structure (300) may be a glass substrate.

The glass base structure (300) as described above can be used to implement a vertical connection terminal in a fine pitch type for interconnecting the first to fourth semiconductor chips (500, 600, 700, 800) and the package substrate (100).

The glass base structure (300) can transmit high-speed electrical and optical signals, thereby enabling high-speed communication between the first to fourth semiconductor chips. To this end, optical fibers (915A, 915B) can be coupled to the glass base structure (300) in a detachable structure. For the detachable structure, a receptacle structure can be applied to the glass base structure, and a ferrule structure can be applied to the optical fiber.

The glass base structure (300) includes a base layer (310), glass base structure bottom pads (not shown) disposed on a lower surface of the base layer (310), through-electrodes (330) penetrating the base layer (310) to connect between the upper surface and the lower surface of the base layer (310), and a wiring structure (not shown) disposed on an upper surface of the base layer (310). Glass base structure connection terminals (350) (which may correspond to the package connection terminals described above) may be attached to the glass base structure bottom pads (not shown). The glass base structure connection terminals (350) may be interposed between the board upper surface pads and the glass base structure bottom pads to electrically connect the glass base structure (300) and the package base substrate (100).

The base layer (310) may include glass, silicon, ceramic, or plastic. For example, the glass base structure (300) may be a glass base structure (glass interposer) in which the base layer (310) is formed from a glass substrate.

Each of the through-electrodes (330) may include a conductive plug penetrating the base layer (310) and a conductive barrier film surrounding the conductive plug. The conductive plug may include Cu or W, and the conductive barrier film may include a metal or a conductive metal nitride. The conductive plug may have a cylindrical shape, and the conductive barrier film may have a cylindrical shape surrounding a sidewall of the conductive plug. A via insulating film may be interposed between the base layer (310) and the through-electrodes (330) to surround a sidewall of the through-electrode (330). The via insulating film may prevent the base layer (310) and the through-electrode (330) from making direct contact. The via insulating film may be formed of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

The wiring structure (not shown, for example, 312 in FIG. 4b) may include a wiring line pattern, a wiring via, and a wiring insulation layer. The wiring structure may be formed by a rewiring process. In FIG. 4b, which will be described later, the wiring structure may correspond to a rewiring structure (312). The wiring line pattern may correspond to a conductive line (317), the wiring via may correspond to a via (319), and the wiring insulation layer may correspond to a dielectric layer (315).

The wiring line pattern and the wiring via may be, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof, but are not limited thereto. The wiring line pattern and the wiring via may be formed by laminating a metal or an alloy of metals on a seed layer including titanium, titanium nitride, or titanium tungsten. The wiring line pattern may be arranged on at least one of the upper and lower surfaces of the wiring insulating layer. The wiring via may penetrate the wiring insulating layer and be in contact with and connected to some of the wiring line patterns. At least some of the wiring line patterns may be formed together with some of the wiring vias to form an integral body. For example, a wiring via in contact with the lower surface of a wiring line pattern and an interposer wiring line pattern can form an integral body.

The wiring insulation layer may be formed from a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI). The wiring structure may include a plurality of stacked wiring insulation layers.

The wiring structure can be formed by a semiconductor BEOL (back end of line) process. The wiring line pattern and the wiring via can include a metal material such as copper (Cu), aluminum (Al), and tungsten (W). The wiring insulating layer can include a high density plasma (HDP) oxide film, a TEOS oxide film, a Tonen SilaZene (TOSZ), a Spin On Glass (SOG), an Undoped Silica Glass (USG), or a low-k dielectric layer.

Some of the wiring line patterns arranged on the upper surface of the glass base structure (300) may be referred to as glass base structure upper surface pads (rewiring upper surface pads). A first chip connection terminal (550) and a second chip connection terminal (650) may be attached to the glass base structure upper surface pads. Each of the first chip connection terminal (550) and the second chip connection terminal (650) may be a bump, a solder ball, or the like.

The glass base structure (300) includes a third waveguide (321). The third waveguide (321) may have a multilayer structure. For example, it may have a multilayer third waveguide (321A, 321B, 321C) as in FIG. 4e described below. The third waveguide (321) may be formed by patterning a silica layer. For example, since the base layer (310) is made of silica glass, the third waveguide (321) may be formed by irradiating a laser into the inside of the base layer (310). That is, the third waveguides (321A, 321B, 321C) may be formed by irradiating a laser at different depths inside the base layer (310). The third waveguide (321) receives an optical signal and/or optical power between it and an optical fiber (915B) coupled to an external light source.

Meanwhile, in one embodiment of the present invention, it has been described as an example that the glass base structure (300) includes the third waveguide (321), but it is not limited thereto. For example, the third waveguide (321) may be formed of a material other than silica, and is intended to differentiate it from the other waveguides, the first waveguide (334) and the waveguide (504 illustrated in 3e).

The glass base structure (300) includes a first waveguide (334). Here, the first waveguide (334) may include a nitride, for example, silicon nitride, and the first waveguide (334) may have a multilayer structure. The first waveguide may be a single-layer or multi-layer SiN thin film. For example, it may have a multilayer first waveguide (334A, 334B) as in FIG. 4i described below. The first waveguide (334) may be formed by patterning a silicon nitride layer. The first waveguide (334) receives an optical signal and/or optical power between it and an optical fiber (915A) coupled to an external light source.

The first waveguide (334) enhances various optical functions such as smooth optical transition of Si to Silica Photonics (PIC to Glass) and high-efficiency passive optical elements through SiN photonics technology mounted on a glass base structure (300). That is, the first waveguide (334) facilitates optical communication between a second waveguide (e.g., the second waveguide (504) illustrated in FIG. 3e) mounted on a photonic package (P500, P600) and a third waveguide (321) mounted on a glass base structure (300).

Meanwhile, in one embodiment of the present invention, it has been described as an example that the glass base structure (300) includes the first waveguide (334), but it is not limited thereto. For example, the first waveguide (334) may be formed of a material other than nitride, and is intended to differentiate it from other waveguides, such as the third waveguide (321) and the second waveguide (504 illustrated in 3e).

The first semiconductor chip (500) may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable and programmable read-only memory (EEPROM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

The first semiconductor chip (500) may include a serial-parallel conversion circuit, a test logic circuit such as a DFT (design for test), a JTAG (Joint Test Action Group), and an MBIST (memory builtin self-test), and a signal interface circuit such as a PHY.

The first semiconductor chip (500) may include a memory cell chip having cells of HBM DRAM and a buffer chip for controlling the HBM DRAM.

The first semiconductor chip (500) can be stacked with the active surface facing downward, i.e., toward the glass base structure (300).

A first semiconductor chip (500) may include a first substrate. The first substrate may include a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first substrate may have an active surface and an inactive surface opposite to the active surface. The first substrate may include various types of individual devices on the active surface. The individual devices may include various microelectronics devices, for example, MOSFETs (metal-oxide-semiconductor field effect transistors) such as CMOS transistors (complementary metal-insulator-semiconductor transistors), image sensors such as system LSIs (large scale integration), CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), active components, passive components, etc.

The first semiconductor chip (500) may include a first semiconductor element formed by individual elements. The first semiconductor element is arranged on an active surface of the first substrate, the first front connection pads and the first rear connection pads are respectively arranged on the active surface and the inactive surface of the first substrate, and the first through-electrodes may electrically connect the first front connection pads and the first rear connection pads by vertically piercing at least a portion of the first substrate.

The first semiconductor chip (500) can be electrically connected to the glass base structure (300) through the first front connection pads (not shown). A first chip connection terminal (550) is interposed between the first front connection pads and the rewiring top surface pads among the wiring line patterns (372), so as to electrically connect the first front connection pads and the rewiring top surface pads.

Meanwhile, although not shown in the drawing, the first semiconductor chip (500) may further include a chip molding layer that surrounds the first semiconductor chip on the upper surface of the first semiconductor chip (500). The chip molding layer may be made of, for example, EMC.

The second semiconductor chip (600) may include a second substrate and second front connection pads (not shown). The second front connection pads may be arranged on an active surface of the second substrate. The second substrate is generally similar to the first substrate described above, and thus a detailed description thereof will be omitted. The second substrate may have an active surface and an inactive surface opposite to the active surface. The second semiconductor chip (600) may include a second semiconductor element. The second semiconductor element may be formed on the active surface of the second substrate.

The second semiconductor chip (600) can be electrically connected to the glass base structure (300) through second front connection pads (not shown). A second chip connection terminal (650) is interposed between the second front connection pads and the rewiring top surface pads among the wiring line patterns (372), so as to electrically connect the second front connection pads and the rewiring top surface pads.

The second semiconductor chip (600) may include one of a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, an application processor (AP) chip, an application specific integrated circuit (ASIC), or other processing chips.

The first semiconductor chip (500) may include a first photonic package (P500). The term photonic package may be a PIC (Photonic Integrated Circuit).

The first photonic package (P500) provides an input/output (I/O) interface between optical and electrical signals of the semiconductor package. The first photonic package provides an optical network for signal communication between components within the first photonic package (e.g., photonic devices, integrated circuits, coupling to external fibers, etc.).

The first photonic package (P500) may include a buried oxide (BOX) substrate. The BOX substrate includes an oxide layer formed over the substrate, and a silicon layer formed over the oxide layer. The substrate may be a material such as, for example, glass, ceramic, a dielectric, a semiconductor, or a combination thereof. The substrate may be a semiconductor substrate, such as a bulk semiconductor, which may or may not be doped (e.g., with a p-type or n-type dopant). The substrate may be a wafer, such as a silicon wafer. Other substrates, such as multilayer or graded substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; a mixed-crystal semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. The oxide layer may be, for example, silicon oxide.

The silicon layer is patterned to form silicon regions for waveguides, photonic components, and grating couplers, according to some embodiments. The silicon layer can be patterned using suitable photolithography and etching techniques. For example, a hardmask layer (e.g., a nitride layer or other dielectric material) can be formed and patterned over the silicon layer, in some embodiments. The pattern of the hardmask layer can then be transferred to the silicon layer using an etching process. The etching process can include, for example, a dry etching process and/or a wet etching process. For example, the silicon layer can be etched to form recesses defining waveguides (also referred to as second waveguides). In some embodiments, more than one photolithography and etching sequence can be used to pattern the silicon layer. One waveguide or multiple waveguides can be patterned from the silicon layer. When multiple waveguides are formed, the multiple waveguides can be individual waveguides or connected as a single continuous structure. In some embodiments, one or more of the waveguides form a continuous loop. Other configurations or arrangements of the waveguides, photonic components, or grating couplers are possible, and other types of photonic components or photonic structures may be formed. In some cases, the waveguides, photonic components, and grating couplers may be collectively referred to as a 'photonic layer.'

The photonic component can be integrated with the waveguide and formed as a second waveguide. The photonic component can be optically coupled to the waveguide to interact with an optical signal within the waveguide. The photonic component can include a photonic device, such as, for example, a photodetector and/or a modulator. For example, the photodetector can be optically coupled to the waveguide to detect an optical signal within the waveguide and generate an electrical signal corresponding to the optical signal. The modulator can be optically coupled to the waveguide to receive an electrical signal and generate a corresponding optical signal within the waveguide by modulating optical power within the waveguide. In this manner, the photonic component facilitates input/output (I/O) of optical signals to the waveguide. In other embodiments, the photonic component can include other active or passive components, such as a laser diode, an optical signal splitter, or other types of photonic structures or devices. The optical power may be provided to the waveguide, for example, by an optical fiber coupled to an external light source (e.g., see 915A and 915B of FIG. 2), or the optical power may be generated by a laser diode (e.g., see 800 of FIG. 2).

In some embodiments, the photodetector can be formed, for example, by partially etching a region of the waveguide and growing an epitaxial material on the remaining silicon in the etched region. The waveguide can be etched using acceptable photolithography and etching techniques. The epitaxial material can include, for example, a semiconductor material, such as germanium (Ge), which may be doped or undoped. In some embodiments, an implantation process can be performed to introduce a dopant into the silicon in the etched region as part of the formation of the photodetector. The silicon in the etched region can be doped with a p-type dopant, an n-type dopant, or a combination thereof. In some embodiments, the modulator can be formed, for example, by partially etching a region of the waveguide and then implanting an appropriate dopant into the remaining silicon in the etched region. The waveguide can be etched using acceptable photolithography and etching techniques. In some embodiments, the etched region used for the photodetector and the etched region used for the modulator can be formed using one or more of the same photolithography or etching step. The silicon in the etched region can be doped with a p-type dopant, an n-type dopant, or a combination thereof. In some embodiments, the etched region used for the photodetector and the etched region used for the modulator can be implanted using one or more of the same implantation step.

In some embodiments, one or more grating couplers can be integrated with the waveguide and formed into the waveguide. A grating coupler is a photonic structure that allows optical signals and/or optical power to be transmitted between the waveguide and a photonic component, such as a vertically mounted optical fiber (e.g., optical fiber 915A as illustrated in FIG. 2 ), or a waveguide of another photonic system. The grating coupler can be formed using acceptable photolithography and etching techniques. In one embodiment, the grating coupler is formed after the waveguide is defined. For example, a photoresist can be formed and patterned on the waveguide. The photoresist can be patterned with openings corresponding to the grating couplers. One or more etching processes can be performed using the patterned photoresist as an etch mask to form recesses in the waveguide that define the grating couplers. The etching process can include one or more dry etching processes and/or wet etching processes. In some embodiments, other types of couplers may be formed, such as structures that couple optical signals between the waveguide and other waveguides of the first photonic package (P500), such as the first waveguide (334A, 334B) (see FIG. 4i). Edge couplers may also be formed that allow optical signals and/or optical power to be transmitted between the waveguide and a photonic component mounted horizontally near a sidewall of the first photonic package (P500).

The second semiconductor chip (600) may include a second photonic package (P600). Since the second photonic package (P600) may be formed in the same manner as the first photonic package (P500) described above, a detailed description thereof will be omitted.

The semiconductor package (1000) may further include a package molding layer (not shown) that surrounds the first to fourth semiconductor chips (500, 600, 700, 800) on the glass base structure (300). The package molding layer may be made of, for example, EMC.

The semiconductor package (1000) may further include a stiffener structure (not shown) attached on the package base substrate (100). The stiffener structure may be attached with a stiffener thermal interface material layer attached on the package base substrate (100) therebetween. The stiffener structure may be spaced apart from the first to fourth semiconductor chips. In some embodiments, the stiffener structure may be attached on the package base substrate (100) so as to be spaced apart from the glass base structure (300). The stiffener structure may extend along an edge of the package base substrate (100) in a planar manner, i.e., in a top-view, to surround the periphery of the first to fourth semiconductor chips. The stiffener structure may extend along an edge of the package base substrate (100) and may have a rectangular ring shape that surrounds the glass base structure (300) in a planar manner. The reinforcing structure may have a shape in which four side walls extending along each of the four edges of the package base substrate (100) are connected to each other.

The reinforcing structure can be made of a metal. For example, the reinforcing structure can include at least one of copper, nickel, and stainless steel. The reinforcing heat transfer material layer can be made of an insulating material, or a material capable of maintaining electrical insulation by including an insulating material. The reinforcing heat transfer material layer can include, for example, an epoxy resin. The reinforcing heat transfer material layer can be, for example, mineral oil, grease, gap filler putty, phase change gel, phase change material pads, or particle filled epoxy.

FIGS. 3A to 3E illustrate an implementation example of forming a first photonic package according to one embodiment. As illustrated in the drawings, the first photonic package (P500) may be manufactured through a process of forming the SOI substrate (502), the second waveguide (504), the photonic component (506), the grating coupler (507), the dielectric layer (508), etc. described above. Here, the SOI substrate (502) may include a substrate (502C), an oxide layer (502B), and a silicon layer (502A).

In FIG. 3B, a dielectric layer (508) is formed on an SOI substrate (502) to form a photonic routing structure (510). The dielectric layer (508) is formed over the second waveguide (504), the photonic component (506), the grating coupler (507), and the oxide layer (502B). The dielectric layer (508) may be formed of one or more layers, such as silicon oxide, silicon nitride, combinations thereof, and may be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on-dielectric process, or a combination thereof. In some embodiments, the dielectric layer (508) may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-cure to convert to another material, such as an oxide, in a remote plasma system), or a combination thereof. Other dielectric materials formed by any acceptable process may be used. The dielectric layer (508) is then planarized using a planarization process, such as a CMP process, a grinding process, or the like. A thinner dielectric layer (508) may allow for more efficient optical coupling between the grating coupler (507) and the photonic component coupled to the external light source.

Due to the difference in refractive indices between the second waveguide (504) material and the dielectric layer (508) material, the second waveguide (504) has high internal reflection such that light is substantially confined within the second waveguide (504) depending on the wavelength of the light and the refractive indices of the respective materials. In one embodiment, the refractive index of the second waveguide (504) material is higher than the refractive index of the dielectric layer (508) material. For example, the second waveguide (504) can include silicon or silicon nitride, and the dielectric layer (508) can include silicon oxide and/or silicon nitride.

Meanwhile, in one embodiment of the present invention, the second waveguide (504) is described as including silicon or silicon nitride as an example, but is not limited thereto. For example, the second waveguide (504) may be formed of a material other than silicon or silicon nitride, in order to differentiate it from the other waveguides, the third waveguide (321) and the first waveguide (334), in terms of name.

In FIG. 3C, a via (512) and a contact (513) are formed in the dielectric layer (508). In some embodiments, the via (512) and the contact (513) are formed as part of forming the redistribution structure (520), and in other embodiments, the via (512) is not formed. In some embodiments, the via (512) is formed by a damascene process, e.g., single damascene, dual damascene, etc. The via (512) can be formed, for example, by forming an opening extending through the dielectric layer (508). In some embodiments, the opening can extend partially into the oxide layer (502B) or can extend completely through the oxide layer (102B) to expose the substrate (502C). In some embodiments, the opening can extend partially into the substrate (502C). The apertures can be formed using any acceptable photolithography and etching technique, such as forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process can include, for example, a dry etching process and/or a wet etching process.

A conductive material may then be formed in the opening according to some embodiments to form a via (512). In some embodiments, a liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, may be formed in the opening from TaN, Ta, TiN, Ti, CoW, or the like, and may be formed using a suitable deposition process, such as ALD, or the like. A seed layer (not shown), which may comprise copper or a copper alloy, may then be deposited in the opening. The conductive material of the via (512) may be formed in the opening using, for example, a plating process. The conductive material may comprise a metal or a metal alloy, such as, for example, copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the dielectric layer (508) such that the top surfaces of the via (512) and the dielectric layer (508) are flush. The via (512) may be formed using other techniques or materials in other embodiments.

In some embodiments, the contact (513) extends through the dielectric layer (508) and is electrically connected to the photonic component (506). The contact (513) allows power or electrical signals to be transmitted to and from the photonic component (506). In this manner, the photonic component (506) can convert electrical signals into optical signals transmitted by the second waveguide (504) and/or convert optical signals from the second waveguide (504) into electrical signals. The contact (513) can be formed before or after the formation of the via (512), and the formation of the contact (513) and the formation of the via (512) can share some steps, such as deposition of a conductive material and/or planarization. In some embodiments, the contact (513) is formed by a damascene process, such as single damascene, dual damascene, etc. For example, in some embodiments, an opening (not shown) for a contact (513) is first formed in the dielectric layer (508) using acceptable photolithography and etching techniques. A conductive material may then be formed in the opening to form the contact (513). Excess conductive material may be removed using a CMP process, or the like. The conductive material of the contact (513) may be formed of a metal or metal alloy, including aluminum, copper, tungsten, or the like, which may be the same as the conductive material of the via (512). The contact (513) may be formed using other techniques or materials in other embodiments.

A redistribution structure (520) is formed over a dielectric layer (508). The redistribution structure (520) includes a dielectric layer (517) and conductive features (514) formed in the dielectric layer (517) that provide interconnections and electrical routing. For example, the redistribution structure (520) may connect an upper device, such as a via (512), a contact (513), and/or an electronic die (522). The dielectric layer (517) may be, for example, an insulating layer or a passivation layer, and may include one or more materials similar to those described above for the dielectric layer (108), such as silicon oxide or silicon nitride, or may include different materials. The dielectric layer (517) and the dielectric layer (508) may be transparent or substantially transparent to light within the same wavelength range. The dielectric layer (517) may be formed using techniques similar to those described above for the dielectric layer (508), or using different techniques. The conductive features (514) may include conductive lines and vias and may be formed by a damascene process, for example, single damascene, dual damascene, etc. As illustrated in FIG. 3D , a conductive pad (516) is formed on a top layer of a dielectric layer (517). After forming the conductive pad (516), a planarization process (for example, a CMP process, etc.) may be performed so that the surfaces of the conductive pad (516) and the top dielectric layer (517) are substantially coplanar. The redistribution structure (520) may include more or fewer dielectric layers (517), conductive features (514), or conductive pads (516) than are illustrated in the drawings.

A portion of the redistribution structure (520) is removed in some embodiments and replaced with a dielectric layer (515). The removed portion of the redistribution structure (520) may in some cases be over or approximately over the grating coupler (507). The material of the dielectric layer (515) may provide more efficient optical coupling between the grating coupler (507) and the optical fiber (see optical fiber (917B) of FIG. 2 ) than the material of the dielectric layer (517) of the redistribution structure (520). For example, the dielectric layer (515) may be more transparent, less lossy, or less reflective than the dielectric layer (517). In some embodiments, the material of the dielectric layer (515) is deposited using a technique that forms a material similar to the material of the dielectric layer (517), but having better qualities (e.g., fewer impurities, less dislocations, etc.). In this way, by replacing a part of the dielectric layer (517) of the rewiring structure (520) with the dielectric layer (515), more efficient operation of the first photonic package (P500) can be allowed and optical signal loss can be reduced.

Portions of the re-wiring structure (520) may be removed using acceptable photolithography and etching techniques, such as, for example, forming and patterning a photoresist and then performing an etching process using the patterned photoresist as an etching mask to remove the dielectric layer (517). The etching process may include, for example, a dry etching process and/or a wet etching process.

A dielectric layer (515) is deposited to replace the removed portion of the rewiring structure (520). The dielectric layer (515) can include one or more materials similar to those described above for the dielectric layer (508), such as silicon oxide or silicon nitride, spin-on glass, or a different material. The dielectric layer (515) and the dielectric layer (508) can be transparent or substantially transparent to light within the same wavelength range. The dielectric layer (515) can be formed using a technique similar to that described above for the dielectric layer (508), or using a different technique. For example, the dielectric layer (515) can be formed using CVD, PVD, spin-on, or the like, although other techniques may be used. In some embodiments, a planarization process (e.g., CMP or a grinding process) is used to remove excess material of the dielectric layer (515). The planarization process may also expose the conductive pads (516). After performing the planarization process, the dielectric layer (515), the top dielectric layer (517), and/or the conductive pad (516) may have substantially equivalent surfaces.

One or more electronic dies (522) are bonded to the redistribution structure (520) according to some embodiments. The electronic dies (522) may be, for example, semiconductor devices, dies, or chips that communicate with the photonic components (506) using electrical signals. In the illustrated embodiment, the electronic dies (522) do not receive, transmit, or process optical signals. In the discussion herein, the term “electronic die” is used to distinguish it from a “photonic die” (e.g., see 551 of FIG. 3e ), which refers to a die that can receive, transmit, or process optical signals, such as converting optical signals to electrical signals or vice versa. In addition to optical signals, the photonic dies may also transmit, receive, or process electrical signals. While one electronic die (522) is illustrated in FIG. 3d , the first photonic package (P500) may include two or more electronic dies (522) in other embodiments. In some cases, multiple electronic dies (522) may be integrated into a single first photonic package (P500) to reduce processing costs. The electronic die (522) includes a die connector (524), which may be, for example, a conductive pad, a conductive pillar, or the like.

The electronics die (522) may include integrated circuits for interfacing with the photonic component (506), such as circuitry for controlling the operation of the photonic component (506). For example, the electronics die (522) may include a controller, a driver, a transimpedance amplifier, or a combination thereof. The electronics die (522) may also include a CPU in some embodiments. In some embodiments, the electronics die (522) includes circuitry for processing electrical signals received from the photonic component (506), such as for processing electrical signals received from the photonic component (506) that include a photodetector. The electronics die (522) may control high frequency signaling of the photonic component (506) in some embodiments based on electrical signals (digital or analog) received from other devices or dies. In some embodiments, the electronics die (522) may be an electronic integrated circuit (EIC), such as one that provides SerDes (Serializer/Deserializer) functionality. In this manner, the electronic die (522) can act as part of an I/O interface between optical signals and electrical signals within the first photonic package (P500). In some embodiments, the first photonic package (P500) described herein can be considered a system on a chip (SoC) or system on an integrated circuit (SoIC) device.

In some embodiments, the electronic die (522) is bonded to the redistribution structure (520) by dielectric-dielectric bonding and/or metal-metal bonding (e.g., direct bonding, fusion bonding, oxide-oxide bonding, hybrid bonding, etc.). In such embodiments, a covalent bond may be formed between the top dielectric layer (517) and an oxide layer, such as a surface dielectric layer (not shown) of the electronic die (522). During bonding, metal bonding may also occur between the die connector (524) of the electronic die (522) and the conductive pads (516) of the redistribution structure (520).

In some embodiments, prior to performing the bonding process, a surface treatment is performed on the electronic die (522). In some embodiments, the top surface of the redistribution structure (520) and/or the electronic die (522) may first be activated, for example, using a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas, exposure to H ₂ , exposure to N ₂ , exposure to O ₂ , or a combination thereof. However, any suitable activation process may be used. After the activation process, the redistribution structure (520) and/or the electronic die (522) may be cleaned, for example, using a chemical clean. The electronic die (522) is then aligned with the redistribution structure (520) and placed into physical contact with the redistribution structure (520). The electronic die (522) may be placed on the redistribution structure (520) using, for example, a pick-and-place process. Thereafter, the redistribution structure (520) and the electronic die (522) may be subjected to a pressurization and/or heat treatment relative to each other (e.g., by applying contact pressure) to bond the redistribution structure (520) and the electronic die (522). For example, the redistribution structure (520) and the electronic die (522) may be subjected to a pressure of less than 200 kPa and a temperature of from 200° C. to 400° C. Thereafter, the redistribution structure (520) and the electronic die (522) may be subjected to a temperature (e.g., from 150° C. to 650° C.) above the eutectic point of the conductive pad (516) material and the die connector (524) material to fuse the conductive pad (516) and the die connector (524). In this manner, the dielectric-dielectric bonding and/or metal-metal bonding of the redistribution structure (520) and the electronic die (522) forms a bonded structure. In some embodiments, the bonded structure is baked, annealed, compressed or otherwise treated to strengthen or finish the bond.

A dielectric material (526) is formed over the electronic die (522) and the redistribution structure (520) according to some embodiments. The dielectric material (526) can be formed of, for example, silicon oxide, silicon nitride, a polymer, or a combination thereof. The dielectric material (526) can be formed by, for example, CVD, PVD, ALD, a spin-on dielectric process, or a combination thereof. In some embodiments, the dielectric material (526) can be formed by, for example, HDP-CVD, FCVD, or a combination thereof. The dielectric material (526) can be a gap fill material in some embodiments, which can include one or more of the exemplary materials described above. In some embodiments, the dielectric material (526) can be a material (e.g., silicon oxide) that is substantially transparent to light of a wavelength suitable for transmitting an optical signal or optical power between the grating coupler (507) and the optical fiber (e.g., see 917B). The dielectric material (526) can be planarized using a planarization process, such as a CMP process, a grinding process, or the like. In some embodiments, the planarization process may expose the electronic die (522) such that the surface of the electronic die (522) and the surface of the dielectric material (526) are coplanar.

The use of dielectric-to-dielectric bonding allows a material that is transparent to light of the relevant wavelength to be deposited over the redistribution structure (520) and/or around the electronic die (522), instead of an opaque material, such as an encapsulant or molding compound. For example, the dielectric material (526) can be formed of a suitably transparent material, such as silicon oxide, instead of an opaque material, such as a molding compound. Using a suitably transparent material for the dielectric material (526) in this manner allows optical signals to be transmitted through the dielectric material (526), such as between the grating coupler (507) and an optical fiber (e.g., see 915B) positioned over the dielectric material (526). Additionally, bonding the electronic die (522) to the redistribution structure (520) in this manner can reduce the thickness of the resulting first photonic package (P500), and can improve optical coupling between the grating coupler (507) and the vertically mounted optical fiber. In some cases, this can reduce the size or processing cost of the photonic package and improve optical coupling to external components.

An optional support (528) is attached to the structure according to some embodiments. The support (528) attached to the structure to provide structural or mechanical stability is a rigid structure. The use of the support (528) can reduce warping or bending, which can improve the performance of the optical structure, such as the second waveguide (504) or the photonic component (506). The support (528) can include one or more materials, such as silicon (e.g., silicon wafer, bulk silicon, etc.), silicon oxide, metal, organic core material, or other types of materials. The support (528) can be attached to the structure (e.g., to the dielectric material (526) and/or the electronic die (522)) using an adhesive layer (527), as shown in FIG. 3e , or the support (528) can be attached using direct bonding or other suitable techniques.

A micro lens (531) is embedded in the support (528) on an upper surface of the support (528). In some embodiments, an etching process is performed to remove a portion of the support (528) to form a recess at the location of the micro lens (531), and then the pre-formed micro lens (531) is placed within the recess of the support (528). Next, a dielectric layer (529) is formed over the support (528), and a refractive index matching agent (533) is formed in the dielectric layer (529) over (e.g., directly over) the micro lens (531). The dielectric layer (529) can be formed of a suitable material, such as silicon oxide, silicon nitride, a polymer, and the like, using a suitable deposition process. An etching process is then performed to remove a portion of the dielectric layer (529) to form a recess over the micro lens (531). Then, a refractive index matching agent (533) is deposited within the recess of the dielectric layer (529). A planarization process, such as CMP, may be performed so that the upper surface between the dielectric layer (529) and the refractive index matching agent (533) becomes flush. In some embodiments, the refractive index matching agent (533) is used to reduce optical loss for light coming from or entering an optical fiber coupled to an external light source (e.g., see 915B of FIG. 2) and has a refractive index of, for example, about 1.4 to match the refractive index of silicon oxide.

In FIG. 3E, the substrate (502C) is removed according to some embodiments. The substrate (502C) may be removed using a planarization process (e.g., CMP or a grinding process), an etching process, a combination thereof, or the like. In some embodiments, the oxide layer (502B) is also thinned. The oxide layer (502B) may be thinned as part of the removal process for the substrate (502C), or the oxide layer (502B) may be thinned in a separate step. The oxide layer (502B) may be thinned using, for example, a planarization process, an etching process, or a combination thereof.

A dielectric layer (535) is formed under the oxide layer (502B) according to some embodiments. The dielectric layer (535) may include one or more materials similar to those described above for the dielectric layer (508) or the dielectric layer (515). For example, the dielectric layer (535) may include silicon oxide, spin-on glass, or the like. The dielectric layer (535) may be formed using a technique similar to that described above for the dielectric layer (508) or the dielectric layer (515), or may be formed using a different technique. For example, the dielectric layer (535) may be formed using CVD, PVD, spin-on, or the like, although other techniques may be used.

Next, a dielectric layer (538) is formed under the dielectric layer (535). The dielectric layer (538) may be formed of the same or similar material using the same or similar forming method as the dielectric layer (535), and therefore details are omitted. Additional dielectric layers may be formed by repeating the same process.

Next, a via (552) is formed to extend through the dielectric layer (e.g., 502B, 535, 538) and connect to the via (512). A conductive pad (553) is formed in the dielectric layer (538) over each via (552). Since the via (552) and the conductive pad (553) can be formed by the same or similar forming method as the via (512) and the conductive pad (516), the details are not repeated here.

FIGS. 4A through 4I illustrate cross-sectional views of a glass base structure (300) having a waveguide at various stages of fabrication according to one embodiment. In various embodiments disclosed herein, the photonic package (e.g., P500) described above is bonded to the glass base structure (300) to form various semiconductor packages.

FIG. 4A illustrates a substrate (311) having a through glass via (TGV) (313). The substrate (311) may be, for example, a glass substrate. However, the substrate (311) may alternatively be a silicon substrate, an active layer of a silicon-on-insulator (SOI) substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and/or interconnection functions. These and any other suitable materials may alternatively be used for the substrate (311). The substrate (311) may correspond to the base layer (310) described above.

The TGV (313) may be formed by etching the substrate (311) to create a TGV opening and filling the TGV opening with a liner (not shown), a barrier layer (not shown), and a conductive material. The TGV (313) may correspond to the through-hole electrodes (330) described above. In one embodiment, the liner may be a dielectric material, such as silicon nitride, silicon oxide, a dielectric polymer, or combinations thereof, formed by a process such as chemical vapor deposition, oxidation, physical vapor deposition, ALD, or the like. The barrier layer may be an electrically conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, or the like, formed using a CVD process (e.g., PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), ALD, or the like. The conductive material may include copper, but other suitable materials, such as aluminum, tungsten, an alloy, doped polysilicon, combinations thereof, or the like, may also be used. The conductive material can be formed by depositing a seed layer, then electroplating copper on the seed layer, and filling and overfilling the TGV aperture. Once the TGV aperture is filled, excess liner/barrier layer and excess conductive material outside the TGV aperture can be removed by a grinding process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

Next, in FIG. 4b, a redistribution structure (312) is formed over a substrate (311). The redistribution structure (312) includes one or more dielectric layers (315) (e.g., silicon oxide layer, spin-on glass, PID, photosensitive polyimide, etc.), and conductive features such as conductive lines (317) and vias (319). The redistribution structure (312) can be formed using the same or similar materials as the redistribution structure (520) of the first photonic package (P500) and using the same or similar forming process.

Next, in FIG. 4c, a third waveguide (321) is formed over the redistribution structure (312). The third waveguide (321) is formed by forming a silica layer over the redistribution structure (312) and patterning the silica layer. The details may be generally similar to forming the second waveguide of the first photonic package (P500) described above. The third waveguide (321) may include a photonic structure, such as an edge coupler (324), which allows optical signals and/or optical power to be transmitted between the third waveguide (321) and a photonic component mounted horizontally near a sidewall of the glass base structure (300), such as an edge-mounted optical fiber (e.g., see 915B of FIG. 2).

Next, in FIG. 4d, a dielectric layer (323) is formed over the third waveguide (321) and the redistribution structure (312), and a conductive pad (325) is formed to extend through the dielectric layer (323, see FIG. 4e) to connect with a conductive feature of the redistribution structure (312). The dielectric layer (323) may be formed of a material that is the same as or similar to the dielectric layer (315) (e.g., silicon oxide). In some embodiments, the refractive index of the dielectric layers (323 and 315) is lower than the refractive index of the third waveguide (321), such that the third waveguide (321) ensures that the light has high internal reflection such that the light is substantially confined within the third waveguide (321). The conductive pad (325) may be formed by a forming method that is the same as or similar to the conductive pad (553) of the first photonic package (P500) described above. A conductive connector (327), also called an external connector, is formed on the lower surface of the glass base structure (300) to connect to the TGV (313). The conductive connector (327) may be, for example, a ball grid array (BGA) connector, a solder ball, a metal pillar, a C4 (controlled collapse chip connection) bump, a micro bump, an electroless nickel-electroless palladium-immersion gold (ENEPIG) technology-formed bump, etc.

FIG. 4e illustrates a cross-sectional view of a glass base structure (300A) having multilayer waveguides according to one embodiment. The glass base structure (300A) is similar to the glass base structure (300) of FIG. 4d, but has multilayer third waveguides (321A, 321B, 321C) formed over the rewiring structure (312). Each of the third waveguides (321A, 321B, 321C) can have different thicknesses measured along the vertical direction of FIG. 4e. The third waveguides (321A, 321B, 321C) having different thicknesses can provide different functions in the formed photonic package.

Referring to FIGS. 4F and 4G, a first waveguide (334A) is formed over a dielectric layer (323) according to some embodiments. In FIG. 4F, a silicon nitride layer (332) is deposited on the dielectric layer (323). The silicon nitride layer (332) may be formed using any suitable deposition technique, such as CVD, PECVD, LPCVD, PVD, or the like. In some embodiments, the silicon nitride layer (332) is formed to have a thickness in a range of about 0.2 μm to about 1.0 μm, although other thicknesses are also possible.

In FIG. 4g, the silicon nitride layer (332) is patterned to form a first waveguide (334A) according to some embodiments. For ease of discussion, the first waveguide (334A) and the subsequently formed first waveguide (334B) (see, e.g., FIG. 4i ) are collectively referred to as the first waveguide (334). The first waveguide (334) can be patterned using any acceptable photolithography and etching techniques. For example, a hardmask layer can be formed and patterned over the silicon nitride layer (332) in some embodiments. The pattern of the hardmask layer can then be transferred to the silicon nitride layer (332) using an etching process. The etching process can include, for example, a dry etching process and/or a wet etching process. The etching process can be selective to silicon nitride as compared to silicon oxide or other materials. The silicon nitride layer (332) can be etched to form a recess defining a first waveguide (334), with sidewalls of the remaining non-recessed portion defining sidewalls of the first waveguide (334). In some embodiments, more than one photolithography and etching sequence can be used to pattern the silicon nitride layer (332). A single first waveguide (334) or multiple first waveguides (334) can be patterned from the silicon nitride layer (332). When multiple first waveguides (334) are formed, the multiple first waveguides (334) can be individual first waveguides (334) or connected as a single continuous structure. In some embodiments, one or more of the first waveguides (334) form a continuous loop. In some embodiments, the first waveguide (334) may include a photonic structure, such as a grating coupler, an edge coupler, or other type of coupler (e.g., a mode converter), that allows optical signals to be transmitted between the two first waveguides (334) and/or between the first waveguide (334) and the waveguide (321).

In some cases, a waveguide formed from silicon nitride (e.g., the first waveguide (334)) may have advantages over a waveguide formed from silica (e.g., the waveguide (321)). For example, because silicon nitride has a higher permittivity than silica, the first waveguide may have greater internal confinement of light than the third waveguide. This may also make the performance or leakage of the first waveguide less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or line width roughness). In some cases, the reduced process sensitivity may make the first waveguide easier or less expensive to process than the third waveguide. These characteristics may cause the first waveguide to have lower propagation loss than the third waveguide. In some cases, the propagation loss (dB/cm) of the first waveguide may be from 0.1% to 50% of that of the third waveguide. In some cases, the first waveguide may also be less sensitive to environmental temperature than the third waveguide. For example, the first waveguide may have a temperature sensitivity that is about 1% of that of the third waveguide. In this manner, the embodiments described herein may allow for the formation of a glass-based structure having both a first waveguide (e.g., the first waveguide (334)) and a third waveguide (e.g., the waveguide (321)).

Referring to FIG. 4h, a dielectric layer (335) is formed over the first waveguide (334) according to some embodiments. The dielectric layer (335) may include one or more materials similar to those described above for the dielectric layer (315). For example, the dielectric layer (335) may include silicon oxide, spin-on glass, or the like. The dielectric layer (335) may be formed using a technique similar to that described above for the dielectric layer (315), or may be formed using a different technique. For example, the dielectric layer (335) may be formed using CVD, PVD, spin-on, or the like, although other techniques may be used. In some embodiments, a planarization process (e.g., CMP or a grinding process) is used to remove excess material of the dielectric layer (335).

Next, in FIG. 4i, a dielectric layer (338A) is formed on the dielectric layer (335), and a first waveguide (334B) is formed on the dielectric layer (338A). Since the dielectric layer (338A/348A) and the first waveguide (334B) can be formed of the same or similar material using the same or similar forming method as the dielectric layer (335) and the first waveguide (334A), respectively, details are omitted. An additional dielectric layer (not shown) and an additional first waveguide (not shown) can be formed by repeating the same processing. The number of the first waveguides and the number of dielectric layers on the dielectric layer (335) illustrated in FIG. 4i are only non-limiting examples.

FIG. 5 is a plan view of a semiconductor package for explaining a first waveguide in detail according to one embodiment. And FIG. 6 is a drawing for explaining optical signal propagation of the semiconductor package of FIG. 5.

Referring to FIGS. 5 and 6, a semiconductor package (1000) includes the glass base structure (300), a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip (500, 600, 700, 800) described above. In addition, the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip include a first photonic package (P500), a second photonic package (P600), and a third photonic package (P700), respectively. An embodiment further including a fifth semiconductor chip (900) is illustrated in the drawing. Since the first semiconductor chip (500) and the second semiconductor chip (600) are as described above, their redundant descriptions are omitted. The third semiconductor chip (700) may be an AI accelerator. The fourth semiconductor chip (800) may be a laser diode. The fifth semiconductor chip (900) may include a fifth photonic package (P900). The positions of each chip are not limited to those shown and may have various arrangements as needed.

The first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900) may be silicon-based photonic packages. The first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900) may be positioned in close proximity to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900), and may be electrically connected thereto. The optical wiring, i.e., the first waveguide (334), may be connected only to the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900). Meanwhile, in FIG. 5, the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900), and the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900) are illustrated as being arranged adjacent to each other on a plane, but are not limited thereto. For example, the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900), and the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900) may be arranged in a three-dimensional stacked relationship. That is, a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fifth semiconductor chip (500, 600, 700, 900) can be stacked on a first photonic package (P500), a second photonic package (P600), a third photonic package (P700), and a fifth photonic package (P900).

Also, referring to FIG. 5, a first waveguide (334) is arranged for optical connection between chips. The first waveguide (334) facilitates optical communication between a silicon photonics-based second waveguide (504) inside each photonic package and a silica photonics-based silica optical waveguide (321) inside a glass base structure.

The second waveguide (504) can be formed of silicon or silicon nitride. Silicon has a high refractive index, which allows for the creation of a small-sized waveguide. It is also compatible with CMOS processes, making it easy to create an electronic-optical integrated circuit.

The third waveguide (321) can be formed of silica. Silica has a lower refractive index than silicon, and thus has similar properties to optical fibers. Silica has very low optical loss, making it advantageous for long-distance transmission. In addition, it is stable against temperature changes and operates reliably in a wide range of environments. It is suitable for application to optical distribution, coupling elements, etc.

In one embodiment of the present invention, the third waveguide (321) provided in the edge region and connected to the optical fiber (915A, 915B) may be formed using a laser. That is, since the third waveguide (321) provided in the edge region is provided using a laser, the third waveguide (321) provided in the edge region may have a larger width and thickness than the first waveguide (334). Accordingly, the loss of the optical signal transmitted from the optical fiber (915A, 915B) may be minimized.

Meanwhile, in one embodiment of the present invention, the third waveguide (321) provided in the edge region is also formed of silica as an example, but is not limited thereto. For example, the third waveguide (321) provided in the edge region may be formed of a polymer or an ion exchange waveguide (IOX).

The first waveguide (334) can be formed of silicon nitride. Silicon nitride has a refractive index between silicon and silica, and can effectively confine light through high internal reflection in the optical waveguide. It has low sensitivity to temperature changes, and is strong against environmental changes. It is suitable for application to precision optical waveguides, etc.

Since silicon and silica have different optical properties, a smooth transition between these two materials via silicon nitride can minimize optical signal loss and maximize efficiency. In addition, since silicon photonics has strengths in highly integrated circuits and high-speed data transmission, and silica photonics is suitable for low-loss long-distance transmission, a smooth transition between them via silicon nitride photonics greatly increases optical efficiency.

In one embodiment of the present invention, a first waveguide-based switching array (361) may be arranged. The switching array (361) may be one of the photonic components of a system semiconductor chip such as an ASIC (Application-Specific Integrated Circuit) and an optical integrated circuit semiconductor chip such as a silicon PIC (Photonic Integrated Circuit). For example, as illustrated in FIG. 5, a semiconductor chip is provided on a glass base structure (300), and a first waveguide (334) for transmitting an optical signal to the semiconductor chip is provided. Here, the optical integrated circuit semiconductor chip (PIC) includes a plurality of photonic components, and one of the photonic components may operate as the switching array (361).

The switching array (361) can transmit optical signals to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900) through optical switching. A modulator may be provided in each path of the switching array (361) for optical switching. For example, the switching array (361) may include a ring resonator and a Mach-Zehnder interferometer for each path.

The switching array (361) may include switching elements. The switching array (361) may include switching elements in a matrix arrangement. The switching array may be referred to as a switching matrix.

The switching elements can be MEMS (Micro-Electro-Mechanical Systems)-based. MEMS is a system that combines microscopic mechanical structures with electronic elements, and mainly includes elements that perform various mechanical functions such as microscopic sensors, actuators, microgears, and microvalves. For example, a MEMS mirror changes the path of light by mechanically moving a small reflector. A MEMS switch changes the connection between optical waveguides using a small mechanical switch. A MEMS shutter blocks or allows light to pass along a specific path using a mechanical shutter. A MEMS-based switching matrix uses these micromechanical systems to control and convert the path of optical signals on a glass substrate.

The switching elements can be thermal. Thermal switching uses temperature changes to change the path of an optical signal. For example, a thermal waveguide array changes the refractive index of an optical waveguide by applying heat to a specific section. This changes the path along which the optical signal propagates. A thermal lens uses heat to create localized temperature changes to bend or focus the path of light in a specific section. A thermal phase modulator uses heat to change the phase of an optical waveguide, thereby changing the interference pattern of the signal. A thermal switching matrix uses these temperature changes to change the refractive index of an optical waveguide, thereby controlling and converting the path of an optical signal.

Meanwhile, in one embodiment of the present invention, the switching array is described as including MEMS-based switching elements or thermal-based switching elements, but is not limited thereto. For example, the switching array may include switching elements utilizing the electro-optic effect or switching elements utilizing the free charge plasma dispersion effect.

The switching element can be integrated with the first waveguide (334, see FIG. 4g) and formed as the first waveguide (334). The switching element can be optically coupled to the first waveguide (334) to interact with an optical signal within the first waveguide (334). The switching element can form a MEMS mirror structure in the first waveguide (334) through photolithography and etching processes. A heater or electrode can be added here to complete a structure capable of driving the MEMS mirror. The MEMS structure is driven using an electrical signal or heat. In the case of electrical drive, an electric field is generated to move the MEMS structure. In the case of thermal drive, a heater is used to generate heat, which deforms the structure. As the MEMS structure moves, the path of the optical signal changes, which sets a desired path of the optical signal within the waveguide and transmits the signal to a specific photonic component.

The first waveguide-based MEMS switching element can realize high-efficiency, low-loss optical switching by utilizing the excellent mechanical and optical properties of silicon nitride. MEMS mirrors or shutters can be manufactured by utilizing the high mechanical strength of silicon nitride. The etching and doping methods can be combined with the waveguide (334) to integrate it with various photonic components. Through this, the optical I/O performance of the AI semiconductor chip can be improved.

Meanwhile, as illustrated in FIG. 6, the optical fibers (915A, 915B) can be coupled to the third waveguide (321) of the glass base structure (300) in a butt coupling manner. The third waveguide (321) is coupled to the first waveguide (334) in an adiabatic coupling manner, and the first waveguide (334) is coupled to the second waveguide (504) or the switching array (361) of the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900) in a butt coupling manner or an adiabatic coupling manner to transmit optical signals to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900). Accordingly, the optical signal is transmitted to the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900) through the optical fiber (915A, 915B), the third waveguide (321), the first waveguide (334), and the second waveguide (504) of the switching array (361), and the optical signal transmitted to the first photonic package (P500), the second photonic package (P600), the third photonic package (P700), and the fifth photonic package (P900) can be converted into an electrical signal and transmitted to the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fifth semiconductor chip (500, 600, 700, 900).

In addition, as illustrated in FIGS. 7 to 9, an optical signal transmitted through an optical fiber (915A, 915B) can be transmitted to a first semiconductor chip (500), a second semiconductor chip (600), a third semiconductor chip (700), and a fifth semiconductor chip (900) through various paths.

For example, the transmission of an optical signal as illustrated in FIG. 7 is similar to the transmission of an optical signal as illustrated in FIG. 6. However, in the embodiment of FIG. 7, the second waveguide (504) of the switching array (361) is provided at the same level as the first waveguide (334), and the second waveguide (504) and the first waveguide (334) are coupled in a butt coupling manner to transmit an optical signal.

In addition, the transmission of the optical signal as illustrated in FIG. 8 is similar to the transmission of the optical signal as illustrated in FIG. 6. However, in the embodiment of FIG. 8, a separate fourth waveguide (505) is provided at the same level as the first waveguide (334) below the second waveguide (504) of the switching array (361), and the fourth waveguide (505) and the first waveguide (334) can be coupled in a butt coupling manner to transmit the optical signal. In addition, the optical signal can be transmitted by coupling with the second waveguide (504) and the fourth waveguide (505) in an adiabatic coupling manner. Therefore, in the embodiment of FIG. 8, the optical signal transmitted through the optical fiber (915A, 915B) can be transmitted to the first semiconductor chip (500), the second semiconductor chip (600), the third semiconductor chip (700), and the fifth semiconductor chip (900) through the third waveguide (321), the first waveguide (334), and the second waveguide (504) of the switching array (361). Here, the fourth waveguide (505) can be formed of silicon nitride.

In addition, the transmission of the optical signal as illustrated in FIG. 9 is similar to the transmission of the optical signal as illustrated in FIG. 6. However, in the embodiment of FIG. 9, a separate fourth waveguide (505) is provided at a different level from the first waveguide (334) below the second waveguide (504) of the switching array (361), and the fourth waveguide (505) and the first waveguide (334) are coupled in an adiabatic coupling manner to transmit the optical signal. In addition, the second waveguide (504) and the fourth waveguide (505) can also be coupled in an adiabatic coupling manner to transmit the optical signal. Therefore, in the embodiment of FIG. 9, the optical signal transmitted through the optical fiber (915A, 915B) can be transmitted to the first semiconductor chip (500), the second semiconductor chip (600), the third semiconductor chip (700), and the fifth semiconductor chip (900) through the third waveguide (321), the first waveguide (334), and the second waveguide (504) of the switching array (361). Here, the fourth waveguide (505) can be formed of silicon nitride.

Although the technical idea of the present invention has been specifically described in accordance with the above preferred embodiments, it should be noted that the above embodiments are for the purpose of explanation and not for the purpose of limitation. In addition, a person skilled in the art will be able to understand that various embodiments are possible within the scope of the technical idea of the present invention.

[Explanation of symbols]

1000, 1000A: Semiconductor Package

10 : Substrate

100 : Package base board

300 : Glass base structure

500: First semiconductor chip

P500: 1st Photonic Package

600: Second semiconductor chip

P600: 2nd Photonic Package

700: Third semiconductor chip

P700: 3rd Photonic Package

800: 4th semiconductor chip

900: Fifth semiconductor chip

P900: 5th Photonic Package

Claims (25)

As a semiconductor package equipped with optical interconnection, A glass-based structure comprising a photonic component implemented through a patterned thin film; and A semiconductor chip including a photonic package disposed on the glass base structure; The above photonic component is a semiconductor package equipped with an optical connection that enables smooth optical communication between the photonic package and the glass base structure. In the first paragraph, The above photonic component is a semiconductor package equipped with an optical interconnect, which includes a first waveguide of a single layer or multilayer. In the second paragraph, The above patterned thin film comprises silicon nitride, A semiconductor package equipped with an optical interconnection, wherein the first waveguide is formed by the patterned thin film. In the second paragraph, The above photonic package includes a second waveguide therein, The above glass base structure includes a third waveguide therein, A semiconductor package equipped with an optical interconnection, wherein the photonic component enables smooth optical transition between the second waveguide and the third waveguide. In the fourth paragraph, The second waveguide comprises a silicon material or silicon nitride, A semiconductor package with an optical interconnect, comprising silica as the third waveguide. In paragraph 4, A semiconductor package having an optical interconnection, wherein the photonic component is positioned between the second waveguide and the third waveguide. In paragraph 4, The above glass base structure, base layer; Penetrating electrodes penetrating the base layer to connect the upper and lower surfaces of the base layer; A wiring structure arranged on the upper surface of the base layer; The third waveguide formed by irradiating a laser into the interior of the base layer; A first dielectric layer formed on the above wiring structure; The first waveguide formed on the first dielectric layer; and A semiconductor package equipped with an optical interconnection, comprising: a second dielectric layer formed on the first waveguide; In Article 7, A semiconductor package with an optical interconnect, wherein the base layer comprises glass. In Article 7, The above glass base structure, A semiconductor package equipped with an optical interconnection, wherein the first waveguide and the second dielectric layer are alternately laminated in multiple layers to form a multilayer first waveguide. In Article 7, The above glass base structure, Comprising a plurality of semiconductor chips and an optical integrated circuit semiconductor chip connected to the semiconductor chips through a first waveguide, The above-mentioned optical integrated circuit semiconductor chip comprises a plurality of photonic components, A semiconductor package having an optical interconnect, wherein one of the plurality of photonic components is a switching array. In Article 10, The above switching array is an optical interconnection-mounted semiconductor package including a MEMS-based switching element, a thermal-based switching element, a switching element utilizing an electro-optic effect, or a switching element utilizing a free charge plasma dispersion effect. In Article 11, A semiconductor package equipped with an optical connection, wherein the switching element is formed in the first waveguide and interacts with an optical signal within the first waveguide. In Article 7 An optical interconnect-mounted semiconductor package further comprising: an optical fiber array of a detachable structure mounted on the glass base structure; In Article 13 The above glass base structure further includes an edge coupler formed on the wiring structure, An optical interconnect-mounted semiconductor package, wherein the optical fiber array is connected to the edge coupler to transmit optical signals and optical power to the third waveguide including the edge coupler. In Article 13 The above glass base structure includes a receptacle structure, The above optical fiber array includes a connector having a ferrule structure, and the receptacle structure and the ferrule structure are detachable from each other, and are an optical connection-mounted semiconductor package. In paragraph 4, The above glass base structure, base layer; Penetrating electrodes penetrating the base layer to connect the upper and lower surfaces of the base layer; A wiring structure arranged on the upper surface of the base layer; The third waveguide formed on the above wiring structure; A first dielectric layer formed on the third waveguide; The first waveguide formed on the first dielectric layer; and A semiconductor package equipped with an optical interconnection, comprising: a second dielectric layer formed on the first waveguide; In Article 16, The above glass base structure is formed by alternately stacking the third waveguide and the first dielectric layer in multiple layers to form a multilayer third waveguide. A semiconductor package with an optical interconnect, wherein the base layer comprises glass. As a semiconductor package with optical interconnection, A glass-based structure including a third waveguide implemented through a patterned third thin film and a first waveguide implemented through a patterned first thin film; and A semiconductor chip including a photonic package having a second waveguide embedded therein, the second waveguide being implemented through a patterned second thin film disposed on the glass base structure; A semiconductor package equipped with an optical connection, which enables smooth optical communication between the photonic package and the glass base structure through optical connections between the first waveguide, the second waveguide, and the third waveguide. In Article 18, The above first thin film is a semiconductor package with an optical interconnection including silicon nitride. In Article 18, A semiconductor package equipped with an optical interconnection, wherein the first waveguide is a nitride waveguide, the second waveguide is a silica waveguide, and the third waveguide is a silicon waveguide. In Article 18, A semiconductor package equipped with an optical interconnection, wherein the first waveguide has a refractive index between the second waveguide and the third waveguide. In Article 18, A semiconductor package equipped with an optical interconnect, wherein the first waveguide forms a switching matrix including MEMS-based switching elements, thermal-based switching elements, switching elements utilizing the electro-optic effect, or switching elements utilizing the free charge plasma dispersion effect. A method for forming a semiconductor package having an optical connection, A step of forming a glass base structure; a step of attaching a photonic package to the upper part of the glass base structure; and A step of attaching a semiconductor chip including a photonic package to the upper part of the glass base structure; comprising: The step of forming the above glass base structure is: A step of preparing a substrate having a glass penetration via; A step of forming a rewiring structure on the above substrate; A step of forming a silica layer on the above rewiring structure and forming a third waveguide by patterning the silica layer; A step of forming a first dielectric layer on the third waveguide; A step of forming a first waveguide by forming a silicon nitride layer on the first dielectric layer and patterning the nitride layer; and A method for forming an optical interconnection-mounted semiconductor package, comprising: forming a second dielectric layer on the first waveguide. In Article 23, Before the step of forming the first waveguide, A step of forming a second silica layer on the first dielectric layer and forming a fourth waveguide by patterning the second silica layer; and A method for forming an optical interconnection-mounted semiconductor package, further comprising the step of forming an additional first dielectric layer on the fourth waveguide. In Article 24, After the step of forming the second genetic layer, A step of forming a second silicon nitride layer on the second dielectric layer and forming a fifth waveguide by patterning the second silicon nitride layer; and A method for forming an optical interconnection-mounted semiconductor package, further comprising the step of forming an additional second dielectric layer on the fifth waveguide.

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