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WO2025073341A1 - Circuit d'amplification de tension - Google Patents

Circuit d'amplification de tension Download PDF

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Publication number
WO2025073341A1
WO2025073341A1 PCT/EP2023/077216 EP2023077216W WO2025073341A1 WO 2025073341 A1 WO2025073341 A1 WO 2025073341A1 EP 2023077216 W EP2023077216 W EP 2023077216W WO 2025073341 A1 WO2025073341 A1 WO 2025073341A1
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WO
WIPO (PCT)
Prior art keywords
voltage
inverter
accordance
cdac
boosting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/EP2023/077216
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English (en)
Inventor
Hanie GHAEDRAHMATI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to PCT/EP2023/077216 priority Critical patent/WO2025073341A1/fr
Publication of WO2025073341A1 publication Critical patent/WO2025073341A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/076—Charge pumps of the Schenkel-type the clock signals being boosted to a value being higher than the input voltage value
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Definitions

  • the present disclosure generally relates to the field of clock circuits and, more specifically, to a clock boosting circuit for boosting the drive voltage of switches in a Capacitive Digital-to-Analog Converter, CDAC.
  • CDAC Capacitive Digital-to-Analog Converter
  • the present disclosure relates to the field of data converters like Digital- to-Analog converters, DACs and, more specifically, to Capacitive Digital-to-Analog Converters, CDACs.
  • DACs often play an important role in electronic systems, where the need to convert digital signals into analog voltages is required. Such conversion may be required for various applications, including audio reproduction, communication systems, control systems, and scientific instrumentation.
  • RDACs Resistor Digital-to-Analog Converters
  • CDAC Capacitor Digital-to-Analog Converter
  • the CDACs principle is founded upon the ability of capacitors to store electric charge, making them ideal for precise analog voltage generation. By controlling the charge stored within each capacitor, CDACs can accurately represent a wide range of analog output values corresponding to the digital input, ensuring high fidelity and linearity.
  • One of the advantages of CDACs is their scalability and resolution. Unlike RDACs, which require a growing number of resistors to achieve higher resolution, CDACs can be easily augmented with additional capacitors to achieve finer granularity in the analog output voltage. This scalability enables CDACs to cater to various application scenarios, from low-resolution consumer electronics to ultra-high precision scientific instruments.
  • Advanced CMOS process technologies in the nano-scale range may have low gate overdrive voltage. Not scaling the threshold voltages of mixed-signal devices as fast as supply voltages makes the analog and mixed-signal design more difficult in deep-submicron CMOS technologies.
  • Vgs, gate-source voltage, and Vgd, gate-drain voltage are typically limited by gate oxide breakdown. Device damage and performance degradation are the result of this breakdown. If the Vgs, Vgd, and Vds, drain-source voltage, are kept within the supply voltage Vdd, the device reliability can be assured.
  • Some techniques to increase the Vgs are proposed like boosting circuits, bootstrapping and charge pump-based circuits.
  • Such boosting circuits may especially be useful in combination with Capacitive Digital-to-Analog Converters, CDACs. There is a need for an improved boosting circuit with a reduced number of components while the boosting is done adequately.
  • a boosting circuit for boosting an input control signal voltage thereby providing a boosted signal voltage for driving a switch of a Capacitive Digital to Analog Converter, CDAC.
  • the boosting circuit comprising an inverter stage comprising a first inverter connected in series with a second inverter, wherein the first inverter is arranged for receiving said input control signal voltage, and wherein an output of said second inverter is connected to a storage capacitor.
  • the boosting circuit further comprising a charge pump and comprising a storage capacitor having an input branch connected to said output of said second inverter and having an output branch connected to said charge pump, and wherein said output branch is arranged to be connected to said switch of said CDAC.
  • the charge pump is arranged to connect a shift voltage to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage Vshift, and is arranged to disconnect said shift voltage from said output branch of said storage capacitor during an ON-phase of said input control signal voltage.
  • the first inverter is biased between a supply voltage and a first low voltage, said first low voltage being higher than ground.
  • the inventor has found that it may be beneficial to boost the voltage at the output branch, as the boosted voltage is provided to the gate of the switch comprised by, for example, the CDAC.
  • the boosting circuit operates in two different phases, which may be explained as follows.
  • the control signal is a clock signal, and considering first that the clock input is low.
  • the first inverter will provide a high voltage, for example Vdd, to the input of the second inverter.
  • the second inverter will provide a second low voltage to the input branch of the storage capacitor.
  • the second low voltage may, for example, be zero volt, depending on the biasing of the second inverter.
  • a shift voltage Vshift is connected to the output branch of the storage capacitor. This will ensure that the storage capacitor is charged to the shift voltage Vshift. As such, during the OFF-phase of the clock signal, the shift voltage Vshift is to be provided to the switch of the CDAC.
  • the situation is considered wherein the clock input is high, for example equals the supply voltage Vdd.
  • the first inverter will provide a first low voltage V
  • the second inverter will thus provide a high voltage to the input branch of the storage capacitor.
  • the high voltage may, for example, be Vdd.
  • the shift voltage Vshift is disconnected from the output branch of the storage capacitor.
  • the result is that the output branch of the capacitor is voltage boosted.
  • the boosted voltage will then equal the shift voltage Vshift plus the high voltage provided by the second inverter Vdd. This boosted voltage is to be provided to the switch of the CDAC.
  • the first inverter is biased between a high voltage, for example the supply voltage Vdd, and a first low voltage Viow.
  • OW is higher than zero volt.
  • the inventors have found that the boosted voltage at the output branch of the storage capacitor may result in a gate-source voltage, Vgs, of a switch in the charge pump to exceed the supply voltage Vdd thereby risking to break the corresponding switch.
  • Vgs gate-source voltage
  • Vdd supply voltage
  • the first inverter may be biased between a first low voltage V
  • the second inverter may be biased between zero volt and the supply voltage Vdd (logic high level).
  • the input of the second inverter is connected to a signal that varies between the low voltage V
  • the output of the second inverter varies between zero volt and the supply voltage level Vdd.
  • OW biasing of the first inverter reduces the voltage over a switch in the charge pump when a boosted voltage is provided at the output branch of the storage capacitor.
  • the maximum voltage of this particular switch may be determined by subtracting the first low voltage V
  • the first low voltage may, preferably, be chosen such that the above identified maximum voltage is lower than the supply voltage thereby reducing the risk of failure of the corresponding switch.
  • a charge pump is comprised by the boosting circuit. Following the above, the charge pump effectively operates in two main phases: the charging phase and the discharging phase.
  • the charge pump accumulates charge on the storage capacitor by connecting the storage capacitor to the shift voltage Vshift- Then, during the discharging phase, the charge pump switches the storage capacitor in series with the load, in this case, the output of the second inverter, and disconnects the output branch of the storage capacitor from the shift voltage Vshift, thereby effectively boosting the voltage level.
  • the present disclosure is directed to a boosting circuit for boosting an input control signal voltage.
  • the input control signal may be related to a clock signal or a data signal.
  • the wording shift voltage is used as a descriptive label to identify a particular voltage.
  • the shift voltage may be provided by a voltage source, identified as a shift voltage source.
  • the charge pump comprises: a Complementary metal oxide semiconductor, CMOS, inverter comprising a P-Metal Oxide Semiconductor, P-MOS, Field Effect Transistor, FET and an N-MOS FET, wherein a source of said PMOS FET is connected to said output branch of said storage capacitor, wherein an input of said CMOS inverter is connected to said output of said first inverter.
  • CMOS Complementary metal oxide semiconductor
  • inverter comprising a P-Metal Oxide Semiconductor, P-MOS, Field Effect Transistor, FET and an N-MOS FET, wherein a source of said PMOS FET is connected to said output branch of said storage capacitor, wherein an input of said CMOS inverter is connected to said output of said first inverter.
  • the CMOS inverter also known as a complementary metal-oxide- semiconductor inverter, is typically a digital logic gate that performs the basic logic function of inversion.
  • the CMOS inverter is constructed using complementary MOSFET pairs, consisting of both an N-channel MOSFET and a P-channel MOSFET.
  • the NMOS conducts when its gate voltage is high, while the PMOS conducts when its gate voltage is low.
  • the CMOS inverter can effectively switch between two complementary output voltage levels: a high voltage level and a low voltage level.
  • the NMOS When the input to the CMOS inverter is at a logic low, i.e. the first low voltage V
  • the present disclosure is especially useful for protecting the P-MOS FET of the above identified CMOS inverter. By ensuring that the gate-source voltage of this particular P-MOS FET is reduced, a potential break down of the P-MOS FET is prevented.
  • the first low voltage output of the first inverter is provided to the gate terminal of the P-MOS FET when the boosted voltage is present at the source terminal of the P-MOS FET.
  • the first low voltage Viow with which the first inverter is biased is lower than a threshold voltage of the N- MOS FET of the CMOS inverter.
  • a threshold voltage refers to the gate-source voltage level at which the MOSFET starts to conduct current between its drain and source terminals.
  • the threshold voltage represents the gate voltage required to create an inversion layer in the semiconductor channel between the source and drain regions of the MOSFET.
  • This inversion layer allows the flow of charge carriers, i.e. electrons or holes, to form a conductive channel, enabling current flow between the drain and source terminals.
  • the threshold voltage is positive, and when the gatesource voltage exceeds this value, the MOSFET starts conducting current. Conversely, for a P-MOS FET, the threshold voltage is negative, and the MOSFET begins conducting when the gate-source voltage falls below this negative value.
  • Typical threshold voltage values for N-MOS FETs in CMOS technologies are usually in the range of 0.2 to 0.6 volts.
  • OW is at least equal to the shift voltage Vshitt- This would make sure that the gate-source voltage of the P-MOS FET is lower than the supply voltage.
  • the boosting circuit may comprise the shift voltage source that is arranged for providing the shift voltage Vshitt-
  • the shift voltage Vshift is equal or lower than said first low voltage V
  • a capacitive Digital to Analog Converter assembly comprising a boosting circuit in accordance with any of the previous examples and comprising: a CDAC comprising a plurality of capacitors for converting a digital input code to an analog output voltage.
  • a boosting circuit to provide a higher voltage to the gate of a MOSFET in a Capacitive Digital-to-Analog Converter, CDAC, may be advantageous to reduce the on-resistance of the corresponding MOSFET.
  • MOSFET When a MOSFET operates in its "on” state, it typically acts as a low- resistance channel between its drain and source terminals, allowing current to flow.
  • the MOSFET's on-resistance, i.e. Rds(on) is typically not constant and can vary depending on several factors, including the gate-source voltage.
  • the MOSFET By applying a higher voltage to the MOSFET gate through the boosting circuit, the MOSFET can operate such that it has relatively low on-resistance values.
  • a lower on-resistance results in reduced power dissipation across the MOSFET, leading to higher power efficiency in the CDAC circuit. This may especially be of importance in battery-operated devices and energy-efficient systems.
  • a lower on-resistance means the MOSFET dissipates less heat during operation. This translates to lower thermal stress on the MOSFET and the surrounding components, enhancing the overall reliability and longevity of the CDAC.
  • a lower on-resistance results in reduced signal distortion, allowing the CDAC to provide a more faithful representation of the digital input as an analog output signal.
  • the CDAC comprises a plurality of Field Effect Transistors, FETs, wherein each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage.
  • each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage, said voltage being any of: a common-mode voltage; an input voltage; a reference voltage.
  • the common-mode voltage i.e. Vcm
  • Vcm is typically the voltage level that appears at the common node of the capacitors in the CDAC circuit. This common node is typically connected to the output of the inverter chain, which is used to control the charging and discharging of the capacitors.
  • the common-mode voltage is used for maintaining the proper operating range of the CDAC circuit. It may ensure that the capacitors stay within the valid voltage range during the digital-to-analog conversion process. Any deviation of the common-mode voltage from its specified value could result in non-linearities, reduced dynamic range, or potential distortion in the analog output signal.
  • the input voltage, i.e. Vin, in a CDAC may refer to the analog input voltage of the SAR ADC.
  • the capacitive DAC comprises a plurality of capacitors cascaded in parallel.
  • the above referenced shared terminal i.e. the common terminal, may be connected to the input of a comparator.
  • the free ends of the capacitors may be connected to an analog input voltage, to a reference voltage or to a common-mode voltage.
  • the common terminal may be connected to common-mode voltage and all free terminals of the capacitors may be connected to the input voltage.
  • the common terminal may be disconnected from common-mode voltage, and the free terminals of the capacitors, i.e. the bottom-plate of the capacitors, may be disconnected from the input voltage. This effectively traps a charge proportional to the input voltage on the plurality of capacitors.
  • the free terminals of the capacitors may then be connected to commonmode voltage, such that the common terminal voltage is driven to a negative voltage.
  • the free end of the capacitor resembling the Most Significant Bit, MSB is disconnected from the common-mode voltage and may be connected to a reference voltage. This effectively drives the common terminal of the plurality of capacitors in a positive direction by an amount that may be equal to half the reference voltage.
  • the comparator may compare the voltage at the common terminal of the plurality of capacitors with a common-mode voltage. A logic “1” will appear at the output of the comparator if the voltage at the common terminal is smaller than the common-mode voltage. If that’s the case, then the bottom plate of the next capacitor will be connected to the reference voltage, etc. This process may continue until all the bits have been determined.
  • the output branch of said storage capacitor is connected to one or more gate terminals of said plurality of FETs of said CDAC.
  • the boosting circuit further comprises a shift voltage source arranged for providing said shift voltage Vshift, and wherein said provided shift voltage Vshift is equal to, or lower than, said reference voltage.
  • a receiver comprising such an SAR-ADC.
  • an electronic apparatus comprising such a SAR-ADC.
  • the electronic apparatus may, for example, be a communication apparatus like a User Equipment, UE, for a cellular communications system or a radio base station for a cellular communications system.
  • UE User Equipment
  • a method of operating a boosting circuit in accordance with any of the previous examples, wherein said method comprises the steps of: connecting a shift voltage Vshift to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage; disconnecting said shift voltage Vshift from said output branch of said storage capacitor during an ON-phase of said input control signal voltage; wherein said method further comprises the step of: biasing said first inverter between a supply voltage dd and a first low voltage V
  • Fig. 1 discloses a single-ended CDAC in accordance with the prior art
  • Fig. 2 discloses a boosting circuit in accordance with the present disclosure
  • Fig. 3 discloses a timing diagram of the boosting circuit in accordance with the present disclosure
  • Fig. 4 discloses a flow chart of a method in accordance with the present disclosure
  • Fig. 5 discloses an electronic apparatus in accordance with the present disclosure.
  • the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.”
  • the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof.
  • the words “herein,” “above,” “below,” and words of similar import when used in this application, refer to this application as a whole and not to any particular portions of this application.
  • words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively.
  • the word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
  • Embodiments of the particular invention are specifically useful in combination with a capacitive Digital-to-Analog Converter, CDAC.
  • a Capacitive Digital-to-Analog Converter, CDAC is a type of digital-to-analog converter that converts digital signals into analog signals using capacitors. It's commonly used in applications such as digital communication systems, instrumentation, and analog signal processing.
  • Fig. 1 shows a schematic 1 of the capacitive DAC, CDAC, adjusted to bottom-plate, BP, sampling where the analog input 2 is sampled on the bottom plate of the capacitor bank during sampling phase while the top-plate, TP, of the capacitor may be connected to V cm 3.
  • the above referenced analog input 2 may be the analog input 2 of the corresponding SAR ADC that comprises the capacitive DAC.
  • the analog input signal 2 thus represents the analog signal that is to be converted to a digital signal by the SAR ADC.
  • the bottom plate of the capacitors may first be connected to common-mode voltage V cm and may then be switched consecutively to either positive reference voltage V re f_ P 4 or negative reference voltage V re f_m 5, depending on the digital output of the SAR logic.
  • Vdd and V ss being a zero voltage source, can also be used as V re f_ P and V re f_m, respectively.
  • One of the techniques that is being used in the conversion process is referred to as the bottom plate sampling technique, as shown in Fig. 1.
  • the basic CDAC structure typically comprises an array of capacitors, each corresponding to a specific bit of the digital input.
  • the capacitors are connected in parallel to a common node, which is the analog output node, that is to be connected to the input of the comparator.
  • the other terminals of each capacitor are connected to switches, controlled by the controlling signals of the digital logic, i.e. the digital signal coming from the SAR logic of the SAR ADC.
  • bottom plate refers to one of the plates of each capacitor in the CDAC.
  • a charge redistribution will take place among the capacitors resulting in an analog voltage that is input to the comparator.
  • the charge redistribution is controlled by connecting the bottom plates of the capacitors to the different voltages Vcm, the Vref_p or Vref_m, which is based on controlling signals which control the switches.
  • Fig. 2 discloses 101 a boosting circuit in accordance with the present disclosure.
  • the boosting circuit is arranged to boost the gate of CDAC switches and results in increasing the overdrive voltages. In conclusion, the on-resistance of the switches is decreased compared to when the switches are driven by supply voltage.
  • the boosting circuit comprises a pair of inverters 102, 103, two PMOS transistors 104, 105 and one NMOS transistor 106 and a storage capacitor 107 to provide the gate-boosting voltage to the CDAC switches 113.
  • the boosting circuit has two output ports, boosted supply 108 and boosted clock 109.
  • the boosted supply 108 is the output port used in the embodiments disclosed herein.
  • a CDAC is used as one of the main building blocks in SAR ADCs. Designing a low resistance and linear enough switch which will drive the CDAC may have a significant effect on the ADC performance. Especially designing the switches in low-voltage regimes becomes challenging because of their low overdrive voltages that result in high on-resistance.
  • Fig. 2 shows the boosting circuit 101 in accordance with embodiments of the present disclosure and a model of the CDAC and the voltage boosting circuit.
  • the voltage boosting circuit comprises the switches M1-M3 104, 105, 106 which behave as a charge pump, storage capacitor C 107, and two inverters 102, 103.
  • the first inverter 102 is biased between Vdd 110 and V
  • Viow 111 is higher than zero volt 112, preferably equal or larger than Vshift 114, to ensure that the V gs of M2 104 does not exceed the supply voltage and break the M2. As a result, the V gs of M2 104 may be kept below or within Vdd 110.
  • the second inverter 103 is typically biased between dd 110 and zero volt 112 and the second inverter 103 may be stronger than the first inverter 102 as the second inverter 103 is to drive the storage capacitor C 107.
  • the boosting circuit works in two phases; when the control input 115 is low, for example zero, the gate of Mi and M2 is connected to Vdd. As the initial voltage of the storage capacitor is zero and the gate of M2 is connected to Vdd, M2 is off, and the Clkboosted port 109 is connected to zero volt through Mi.
  • the V gs of M4 should preferably not exceed the Vdd. That means the Vshift should preferably be less than Vref_ P when V re f_ P is connected to the source of M4 and less than V re f_m when V re f_m is connected to the source of M4.
  • the gate of Mi and M2 are connected to Viow which is preferably less than Vth of the Mi such that Mi is turned off.
  • the voltage over the storage capacitor is then equal to Vdd + Vshift and causes the M2 to turn on.
  • the gate of M4 which models the CDAC switches is boosted to Vdd + Vshift, and the switch on-resistance reduces. It is further noted that the gate-source voltage of M2 is Vdd + Vshift - V
  • OW is the voltage with which the first inverter is biased. By choosing V
  • the control input being a clock signal
  • the boosted clock signal Cl kboosted is indicated with reference numeral 203 and the boosted signal voltage boosted is indicated with reference numeral 204.
  • Vdd + Vshift which equals 750mV+275mV
  • Fig. 4 discloses a flow chart 301 of a method in accordance with the present disclosure.
  • the flow chart is related to a method of operating a boosting circuit in accordance with any of the examples provided above.
  • the method comprises a step of connecting 302 a shift voltage to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage.
  • the method further comprises a step of disconnecting 303 said shift voltage from said output branch of said storage capacitor during an ON-phase of said input control signal voltage.
  • the method also comprises the step of biasing 304 said first inverter between a supply voltage and a first low voltage, said first low voltage being higher than zero volt.
  • Fig. 5 discloses an electronic apparatus in accordance with the present disclosure.
  • the electronic apparatus 42 comprises an input terminal 44, an input device 43, an output terminal 46 and an output device 45.
  • the electronic apparatus may further comprise a processor 47 connected to a memory 48.
  • the electronic apparatus may comprise a CDAC as indicated with reference numeral 49.
  • the CDAC comprises a boosting circuit in accordance with the present disclosure.
  • the electronic apparatus 42 may be a communication apparatus such as a User Equipment, UE, or a base station like an eNodeB or a gNodeB.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Un circuit d'amplification (102, 103, 104, 105, 106, 107) permettant de fournir une tension de signal amplifiée (108) pour piloter un commutateur d'un CDAC est divulgué. Il comprend un étage onduleur (102, 103) comprenant un premier onduleur (102) connecté en série avec un second onduleur (103). Le premier onduleur (102) est conçu pour recevoir une tension de signal de commande d'entrée. Une sortie dudit second onduleur (103) est connectée à un condensateur de stockage (107). Il comprend en outre une pompe de charge (104, 105, 106). Le condensateur de stockage (107) présente une branche d'entrée connectée à ladite sortie dudit second onduleur (103) et une branche de sortie connectée à ladite pompe de charge (104, 105, 106). Ladite branche de sortie est conçue pour être connectée audit commutateur dudit CDAC. La pompe de charge (104, 105, 106) est conçue pour connecter une tension de décalage à ladite branche de sortie dudit condensateur de stockage (107) pendant une phase d'ARRÊT de ladite tension de signal de commande d'entrée et déconnecter ladite tension de décalage de ladite branche de sortie dudit condensateur de stockage (107) pendant une phase de MARCHE de ladite tension de signal de commande d'entrée. Le premier onduleur (102) est polarisé entre une tension d'alimentation (110) et une basse tension, ladite première basse tension (111) étant supérieure à zéro volt.
PCT/EP2023/077216 2023-10-02 2023-10-02 Circuit d'amplification de tension Pending WO2025073341A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
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