WO2025066449A1 - Pulse signal monitoring circuit, chip, and electronic device - Google Patents

Abstract

Embodiments of the present disclosure provide a pulse signal monitoring circuit, a chip, and an electronic device. The circuit comprises a pulse monitoring module. The pulse monitoring module comprises: a pulse period monitoring module used for monitoring, on the basis of a reference clock signal, the period of a pulse signal to be tested and the period change between two adjacent periods; and a pulse duty ratio monitoring module used for monitoring, on the basis of the reference clock signal, the duty ratio of said pulse signal and the duty ratio change between two adjacent periods.

Description

Pulse signal monitoring circuit, chip and electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure is based on Chinese patent application CN202311263663.8, filed on September 27, 2023, with the invention name “Pulse signal monitoring circuit, chip and electronic device”, and claims the priority of the patent application, and all the contents disclosed therein are incorporated into this disclosure by reference.

Technical Field

The present disclosure relates to the field of electronic circuits, and in particular, to a pulse signal monitoring circuit, a chip and an electronic device.

Background Art

With the development trend of automobile electrification, intelligence and Internet of Things, automotive chips need to integrate more and more functions to meet market demand, and integrated circuit (IC) design, especially system-on-chip (SOC) design, needs to integrate more and more intellectual property (IP) to meet more complex market demands. On the other hand, automobile products, as a means of transportation, are closely related to life safety, so such chips have higher requirements in terms of safety and reliability.

In order to ensure the stability of pulse signals on digital vehicle-mounted chips, the pulse sources in digital chips are mainly generated by on-chip oscillators, phase-locked loops and external crystal oscillators. Long-term operation or noise interference from the external environment is very likely to cause pulse signal failure, resulting in relatively large safety accidents and threatening personal safety.

At present, the monitoring of chip pulse signals mainly monitors clock signals with a duty cycle of 50%, and there is no monitoring of pulse signals with a duty cycle of non-50%. In terms of clock monitoring, there are mainly two categories. One is to monitor clock frequency deviation. The relevant technology uses three links to monitor frequency deviation, which is cumbersome to implement and cannot detect clock loss. The second is to monitor clock loss. When there is a clock signal, a periodic pulse signal will be output. When the clock signal is lost, a high or low level signal will be output. However, when the frequency of the clock signal to be measured changes, a high or low level signal will also be output, so it is impossible to determine whether the clock is locked.

In summary, there is no good solution to the above problems.

Summary of the invention

The embodiments of the present disclosure provide a pulse signal monitoring circuit, a chip and an electronic device to at least solve the problem in the related art that a pulse signal with a duty cycle other than 50% cannot be monitored.

According to one embodiment of the present disclosure, a pulse signal monitoring circuit is provided, which includes: a pulse period monitoring module, which is used to monitor the period of a pulse signal to be measured and the period change between two adjacent periods based on a reference clock signal; and a pulse duty cycle monitoring module, which is used to monitor the duty cycle of the pulse signal to be measured and the duty cycle change between two adjacent periods based on a reference clock signal.

According to another embodiment of the present disclosure, a chip is provided, comprising the pulse signal monitoring circuit in any one of the above embodiments.

According to another embodiment of the present disclosure, an electronic device is provided, comprising the pulse Signal monitoring circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure;

FIG2 is a structural block diagram of a pulse period monitoring module according to an embodiment of the present disclosure;

FIG3 is a structural block diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure;

FIG4 is a structural block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure;

FIG5 is a structural block diagram of a clock frequency deviation monitoring module according to an embodiment of the present disclosure;

FIG6 is a structural block diagram of a clock presence monitoring module according to an embodiment of the present disclosure;

7 is a structural block diagram of a pulse signal monitoring circuit according to another embodiment of the present disclosure;

FIG8 is a schematic diagram of a processing flow of a pulse monitoring module according to an embodiment of the present disclosure;

FIG9 is a schematic diagram of a processing flow of a clock monitoring module according to an embodiment of the present disclosure;

FIG10 is a schematic diagram of a signal aggregation process of multiple clock monitoring modules according to an embodiment of the present disclosure;

FIG11 is a waveform diagram of a pulse period monitoring module according to an embodiment of the present disclosure;

FIG. 12 is a waveform diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

The pulse signal monitoring circuit in the embodiment of the present disclosure is mainly used in chips to realize real-time monitoring of pulse signals in the chip. Chip products may include but are not limited to automotive electronic chips, consumer electronic chips, communication chips, etc.

The embodiment of the present disclosure provides a pulse signal monitoring circuit. FIG1 is a structural block diagram of the pulse signal monitoring circuit of the embodiment of the present disclosure. As shown in FIG1 , the pulse signal monitoring circuit includes a pulse monitoring module 10 .

In this embodiment, the pulse monitoring module 10 may include the following structure:

A pulse period monitoring module 12, used for monitoring the period of the pulse signal to be measured and the period change between two adjacent periods based on the reference clock signal;

The pulse duty cycle monitoring module 14 is used to monitor the duty cycle of the pulse signal to be tested and the change of the duty cycle between two adjacent cycles based on the reference clock signal.

In this embodiment, the pulse signal to be measured may be a pulse signal with any duty cycle.

Through the embodiments of the present disclosure, pulse signals with any duty cycle can be monitored, and period abnormality monitoring and duty cycle abnormality monitoring of pulse signals can be realized, which solves the problem in the related technology that pulse signals with duty cycles other than 50% cannot be monitored. Signal abnormalities in the chip can be discovered in time to ensure stable operation of the chip system.

In some embodiments, the pulse monitoring module 10 may include a first synchronizer 16 for synchronizing the input pulse signal to be tested to the clock domain of the reference clock signal to output a synchronized pulse signal.

In some embodiments, the pulse monitoring module 10 may further include a first edge monitoring module 18, whose input end is connected to the output end of the first synchronizer, for monitoring the rising edge of the synchronization pulse signal and outputting a first trigger signal when the rising edge of the synchronization pulse signal arrives.

In some embodiments, the first edge monitoring module 18 is further configured to monitor the falling edge of the synchronization pulse signal and When the falling edge of the synchronization pulse signal arrives, the third trigger signal is output.

In some embodiments, the pulse period monitoring module and the pulse duty cycle monitoring module may share a synchronizer and an edge detection module, or may each independently use a synchronizer and an edge detection module.

In this embodiment, the synchronizer is used to realize the synchronous release of the asynchronous signal in the input clock domain through synchronization processing. The synchronizer can synchronize the reset signal to the desired clock domain for release, and reduce the probability of metastable state that may occur when the reset signal is released due to crossing the clock domain.

FIG. 2 is a structural block diagram of a pulse period monitoring module according to an embodiment of the present disclosure. As shown in FIG. 2 , the pulse period monitoring module 12 may include the following structures:

The period calculation module 122, whose input end is connected to the output end of the first edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the first trigger signal arrives next time, and output the pulse signal period.

The period change monitoring module 124 has an input end connected to the output end of the period calculation module and is used to compare whether the periods of two adjacent pulse signals are the same, and output a second trigger signal when the periods of the two adjacent pulse signals are different.

The change cycle counting module 126 has an input end connected to the output end of the period change monitoring module and is used to count the second trigger signal.

In some embodiments, the pulse period monitoring module is also used to compare the number of second trigger signals output by the change period counting module 126 with a preset period change threshold, and output a period change alarm signal when the number of the second trigger signals is greater than the preset period change threshold.

In an exemplary embodiment, the pulse period monitoring module uses a single edge detection module. In this case, the pulse period monitoring module also includes a rising edge monitoring module 128, whose input end is connected to the output end of the first synchronizer, for monitoring the rising edge of the synchronization pulse signal and outputting a first trigger signal when the rising edge of the synchronization pulse signal arrives.

In this embodiment, the input end of the period calculation module 122 is connected to the output end of the rising edge monitoring module.

In some embodiments, according to monitoring requirements, the pulse period monitoring module may include a combination of one or more of the above structures. The pulse period monitoring module may only support real-time monitoring of the pulse period or pulse frequency, or may generate an indication signal when the pulse changes to a certain value, and the central control determines whether to respond.

In some embodiments, the cycle calculation module 122 and the change cycle counting module 126 can be implemented by a counter. The cycle calculation module can use the rising edge of the first trigger signal, i.e., the synchronous pulse signal, as a counting mark, start at a counting mark, end at the next counting mark, record the current value and then clear it. The change cycle counting module can use the rising edge of the second trigger signal as a counting mark, and clear it when the alarm signal is output or the pulse signal cycle returns to normal.

In some embodiments, the period variation threshold may be set according to the sensitivity of the alarm abnormality. The smaller the period variation threshold, the higher the sensitivity to the pulse signal period abnormality.

Through the embodiments of the present disclosure, real-time monitoring of the pulse period of a pulse signal with any duty cycle can be achieved, and abnormal period conditions of the pulse signal can be discovered in time, thereby ensuring the normal operation of the chip system.

In some other embodiments, the first edge monitoring module 18 is further used to monitor the falling edge of the synchronization pulse signal, and output a third trigger signal when the falling edge of the synchronization pulse signal arrives.

FIG3 is a structural block diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure. As shown in FIG3 , the pulse duty cycle monitoring module 14 may include the following structure:

A duty cycle calculation module 142, whose input end is connected to the output end of the first edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the third trigger signal arrives. The number of high-level pulses is obtained, the ratio of the number of high-level pulses to the pulse signal period is determined as the pulse signal duty cycle, and the pulse signal duty cycle is output.

The duty cycle change monitoring module 144 has an input end connected to the output end of the duty cycle calculation module and is used to compare whether the duty cycles of two adjacent pulse signals are the same. When the duty cycles of the two adjacent pulse signals are different, a fourth trigger signal is output.

The duty cycle change counting module 146 has an input end connected to the output end of the duty cycle change monitoring module and is used to count the fourth trigger signal.

In some embodiments, the pulse duty cycle monitoring module can also compare the number of fourth trigger signals output by the duty cycle change counting module 146 with a preset duty cycle change threshold, and output a duty cycle change alarm signal when the number of the fourth trigger signals is greater than the preset duty cycle change threshold.

In an exemplary embodiment, the pulse duty cycle monitoring module uses a single edge detection module. In this case, the pulse period monitoring module also includes a falling edge monitoring module 148, whose input end is connected to the output end of the first synchronizer, for monitoring the falling edge of the synchronization pulse signal and outputting a third trigger signal when the falling edge of the synchronization pulse signal arrives.

In this embodiment, the duty cycle calculation module 142 has an input end connected to the output end of the rising edge monitoring module and the output end of the falling edge monitoring module.

In some embodiments, according to monitoring requirements, the pulse duty cycle monitoring module may include a combination of one or more of the above structures. The pulse duty cycle monitoring module may only support real-time monitoring of the duty cycle, or may generate an indication signal when the duty cycle changes to a certain value, and the central control determines whether to respond.

In some embodiments, the duty cycle calculation module 142 and the duty cycle change counting module 146 may be implemented using counters.

In this embodiment, the duty cycle calculation module can use the rising edge of the first trigger signal, i.e., the synchronization pulse signal, as the count start mark, and the falling edge of the third trigger signal, i.e., the synchronization pulse signal, as the count end mark, record the current value and then clear it to zero. Then, the duty cycle is calculated by combining the pulse signal period obtained in the period calculation module 122.

In this embodiment, the duty cycle change counting module may use the rising edge of the fourth trigger signal as a counting mark, and clear it when an alarm signal is output or the duty cycle of the pulse signal returns to normal.

In some embodiments, the duty cycle change threshold can be set according to the sensitivity of the alarm abnormality. The smaller the duty cycle change threshold, the higher the sensitivity to the abnormal duty cycle of the pulse signal.

Through the embodiments of the present disclosure, pulse signals of any duty cycle can be monitored, abnormal duty cycle monitoring of pulse signals can be achieved, signal abnormalities in the chip can be discovered in time, and stable operation of the chip system can be ensured.

In another embodiment, when the pulse period monitoring module and the pulse duty cycle monitoring module share an edge monitoring module, the rising edge monitoring module and the falling edge monitoring module are the same edge monitoring module, namely, the first edge monitoring module 18 .

FIG. 4 is a structural block diagram of a pulse signal monitoring circuit according to an embodiment of the present disclosure. As shown in FIG. 4 , the pulse signal monitoring circuit may further include a clock monitoring module 20 .

In this embodiment, the clock monitoring module 20 includes the following structure:

A clock frequency deviation monitoring module 22, configured to monitor the frequency and frequency deviation of a clock signal to be measured based on the reference clock signal;

The clock presence monitoring module 24 is used to monitor the presence status of the clock signal to be tested based on the reference clock signal.

In this embodiment, the clock signal to be measured may be a pulse signal with a duty cycle of 50%.

In this embodiment, the reference clock signal is the only reference of the clock monitoring module and may be derived from an external crystal oscillator or a stable clock generating unit. The stability of the reference clock must be ensured.

Through the embodiments of the present disclosure, flexible monitoring of pulse signals and clock signals with duty cycles other than 50% can be achieved, and different monitoring modules can be called or connected for processing according to monitoring requirements, thereby expanding the scope of application of the chip monitoring system.

In some embodiments, the clock monitoring module further includes:

A frequency divider, used for dividing the input clock signal to be measured based on a preset frequency division coefficient, and outputting a frequency division signal;

A second synchronizer, whose input end is connected to the output end of the frequency divider, is used to synchronize the frequency-divided signal to the clock domain of the reference clock signal and output a synchronized clock signal;

A second edge monitoring module, whose input end is connected to the output end of the second synchronizer, is used to monitor the rising edge of the synchronization clock signal and output a fifth trigger signal when the rising edge of the synchronization clock signal arrives;

A counting module, whose input end is connected to the output end of the second edge monitoring module, is used to start counting the reference clock signal when the fifth trigger signal arrives, and to end counting when the fifth trigger signal arrives next time, and output the count value.

In some embodiments, if the frequency of the clock signal to be measured is correct, the count value is the frequency ratio of the reference clock signal and the synchronous clock signal (or the divided clock signal to be measured).

In some embodiments, the clock frequency deviation monitoring module and the clock presence monitoring module may share a frequency divider, a synchronizer, an edge detection module, and a counting module, or may be used independently.

FIG5 is a structural block diagram of a clock frequency deviation monitoring module according to an embodiment of the present disclosure. As shown in FIG5 , the clock frequency deviation monitoring module 22 may include the following structures:

The frequency deviation detection module 222 has an input end connected to the output end of the counting module, and is used to output a frequency deviation alarm signal when the count value is greater than a preset frequency deviation upper limit or less than a preset frequency deviation lower limit.

The frequency detection module 224 has an input end connected to the output end of the counting module and is used to determine the frequency of the clock signal to be measured according to the counting value, the frequency division coefficient and the reference clock frequency.

In this embodiment, the upper limit value of the frequency deviation and the lower limit value of the frequency deviation can be flexibly configured according to the requirements of the frequency deviation detection accuracy. The upper limit value of the frequency deviation is the sum of the standard count value when no frequency deviation occurs and the frequency deviation detection accuracy, and the lower limit value of the frequency deviation is the difference between the standard count value and the frequency deviation detection accuracy.

In some embodiments, the frequency detection module requires a stable clock source as a reference clock, which can come from an external crystal oscillator, an off-chip clock chip, or other stable clock sources. According to the Nyquist sampling theorem, in order to ensure accurate sampling, the reference clock frequency must be greater than twice the frequency of the clock to be measured.

FIG6 is a structural block diagram of a clock presence monitoring module according to an embodiment of the present disclosure. As shown in FIG6 , the clock presence monitoring module 24 may include the following structure:

The in-place detection module 242 has an input end connected to the output end of the counting module, receives the input count value and a preset in-place detection threshold, and is used to determine that the in-place state of the clock signal to be measured is a lost state when the count value is greater than the in-place detection threshold, and output an in-place alarm signal.

In some embodiments, the presence detection threshold may be set according to a frequency range of the clock signal to be detected.

In an exemplary embodiment, if the clock signal to be tested is not lost, the signal width after frequency division ranges from 0.5M to 2M, where M is the pulse width of the stable and non-lost low-speed clock source, and the in-place detection threshold can also be set to 0.5M to 2M.

In an exemplary embodiment, when the clock frequency deviation monitoring module and the clock presence monitoring module share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the input end of the clock frequency deviation monitoring module and the input end of the clock presence monitoring module are connected to the output end of the same counting module;

In another exemplary embodiment, the clock frequency deviation monitoring module and the clock presence monitoring module do not share the In the case of a frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the clock frequency deviation monitoring module and the clock in-position monitoring module respectively include a group of the frequency divider, the second synchronizer, the second edge monitoring module and the counting module.

In this embodiment, the input ends of the frequency deviation detection module, the frequency detection module, and the presence detection module may be connected to the counting modules in the corresponding groups.

FIG. 7 is a structural block diagram of a pulse signal monitoring circuit according to another embodiment of the present disclosure. As shown in FIG. 7 , the pulse signal monitoring circuit may further include the following structure:

The plurality of clock monitoring modules 20 , the frequency deviation monitoring and summarizing module 30 and the in-position monitoring and summarizing module 40 .

In this embodiment, a plurality of the clock monitoring modules are used to output multiple frequency deviation detection signals and multiple in-place detection signals, wherein each of the clock signals to be measured is input into one of the clock monitoring modules, and a frequency deviation detection signal is output from the clock frequency deviation monitoring module of each of the clock monitoring modules, and a in-place detection signal is output from the clock in-place monitoring module of each of the clock monitoring modules, wherein the frequency deviation detection signal includes a frequency deviation alarm signal and a normal frequency deviation signal, and the in-place detection signal includes an in-place alarm signal and a normal in-place signal;

In this embodiment, the frequency deviation monitoring summary module has an input end connected to the output ends of the multiple clock monitoring modules, receives the input multiple frequency deviation detection signals and a preset frequency deviation detection mask, determines whether each frequency deviation detection signal is output according to the frequency deviation detection mask, and performs an OR operation on the multiple frequency deviation detection signals after mask processing, and outputs a summarized frequency deviation detection result;

In this embodiment, the input end of the in-place monitoring summary module is connected to the output ends of the multiple clock monitoring modules, receives the input multiple in-place detection signals and a preset in-place detection mask, determines whether each of the multiple in-place detection signals is output according to the in-place detection mask, performs an OR operation on the multiple in-place detection signals after mask processing, and outputs a summarized in-place detection result.

Through the disclosed embodiments, it is possible to monitor multiple clock inputs, and the monitoring results can be reported after being summarized by the summary logic. According to the sensitivity of the monitoring scenario to the clock frequency deviation or the in-position state, the frequency deviation detection mask and the in-position detection mask can be configured to determine whether the monitoring results are output.

FIG8 is a schematic diagram of a processing flow of a pulse monitoring module according to an embodiment of the present disclosure. As shown in FIG8 , the pulse monitoring module includes the following structure:

The synchronizer realizes the synchronous release of the asynchronous signal in the input clock domain through synchronization processing. In this embodiment, it is used to synchronize the clock domain of the input pulse (in_pulse), that is, the pulse signal to be measured, with the clock domain of the reference clock.

The rising edge sampler samples the rising edge of the input pulse under the control of the working clock gating signal (wclk_gate).

The period calculation module calculates the number of reference clocks between two adjacent rising edges of the pulse signal to be measured, that is, the period of the pulse signal.

The cycle change monitoring module compares whether the number of cycles has changed between two cycles.

The change cycle counting module records the number of changes in the cycle number.

The falling edge sampler samples the falling edge of the input pulse under the control of the working clock gating signal (wclk_gate).

The duty cycle calculation module calculates the number of reference clocks between the rising edge and the falling edge of the pulse signal to be measured, and calculates the duty cycle of the pulse to be measured in combination with the cycle output by the cycle calculation module.

The duty cycle change monitoring module compares the duty cycles calculated twice before and after to see if they have changed.

The duty cycle change counting module records the number of duty cycle changes.

In this embodiment, the synchronizer is equivalent to the first synchronizer in the above embodiment, and the rising edge sampler and the falling edge sampler are equivalent to the first edge monitoring module in the above embodiment.

In some embodiments, the pulse monitoring module also includes registers for storing processing results of other modules.

In this embodiment, the workflow of the pulse monitoring module may include the following steps:

Step S101, synchronizing input pulses in a reference clock domain.

Step S102, sampling the rising edge of the input pulse to identify the range of a single cycle.

Step S103, calculate the number of cycles, determine the number of reference clocks between two rising edges, clear the counter when a rising edge is encountered, perform the next round of counting, and store the current count value in the register. The reference clock divided by the current value is the frequency value of the pulse.

Step S104, start counting the number of cycles of the reference clock when the pulse high level is valid, and record the current value after counting to the maximum value. Since the number of pulses in the entire cycle has been obtained in step S103, the duty cycle can be obtained by dividing it.

Step S105, monitoring the count values of step S103 and step S104, and comparing them with the count values of the next cycle, and reporting an interrupt when the difference is greater than a threshold, indicating that the cycle and duty cycle have changed.

In some embodiments, the threshold value in step S105 can be set according to the sensitivity of monitoring, and the minimum threshold value can be zero. As long as the number of cycles or duty cycles of two adjacent ones are different, an interrupt signal is reported.

In some embodiments, after step S105, the process further includes counting the number of period changes or the number of duty cycle changes, and comparing the number of changes with a period change threshold or a duty cycle change threshold, and generating a corresponding alarm signal when the threshold is exceeded.

In an exemplary embodiment, the pulse monitoring module is used to perform period monitoring and duty cycle monitoring on pulse signals with any duty cycle, and the clock monitoring module is used to perform frequency deviation monitoring and in-position monitoring on pulse signals (ie, clock signals) with a duty cycle of 50%.

FIG. 9 is a schematic diagram of a processing flow of a clock monitoring module according to an embodiment of the present disclosure. As shown in FIG. 9 , the clock monitoring module includes the following structure:

The frequency divider provides clocks of different frequencies and divides the original clock frequency to be tested to achieve the purpose of frequency reduction.

The synchronizer realizes the synchronous release of asynchronous signals in the input clock domain through synchronous processing. The clock signal to be tested can be synchronized to the desired clock domain for release, and the probability of metastable state that may occur when the clock signal to be tested is released due to crossing clock domains can be reduced.

The rising edge sampler is used to monitor the rising edge of the clock signal to be measured.

The counter is used to realize the counting function, mainly to calculate the number of reference clocks between two adjacent rising edges of the clock to be measured.

The frequency deviation detection module is used to compare the count value with the frequency deviation lower limit value and the frequency deviation upper limit value to determine whether the clock is out of lock and output the frequency deviation status (ie, the frequency deviation detection signal).

The frequency detection module is used to calculate the frequency of the clock signal.

The presence detection module is used to compare the count value with the presence detection threshold value, thereby determining whether clock loss occurs and outputting a presence status (ie, a presence detection signal).

In this embodiment, the synchronizer is equivalent to the second synchronizer, the rising edge sampler is equivalent to the second edge monitoring module, and the counter is equivalent to the calculation module.

In some embodiments, the clock monitoring module also includes registers for storing processing results of other modules.

In some embodiments, the clock monitoring module supports three functions, namely, clock frequency deviation monitoring and reporting, clock in place Monitoring and reporting, clock frequency monitoring.

In an exemplary embodiment, the workflow of the clock monitoring module for monitoring and reporting clock frequency deviation may include the following steps:

Step S201, generating a configurable frequency division coefficient, which may be derived from other clock domains, and then needs to be synchronized to the clock domain to be tested, and then used in subsequent frequency division units after the signal is stable.

In step S202, the clock to be tested is divided, wherein the division coefficient comes from step S201, and the clock to be tested is divided to at least one half of the reference clock. The reference clock serves as the only reference for the clock monitoring module and can be derived from an external crystal oscillator or a stable clock generating unit. The stability of the reference clock must be ensured.

Step S203, synchronize the divided clock to be tested in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after the division is used as a cycle of the counter. If the frequency of the clock to be tested is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be tested.

Step S204, generating a counting flag, counting to the frequency division flag being pulled high and then cleared and counting again, this flag is the rising edge of the clock to be measured after frequency division in the reference clock domain, and the high level duration is one reference clock cycle.

Step S205, counting starts from zero in the reference clock domain, and when the counting flag is pulled high, it is cleared and restarted.

Step S206, judging whether the counting period is within an acceptable range. According to the requirements for clock quality, the frequencies of the clock to be measured and the reference clock can provide upper and lower threshold values for counting. If the counting value is lower than the lower limit or higher than the upper limit, a clock frequency abnormality will be reported.

In the disclosed embodiment, the frequency division coefficient and threshold of the clock to be tested can be flexibly configured. For different chips and scenarios, it is only necessary to modify the parameters according to the actual situation, and the flexibility and maintainability of the system are enhanced.

In an exemplary embodiment, the workflow of the clock monitoring module for monitoring and reporting the clock in place may include the following steps:

Step S301, generate a configurable frequency division coefficient, which can be derived from other clock domains, and then need to be synchronized to the clock domain to be tested, and then used in subsequent frequency division units after the signal is stable.

In step S302, the clock to be tested is divided, wherein the division coefficient comes from step S301, and the clock to be tested is divided to at least one half of the reference clock. The reference clock serves as the only reference of this monitoring unit and can be derived from an external crystal oscillator or a stable clock generating unit. The stability of the reference clock must be guaranteed.

Step S303, synchronize the divided clock to be tested in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after the division is used as a cycle of the counter. If the frequency of the clock to be tested is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be tested.

Step S304, generating a counting flag, counting to the frequency division flag being pulled high and then cleared and counting again, this flag is the rising edge of the clock to be measured after frequency division in the reference clock domain, and the high level duration is one reference clock cycle.

Step S305, counting starts from zero in the reference clock domain, and clears to zero and restarts when the counting flag is pulled high.

Step S306, compare the count value in step S305 with the set threshold. When the count value is greater than the threshold, it means that the clock has not flipped as expected, and the loss alarm is raised.

In an exemplary embodiment, the workflow of the clock monitoring module for performing clock frequency monitoring may include the following steps:

Step S401, generating a configurable frequency division coefficient, which may be derived from other clock domains, and then needs to be synchronized to the clock domain to be tested, and then used in subsequent frequency division units after the signal is stable.

Step S402, divide the clock to be tested, where the frequency division coefficient is derived from step S401, divide the clock to be tested to at least half of the reference clock. The reference clock is the only reference of this monitoring unit and can be derived from an external crystal oscillator. Or a stable clock generating unit must ensure the stability of the reference clock.

Step S403, synchronize the divided clock to be tested in the reference clock domain, synchronize it in the reference clock domain, and use it for the rising edge sampler. Each cycle after the division is used as a cycle of the counter. If the frequency of the clock to be tested is normal, then the count value will be the frequency ratio of the reference clock and the divided clock to be tested.

Step S404, generating a counting flag, counting to the frequency division flag being pulled high and then cleared and counting again, this flag is the rising edge of the clock to be measured after frequency division in the reference clock domain, and the high level duration is one reference clock cycle.

Step S405, counting starts from zero in the reference clock domain, and when the count flag is pulled high, it is cleared and restarted, and the count value is output. According to the reference clock frequency and the frequency division coefficient, the frequency of the clock to be measured can be calculated from the count value.

FIG10 is a schematic diagram of a signal aggregation process of multiple clock monitoring modules according to an embodiment of the present disclosure. As shown in FIG10 , monitoring of multiple clock signals to be measured can be achieved by instantiating the clock monitoring modules multiple times.

In this embodiment, the monitoring result of the clock monitoring module can be sent by register reading and writing. If the output status of multiple clock sources needs to be summarized, a one-bit status bit can be generated through the summary logic for reporting.

In some embodiments, if certain scenarios are not sensitive to clock frequency deviation or in-bit status, mask bits can be added to determine whether the monitoring results are output by configuring the mask bits. However, the mask value does not affect the operation of the monitoring module. The clock monitoring module is only affected by the internal enable signal of the module.

In this embodiment, the mask includes a frequency deviation detection mask and a presence monitoring mask.

In some embodiments, the effective level and level of the mask can be set according to actual needs.

In an exemplary embodiment, taking the two-level mask high level as an example, when the mask bit is 1, the detection signal is shielded, and the detection signal is 1, which can indicate the output of an alarm signal. Each mask bit is inverted bit by bit and then ANDed with the corresponding frequency deviation/in-place detection signal. Only when the mask bit is 0 and the detection signal is 1, an alarm signal is output, and no alarm signal is output in other cases. When the signal is aggregated, an OR operation can be performed on multiple masked frequency deviation/in-place detection signals. As long as any frequency deviation/in-place alarm signal is output, the aggregated frequency deviation/in-place detection result is output as 1, generating an alarm.

In some embodiments, the logic operation process of the mask high level is as follows:

Y ₀ ＝clock_unlock ₀ &&(~mask ₀ )

...

Y _N =clock_unlock _N &&(~mask _N )

Y _total =|{Y ₀ ,Y ₁ ,Y ₂ ,Y ₃ ...Y _N }

Among them, Y ₀ and Y _N represent the frequency deviation/presence detection signals after mask processing. Since the frequency deviation abnormality can also be called clock unlock, clock_unlock0 to clock_unlockN represent the frequency deviation detection signals respectively. The frequency deviation detection signal can be replaced by the presence detection signal. Mask ₀ and mask _N represent the mask bits corresponding to each detection signal. Y _total represents the summarized frequency deviation/presence detection result.

In an exemplary embodiment, taking the two-level mask low level as an example, when the mask bit is 0, the detection signal is shielded, and when the detection signal is 1, an alarm signal is output. An AND operation is performed on each mask bit and the corresponding frequency deviation/in-place detection signal. Only when the mask bit is 1 and the detection signal is 1, an alarm signal is output, and no alarm signal is output in other cases. When the signal is aggregated, an OR operation can be performed on multiple masked frequency deviation/in-place detection signals. As long as any frequency deviation/in-place alarm signal is output, the aggregated frequency deviation/in-place detection result is output as 1, generating an alarm.

In some embodiments, the logic operation process of the mask low level is as follows:

Y ₀ =clock_unlock ₀ &&(mask ₀ )

...

Y _N =clock_unlock _N &&(mask _N )

Y _total =|{Y ₀ ,Y ₁ ,Y ₂ ,Y ₃ ...Y _N }

Among them, Y ₀ and Y _N represent the frequency deviation/presence detection signals after mask processing. Since the frequency deviation abnormality can also be called clock unlock, clock_unlock0 to clock_unlockN represent the frequency deviation detection signals respectively, mask ₀ and mask _N represent the mask bits corresponding to each detection signal, and Y _total represents the summarized frequency deviation/presence detection result.

In some embodiments, when summarizing the clock presence status, the frequency deviation detection signal clock_unlock may be replaced by the presence detection signal.

FIG. 11 is a waveform diagram of a pulse period monitoring module according to an embodiment of the present disclosure. As shown in FIG. 11 , the pulse period monitoring module involves the following signals:

Reference clock (ref_clk), input pulse (in_pulse), input pulse synchronization signal (in_pulse_sync), input frequency count flag (in_freq_cnt_flag), input frequency count (in_freq_cnt).

In this embodiment, the reference clock may come from a stable clock source such as an external crystal oscillator, an off-chip clock chip, etc. To ensure the accuracy of sampling, the reference clock frequency must be greater than twice the pulse frequency.

In this embodiment, the input pulse (in_pulse) is synchronized to the clock domain of the reference clock (ref_clk) to obtain an input pulse synchronization signal (in_pulse_sync). The input frequency count flag (in_freq_cnt_flag) is used as a cycle completion mark, which is triggered by the rising edge of the input pulse synchronization signal (in_pulse_sync) and can last for a reference signal cycle.

In this embodiment, the input frequency count (in_freq_cnt) is used to count the number of reference clocks between two adjacent input frequency count flags. After the counter counts from one flag bit to the next flag bit, it saves the current count value cnt and then clears it to start the next round of counting.

In some embodiments, if the frequency of the reference clock is known to be Fref, the frequency of the input pulse (i.e., the pulse signal to be measured) can be calculated using Fref/cnt or Fref/(cnt+1), where the specific use of cnt or cnt+1 is determined by the initial value of the counter. If the counter starts counting from 0, the input pulse frequency is Fref/cnt, and if the counter starts counting from 1, the input pulse frequency is Fref/(cnt+1).

FIG12 is a waveform diagram of a pulse duty cycle monitoring module according to an embodiment of the present disclosure. As shown in FIG12 , the pulse duty cycle monitoring module involves the following signals:

Reference clock (ref_clk), input pulse (in_pulse), input pulse synchronization signal (in_pulse_sync), input frequency count flag (in_freq_cnt_flag), input duty cycle count (in_duty_cnt).

In this embodiment, the calculation of the duty cycle is similar to the frequency calculation, and both are performed by counting the reference clock to calculate the pulse length. The difference is that the pulse duty cycle monitoring module counts the high level of the pulse, and uses the rising edge sampling and falling edge clearing method to store the input duty cycle count (in_duty_cnt) into the register. Then, the duty cycle can be calculated based on the reference clock frequency and the input frequency count value (in_freq_cnt).

In an exemplary embodiment, assuming that the frequency count value of a single cycle is data_freq and the duty cycle count value is data_duty, the duty cycle can be expressed as: data_duty/data_freq or (data_duty+1)/(data_freq+1), and whether to add 1 depends on the initial value of the counter.

Through the embodiments of the present disclosure, the duty cycle calculation of any pulse signal can be realized, which improves the applicability of the chip monitoring system. At the same time, the fault monitoring is realized by comparing the count values before and after the duty cycle/period of the pulse signal, which increases the system's stability.

An embodiment of the present disclosure further provides a chip, which includes the pulse signal monitoring circuit in any one of the above embodiments.

In some embodiments, the chip can be applied to various scenarios such as automotive electronics, consumer electronics, and communications, etc. The present disclosure does not limit this.

An embodiment of the present disclosure further provides an electronic device, which includes the pulse signal monitoring circuit in any one of the above embodiments.

In some embodiments, the device may also include the chip in the above embodiments.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

The above description is only an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims (19)

A pulse signal monitoring circuit, the circuit comprising a pulse monitoring module, the pulse monitoring module comprising: A pulse cycle monitoring module, used for monitoring the cycle of the pulse signal to be measured and the cycle change between two adjacent cycles based on the reference clock signal; A pulse duty cycle monitoring module is used to monitor the duty cycle of the pulse signal to be tested and the duty cycle change between two adjacent cycles based on the reference clock signal. The circuit according to claim 1, wherein the pulse monitoring module further comprises: A first synchronizer, used for synchronizing the input pulse signal to be tested to the clock domain of the reference clock signal to output a synchronization pulse signal; The pulse period monitoring module comprises: A rising edge monitoring module, whose input end is connected to the output end of the first synchronizer, is used to monitor the rising edge of the synchronization pulse signal and output a first trigger signal when the rising edge of the synchronization pulse signal arrives; A period calculation module, whose input end is connected to the output end of the rising edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the first trigger signal arrives next time, and output the pulse signal period. The circuit according to claim 2, wherein the pulse period monitoring module further comprises: The period change monitoring module has an input end connected to the output end of the period calculation module and is used to compare whether the periods of two adjacent pulse signals are the same, and output a second trigger signal when the periods of the two adjacent pulse signals are different. The circuit according to claim 3, wherein the pulse period monitoring module further comprises: A change cycle counting module, whose input end is connected to the output end of the period change monitoring module, is used to count the second trigger signal. The circuit according to claim 4, wherein The pulse cycle monitoring module is also used to compare the number of second trigger signals output by the change cycle counting module with a preset cycle change threshold, and output a cycle change alarm signal when the number of the second trigger signals is greater than the cycle change threshold. The circuit according to claim 2, wherein the pulse duty cycle monitoring module comprises: A falling edge monitoring module, whose input end is connected to the output end of the first synchronizer, is used to monitor the falling edge of the synchronization pulse signal and output a third trigger signal when the falling edge of the synchronization pulse signal arrives; A duty cycle calculation module, whose input end is connected to the output end of the rising edge monitoring module and the output end of the falling edge monitoring module, is used to start counting the reference clock signal when the first trigger signal arrives, and end counting when the third trigger signal arrives to obtain the number of high-level pulses, determine the ratio of the number of high-level pulses to the pulse signal period as the pulse signal duty cycle, and output the pulse signal duty cycle. The circuit according to claim 6, wherein the pulse duty cycle monitoring module further comprises: The duty cycle change monitoring module has an input end connected to the output end of the duty cycle calculation module and is used to compare whether the duty cycles of two adjacent pulse signals are the same. When the duty cycles of the two adjacent pulse signals are different, a fourth trigger signal is output. The circuit according to claim 7, wherein the pulse duty cycle monitoring module further comprises: A duty cycle change counting module, whose input end is connected to the output end of the duty cycle change monitoring module, is used to count the fourth trigger signal. The circuit according to claim 8, wherein The pulse duty cycle monitoring module is also used to compare the number of fourth trigger signals output by the duty cycle change counting module with a preset duty cycle change threshold, and output a duty cycle change alarm signal when the number of the fourth trigger signals is greater than the duty cycle change threshold. The circuit according to claim 6, wherein, in the case where the pulse period monitoring module and the pulse duty cycle monitoring module share an edge monitoring module, the rising edge monitoring module and the falling edge monitoring module are the same edge monitoring module. The circuit according to claim 1, wherein the circuit further comprises a clock monitoring module, wherein the clock monitoring module comprises: A clock frequency deviation monitoring module, used to monitor the frequency and frequency deviation of the clock signal to be measured based on the reference clock signal; The clock presence monitoring module is used to monitor the presence status of the clock signal to be tested based on the reference clock signal. The circuit according to claim 11, wherein the clock monitoring module further comprises: A frequency divider, used for dividing the input clock signal to be measured based on a preset frequency division coefficient, and outputting a frequency division signal; A second synchronizer, whose input end is connected to the output end of the frequency divider, is used to synchronize the frequency-divided signal to the clock domain of the reference clock signal and output a synchronized clock signal; A second edge monitoring module, whose input end is connected to the output end of the second synchronizer, is used to monitor the rising edge of the synchronization clock signal and output a fifth trigger signal when the rising edge of the synchronization clock signal arrives; A counting module, whose input end is connected to the output end of the second edge monitoring module, is used to start counting the reference clock signal when the fifth trigger signal arrives, and to end counting when the fifth trigger signal arrives next time, and output the count value. The circuit according to claim 12, wherein the clock frequency deviation monitoring module comprises: The frequency deviation detection module has an input end connected to the output end of the counting module and is used to output a frequency deviation alarm signal when the count value is greater than a preset frequency deviation upper limit or less than a preset frequency deviation lower limit. The circuit according to claim 12, wherein the clock frequency deviation monitoring module comprises: A frequency detection module, whose input end is connected to the output end of the counting module, is used to determine the frequency of the clock signal to be measured according to the counting value, the frequency division coefficient and the reference clock frequency. The circuit according to claim 12, wherein the clock presence monitoring module comprises: The in-place detection module has an input end connected to the output end of the counting module and is used to determine that the in-place state of the clock signal to be measured is a lost state and output an in-place alarm signal when the count value is greater than a preset in-place detection threshold. The circuit according to claim 12, wherein In the case where the clock frequency deviation monitoring module and the clock presence monitoring module share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the input end of the clock frequency deviation monitoring module and the input end of the clock presence monitoring module are connected to the output end of the same counting module; When the clock frequency deviation monitoring module and the clock presence monitoring module do not share the frequency divider, the second synchronizer, the second edge monitoring module and the counting module, the clock frequency deviation monitoring module and the clock presence monitoring module respectively include a group of the frequency divider, the second synchronizer, the second edge monitoring module and the counting module. The circuit according to claim 11, the circuit comprises a plurality of the clock monitoring modules, the circuit further comprises a frequency deviation monitoring summary module and an in-position monitoring summary module, wherein: The multiple clock monitoring modules are used to output multiple frequency deviation detection signals and multiple in-place detection signals, wherein each of the clock signals to be measured is input into one of the clock monitoring modules, and a frequency deviation detection signal is output from the clock frequency deviation monitoring module of each of the clock monitoring modules, and a in-place detection signal is output from the clock in-place monitoring module of each of the clock monitoring modules, wherein the frequency deviation detection signal includes a frequency deviation alarm signal and a normal frequency deviation signal, and the in-place detection signal includes an in-place alarm signal and a normal in-place signal; The frequency deviation monitoring and summarizing module, whose input end is connected to the output ends of the multiple clock monitoring modules, receives the input multiple frequency deviation detection signals and a preset frequency deviation detection mask, determines whether each frequency deviation detection signal is output according to the frequency deviation detection mask, and performs an OR operation on the multiple frequency deviation detection signals after mask processing, and outputs a summarized frequency deviation detection result; The in-place monitoring summary module has an input end connected to the output ends of the multiple clock monitoring modules, receives the input multiple in-place detection signals and a preset in-place detection mask, determines whether each of the multiple in-place detection signals is output according to the in-place detection mask, performs an OR operation on the multiple in-place detection signals after mask processing, and outputs a summarized in-place detection result. A chip comprising the pulse signal monitoring circuit described in any one of claims 1 to 17. An electronic device, comprising the pulse signal monitoring circuit described in any one of claims 1 to 17.